8K/16K 5.0V Microwire Serial EEPROM: Features
8K/16K 5.0V Microwire Serial EEPROM: Features
8K/16K 5.0V Microwire Serial EEPROM: Features
93C76/86
1024 x 8- or 512 x 16-bit organization (93C76) CLK 2 7 PE
2048 x 8- or 1024 x 16-bit organization (93C86) 3 6 ORG
DI
• Self-timed ERASE and WRITE cycles DO 4 5 VSS
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry SOIC Package
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
1 8
VCC
93C76/86
• Sequential READ function CS
CLK 2 7 PE
• 10,000,000 ERASE/WRITE cycles guaranteed
DI 3 6 ORG
• Data retention > 200 years
DO 4 5 VSS
• 8-pin PDIP/SOIC package
• Temperature ranges supported
- Commercial (C): 0°C to +70°C BLOCK DIAGRAM
- Industrial -40°C to +85°C
- Automotive (E) -40°C to +125°C
VCC VSS
DESCRIPTION
Memory Address
The Microchip Technology Inc. 93C76/86 are 8K and
Array Decoder
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power Address
non-volatile memory applications. These devices also Counter
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93C76/86 is available in standard 8-pin DIP and 8- Data Output
Register Buffer
DO
pin surface mount SOIC packages.
DI
Mode
PE Decode
CS Logic
Clock
CLK
Generator
VCC ...................................................................................7.0V
VHI = Vcc - 0.2V (Note 1)
All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V VHI = 4.0V for (Note 2)
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C Timing Measurement Reference Level
ESD protection on all pins................................................4 kV Input 0.5 VCC
*Notice: Stresses above those listed under “Maximum ratings” Output 0.5 VCC
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
Note 1: For VCC ≤ 4.0V
other conditions above those indicated in the operational listings 2: For VCC > 4.0V
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
ORG Memory Configuration
PE Program Enable
VCC Power Supply
Req. CLK
Instruction SB Opcode Address Data In Data Out
Cycles
READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22
EWEN 1 00 1 1 X X X X X X X X X — High-Z 14
ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14
ERAL 1 00 1 0 X X X X X X X X X — (RDY/BSY) 14
WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22
WRAL 1 00 0 1 X X X X X X X X X D7 - D0 (RDY/BSY) 22
EWDS 1 00 0 0 X X X X X X X X X — High-Z 14
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.
CLK
DI 1 1 0 AN ... A0
CLK
DI 1 0 0 1 1 X ... X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
CLK
DI 1 0 0 0 0 X ... X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’S
CS STANDBY
CLK
DI 1 0 1 AN ... A0 DN ... D0
TCZ
HIGH IMPEDANCE
DO BUSY READY
TWC
CS STANDBY
CLK
DI 1 0 0 0 1 X ... X DN ... D0
TCZ
HIGH IMPEDANCE BUSY READY
DO
ORG=VCC, 8 X’s
TWL
ORG=VSS, 9 X’s Guarantee at Vcc = +4.5V to +5.5V.
CS STANDBY
CLK
DI 1 1 1 AN ... ... A0
TCZ
HIGH IMPEDANCE
DO BUSY READY
TWC
CS STANDBY
CLK
DI 1 0 0 1 0 X ... X
TCZ
HIGH IMPEDANCE
DO BUSY READY
TEC
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s Guarantee at VCC = +4.5V to +5.5V.
4.0 PIN DESCRIPTIONS Table 1-7 for more details). CLK and DI then become
don't care inputs waiting for a new start condition to be
4.1 Chip Select (CS) detected.
93C76/86 – \P
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead