Lecture ESD 40
Lecture ESD 40
Lecture ESD 40
to nano-metric ASICs
Manoj Sachdev
University of Waterloo
[email protected]
September 2007
1
Outline
Group Introduction
ESD Basics
Basic ESD Protection Circuits
Nano-metric ESD Challenge
ESD circuits for nano-metric regime
2
Group Introduction
5 PhDs, 2 masters and
2 PDFs
Applied, industrially
driven research
Generous funding levels
Core strengths in circuit
design, testing, quality
and reliability
3
Group: Low Power Research
Driven by low power signal
processing & bio-implantable
applications
Research focus
Active power reduction, clocking
strategies
Dynamic voltage scaling
architecture for portable app.
Leakage power reduction:
Investigation of RBB effectiveness
with scaling 4
Group: High Performance Circuits
Driven by high speed
arithmetic circuits (Adders,
register files, ALU), and CDRs
Research focus
To build timing diagnostics into
multi-GHz ALUs
Leakage and active power
reduction
Clock de-skewing
Thermal issues in high
performance circuits 5
Group: Memory Research
Driven by embedded SRAMs
and Soft Error Robustness
Research Focus
SRAM cell stability & ckt
techniques for detection
Low power embedded SRAMs
Soft Error Robust memories &
flip-flops
Error Correction Circuit’s for
soft error mitigation
6
Group: ESD Research
Driven by reducing chip failures
due to ESD
Research Focus
ESD strategies for multiple supply
domains
ESD protection circuits for High
speed I/Os
Fast response ESD protection
circuits
7
Outline
Group Introduction
ESD Basics
Basic ESD Protection Circuits
Nano-metric ESD Challenge
ESD circuits for nano-metric regime
8
ESD Basics :Motivation
10
Human Body Model (HBM)
R A B Rb=1.5k
V
DUT
Cb=100pF
V
DUT
200pF
V DUT
Cap
VDD VDD
VESD VESD
VSS VSS
15
Zapping Modes
Positive ESD with Negative ESD with
respect to VDD respect to VDD
(PD-mode) (ND-mode)
VDD VDD
VESD VESD
VSS VSS
16
HBM / MM / CDM Testers
HBM/MM/CDM testers apply
ESD stress to the DUT
Magnitude/polarity of the stress
set by the user
Test can be destructive
Results in pass or fail
19
ESD Protection Methods
Snapback-based Non-snapback-based
Turn on before oxide Trigger and conduct during
breakdown the whole ESD event
Minimum parasitics Do not trigger under
normal power-up
20
Diode Under ESD Conditions
Forward biased:
Low trigger voltage
Low on resistance
Reverse biased:
High trigger voltage
High on resistance
21
MOS Under ESD Conditions
Has a parasitic bipolar transistor
Avalanche breakdown gives Igen and Isub
When Vbase = 0.7V, npn turns on Æ Snapback
When I(drain) = It2 , npn can be destroyed
Drain
n+ Igen n+
Vbase Isub
Rsub
p-sub 22
Snapback Protection: MOSFET
MOSFET is used in
Grounded- Gate VDD
PAD
configuration
(GGNMOS)
PreDriver
23
ESD Protection Wish List
Vt1 < Oxide breakdown
To trigger NMOS before oxide breaks down
Vt2 > Vt1
To ensure uniform triggering of all fingers
Vh > VDD
To enhance latch-up immunity (VDD + 10%)
It2 as high as possible
Increase current carrying capability Æ ↑ESD
VDD
Anode PAD
PreDriver
n+ p+ n+ p+ I/O
PAD
n-well p+
n-
PreDriver
p-
n+
VSS
p-sub PAD
ESD Protection Buffer stage
Device
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SCR Characteristic
Avalanche breakdown of nwell-psub ↑ IRnwell and IRpsub
When VBE reaches 0.7V, npn (or pnp) turns on
Positive feedback turns on the pnp (or npn) Æ Snapback
Anode
I(anode)
Rn-well
(Vt2, It2)
(Vh, Ih)
(Vt1, It1)
Rp-sub
V(anode)
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ESD Devices: Comparison
Protection level:
SCR and FB diode are the
best
Trigger voltage:
FB Diode is too low
NMOS is the best
SCR should be modified
Holding voltage:
NMOS is ok
SCR should be modified
Figure of merit
Protection level/Capacitance
27
Non-Snapback Protection: Clamps
ESD event Æ V(1) rises
turning on M0
RCCC + inverters should
keep M0 “on” to discharge
all ESD energy
Advantages ESD event:
Protect against different tr: between 100ps and 60ns
zapping conditions duration: up to 1μs
Regular power-up:
Disadvantages
In millisecond range
Can turn on during normal
Hot plug app. power-up
power-up
as low as 1μs
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Outline
Group Introduction
ESD Basics
Basic ESD Protection Circuits
Nano-metric ESD Challenge
ESD circuits for nano-metric regime
29
Challenges with Scaling
2
0
-2
-4
-6
0 20 40 60 80 100 120
Time (ns)
33
Outline
Group Introduction
ESD Basics
Basic ESD Protection Circuits
Nano-metric ESD Challenge
ESD circuits for nano-metric regime
34
Strategy – Device Simulation
MOS models, circuit simulators are not designed
to handle snapback behavior
ESD circuits are designed with device simulators
(Medici and Sequoia)
Device cross section is created in the simulator
Quasi-DC simulation predicts DC characteristic, i.e. Vt1
and Vh
It2 is estimated using thermal simulation and monitoring
maximum temperature of the ESD protection device
35
Design Steps
1. Calibrate the device simulator with the
desired technology
Junction depth and substrate doping are
available from technology documents
2. Verify the technology model by simulating a
MOS transistor
Trial and error is used to achieve the typical
I(on), Vth, current gain and
3. Draw the cross-section of the ESD device
36
Design Example #1 – LVTSCR
p-type
n-type
contact
oxide
(Vh, Ih)
(Vt1, It1)
38
V(anode)
Gate-Coupling
↑Vgs Æ ↑Isub Æ npn triggers faster Æ ↓Vt1
For higher Vgs (strong inversion region): impact
ionization is decreased Æ Vt1 increases
4.8
4.6
4.4
Vt1 (V)
4.2
3.8
3.6
3.4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
39
V(Gate) (V)
Substrate Triggering
↑Vsub Æ Transistor triggers with lower ↓Vt1
Drain
4.5
4
+ +
n n Vt1 (V)
3.5
3
p-sub
2.5
Sub 2
0 0.25 0.5 0.75 1 1.25 1.5
V(Sub) (V)
40
GST-LVTSCR
SCR is modified by adding a
gate electrode to reduce Vt1
(LVTSCR)
MG provides gate triggering
Can be as small as 5μm
MS provides substrate
triggering
Simulation results
Vt1 reduces from 12V to 4.85V
41
Semenov et. al., Microelectronics Reliability, 2005
GST-LVTSCR (Measurement)
GST-LVTSCR was
fabricated in 0.13μm
Leakage (A)
HBM measurements
TLP I-V
5.00E-01 TLP Leakage
42
Example #2 – Increasing Vh
Anode
In holding region both Q1 and I1
Rn-well
Q2 are in saturation
Q1
SCR
Q2
Vh= VEB1+ VCE2(sat)
Rp-sub
High Vh SCR (RE is added) RE I2
Cathode
Vh = VEB1+ VCE(sat) + REI1 Anode RE Cathode
Vh = VEB1 + VCE(sat)+ VEB1RE/Rn-well
RE↑ → Vh↑ n+ p+ n+ p+
n-well
p-sub
Semenov et. al., ISQED, 2004 43
Increasing Holding Voltage
V(anode) (V)
Simulation results
0 5 10 15 20 25
1
Vh is increased without an
0.0001
increase in Vt1 Log I(anode) (A) 1E-06
1E-12
LVTSCR 1.20E-01
LVTSCR
1.00E-01 HighVhDiode
2.00E-02
0.00E+00
0 1 2 3 4 5 6
447 8
V(anode) (V)
Example #3 – ESD Clamps
CC M1 M4
1 2 3
M0
RC M2 M3 R1
VSS
4
turns off after 1μs
Voltage (V)
3
1
is less than 6V 0
-1
0E+0 3E-7 5E-7 8E-7 1E-6 1E-6 2E-6
Time (s)
47
Device-Level Simulation
Device simulation is
done with Sequoia
Peak temperature is in
transistor M0
During a 2kV HBM
stress Tmax of the clamp
is 375K
Hot-spot is in the gate-
drain boundary
48
Measurements
Clamp was fabricated in
0.18μm technology Log Leakage (A)
1E-09 0.0000001 0.00001 0.001 0.1 10
Current (A)
1.5
TLP test 1
Second breakdown 0
TLP Leakage
current is 1.8A 0 5
Voltage (V)
10 15
49
Example #4 – CML Driver Design
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Measured Results
5000
3000
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Acknowledgement
Help of Hossein Sarbishaei, Sumanjit
Singh, and Oleg Semenov is greatly
appreciated for this presentation
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