Power Artist Ref

PowerArtist 1
2
Reference Manual 3
Software Release 2011.1.3
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PowerArtist™ Reference Manual
Table of Contents
CHAPTER 1 Energy and Power Analysis

Introduction ................................................................................................................. 1
Energy and Power Fundamentals............................................................................... 1
Definitions......................................................................................................... 1
Dynamic Power ................................................................................................ 2
Static Power ..................................................................................................... 4
Sample Calculation ..................................................................................................... 5
Power Component Hierarchy ...................................................................................... 6
Dynamic Power Component............................................................................. 7
Static Power Component.................................................................................. 8
CHAPTER 2 Internals
Introduction ................................................................................................................. 9
Chapter Organization ....................................................................................... 9
Transition Counting on Nets........................................................................................ 9
Activity Calculation .................................................................................................... 11
Duty Cycle Calculation .............................................................................................. 11
Micro-Architectural Inferencing ................................................................................. 13
Default Transition Time Calculator............................................................................ 15
CHAPTER 3 Command Reference

Introduction ............................................................................................................... 17
Power Analysis Engines................................................................................. 17
Tcl Command Wild Carding ........................................................................... 18
Accessing Command-Line Help ..................................................................... 18
Getting Extended Names from Alias Names.................................................. 19
Chapter Organization ..................................................................................... 20
Alphabetical List of PowerArtist Command File Commands ..................................... 21
Alphabetical List of pt_set Variables ....................................................................... 144
Open Access Database Access Utilities ................................................................. 199
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CONTENTS PowerArtist™ Reference Manual iv
Design Navigation Utilities............................................................................ 199

Netlist Traversal Utilities............................................................................... 203
Design Query Utilities................................................................................... 207
Analysis Reporting Utilities........................................................................... 219
Reduction Reporting Utilities ........................................................................ 227
Power Database Mapping Utilities ............................................................... 230
Legacy Flow OpenAccess Database Tcl API Commands ...................................... 233
Additional Utilities.................................................................................................... 245
CHAPTER 4 File Formats

Introduction ............................................................................................................. 259
Chapter Organization ................................................................................... 259
Net Name Matching for External Files.......................................................... 259
Capacitance File Format ......................................................................................... 260
Transition Time File Format .................................................................................... 261
Sequence Library Defaults File Format................................................................... 262
Escaping Library Names .............................................................................. 262
Specifying Default Cells ............................................................................... 262
SPEF File Format.................................................................................................... 263
Etcl File Format ....................................................................................................... 264
Sample Etcl File ........................................................................................... 265
Mode File Format .................................................................................................... 266
Global Activity File Format ...................................................................................... 268
Auxiliary GAF File ................................................................................................... 269
Verilog Startup File Format ..................................................................................... 271
Vectorless Activity File Format................................................................................ 272
ptSourceFiles.tcl File Format .................................................................................. 273
PowerArtist Configuration Files............................................................................... 275
VCDe File Format ................................................................................................... 276
VCDe Format Definition ............................................................................... 276
VCDe Interface Definition............................................................................. 277
Example ....................................................................................................... 277
CHAPTER 5 PowerArtist Error Messages

Introduction ............................................................................................................. 279
Critical Messages ......................................................................................... 280
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CONTENTS PowerArtist™ Reference Manual v
CHAPTER 6 Advanced Usage Tips

Using LSF ............................................................................................................... 283
APPENDIX A Supported Sys. Verilog, Verilog 2001 & VHDL Constructs

SystemVerilog Support ........................................................................................... 286
Verilog 2001 and VHDL Support............................................................................. 288
APPENDIX B Listing of Commands, Variables and Utilities
INDEX.....................................................................................................................................................293
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CONTENTS PowerArtist™ Reference Manual vi
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1
Chapter 1
Energy and Power Analysis 1
Introduction
This chapter describes important concepts related to estimating power. It also
provides details of the internal calculations performed during power analysis. This
information can help you gain a deeper understanding of analysis results. The
following description applies to all PowerArtist tools.
Energy and Power Fundamentals
Definitions
Energy is the work required to move charge through a voltage, therefore
E = QV
Equation 1
where E is energy (in joules), Q is charge (in coulombs), and V is voltage (in volts).
Power is energy per second, so
E
P =
T
Equation 2
where P is power (in watts) and t is time (in seconds).
Total power can be divided into two components: dynamic power and static power.
Each is described in more detail in the following sections.
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CHAPTER 1 — Energy and Power Analysis PowerArtist™ Reference Manual 2
Dynamic Power
Consider the circuit shown in Figure 1, which is a simple model of the charging and
discharging of circuit capacitance.
Figure 1 Simple Circuit Capacitance
Although this derivation may be unfamiliar to you, it provides the best approach for
understanding the energy drawn from the power supply; it provides the exact answer
without having to make any approximations. Using Equation 1, the energy drawn
from the pulse generator to charge the capacitor to a voltage V is
E = QV = (CV)V = CV2
Equation 3
The energy drawn from the pulse generator while the capacitor is discharging is
zero, so during one pulse cycle the energy drawn from the generator is
E = CV2
Equation 4
Notice that this equation is similar to the equation for energy stored on a capacitor:
1
E = — CV2
2
Equation 5
Effectively, half of the energy supplied by the pulse generator is dissipated in
charging the capacitor. The other half, which is stored on the capacitor, will be
dissipated when it is discharged.
From Equation 2, the power consumed over the pulse cycle, tp, is
CV2
P = ——
tp
Equation 6
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This is the dynamic power associated with charging and discharging a capacitance.
If the pulses continue at a frequency, f, the dynamic power can be written as
P = CV2f
Equation 7
Equation 7 is the common equation for dynamic power. The f in this equation usually
represents the clock frequency. In calculating dynamic power for a complex device, it
is useful to relate nodes that are not toggling at a regular rate to the clock frequency.
Consider a node that toggles N times over an interval T. We know that
Number of Cycles
Frequency =
Time
Equation 8
Also because one cycle is equivalent to two transitions of the signal you have
N
Number of Cycles = —
2
Equation 9
You could write the effective frequency of the signal as
N 1
feff = — —
2 T
Equation 10
To relate this to the clock frequency, note that during the same interval T, there are
Kclk clock cycles where
T
Kclk =
tclk
Equation 11
Substituting for T and tclk (= 1 / fclk) in the equation for feff you get
N fclk αfclk
feff = =
Kclk 2 2
Equation 12
where α is called the activity factor and is the expected number of transitions per
clock cycle. If fclk is the highest clock frequency in the design, then α is a real
number with a value between 0 and 2. Substituting into Equation 7, you get
CV 2 αfclk
P =
2
Equation 13
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You can now draw some important conclusions about the relationship between
energy and power from Equation 4 and Equation 13. Equation 4 says that if you
were to charge and discharge a capacitor N times, the energy (NCV2) required to do
so is independent of the period over which you do it. On the other hand, Equation 13
says that more power is consumed if the capacitor is toggled N times in a shorter
period.
Static Power
Figure 2 shows a circuit that is a simple model of static (or DC) power drawn from a
DC source.
DC
Figure 2 Simple Static Circuit
Referring to Equation 1, you can substitute for the charge, Q = It, to obtain
E = IVt
Equation 14
The power is easily found from Equation 2
E
P = = IV
t
Equation 15
which is the common equation for DC power.
In contrast to dynamic power and energy, you can conclude from these equations
that static energy is time dependent, while static power is time independent.
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Sample Calculation
Sample Calculation
As an example, consider a device with both dynamic and static components. The
dynamic power is consumed in the charging and discharging of a 2pF capacitor with
a 15MHz clock. The static power is consumed by a 1mA DC current source. The
power supply voltage is 5.25 volts and the simulated time period is 400ms.
You can calculate the total power directly using Equation 13 and Equation 15,
therefore you have
CV 2 αfclk
Ptotal = + IV
2
Equation 16
The activity factor α is 2. Because there are two transitions per cycle of fclk, you can
write
Ptotal = (2 •10-12 • 5.252 • 2 • 15 •106 / 2) + (1 • 10-3 • 5.25)

= 8.27 •10-4 + 5.25 • 10-3
= 6.08mW
Equation 17
You can check this solution by calculating the energy consumed. The dynamic
energy is consumed by charging and discharging the capacitor over a period 400ms
at a rate of 15 MHz. This is equivalent to 6 million charging and discharging cycles.
The static energy is consumed by the DC current flow for 400ms. The total energy
then is
Etotal = Edyn + Est

= CV2N + IVt
= (2 • 10-12 • (5.25)2 • 6 • 106) + (1 • 10-3 • 5.25 • 0.4)
= 3.31 • 10-4 + 2.1 • 10-3
= 2.431mJ
Equation 18
Using Equation 2 to obtain the total power, you get the following:
2.431mJ
Ptotal = = 6.08mW
400ms
Equation 19
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Power Component Hierarchy

PowerArtist computes power dissipation using the following equation:
Ptotal = Pdynamic + Pstatic

= (Pdyn_cells + Pdyn_loads) + (Pstatic_current + Pstatic_state)
Equation 20
Where... Is...
Pdyn_cells The sum of the dynamic internal power consumed by all cells.
Pdyn_loads The sum of the power consumed in charging all of the nodal capacitances.
Pstatic_current The sum of the static (state-independent) power consumed by all cells.
Pstatic_state The sum of the state-dependent static power consumed by all cells.
Dynamic power represents energy dissipated during toggle events. There are two
contributions to dynamic power:
1. Cell dynamic power (Pdyn_cells) represents the energy consumed internal to the
cell whenever one of its internal nodes changes state. There are primarily two
effects to consider:
a. The charging and discharging of capacitance within the cell.
b. The crowbar currents that flow from VDD to VSS whenever an internal node
switches.
2. Net, or load, dynamic power (Pdyn_loads) is a measure of energy consumed driving
the output net(s) of a cell to a new logic level. It accounts for the charging and
discharging of capacitances external to the cell, which include:
a. The net’s wire capacitance.
b. Parasitic capacitance of pins on the net.
Static power represents energy consumption due to a flow of current from VDD to
VSS when the cell is not switching (that is, no logical events occur). Static power
could be state dependent, that is, the energy consumption could change depending
on logical states of the cell’s inputs and internal nodes. There are two physical
effects that cause static power dissipation:
1. Through currents, which are a direct result of transistor-level design styles such as
analog and pseudo-NMOS styles. Through currents can be avoided by using fully
complementary CMOS structures.
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2. Leakage currents, which are due to sub-threshold and reverse biased junction
currents. These are usually in the Pico-Amp to Nano-Amp range, depending on
circuit size, but can be higher for low threshold voltage processes.
Dynamic Power Component

With regard to the equation discussed in the previous section, Pdyn_cells + Pdyn_loads
is calculated by first analyzing power dissipating events for each library cell
instantiated in a netlist. Such events are represented by power and energy model
features of the Liberty library format. The number of such events during the entire
time of analysis is obtained.
The capacitive load for an output pin is determined by summing up the input pin
capacitances (obtained from the gate-level library) and wiring capacitance. Wiring
capacitance is either estimated based on vendor-supplied wire load models or
back-annotated using a load capacitance file. Then, based on the calculated total
load capacitance, a corresponding power dissipation value is obtained from the
power model of the cell.
The accuracy of power analysis depends on how well these effects are modeled.
PowerArtist accounts for the following dynamic power dissipation effects:
 Internal cell capacitive and short-circuit power caused by the charging and
discharging of nodes internal to a cell (the clock buffers in a sequential cell, for
example). Capacitive power is consumed when a current flows to or from a
capacitive load. Short-circuit power on the other hand is consumed when a direct
path between VDD and GND is momentarily established while the cell is
transitioning between states. Internal dynamic cell power is a significant source of
power dissipation in static CMOS circuits (especially in sequential cells, which
have relatively large amounts of internal capacitive loading).
 Dependency of internal cell power on input ramptime and output load. The short-
circuit component of internal cell power varies significantly with changes in the
slope of the input transition, as well as the output load the cell is driving. Both of
these parameters affect the amount of time the open VDD/GND path exists in the
cell.
 External capacitive power. Power dissipation caused by the charging and
discharging of nets and parasitic capacitive loads on the nets is also significant in
static CMOS circuits.
 Partial-voltage swing output power. For most drivers, the voltage swing on the on
the output pin is between VDD and GND. However, in some situations, the voltage
swing may be limited to less than this. This is the case with some high-speed
CMOS I/O families.
 Three-state bus power. When a three-state bus changes logical states, it is
important to know which driver caused the change to accurately compute the
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capacitive power dissipation for that event. This prevents over-counting or under-
counting of power due to three-state bus events.
The power dissipation attributable to every power dissipating event, as specified in a
gate-level library, is then multiplied by the number of times the event occurs during
simulation (as determined by analyzing the simulation results), to calculate the
energy attributable to that power dissipating event over the course of the simulation.
Static Power Component

Pstatic_current is calculated by multiplying the static current specified for each cell by
VDD for that cell, and summing for all cells in the design.
Pstatic_state is a little more complicated, because it requires a knowledge of the
amount of time that the cell spent in a particular state. That information is collected
during simulation and used for the power analysis. Static power dissipation of the cell
for a particular state is normalized to the amount of time that the cell spent in the
state. Cells that do not spend any time in a static-power-consuming state do not
incur any state-dependent static power. (They still incur static power due to state-
independent static current.)
The accuracy of power analysis depends on how well these effects are modeled.
PowerArtist accounts for the following static power dissipation effects:
 State-independent cell power. This arises in analog circuit blocks (PLL, for
example) and in CMOS leakage currents (which in most cases are small enough
that they do not need to be modeled).
 State-dependent cell static power. Unlike dynamic power, state-dependent static
power is consumed whenever the cell is in a certain logic state rather than when
the cell makes a logic transition. This is important for modeling power in I/O pads,
cells with passive pull-up/pull-down components, and certain precharge or
dynamic-logic style cells.
 Static power dissipation in I/O pads with external terminations. While static power
dissipation of internal chip cells is determined entirely by the logic conditions and
electrical parameters inside the chip, power dissipation of externally terminated I/
O pads will depend on the values of termination voltage and optional pull
resistors.
PowerArtist is capable of modeling all power dissipation effects discussed above. For
highest accuracy, a library power model should include these effects. Effects such as
leakage power, which may result in insignificant contribution to power dissipation,
may be optionally omitted for higher analysis performance.
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9
Chapter 2
Internals 2
Introduction
This chapter provides details on some of PowerArtist’s internal processes and
algorithms and provides information on the different methods you can use to control
them.
Chapter Organization
The following subjects are covered in this chapter:
 Transition Counting on Nets
 Activity Calculation
 Micro-Architectural Inferencing
 Default Transition Time Calculator
Transition Counting on Nets

The following table documents how the GAF creation process counts transitions on
nets, by default, when unknown or high-impedance conditions are detected.
Table 1 How GAF Creation Counts Transitions
Transition Action
X -> 0 Counts as a transition
X -> 1 Counts as a transition
0 -> X Does not count as a transition
1 -> X Does not count as a transition
0 -> Z Does not count as a transition
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CHAPTER 2 — Internals PowerArtist™ Reference Manual 10
Transition Counting on Nets
Table 1 How GAF Creation Counts Transitions
Transition Action
1 -> Z Does not count as a transition
Z -> 0 Counts as a transition
Z -> 1 Counts as a transition
If you use the -ignore_toggles_through_x option to CalculatePower, transitions to the

X state are not taken into consideration. For example, the transition sequence
0X0 does not count as a transition. However, the transition 0X1 is counted
as a transition.
For example, you can use the -ignore_toggles_through_x option if you have
simulation models that deliberately force X’s onto bus lines to indicate that the data
on the bus line is invalid for some period of time.
The power of an RTL instance is estimated based on cumulative toggle count on
each of the nets connected to the instance and, generally, their duty cycle. Any
transition to state X (or Z) is not counted. Transitions from X1 or X0 are counted
as full transitions. The same applies for transitions from Z0 and Z1. Effectively,
on average PowerArtist counts 50% of the toggles.
Time spent in the X state is split evenly between states 1 and 0; therefore, a net that
spent the entire simulation in state X will have a duty cycle of 0.5. So too will a net
that spent 1/3 of its time in state 1, also have spent 1/3 in 0 and 1/3 in X. RTL power
analysis, therefore, can be said to treat X states as 1/2 in state 0 and 1/2 in state 1.
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Activity Calculation
Activity Calculation
The term “activity” as it refers to a net can be defined as the ratio of the frequency of
a net to the clock frequency. Activity is calculated by taking the total toggles on a net,
dividing them by the total toggles on the clock net for the same time and multiplying
that number by 2. The activity of a group of nets is the average of the activities of all
the named nets in the group. For example, if Activity(net1) = .5 and Activity(net2) =
.75, the average will be 1.25/2 = .625.
If you are performing vector analysis, each group will have average activity values as
a function of time. The average activity value is computed by calculating the activity
value for all nets in that group from your simulation data and computing their average
value. The nets include ports of modules as well as local nets. Remember, a group is
not only a module but all children instantiations of the module.
Duty Cycle Calculation

The GAF creation process run by the CalculatePower command performs duty cycle
calculation for PowerArtist. This section describes the details of how that calculation
is performed. Duty cycle is defined as follows:
duty_cycle = T1 / (T1+T0)
where T1 = the total time in which the signal remains in the 1 state, T0 = the total
time in which the signal remains in the 0 state. In case of X/Z values, PowerArtist
needs to determine whether this value (X/Z) should be considered as a 0 or 1.
The way in which the value (0 or 1) of X/Z is determined depends on where the X
comes with respect to the value change:
 X comes at the end of the value change.
If the signal’s last value change is X/Z then we assume that half the time the
signal was in the 1 state and half the time the signal was in the 0 state. That’s why
if a signal’s initial value is X and it never changes its value, then GAF creation
outputs .5 as its duty cycle.
 X comes at the beginning or in the middle of a value change sequence.
If there are further value changes of a signal after the X state, PowerArtist
assumes that X is the opposite of the new value.
That is:
if X-->1 then X is 0 here
if X-->0 then X is 1 here
Based on these two assumptions PowerArtist calculates the duty cycle.
Consider the following example taken from a VCD file.
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Duty Cycle Calculation
Value Changes of a Signal with Tag '-'

#0
0-
#25
1-
#55
x-
#95
1-
#135
x-
#155
0 state -- 25ns ( 25 -0 )
1 state -- 30ns ( 55 -25 )
x state -- 40ns ( 95 - 55 )
1 state -- 40ns ( 135 - 90 )
x state -- 20ns ( 155 - 135 )
Here, there are two X value changes. PowerArtist needs to determine whether to
consider them as '0' or '1'.
 The first x (55-95) falls in the second case, that is, there are value changes after x;
therefore, x is assumed to be the opposite of its new value(1), which is 0.
 The second x (135-155) falls in the first case, that is, x is the last value change;
therefore, GAF creation assumes that half the time (20/2 = 10) the signal was in
the 1 state and the remaining time it was in the 0 state.
Given the values in this example, the duty cycle is calculated as:
T0 = 25 + 40 (1st X will be 0 now) + 10 (half of 20) == 75
T1 = 30 + 40 + 10 (half of 20) == 80
duty_cycle = 80/ (80+75) == .516129
If you specified the “-forced_x 0” option to the CalculatePower command that forces
X to be 0, the calculation will be as follows:
T0 = 25 + 40 + 20 = 85
T1 = 30 + 40 = 70
duty_cycle = 70/155 = .4516
Similarly, you can also use the “-forced_x 1” option to the CalculatePower command
to change the duty cycle.
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Micro-Architectural Inferencing
The first step in the power analysis process is for the language compilers to analyze
your HDL design and perform “micro-architectural inferencing”. This step, performed
by the Elaborate command), creates the scenario (.scn) file. Micro-architectural
inferencing is a high-level inferencing step where RTL, block-level components are
extracted from your HDL design.
For example, it is during this step that sequential elements (for example, registers
and latches), instantiated elements (for example, IO cells and memories), data path
elements (for example, adders and multipliers) and control logic (for example,
decoders and multiplexors) are extracted from your code. These then become the
elements that the analyzers use during their power calculations.
HDL code can be structural, behavioral, or mixed. The language compilers perform
inferencing on the behavioral portions of your code. In general, language compilation
operates as follows:
1. Your HDL source is located and parsed into an intermediate representation.
2. For each module (Verilog) or entity (VHDL) in your design, the language compiler
checks if it matches a cell in the library file. If a match is found, no further
processing is performed on the HDL code that defines the module or entity. If a
match is not found, then the language compilation is performed on the HDL code
representing the module or entity.
When the language compilers encounter RTL HDL code (as opposed to structural
instantiations), they infer RTL block-level components which effectively become
another level in your design hierarchy. This process is much like when you perform
gate-level synthesis on your design. However, rather than synthesizing to the gate
level, the compilers synthesize to parameterized higher-level components like n-bit
adders because as noted earlier, the Apache models support multiple input and
output bits.
This parameterization is also true for sequential and control logic inferred modules.
You can recognize these elements because they have “module type names” like
#adder# or #mux21#. The 18 component types that are inferenced are the 14
primitive components (register, latch, adder, multiplier, 2-1 mux, tri state, buffer,
inverter, and, nand, or, nor, xor and xnor) and the 4 macro components (register file,
latchfile, unencoded mux, and decoder). The 4 macro components are modelled as
interconnections of one or more of the 14 primitive components. The inferencing step
follows standard synthesis guidelines and rules established by the many EDA
vendors who perform gate-level synthesis for gate-level simulation and place and
route.
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The following Verilog and VHDL code fragments perform identical operations.
Verilog
module a(out, clk, reset, in1, in2);
output [2:0] out;
input clk, reset;
input [1:0] in1, in2;
always @(posedge clk or posedge reset)
if (reset)
out = 0;
else
out = in1+in2;
endmodule
VHDL
entity a is
port (out: in std_logic_vector(2 downto 0);
clk, reset: in bit;
in1, in2: std_logic_vector(1 downto 0));
end a;
architecture trial of a is
begin
process (clk, reset) begin
if reset = '1' then
out <= '0';
elsif clk' event and clk = '1'
out <= in1+in2;
end if;
end process;
end trial;
This generates two new sub-modules, #1 and #2.

 #1 is due to the addition operator, is inferred as a 2-bit-wide ripple carry adder
(adder_rip) and has a module type name of #adder#.
 #2 is a 3-bit-wide d flip flop due to the assignment statement, is inferred as a
register, has a module type name of #register#, and has clk as its clock and reset
as the asynchronous reset.
These two elements are interconnected in the netlist.
Once the language compiler completes micro-architectural inferencing, the scenario
file contains a complete interconnected netlist consisting of inferred modules. The
next step maps inferred elements to their corresponding Apache models and
instantiated elements to library file entries. If there are multiple Apache models
representing different micro-architectures, for instance ripple versus carry lookahead
adders, the architecture that takes the least space on the die will be chosen.
The final step occurs during power analysis. Apache power models are technology
independent. The inferenced components must be mapped onto a particular target
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Default Transition Time Calculator
technology specified by your power library files. The mapping process involves
selecting representative libraries cells for the 14 primitive components.
For default cell selection, you have the choice of either explicitly specifying default
cells in an SLD file or allowing PowerArtist to automatically select the default cells
(preferred). If you specify default cells in the SLD, for each default cell type, you
have to choose one cell name from the power library file that would have the highest
probability of being the cell chosen by your synthesis tool. This cell can then be used
during all calculations that require that cell type.
As previously mentioned, it is recommended that you allow PowerArtist to
automatically select default cells. This method is available for Liberty libraries. During
automatic selection, for each inferred instance, PowerArtist examines the projected
capacitive loading on the instance and searches the power library files for cells
whose power models best fit this particular inferred instance. While a register directly
maps to a flop in a power library file, an n-bit wide ripple carry adder would require
full adder, exclusive-or, nand, and inverter cells. PowerArtist examines the function
statement of each cell in the power library and determines if it matches one of the
primitive components. If it matches, and if it also contains a slew and delay model, it
becomes a candidate for use during power analysis. If the cell function statement is
complex, PowerArtist might not recognize it as one of the default cell types.
Also, with the change of wire load model, the load being driven by the inferred
sequential/combinational logic may change significantly (increase or decrease),
which could result in a difference in the kind of default cells being selected. A
difference in the selection of default cells will result in difference in leakage power.
Consequently, leakage power for a particular design will vary with the selected wire
load model.

PowerArtist determines the default transition time based on different factors.
 the setting of the -default_transition_time command option
 the presence of an SLD file with the DefaultTransitionTime parameter set
If you do not specify a default transition time using the CalculatePower/ReducePower
-default_transition_time option, and you do not have an SLD file with
DefaultTransitionTime specified, PowerArtist will calculate the optimal default
transition time, using the following internal process:
1. It calculates the smallest typical load, which is the average of the pin caps of a
standard single-drive, 2-input, NAND gate.
2. It then calculates the default slew as the average cell slew of a low-range default
inverter plus the average cell slew of a mid-range default inverter divided by two
or, basically:
(avgCellSlewOfLowRangeDfltInv + avgCellSlewOfMidRangeDfltInv) / 2
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The average slew of a cell is calculated using transition tables, of which there may
be up to four—a rise and fall table for each input. These tables are indexed by
input transition time and capacitance.
3. For each transition table, PowerArtist selects a middle value for the input transition
time, and uses the capacitance value calculated in step 1 (that is, the smallest
typical load) to find the output transition time. It then averages the output transition
times found in each of the tables.
4. Using the average value found in step 3 as the input transition time for the
transition tables, PowerArtist repeats step 3. This should cause the transition
times to converge to a single value.
If you have an SLD file that provides the default cell information, and that same SLD
file has the DefaultTransitionTime parameter set, then the value of that parameter is
used by PowerArtist. If you provide an SLD file that does not have the
DefaultTransitionTime set, the default transition time is calculated based on the
default inverter in the SLD file using the algorithm described in the previous
paragraph. The one difference in this case is that the typical load is considered to be
four times (4x) the input capacitance of the inverter.
PowerArtist allows you to specify cells you do not want to be selected as default cells
using the SetAttribute command to define cells that should not be used during
default cell selection.
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17
Chapter 3
Command Reference 3
Introduction
This chapter describes all of the commands accepted in the PowerArtist command
file including the pt_set variables. These commands and variables control the
different power analysis and reduction engines that comprise the PowerArtist
software. The one you choose will depend on the type of analysis you are
performing.
Power Analysis Engines

PowerArtist consists of several different analyzers (engines). The one you use will
depends on the type of power analysis or reduction you are performing. The
following table describes the available analyzers. The commands in this chapter
control the analyzers.
Table 2 Analysis Engines
Analyzer Description
Time-Based (Peak)  Time-based analyzer (CalculatePower -analysis_type time_based)

In the PowerCanvas, select Tools > Time Based Power
Analysis.
Use this for power gating and power-over-time exploration. This is
enabled through the Time-Based Power Analysis wizard in the GUI.
This analyzer provides power over time waveforms and outputs
average and maximum power numbers. It has the following
advantages of the average power analyzer:
• It is 2-3X faster.
• It has far smaller capacity requirements.
• It does not require you to monitor ports of library elements.
The disadvantage of this engine is that it has fewer power reporting
options than the average power calculator has for reporting average
power.
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CHAPTER 3 — Command Reference PowerArtist™ Reference Manual 18
Table 2 Analysis Engines
Analyzer Description
Average Power  Average power analyzer (CalculatePower -analysis_type average)

In the PowerCanvas, select Tools > Average Power Analysis.
 Vectorless average power analyzer (CalculatePower -analysis_type
average -vectorless_input_file
RTL Reduction  Power reduction engine (ReducePower)

In the PowerCanvas, select Tools > Power Reduction Analysis.
Review the results of this engine in the PowerCanvas.
Tcl Command Wild Carding

Many of the PowerArtist Tcl commands support wild card characters that allow you to
match multiple elements. These elements might be, for example, net or instance
names. In UNIX, there are two types of wild carding supported: glob and regular
expressions. Glob style is supported by the various shell commands such as ls. The
typical characters that are used are * and ?. PowerArtist uses glob wild carding style.
The following example uses the SetLibrary command.
SetLibrary -instance “top.i1.*” -library mylib
This example matches all of the children of instance top.i1 because it uses the *
character. So the above string would match:
top.i1.i2
top.i1.i2.i3
top.i1.i4
Accessing Command-Line Help

You can access command-line help in a number of different ways:
 You can specify a command name with the -help command-line option as follows:
% ptshell -cmd “CalculatePower -help”
This command prints help information for the CalculatePower command and exits
ptshell.
 You can also access help from within the ptshell, for example:
ptshell % help command
This example returns a list of all command file commands. This method does not
exit the ptshell.
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getExtendedName
 You can also type the command name followed by the -help option in the ptshell:
ptshell % Elaboarate -help
This example print help information for a specific command (Elaborate). This
method does not exit the ptshell.
Getting Extended Names from Alias Names

If you only have a command option’s alias name and you want to find out the
extended name, you can use the getExtendedName command that you run from the
ptshell.
getExtendedName
Given an alias name, this command returns the full (extended) option name. You can
execute this command directly from the ptshell or you can put it into a variable (this
command returns the value of a variable rather than printing to standard output).
Syntax
getExtendedName alias_name
Note that you can optionally specify the hyphen (-) preceding the option name.
Example 1
getExtendedName -finish
This generates as output:
finish_time
Example 2
getExtendedName -cpf_out_file
In this case, the alias maps to multiple option/pt_set variable names. This generates
as output:
average_cpf_output_file reduction_cpf_output_file time_based_cpf_output_file
This means that the -cpf_out_file alias maps to three different pt_set commands
(depending on the type of analysis you are doing).
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getExtendedName
Example 3
set foo [getExtendedName write_pdb]

This generates as output:
time_based_write_power_db elaborate_write_power_db average_write_power_db
reduction_write_power_db
This chapter consists of the following sections:
 Alphabetical List of PowerArtist Command File Commands
 Alphabetical List of pt_set Variables
 Open Access Database Access Utilities
 Additional Utilities
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AddLibrary
Alphabetical List of PowerArtist Command File Commands

You can use any of the commands listed in this section in a PowerArtist command
file. The order of commands is important. You need to run the Elaborate command
(elaborate your design) before you can run CalculatePower (power analysis). You
need to specify the source files and libraries for a design, before you run Elaborate.
PowerArtist command files are Tcl programs—each command is executed before the
command that follows it.
AddLibrary
This command defines the logical libraries in your VHDL design. You must specify
this command before the Elaborate command.
Syntax
AddLibrary logical_name physical_file_name
Example
If you are using wwvmkr to create the ptSourceFiles.tcl file, you will see lines similar
to the following:
AddLibrary LIB_MYLIB ./ww_libmylib
CalculatePower
The CalculatePower command performs either average power analysis or time-
based power analysis. If you are performing a reduction run rather than an average
or time-based power run, you should use the ReducePower command.
Note: The following syntax lines list only the required arguments. The arguments
here are considered “required” if they are necessary to achieve acceptable power
number. For example, you can run a power analysis without setting a -start_time and
-finish_time, but simulation may include a beginning and ending piece that you don’t
want to consider in your power estimation.
Syntax for Average Power Analysis
CalculatePower -analysis_type average

(-vectorless_input_file file_name | -activity_file file_name
-gaf_file file_name) -scenario_file file_name
-synlib_files {file_name1 file_name2 ...}
-top_instance top_simulation_instance
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[-average_write_power_db true | false] [-finish_time string]

[-start_time string] [-additional_average_options ...]
Syntax for Time-Based Power Analysis
CalculatePower -analysis_type time_based

-activity_file file_name -synlib_files {file_name1 file_name2
...}
[-finish_time string] [-start_time string]
(-interval_size float | (-num_clock_cycles int -reference_clock
clock_name)) [-time_based_report_file file_name]
[-time_based_write_power_db true | false]
[-additional_tine_based_options ...]
Common Options
-active_edge auto | positive | negative

Specifies the edge of the clock that defines the start point for the first interval.
Default: auto
-activity_debug_flags value
Prints debug information during activity analysis.
-activity_file file_name
Specifies an input stimulus file generated due to a functional simulator run. The
file may be in FSDB, VCD or IAF (generated by Apache PLI routines) format. You
must specify either -activity_file or -vectorless_input_file for an average power
analysis.
Default: activities.iaf
Alias: -iaf
-analysis_type average | time_based
Performs average power analysis or time-based power analysis. Note: to see
command-line help for time-based analysis, type “CalculatePower -analysis_type
time_based -help”. If you just type CalculatePower -help, you will only see the
options that apply to an average analysis.
Default: average
-arc_based_estimation true | false
When set to true, enables arc-based power estimation for gate-level instances in
the design. By default, PowerArtist uses pin-based power estimation, which is
significantly faster than arc-based power estimation but slightly less accurate. By
default, arcs are still monitored for the following instances:
 IO pads
 instantiated memories
 non-memory cells containing bus pins
 macro combinational cells with 11 or more pins
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CalculatePower
Additionally, even if you do use the default pin-based estimation, you can enable
arc monitoring for specific cells and instances using the MonitorArcs command.
Default: false
-average_cpf_in_file file_name
Specifies an input file containing power constraints in CPF. This is a beta flow.
Though the software supports a subset of the total CPF 1.1 command set, it will
read CPF files that use all of the available commands. Commands not supported
are ignored. Similarly, the software ignores any command options that are
specified but not supported. For more information, see Using a CPF Input Flow
(Beta).
Alias: -cpf
-average_report_file file_name
Writes a report file for average power analysis with the specified file name.
Alias: -rpt
Default: If you do not specify this option, the output will be generated to stdout.
-average_report_options string
Specifies one or more options that determine the contents of the report file.
0 Prints internal driver power in separate section.
a Includes area information.
c Moves power due to clock switched-cap into the clock report. Specifically, this
option is used for extracting the clock power component of an instance of a
register or latch. The clock power component is obtained from Liberty vectors
modeling just a rise or fall on a clock pin, which may or may not be qualified by
a boolean expression.
Examples:
(01 CLK), (01 CLK || 10 CLK), (01 CLK && CS)
C Moves power due to clock switched-cap into the clock report. Specifically, this
memory or IP block. The clock power component is obtained from Liberty
vectors modeling just a rise or fall on a clock pin, which may or may not be
qualified by a boolean expression.
d Shows only new deltas on parents when writing a power difference report.
e The power report will be written using scientific notation.
g Includes net frequency and glitch information.
i Indents hierarchy. Children instances are nested and indented underneath their
parent.
I Outputs load power information for primary input nets.
m Excludes inferred instances.
M Outputs retention flops of the library cell to which the inferred instance mapped.
N Includes net transition time information in report.
p Includes hierarchical parents.
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P Includes pin transition time information in report.

r Uses relative percentages to demonstrate power differences in the power
difference report.
t Prints combined static and dynamic instance power.
u Excludes vendor gates from power and area reports.
v For gate-level instances, this option replaces the gate name with vendor_gate
in the report.
V Reports power dissipation per power supply.
z Excludes nets with non-zero frequency from reports generated with net
frequency and glitch information (using the -average_report_options g option).
Alias: -r
-average_upf_in_file file_name
Specifies a UPF file as input for an average power analysis.
-average_write_power_db true | false
Writes out a power database (.pdb) for an average power analysis. When this
option is specified, the analyzers will output the OpenAccess database
representation of all the power analysis results.
Default: false
-calculate_log file_name
Specifies the name of the output log file for this command.
Default: CalculatePower.log
Alias: -log
-compress_gaf true | false
Writes out a compressed .gaf file compressed using wwgzip (which is the gzip
shipped with PowerArtist).
Default: false
-default_dont_use_cells file_name
Excludes the cells in the given file consideration during the default cell selection
process.
The format of the file is as follows:
cell_name library_name
Sample File
DFFRX1 typical_13
TLATX1 typical_13
Note: this option is obsolete. You should use the SetAttribute command instead.
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-default_output_load float
Sets the default output load to float Farads. This load capacitance is applied to
all primary outputs not listed in the load or wiring cap files (specified using either
the -capacitance_file or -load_file options).
Default: 0
Alias: -dl
-default_transition_time float
Sets the default transition time to float seconds for any net for which slew is not
specified.
Alias: -dt
-detailed_vertical_report true | false
Generates a detailed vertical power report.
Default: false
-domain_frequency_cell_selection true | false
When set to true, this option activates frequency-based cell assignment. There is
no default value for the -domain_frequency_cell_selection option. When combined
with the -frequency option to the SetClockNet command, this option determines
when frequency-based cell selection occurs. Frequency-based cell selection
occurs in either of the following two situations:
 -domain_frequency_cell_selection is specified and set to true.
 -domain_frequency_cell_selection is not specified at all and -frequency is
specified on one or more SetClockNet commands.
Otherwise, non frequency-based cell selection occurs.
Default: (see description)
-finish_time string
Stops collecting data at the specified string. If string ends with the letter “s”, it
is specified as time, otherwise it is specified in simulator ticks. It is strongly
recommended that you determine a -start_time and -finish_time in order to select
the most representative time slice for your analysis run.
Default: If you do not specify -finish_time, the analysis runs to the end of your
activity file.
Alias: -finish
-flop_clock_activity file_name_prefix
Monitors the activity of clock pins in registers in your design and generates flop
clock activity analysis text files and waveforms in .ptcl format. The
file_name_prefix specifies the prefix you want to use for these flop clock
activity output files (for example, “fca” is commonly used). For more information on
the output files this option produces, see Monitoring Flop Clock Activity.
-fsdb_output_file file_name
Outputs power over time waveforms in the FSDB format to the specified file name.
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-gaf_file file_name
Specifies the name to be given to the Global Activity File (GAF) that is generated
by processing the -activity_file argument during an average power calculation.
The average power calculation engine then reads in this file. This argument is
required.
Default: (none)
Alias: -a
-gate_level_netlist true | false
Directs PowerArtist to regard the design as a gate-level. This has the following
effects on the tool flow:
 During compilation, Elaborate will ensure that the design is a gate-level netlist.
If RTL operators are encountered (other than direct assignments of one signal
to another), then a warning is printed and the operators are removed from the
design.
 During either average or time_based power analysis, PowerArtist will skip
default cell selection for RTL operators. If all simulation activity has been
directly recorded and then power analysis skips activity propagation for
additional runtime efficiency.
Alias: -gate
-interval_size float
Specifies a number of intervals into which the simulation will be broken during a
time-based power analysis. For more information on the usage of this option and
an example, see Controlling Your Time-Based Power Analysis. Note that you
need to either specify -interval or -reference_clock and -num_clock_cycles. This is
used for gate-level designs.
Default: false
-mixed_sim_prob_estimation true | false
Enables activity propagation when the simulation dump is partial and does not
capture all nets, or when the design description does not exactly match the
simulation data.
Default: false
-mode_file file_name
Reads the specified mode control file. Note that you cannot use this option with
the -gate_level_netlist option. This flow is only valid for RTL average power
analysis. For more information on the mode file, see Mode File Format.
-multiple_testbench_control_file file_name
Calculates an averaged power number based on multiple GAF files that were
generated using different testbenches. These GAF files are specified via a control
file you specify as an argument to this variable. Each GAF must be written for the
same design (top level), but cover different portions of the design, or supply
different vector sets. The testbenches do not need to be of equal length or
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CalculatePower
mutually exclusive, but they are required to have the same top instance.
Alias: -mt
-num_clock_cycles int
Sets the interval size as a number of clock cycles for RTL time-based analysis.
The interval size is the period of the block into which PowerArtist will split the
simulation. It is recommended that you choose an interval greater than or equal to
two clock cycles. This can be a very performance-intensive operation. Imagine
how long it took to simulate your entire design. If you select a small
num_clock_cycles value it is as if you are redoing your entire system and
performing a power calculation step at the same time. If you specify this option,
you must also specify the -reference_clock. Note that you need to either specify
-interval_size or -num_clock_cycles and -reference_clock.
Default: 0
-power_tech_file file_name
Specifies a PACE technology file for capacitance estimation. Capacitance
estimation using PACE overrides capacitance estimation using wire load models,
whereas other capacitance annotation methods override capacitance estimation
using PACE. For more information, see Using PACE Technology Files During
Power Analysis (Beta) in the PowerArtist User Guide and
Chapter 9, Generating PACE Technology Files (Beta) in the PowerArtist Library
Developer’s Guide.
-print_missing_sim_nets true | false
Prints the names of nets that are in your scenario file but are not in your
simulation file.
Default: false
-ptcl_output_file file_name
Outputs power-over-time waveforms in the PTCL format to the specified file name.
-quiet true | false
Suppresses printing of note-level messages.
Default: false
-reference_clock clock_name
Specifies the reference clock for time-based power analysis. It controls when a
clock starts and the length of its period. Note that you need to specify either -
reference_clock. and -num_clock_cycles or -interval_size. This is used for RTL
power analysis.
-saif_file file_name
Specifies a SAIF file to use for power analysis instead of a VCD or an FSDB file.
For details on this flow, see Analyzing Average Power Using a SAIF File.
-save_clock_trees_netlist true
Generates power database schematics for the clock tree in the design.
Default: false
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-save_x_nets_file file_name
Creates a file listing any nets that are in an X state during the simulation. This
creates a file with three columns.
Sample Output
count.n29 1 0.000000011000
count.n46 2 0.000000034000
The first column is the signal name. The second column is the number of times
the signal transitions to an X state. The third column is the cumulative time spent
by the signal in the X state. You can use the -allowed_x_time option to set the
tolerance of X detection, that is, the allowable time span beyond which signals
stuck at X get reported. You can sort this file by any of the three columns using
the UNIX “sort” utility, for example:
% sort -r -n -k 2 x_net_file_name
-r reverses the order of the result so the largest values are at the top.
-n performs a numerical sort.
-k col_num indicates the column number by which to sort.
Note
Note that enabling X net reporting can increase the run time for GAF creation.
Also, instead of using the default setting of 10 ns, it is recommended that you set
-allowed_z_time to a value that is most appropriate for the simulation.
Alias: -save_x_nets
-scenario_file file_name
Specifies a scenario file name. If you are in composite mode, this specifies the
root from which PowerArtist will search for other scenario files.
Default: (none)
Alias: -scn
-skip_clock_analysis true | false
Allows you to run PowerArtist without a SetClockNet command. When set to true,
the clock file is ignored. The default for this options is false. The following
conditions will print warning/error messages:
 If you do not set this option to true and you do not specify a SetClockNet
command, you will get the following error message:
Error: Neither a SetClockNet command nor a
skip_clock_analysis option is specified. One of them is
required.
 If you set this option to true but you do not specify at least one SetClockNet
command, you will get the following warning message:
Warning: No SetClockNet command is specified. A skip_clock_analysis option
is specified. Therefore, clock tracing and inferencing analysis will be disabled.
Unless the design has clock trees instantiated, inaccurate results may occur.
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 If you specify both a skip_clock_analysis option and a SetClockNet command,

you will get the following warning message:
Warning: A SetClockNet command and the skip_clock_analysis option
have been specified. Therefore, ignoring the skip_clock_analysis
option. Clock tracing and/or inferencing will be performed.
-spef_file file_name
Specifies a SPEF file. This file is used to back-annotate the pin and internal net
capacitance values. For details see, Back-Annotating Capacitance Using SPEF.
Alias: -spef
-start_time string
Starts collecting data at the simulation time. If string ends with the letter “s”, it is
specified as time, otherwise it is specified in simulator ticks. It is strongly
Default: If you don’t specify -start_time, then analysis begins at the first simulation
time stamp in your activity file.
Alias: -start
-statistics register_activity
Specifies that PowerArtist capture register activity statistics for use in the
CoolTime product. CoolTime requires register activity information for a vectorless
instantaneous voltage drop analysis. Given the “-statistics register_activity” option,
CalculatePower reports the “peak” register activity over your chosen simulation
duration. This means that you also have to supply an interval size that is used to
break your simulation up into N intervals. This peak activity is output in your
CalculatePower.log file.
Example
CalculatePower -statistics register_activity -start_time 10ns
-finish_time 1ms -interval_size 20e-09
This would generate a new Note 2130 in the log file. The note would appear as
follows:
wwgaf: Note 2130: Peak Register Activity = .7

Peak cycle start time = 5e-08
Peak cycle end time = 7e-08
You can then supply the Peak Register Activity (.7 in this example) to CoolTime.
The Note also records the start and end time of the peak interval.
-suppress_messages {warn_num1 warn_num2 ...}
Adds the specified Tcl list of warning numbers to the supplied list of warnings to be
suppressed. Note that if you specify multiple -suppress_warnings options that the
list of message numbers you subsequently supply will overwrite the original list.
Default: (none)
Alias: -nowarn
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Adds the specified file or Tcl list of files to the list of Liberty technology files. The
asterisk wild card is allowed, and is expanded by the shell. You can also use the
ReadLibrary command to specify which Liberty libraries to read.
Alias: -synlib
-time_based_cpf_in_file file_name
Specifies an input file containing power constraints in CPF. This is a beta flow.
Though the software supports a subset of the total CPF 1.1 command set, it will
read CPF files that use all of the available commands. Commands not supported
are ignored. Similarly, the software ignores any command options that are
specified but not supported. For more information, see Using a CPF Input Flow
(Beta).
Alias: -cpf
-time_based_report_file file_name
Writes a report file for time_based power analysis with the specified file name.
Alias: -rpt
Default: (none)
-time_based_report_options string
Specifies reporting options for time-based power analysis. Options are:
M Outputs retention flops of the library cell to which the inferred instance is
mapped.
Alias: -r
-time_based_upf_in_file file_name
Specifies an input file in UPF 1.0. For details on how to use this option, see Using
a UPF Input Flow (Beta).
Alias: -upf
-time_based_write_power_db true | false
Writes out a Power Database (.pdb) for use in the PowerArtist PowerCanvas.
When this option is specified, the time-based power analyzer will output the
OpenAccess database representation of all the power analysis results. Normally,
you would always specify this option.
Default: false
Alias: -write_pdb
Specifies the full hierarchical name of the top-level module in the simulation
hierarchy. This should correspond to the module specified with the Elaborate -top
option. For example, if your testbench is called “bench” and it instantiates the top
module as “dut”, specify -top_inst bench.dut.
Default: (none)
Alias: -topinst
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-transition_time_file file_name
Back-annotates transition times (slews) for nets and pins from the specified file.
For more information, see Transition Time File Format.
Default: (none)
Alias: -tt
-use_existing_gaf true | false
When set to true, PowerArtist re-reads an existing GAF stimulus file during
simulation-based average power analysis. This allows you to perform what-if
experiments without re-reading your stimulus file, which can be time-consuming.
Default: false
-use_library_file_names true | false
When set to true, stores cell libraries by file name rather than by the logical library
name inside the Liberty file. Whenever you specify a library name, it is interpreted
as a file name rather than the name inside the .lib that has the line “library
logical_library_name {....}”. This option is required if you have multiple library
files that share the same logical library name.
Default: false
-use_scan_flops true | false
Uses only scan flip-flops for default flip-flop cell selection. By default, all types of
flip-flops are considered for default flip-flop selection, including scan flip-flops.
Default: false
-use_rtl_sim_data true | false
Uses RTL simulation data for average gate-level power analysis. To use this
feature, you must have generated your activity file (GAF) using a name-mapped
flow. For details, see Name Mapping Flow.
Default: false
Alias: -rtlsim2gate
-vectorless_input_file file_name
Reads the specified file as a Vectorless Activity File (VAF) and run s a vectorless
average power analysis.
Alias: -vectorless_input
-vertical_report_instances {inst1 inst2 ...}
Produces a vertical report that provides summary information for the specified list
of instances. This is valid only for average power analysis. Note that vertical
reports do not include instances that are reported as part of clock tree power.
-vertical_report_sort_mode (alphabetical | power)
Sorts the vertical report when it is generated by the -vertical_report_instances
option.
Default: alphabetical
Alias: -sort
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-wait_for_license true | false

Specifies that PowerArtist wait for a license to become available and to not exit.
Default: false
Alias: -wait
-zero_delay true | false
Specifies that the activity file was generated by a simulator in zero-delay mode.
See Zero Delay Simulation for information the effects of specifying this option.
This can only be used with a time-based analysis.
Default: false
Uncommon Options
-activity_perform_esl_analysis true | false

Enables ESL power analysis.
Alias: -esl
-allowed_x_time string
Specifies an amount of time a net can be in an X state continuously (not discrete).
If any signal is in X state (continuously) for more than the time specified with -
allowed_x_time then it is reported as WARNING 3344. For example:
#0
0$
#10
x$
#20
0$
#30
x$
#40
0$
#50
x$
#60
0$
#70
x$
Here, the total x duration is 10(20-10) + 10(40-30) + 10(60-50) + 10(70-60) =

40ns. But the signal never remains in X state for more than 10ns of time—it
changes its value to 0. Therefore, if -allowed_x_time = 10 ns (or less) all four
occurrences will be counted. If -allowed_x_time is greater than 10ns, nothing will
be counted. So here x state means 1 x state continuously—not the entire X-state
during the simulation.
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If string ends with the letter “s”, it is specified as time, otherwise it is specified in
simulator ticks.
Default: 10ns
-allowed_z_time string
Specifies an amount of time a net can be in an Z state. If string ends with the letter
“s”, it is specified as time, otherwise it is specified in simulator ticks. The nets that
exceed the allowed time in the Z state are reported in a text file (see -ftn_report).
Default: 100ns
-average_cpf_output_file file_name
Writes out CPF constraints that capture Multi Supply Voltage (MSV) and Power
Shut-Off (PSO) design intent. You can then use these constraints in other tools
such as Cadence’s RTL Compiler™. The resulting file is in ASCII format,
therefore, you can add to or modify the generated CPF commands. The
commands are not expected to capture of all the information required to
synthesize the design. For details, see Using a CPF Output Flow (Beta) in the
PowerArtist User Guide.
Alias: -cpf_out_file
-average_html_report_title file_name
Generates an HTML report file with the specified name. By default, no HTML file
is produced.
-average_results_file file_name
This is only used to create power difference reports. If you are not generating
them, do not use this option. Power analysis data is now stored in the power
database.
Alias: -o
-capacitance_file file_name
Reads the specified file as a back-annotated inter-module wire capacitance file.
See Capacitance File Format for more information.
Default: (none)
Alias: -c
-check_synlib_semantics true | false
Performs semantic checks on specified Liberty files.
Default: false
-compare_with_results_file file_name
Reads the specified result file generated using the -average_results_file option
and prints a report section showing the difference in power between the result file
and the current estimation.
Default: (none)
Alias: -diff
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CalculatePower
-count_glitches_as_toggles true | false

In average mode, counts zero-duration glitches as toggles.
Default: false
-critical_messages tcl_list_message_ids
Specifies a list of message IDs to be flagged as critical. If PowerArtist encounters
these message numbers, they are highlighted as critical in the final message
summary. Note that when you specify a message ID list, it will overwrite the
current list of critical messages including the default list determined by Apache. If
you want to maintain the default list and simply add to it, you must include the
message IDs that are considered critical by default.
Default: 1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309 8517
Alias: -critical_msgs
-current_output_file file_name
Writes out the average current per instance to a file named current_output.tcl (by
default).
-debug_instances_file file_name
Selectively enables debug messages for instances specified in the given file. The
format of the debug file is as follows:
-xdebug_switches
full_hierarchical_leaf_level_instance_name1
...
-disable_glitch_propagation true | false

Disables delta (glitch) propagation.
Default: false
Alias: -g
-enhanced_vcd true | false
Reads the IAF file as an Enhanced VCD format file. See Acquiring
Simulation Data in the PowerArtist User Guide for more information about IAF
and Enhanced VCD. Note that you should try to use FSDB files instead of Enhanced
VCD. FSDB files are more compressed and process faster.
Default: false
Alias: -vcde
-etcl_file file_name
Specifies the name of final ETCL file—for use in CoolTime—to be generated by
the time_based engine. Note that you must specify the -analysis_type time_based
option with this option.
-forced_x 0 | 1
Replaces X with a binary value of 1 or 0 wherever they occur while reading a VCD
or FSDB simulation trace file.
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CalculatePower
-ftn_report_file file_name
Specifies a name for the report containing names of the Floating Tri-state Nets
(FTN).
Default: (none)
Alias: -ftn_report
-heartbeat string
Prints progress information during GAF file creation. The specified string is taken
as the time between emitting progress messages. If string ends with the letter “s”,
it is specified as a fraction of simulation seconds; otherwise it is considered to be
simulation ticks.
For example, if the time scale for your simulation results is 10 ns. Specifying “-
heartbeat 1” will print a progress message every 10 ns of simulation time. If you
specify “-heartbeat 20ns”, you will get a heartbeat message approximately every
20 ns of simulation time.
The generated message is similar to the following:
Note 2086: Simulation time is now xxx (yyy simulator ticks).
The simulation time in the messages is approximate to the heartbeat because you
must have simulation signal change results in your activity file that occur
approximately every heartbeat.
Default: (none)
-html_report_directory dir_name
Specifies a collection directory that allows for the organization of HTML reports
from various executions or designs, into a single HTML page. You can collect all
HTML reports in a central location. This option writes HTML files into the specified
directory. The top-level file is named index.html. This option must be used with the
-average_html_report_title argument.
Default: (none)
-ignore_SPEF_C_comments true | false
Ignores “C-style” comments in the SPEF file.
Default: false
-ignore_toggles_through_x true | false
Ignores transitions to the X state during toggle calculations.
Default: false
Alias: -ix
-instance_power_threshold float
Eliminates instances with less than float percentage of the total power from the
power report.
Alias: -e
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CalculatePower
-interpret_pin_caps_as min | max | avg

Instructs PowerArtist to use the rise_capacitance_range and
fall_capacitance_range attributes to calculate pin capacitances. The actual pin
capacitance values are calculated in the following manner:
 min: pin capacitance = (Min_rise + Min_fall) / 2
 max: pin capacitance = (Max_rise + Max_fall) / 2
 avg: pin capacitance = (Min_rise + Max_rise + Min_fall + Max_fall) / 4
For more information on how pin capacitance is calculated, see Estimating Pin
Capacitance.
Alias: -pin_caps
-library_defaults_file file_name
Specifies the Sequence Library Defaults (SLD) file.
Alias: -sld
-load_file file_name
Reads the specified back-annotated load capacitance file. See Capacitance File
Format for more information. This file contains the names of the primary outputs of
your design.
Default: (none)
Alias: -l
-max_clock_depth int
Limits forward clock-tracing depth to the number specified. Prevents excessive
time spent in forward tracing.
Default: 40
-maximum_number_of_errors int
Maximum number of errors to be printed for any given message.
Default: 50
-max_time_stamps int
Specifies the maximum number of time stamps printed in the report for each
instance or class of instances defined by the MonitorInstances command. The
time stamps correspond to the times when the power was the highest for those
instances.
Default: 10
-multiple_license_files true | false
Allows PowerArtist licenses to be served by multiple licenses.
Default: false
-no_maximum_error_list message_num1 message_num2 ...
Removes any limit on the number of messages that can be printed. Use this
option sparingly.
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CalculatePower
-no_module_net_capacitances true | false

Disables estimation of inter/intra-module net capacitances.
Default: false
Alias: -n
-no_slew_calculation true | false
An internal slew calculator is enabled by default in all power engines of
PowerArtist. The -noslewcalc option disables this slew calculator.
Default: false
Alias: -noslewcalc
-output_current true | false
Writes out current information to the waveform files instead of power numbers.
You might want to use this feature, for example, if you were looking for di/dt
changes for voltage drop analysis.
Default: false
-peak_cycle_file file_name
Generates an output file that contains the commands that Elaborate needs to
generate the etcl (.etcl) file. An etcl file saves the primary inputs and register state
information for a given point in time. It can be used by CoolTime when calculating
dynamic voltage drop analysis. If the “-peak_cycle_processing_mode” option is
set to “auto”, then this file will contain the studio_state_setup_time_based
command, and is passed on to CalculatePower for generating an etcl file;
otherwise, the file will contain peak power information for each clock cycle.
-peak_cycle_processing_mode auto | interactive
Selects the processing mode for generating an etcl file. Selects the processing
mode for generating an etcl file.
 auto: the time-based engine will automatically determine the clock cycle with
the highest power and will run CalculatePower with the correct options to
generate the required etcl file. If multiple cycles have the same power, then the
first one that occurs in time will be selected.
 interactive: the GUI will generate a peak cycle file. When power analysis
completes, you will be taken to another GUI page that allows you to
interactively scan the power on each clock cycle and choose the cycle of
interest. Once you complete this step, PowerArtist generates the required etcl
file.
Default: auto
-reset_library_negative_power true | false
On an arc-by-arc basis, after the power computation for an arc is done, if its power
is less than 0, this option sets it to 0.
Default: false
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CalculatePower
-reset_negative_power true | false

Sets the power value to 0 for all instances with a negative power value.
Default: false
-statics_threshold float
Specifies that PowerArtist monitor only static vectors with power greater than the
specified percentage. For RTL designs with huge numbers of instantiated gates,
using this option will improve both the run time and memory usage. Values of 5 to
20 percent are usual, 0 to 50 percent is allowed.
Default: 0
-stimulus_processing_passes integer
Runs GAF creation serially in integer passes to trade off the memory footprint for
run time. The higher the integer value provided, the longer the run time and
smaller the memory footprint. This only needed for very large gate-level designs.
Range: 2 to 10
Alias: -split
-time_based_cpf_output_file file_name
synthesize the design. For details, see Using a CPF Output Flow (Beta) in the
PowerArtist User Guide.
-unlimit_interval_size true | false
Allows you to specify an interval size smaller than 1ns for time-based power
analysis. This should only be used for gate-level analysis.
Default: false
-use_non_scan_flops true | false
During power analysis, PowerArtist searches the library for non scan flip-flop
definitions for use as default cells.
Default: false
-voltage float
Sets design voltage to the specified value. This option is obsolete. Use the
CreateVirtualSupply should be used instead.
Default: (none)
Alias: -v
-wireload_library lib_name
Specifies the logical Liberty library name in which a power analyzer will search for
wire load models. This is useful when reading in multiple libraries that could
contain wire load models. This option is obsolete. Use the SetWireLoadModel
command instead.
Apache Design, Inc.

CompileFile
CompileFile
This command defines how to compile each of the source files in your design. This is
most often used in conjunction with the AddLibrary command for VHDL or mixed
VHDL and Verilog designs. The CompileFile command must come before the
Elaborate command.
Syntax
CompileFile -type (verilog | vhdl) -file physical_file_name

[-sv true | false] [-87 true | false] [-93 true | false]
[-95 true | false] [-2001 true | false] [-library library_name]
Options
-type verilog | vhdl

Specify either Verilog or VHDL. If you do not supply this option, VHDL will be
assumed.
-file physical_file_name
Specifies the location on disk of the source file.
-sv true | false
Specifies whether or not the file should be compiled as System Verilog file. If
specified, this option overrides the -93 yes or -2001 yes options.
-87 true | false
Specifies whether or not the file should be compiled as VHDL 87.
Default: false—file is expected to be VHDL 93 compliant.
-93 true | false
Specifies whether or not the file should be compiled as VHDL 93.
Default: true
-95 true | false
Specifies whether or not the file should be compiled as Verilog 95.
Default: true
-2001 true | false
Specifies whether or not the file should be compiled as Verilog 2001.
Default: false—file is expected to be Verilog 95 compliant.
-library library_name
Specifies the name of either a logical or a physical library name for VHDL only
(not used with Verilog). This field is required for VHDL. If it is a physical library,
then you must have supplied the AddLibrary command to provide the logical
library name. If you do not supply a -library option, the name “WORK” will be
assumed.
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CpfIncludeFile
Example 1
CompileFile -type vhdl -file /imp/proj1/myfile.vhd -library

LIB_MYLIB
This compiles myfile.vhd into logical library LIB_MYLIB as a VHDL -93 file.
Example 2
CompileFile -file top.v -type verilog -sv true

This compiles file top.v as a System Verilog 2005 file.
Example 2
CompileFile -type vhdl -file /imp/proj1/file2.vhd -87 true

-library ./ww_lib_mylib
This compiles file2 into LIB_MYLIB, assuming the AddLibrary command example as
a VHDL 87 file.
If you are using the wwvmkr utility and ptCompileScript to generate the
ptSourceFiles.tcl file, you will see that:
 Many AddLibrary commands reoccur throughout the file
 The -87 option may reoccur
This is not a problem. If it is more convenient for you to duplicate these due to an
automatic process you may be doing, feel free to do so. Just make sure that
definitions do not change.
CpfIncludeFile
This command allows you to pass in a CPF file name that is required to be sourced
in the PowerArtist generated CPF file. As an example, you can use this functionality
to specify a CPF file having library-related define commands. This file name is then
added to a Tcl “source” command and placed just before the set_design command of
the top-level module in the resulting CPF output file.
Syntax
CpfIncludeFile -name file_name
Example
CpfIncludeFile -name libraryDef.cpf

Given this command, PowerArtist will generate the following CPF command just
before the set_design command:
source libraryDef.cpf
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CreateDomain
CreateDomain
This command defines a domain in your design. The domain may be a simple
voltage domain where you want to control your power supply values or it may be a
power domain. This command creates the domain by associating virtual supplies
with specific hierarchical instances. To distinguish a power gating domain from a
normal voltage domain, you must specify the -on condition when you create the
virtual supply.
Syntax
CreateDomain [-name domain_name] -instance instance_name(s)

-virtual_supply supply_name(s)
Arguments
-name domain_name
Specifies the name of the domain being created. This is required for the CPF
output flow.
-instance instance_name(s)
Specifies a hierarchical path to one or more instances. You can specify a Tcl list of
instances. Each instance name may include the * wild card character. The power
domain is assigned for the instance and all of its children in the hierarchy. As with
the SetLibrary command, CreateDomain commands applied to child instances of
a power domain will create a new domain and override the effects of any previous
CreateDomain commands. The first instance name in the list will become the
domain name in the vectorless power reports; therefore, if you want to track power
per individual instance, then use only one instance name per CreateDomain
statement.
-virtual_supply supply_name(s)
Specifies one or more virtual supplies previously defined using the
CreateVirtualSupply command. If you want to control multiple virtual supplies for a
domain, do not supply two separate commands—instead, supply multiple virtual
supplies as a Tcl list.
Example 1
CreateDomain -instance top.block1.domain1 -virtual_supply VDDSW

CreateDomain -instance top.block2.domain1 -virtual_supply { VDDSW VDDCSW }
CreateDomain -instance top.block1.domain2 -virtual_supply VDDSW1
If the RTL was not partitioned so that the logical hierarchy of the design matches the
way you want the partitions to line up, you can specify a list of instances to create the
desired domain. Such an example would be:
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CreateGraph
CreateDomain -instance {top.block1 top.block2.sb1}

-virtual_supply VDDCSW
Example 2
# The domain name will be PD0

CreateDomain -name PD0 -instance {top top.i1} -virtual_supply {VDD VDDNSW VDDCSW}
# The domain name will be PD1
CreateDomain -name PD1 -instance {top.i2} -virtual_supply {VDD VDDNSW VDDCSW}
These examples show how you can create domains with different names.
CreateGraph
This command generates a graph of data related to clock gating opportunities. It
helps you determine the value to be used for the -cumulative_savings argument to
the WriteClockGatingConstraints command.
Syntax
CreateGraph -graph_class clock [-graph_output_file file_name]

-power_db_name file_name [-graph_log file_name]
[-graph_type power_savings]
Arguments
-graph_class clock
Specifies the type of reduction data that should be examined for plotting.
Currently, this command only supports the “clock” value. This will generate graph
data related to clock gating opportunities. This argument is required.
-graph_output_file file_name
Specifies the PTCL file name containing graph data. If you don’t specify this
option, the PTCL is output to the log file, which by default is named
CreateGraph.log.
-power_db_name file_name
Specifies the name of the power database (.pdb) file that contains the reduction
data to be used to generate the graphs. This argument is required.
Alias: -pdb
-graph_log file_name
Specifies the log file name containing any messages generated by this command.
Default: CreateGraph.log
-graph_type power_savings
Specifies the form of the graph to be generated. Currently, the graph type
supports only “power_savings”. This generates a cumulative power savings curve
as a function of the number of RTL reduction opportunities.
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CreateVirtualSupply
CreateVirtualSupply
This command creates/defines virtual supplies. One supply can have multiple virtual
supplies. This is most useful for voltage domain or power gating applications. In this
application, you can define one virtual supply per library supply rail, per power
domain. This manner of creating virtual supplies supports the specification of on/off
conditions for power gating applications.
To use voltage domain applications, you will at a minimum need the SetLibrary
command. You might also use the CreateVirtualSupply command to create virtual
supplies with different voltages than those defined as the default operating condition
in the library. If you provide a voltage, it becomes the estimation voltage and then the
library’s characterization voltage will be derated using the new estimation voltage
value. That new voltage will then be used to compute new energy and power
numbers. This flow incorporates the standard PowerArtist derating technique.
For power gating, you will use the -supply, -virtual_supply and -on options.
Syntax
CreateVirtualSupply (-supply power_rail_name | -pg_type pgtype)

-virtual_supply supply_name [-voltage voltage]
[-on condition] [-default on | off]
Arguments
-supply power_rail_name
Specifies a power rail in one or more libraries. The power rail name can be
qualified by a logical library name. If you do not specify a logical library name,
then the -virtual_supply will apply to all libraries sharing that supply name when
the virtual supply is associated with one or more instances using the
CreateDomain command. The logical library name must be found in the libraries
specified by the -synlib_files command option. One, but not both, of either -supply
or -pg_type is required.
-pg_type pgtype
The legal pgtype options are primary_power, internal_power, backup_power,
primary_ground, internal_ground and backup_ground. The virtual supply will be
associated with all pg_pins in your Liberty library for which the pg_type attribute
has the same value as you specified it to this command. The power calculation for
any vector associated with this pg_pin (specified in your Liberty library using the
related_power_pin attribute where the attribute value is the pg pin name) will use
the voltage and on condition specified with the CreateVirtualSupply command. If
you use this option and your libraries do not specify pg_type attributes, all power
rails will be treated as primary_power rails.
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CreateVirtualSupply
The critical portions of a cell description from a Liberty cell using the pg_type
attribute is:
cell (XYZ) {
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pin(A) {
internal_power() {
related_pg_pin : VDD;
when : "!EN";
rise_power(template_1x7) {...}
fall_power(template_1x7) {...}
}
}
pin(EN) {
related_power_pin : VDD;
related_ground_pin : VSS;
internal_power() {
when : "!A";
rise_power(template_1x7) { ... }
fall_power(template_1x7) { ... }
}
}
leakage_power() {
when :"!A & !EN";
}
}
-virtual_supply supply_name
Specifies a unique name for a virtual supply.
-voltage voltage
Specifies the estimation voltage for the specified virtual supply. By default units
are Volts. You can specify an optional unit. 1.0V is the same as 1.0, which is the
same as 1000mV. There can be no space between the number and the unit.
-on condition
Specifies that this virtual supply will be used for a power domain. The condition is
a double quoted string that represents any legal boolean condition in the target
language. When this condition evaluates to TRUE, the virtual supply is expected
to be on, causing both static and dynamic power. When the condition evaluates to
Apache Design, Inc.

CreateVirtualSupply
FALSE, the virtual supply is expected to be off. For each instance connected to
this virtual supply, the portion of the static and dynamic power due to this supply
will be set to 0. Optionally, the condition string can be a constant 0 (FALSE) or a
constant 1 (TRUE). This type of expression requires no run time evaluation and
MUST be used during RTL vectorless analysis to set the power domain into a
particular state for the analysis.
-default on | off
Specifies the state of the main power net of the domain (and thus the state of the
domain) in the default power mode in CPF.
Default: on
Example 1
CreateVirtualSupply -supply VDD -virtual_supply VDDSW

CreateVirtualSupply -supply stdcell1.VDDC -virtual_supply VDDCSW -voltage 1.1V
CreateVirtualSupply -supply VDD -virtual_supply VDDSW1 -on "A&B"
In this example, VDD has two virtual supplies created for it: VDDSW and VDDSW1.
The supply VDDC found in library stdcell1 has a virtual supply VDDCSW and its
estimation voltage is set to 1.1V. If the default estimation voltage specified by the
library is not 1.1V, then derating will occur during power analysis. In addition, the
virtual supply VDDSW1 will be associated with a power gating application. Whenever
the signals A and B are both true during a simulation run, the power domain
associated with this supply will be assumed to be active; otherwise, it is assumed to
be in stand-by mode.
Example 2
CreateVirtualSupply -supply vdd -virtual_supply VDD_typ -on !sleep -default off

CreateVirtualSupply -supply VDD -virtual_supply VDDSW -default on
This example shows the use of the -default switch that specifies the default state of
the virtual supply.
Example 3
CreateVirtualSupply -virtual_supply VS1 -on 1 -voltage 1.6 -pg_type "primary_power"
The virtual supply VS1 is on all the time and will be estimate with a 1.6V voltage. If
no pg_type attributes exists in the technology library, then all supplies will be mapped
to VS1. Otherwise, the pins tagged with pg_type : primary_power will be used to
locate the supplies.
Apache Design, Inc.

DefineGroup
DefineGroup
This command defines instance groups for the GenerateActivityWaveforms
command. You can also use this command to remove existing groups. Note that if
you specify an existing group name, this command will redefine that group with the
new instance list.
Syntax
DefineGroup group_name [instance(s) [-levels int]]
Arguments
group_name
The name of the group to which you are assigning the given elements (or the
group you are removing).
instance(s)
A Tcl list of hierarchical instance names to be included in the given group name. If
you have one element, it is not necessary to enclose the instance(s) in curly
braces unless there are characters like [ ] that must be escaped. If you specify an
empty instance list, PowerArtist will delete the specified group.
-levels int
This option defines the hierarchical levels that are included in the defined group.
You can specify any value equal to or greater than 0.
Example 1
DefineGroup top top

This example creates a group named top that contains an instance named top.
Example 2
DefineGroup memory top.r1.m1

This example creates a group named memory that contains an instance named
top.r1.m1.
Example 3
DefineGroup channels {top.r1 top.t1}

This example creates a group named channels that contains instances top.r1 and
top.t1.
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DefineHalfMemScalingFactor
Example 4
DefineGroup channels
This example reports the contents of the group named ‘channels’. If the specified
group name does not exist, PowerArtist will report an error noting that there is no
such group.
Example 5
DefineGroup top {}
This example removes the group named top.
Example 6
DefineGroup top_name {top} -levels 0

This example creates a group named top_name that will include the all nets in the
entire hierarchy starting from instance 'top'. The effect of this command is the same
as the 'DefineGroup top_name {top}' command.
Example 7

This example creates a group named top_name that will include only nets that are
part of the hierarchical instance 'top'.
Example 8

This example creates a group named top_name that includes all nets and child
instances of instance 'top'.
DefineHalfMemScalingFactor
This command is used by the Split Memory Words PowerBot to perform memory
splitting during power reduction analysis. You can use this command to define the
parameters for calculating the power of half-size memories. If your Liberty files
contain half-size memories, then this command will not be applied. If it does not,
reduction will calculate the dynamic/static power of half-size memories based on the
scaling factors you specify with this command. This PowerBot calculates the power
by taking the power numbers calculated from the full-size memory and multiplying
them by the specified scaling factors.
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DefineLibAlias
Syntax
DefineHalfMemScalingFactor -dynamic_scale_factor dynamic_factor

-static_scale_factor static_factor -area_penalty_factor
area_factor [-mem_type RAM | ROM] [-mem_size word_x_width]
Arguments
-dynamic_scale_factor dynamic_factor_float
Specifies a scaling factor for computing the dynamic power of half-size memories
of the specified original size (-mem_size) and the specified type (-mem_type). You
can specify any floating point value between 0 and 1.
Default: 0.7
-static_scale_factor static_factor_float
Specifies a scaling factor for computing the static power of half-size memories of
the specified original size (-mem_size) and the specified type (-mem_type). You
can specify any floating point value between 0 and 1.
Default: 0.7
-area_penalty_factor area_factor
Specifies an area penalty factor that will be used to compute the area penalty (for
instances and nets) of circuitry introduced for half-size memories of the specified
original size (-mem_size) and the specified type (-mem_type). You can specify
any floating point value between 0 and 1.
Default: 0.7
-mem_type RAM | ROM
Specifies the type of the original memory that is to be split. If not specified, the
parameters set in this command are applied to all types of memories.
-mem_size word_x_width
This specifies size of original memory that is to be split. If not specified, the
parameters set in this command are applied to memories of all sizes.
Example
DefineHalfMemScalingFactor -dynamic_scale_factor 0.5

-static_scale_factor 0.5 -area_penalty_factor 0.5 -mem_type RAM
This example sets the scaling factor for dynamic power and static power of half-size
memories of type RAM to 0.5. It also sets the area penalty for half-size memories of
type RAM to 0.5.
DefineLibAlias
This command defines aliases for libraries used for VHDL or mixed VHDL and
Verilog designs. You must specify this command before the associated CompileFile
and Elaborate commands. Given two library names (lib_name1 and lib_name2), this
command will designate that both names refer to the same design library. Any design
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DefineMemActivityThreshold
unit that is compiled into lib_name1 will also be accessible from lib_name2.
Configuration declarations, configuration statements, and use clauses may refer to
the design unit from within either library.
Syntax
DefineLibAlias lib_name1 lib_name2
DefineMemActivityThreshold
This command defines the number of clock cycles during which a memory address
bus must maintain a stable state (1 or 0) for it to be considered as a candidate for
splitting by the SMW PowerBot.
Syntax
DefineMemActivityThreshold -num_clocks num_clock_cycles

[-mem_type RAM | ROM] [-mem_size word_x_width]
Arguments
-num_clocks
Specifies the number of clock cycles (as an integer) for which the address bus
must be stable.
-mem_type
Specifies the type of memory to which the given threshold (clock cycles) will apply.
If not specified, the threshold is applied to all types of memories.
-mem_size
Specifies the size of memory to which the given threshold (clock cycles) will apply.
If not specified, the threshold is applied to all sizes of memories.
DefineMemory
This command identifies/defines memory cells and critical memory ports in your
Liberty libraries.
The DefineMemory command is also used by the Split Memory Words and Gate
Memory Clock power reduction techniques (PowerBots) to identify critical memory
ports like chip-select, read/write enable etc. The DefineMemory command allows the
ReducePower command to classify memories into one of the following types:
 Single clock/multi port SRAM
 SRAMs with bit-write support
 Single port register file
 A two-port register file with memory and write enables
 ROM
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DefineMemory
If an instance can’t be mapped into one of these types of memories, PowerArtist

checks to see if it can be treated as a memory that is not internally clock gated and
the memory enable can be used to gate the clock. If an instance does not meet any
of these criteria, the reduction will skip it.
You can specify multiple DefineMemory commands. All option values are case
insensitive. Options may also include standard glob-style wild cards. For ROM cells,
the -access_enable and -write_address are optional.
PowerArtist reports power associated with memory cells in the “Internal memory
power” section of the average and time-based power reports.
Syntax
DefineMemory
-library {lib_name1 lib_name2 ...} [-attribute mem_attribute]
-access_enable {access_enbl_port_name1 access_enbl_port_name2
...}
[-read_address {read_address_port1 read_address_port2 ...}]
[-write_address {write_address_port1 write_address_port2 ...}]
[-data {pin_name1 pin_name2 ...}]
[-memory_enable {mem_enbl_or_sel_port1 mem_enbl_or_sel_port2
...}]
[-cell {cell_name2 cell_name2 ...}]
[-input_latency number_clock_cycles]
[-output_latency number_clock_cycles]
Arguments
You can use standard glob-style wild cards with all of the following arguments.
-library {lib_name1 lib_name2 ...}
Specifies a Tcl list of logical library names—not the library file name.
-attribute mem_attribute
Specifies a memory attribute present in the .lib. This is optional if you specified -
library.
-access_enable {access_enbl_port_name1 access_enbl_port_name2 ...}
Defines the given Tcl list of ports as access enable ports that indicate whether a
read or write operation will occur.
-input_latency number_clock_cycles
Specifies the number of clock cycles (as an integer) that it takes to pass the input
data to the memory core.
Default: 0
-output_latency number_clock_cycles
Specifies the number of clock cycles (as an integer) that it takes to for the data to
be read from the memory core and be presented at the memory output.
Default: 0
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DefineMemory
A value of 0 means that the data is available in the same clock cycle and can be
latched in the next clock cycle. Specifying latency values has the following critical
impacts:
 First, the memory enable time gets stretched by the number of cycles specified
by the input latency. This means that the clock can be gated only if the clock
was not gated in the previous cycle. This condition needs to hold for the
number of clock cycles specified in by the -input_latency option.
 Second, ODC conditions then need to be aligned by input_latency +
output_latency clock cycles.
-read_address {read_address_port1 read_address_port1 ...}
Defines the given Tcl list of ports as read address ports.
-write_address {write_address_port1 write_address_port2 ...}
Defines the given Tcl list of ports as write address ports.
-data {pin_name1 pin_name2 ...}
Defines the given Tcl list of ports as input and output pins carrying data ports.
-memory_enable {mem_enbl_or_sel_port1 mem_enbl_or_sel_port2 ...}
Defines the given Tcl list of ports as memory enable or select ports.
-cell {cell_name2 cell_name2 ...}
Defines the given Tcl list of cells as memory cells during the analysis. The -cell
argument is optional. If you do not specify it, the analysis will consider all cells in
the given library (specified by the -library option) as memory cells.
Important Notes About this Command
 You need to specify either the -library or the -attribute option. You cannot specify
both.
 If the DefineMemory command is going to be used for power analysis only, then
you only need to specify the -library option.
 Wild cards are accepted in the library/cell/port names, but the expression you
specify should identify a unique name. For example, if your chip enable port is CE
and the read/write enable is WE, then *E is an incorrect definition for -
memory_enable, as it will identify both CE and WE. Instead, you need to specify
CE.
 For vectored ports, always use a * at the end of the name. For example, if there is
a 32-bit data bus named DA, then specify it as:
-data {DA* QA*}
 If the .lib specified using the -library option contains all memory cells (which is
usually the case) then -cell is optional.
 If your memory has memory(), memory_read(), memory_write() attributes, then
-read_address, -write_address and -data are optional. This is because
PowerArtist can identify data and address ports using these attributes.
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Elaborate
Example 1—Single Port Clocked SRAM
DefineMemory -library RR12BX32_lib -access_enable {*WE}

-memory_enable {ME TME} -read_address {*ADR*}
-write_address {*ADR*} -data {D* Q* TD*}
Given this command, PowerArtist searches the cell definitions in the RR12BX32
library for the specified ports. Specifically, it searches for access enable ports that
end with WE, memory enable ports named ME and TME, read address ports and
write address ports that match *ADR*. It also searches for any input/output pins that
start with D, Q or TD. Since the -cell option is not specified, all cells are checked.
Example 2—Single Port Clocked ROM
DefineMemory -library rom512_lib -memory_enable {ME}

-read_address {ADR*} -data {Q*}
Example 3—Port Register File
DefineMemory -library regfile_lib -access_enable {cine_*}

-memory_enable {cine_*} -read_address {raid*}
-write_address {wry*} -data {di* do*}
Example 4
DefineMemory -attribute ram

Given this option, any library with the memory attribute “ram” will be defined as a
memory library.
Elaborate
This command elaborates your HDL design which may be at the RT, mixed RT and
gate or gate level of abstraction. The design may be written in VHDL, Verilog,
SystemVerilog or a combination of them all. After it elaborates your design, it stores
the results in a scenario file and an optional power database.
Note: The following syntax lines list only the required arguments. The arguments
here are considered “required” if they are necessary to achieve acceptable power
numbers.
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Elaborate
Syntax
Elaborate -scenario_file file_name

-synlib_files {file_name1 file_name2 ...} -top design_unit_name
-verilog_startup_file file_name [-options...]
Common Options
-black_box_modules {module1 module2 ...}

Instructs PowerArtist to not infer logic for each module/unit in the specified Tcl list
and its corresponding hierarchical children. You can use wild cards.
For example, “-black_box_modules dw*” will mark all modules starting with “dw” to
be black boxed. The wild card matching follows the same convention as UNIX
shell wild card file name matching, specifically:
* : matches zero or any number of characters
? : matches any single character
[abc] : matches any single character within the braces, one of “abc” in this case.
Characters are matched using the case-sensitivity of the HDL language used.
Names are matched sensitive to case in Verilog, or insensitive to case in VHDL or
mixed-language designs. This is also impacted by the -case_sensitive, -
case_insensitive and upper and lower case options too.
Default: (none)
Alias: -blackbox
-blast_regfile list | all
Specifies either a Tcl list of 2-D arrays to bit-blast or all (all arrays will be bit-
blasted). For more information on using this option, see Controlling Array
Inferencing in the PowerArtist User Guide.
Default: 1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309 8517
-elaborate_ignore_directives tcl_list_of_values
Ignores directives to other tools. You may have a directive in your flow to ignore
parsing your source. This is often done with a translate_off pragma. For example:
module top (in, out);

input in;
output out;
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Elaborate
// quickturn translate_off
// synopsys translate_off
assign out = in;
endmodule
In this case, you would use the following option specification to turn off the
translate_on/translate_off directives:
-elaborate_ignore_directives {quickturn synopsys}
-elaborate_log file_name
Specifies the name of the log file for the Elaborate command.
Default: Elaborate.log
Alias: -log
-elaborate_write_power_db true | false
Writes to the power database. When set to true, the inferencing engine will output
the OpenAccess database representation of a hierarchical netlist of your design.
Default: false
Alias: -write_pdb
-gate_level_netlist true | false
Directs PowerArtist to regard the design as a gate-level. This has the following
 During compilation, Elaborate will ensure that the design is a gate-level netlist. If RTL
operators are encountered (other than direct assignments of one signal to another), then
a warning is printed and the operators are removed from the design.
 During either average or time_based power analysis, PowerArtist will skip
default cell selection for RTL operators.
Alias: -gate
Default: false
-ignore_translate_off true | false
Ignores translate_off and translate_on meta comments in all files.
Default: false
-ignore_translate_off_files file_name1 file2_name2...
Specifies a Tcl list of files in which to ignore the translate_off and translate_on
meta comments.
-list_required_traces file_name
Generates a file containing a list of nets that must be monitored (recorded) to
ensure an accurate power analysis. The resulting file will contain one net name
per line. This file is used in a Palladium flow. For more information, see Acquiring
Simulation Data in Palladium Flows.
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Elaborate
-parameter_maps name=value
Assigns values to different parameters for a top-level VHDL or Verilog module. For
example, suppose you have the following Verilog (or equivalent VHDL fragment:
module top(in,out);
parameter size=2;
input [size-1:0] in;
output [size:0] out;
assign out = in+1;
endmodule
You could override the size parameter by adding the -parameter_maps option in
your command file:
Elaborate -parameter_maps size=4
When PowerArtist elaborates the Verilog design, “size” would be set to 4. If you
have multiple parameters you want to override, you could use multiple instances
of the pt_set parameter_maps variable or include multiple values with a Tcl list of
name=value pairs. For example:
Elaborate -parameter_maps p1=4
Elaborate -parameter_maps p2=5
accomplishes the same operation as:
Elaborate -parameter_maps {p1=4 p2=5}
You can also use the -parameter_maps option to set generics. Take, for example,
the following VHDL fragment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS
GENERIC(SIZE : integer);
PORT ( AA, BB, TT : IN STD_LOGIC_VECTOR(SIZE-1 downto 0);
CC : OUT STD_LOGIC_VECTOR(SIZE-1 downto 0));
END TOP;
ARCHITECTURE A0 OF TOP IS
BEGIN
CC <= BB AND TT;
END A0;
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Elaborate
Given this fragment, you could add the following lines to your command file to set
the SIZE parameter:
Elaborate -parameter_maps SIZE=4
Alias: -param_map
Specifies a scenario file.
Default: (none)
Alias: -scn
Adds the specified file or Tcl list of files to the list of Liberty technology files. You
can also use the ReadLibrary command to specify which Liberty libraries to read.
Default: (none)
Alias: -synlib
-system_verilog true | false
Treats all files in the Verilog startup file (specified with the -verilog_startup_file
option) to be System Verilog files.
Default: false
-tag_blocks true | false
Tags registers with the surrounding block name. These tags will be used later in
the MapRetentionCell command to control retention cell default cell selection.
Default: false
-top [library_name.]design_unit_name
Specifies the top-level module name. Note that the “library_name.” is only needed
for VHDL designs where the same design unit name is in multiple libraries.
Default: (none)
-verilog_2001 true | false
Enables recognition of Verilog 2001.
Default: false
-verilog_startup_file file_name
Reads in the specified startup file. You will most likely require this option for your
Verilog design. As an unlikely alternative, you may use the CompileFile command
to specify your Verilog files. We recommend only using this command for either
VHDL or mixed Verilog/VHDL designs. The Elaborate command recognizes and
expands UNIX environment variables that appear in this startup file. You can
specify environment variables either with brace delimiters as in “${VARNAME}” or
without, as in “$VARNAME”. If you do not use brace delimiters, the variable name
is considered to end with the last alpha-numeric or underscore (_) character.
Environment variables within comments are not expanded. If there is no definition
for a variable required in the startup file, an error is reported and the program will
terminate with error status.
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Elaborate
Default: (none)
Alias: -f
Uncommon Options
-case_insensitive true | false

Constructs a scenario database using case-insensitive name matching. By
default, the scenario database is constructed to be case sensitive if the design is
entirely in Verilog, or case insensitive if the design is VHDL or combination of
VHDL and Verilog.
Default: false
-case_sensitive true | false
Directs the Elaborate command to construct a scenario database using case-
sensitive name matching.
Default: false
-lower_case_vhdl true | false
Generates lower-case names for VHDL.
Default: false
-macro_directories directory1 directory2...
Specifies a Tcl list of directories that contain power macro models. The Elaborate
command searches these directories in the order listed, and the default directory
is searched last.
You can use the power-aware models in these directories to replace HDL models
without modifying your design source. See the Getting Your Design into
PowerArtist chapter in your user guide for more information about power
macros.
Default: $POWERTHEATER_ROOT/pthdl_src/macros
Alias: -macros
-min_regfile_bit_count int
Specifies a minimum bit count (words x length) of 2-D arrays to be preserved as
register files or latch files. For more information on using this option, see
Controlling Array Inferencing in the PowerArtist User Guide.
Default: 32
-min_regfile_word_count int
Specifies a minimum word count 2-D arrays to be preserved as register files or
latch files. For more information on using this option, see Controlling Array
Default: 8
-min_regfile_word_length int
Specifies a minimum word length of 2-D arrays to be preserved as register files or
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Elaborate

Default: 3
Default: false
option sparingly.
-no_default_macros true | false
Instructs Elaborate to not search for macros in the directory specified with the
-macro_directories option—not the default macros in the default
$POWERTHEATER_ROOT/pthdl_src/macros directory.
Default: false
-output_ascii_netlist file_name
Writes the netlist data to the specified ASCII file.
Default: (none)
Alias: -o
-preserve_regfile list | all
Specifies either a Tcl list of 2-D arrays to be preserved or all (all arrays will be
preserved). For more information on using this option, see Controlling Array
-quiet true | false
Default: false
-suppress_messages warn_num1 warn_num2 ...
suppressed. Note that the list of message numbers you supply will overwrite the
original list.
Default: (none)
Alias: -nowarn
Default: false
Alias: -wait
-work_library lib_name
Specifies the work library of the top design unit.
Alias: -wrk
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GenerateActivityWaveforms
This command runs vector analysis in batch mode. You need to have read in your
library files prior to running this command. Vector analysis supports two modes of
operation: clock cycle mode and time-based mode. In clock cycle mode, you need to
provide a reference clock and the clock cycles over which you want to perform the
analysis. This will produce a graph of activity as a function of clock cycles. In the
time-based mode, you provide the simulation time duration over which to perform the
analysis. This will produce a graph of frequency as a function of time. Use the -
activity_waveform_graph_type argument to specify the mode of operation.
Syntax for Clock-Cycle Mode
GenerateActivityWaveforms -activity_file file_name

-scenario_file file_name -top_instance inst_name
-activity_waveform_clock_name clock_name
-activity_waveform_clock_edge (pos | neg | auto)
-activity_waveform_cycles_per_interval int
-activity_waveform_graph_type activity_per_cycle
-activity_waveform_group_list group_list
-activity_waveform_number_of_intervals int | all
-activity_waveform_start_clock_cycle int
-ptcl_output_file file_name | -fsdb_output_file file_name
[-activity_waveform_log file_name]
Syntax for Time-Based Mode
GenerateActivityWaveforms -activity_file file_name

-scenario_file file_name -top_instance inst_name
-activity_waveform_graph_type frequency_per_interval
-activity_waveform_interval_size time
-activity_waveform_start_time time
[-activity_waveform_log file_name]
-ptcl_output_file file_name | -fsdb_output_file file_name
Arguments
Specifies the name of your VCD/FSDB/IAF file that will provide the toggle
information.
Alias: -iaf
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Default: (none)
Alias: -scn
-top_instance inst_name
Specifies the activity_file point that matches the -top you used to build the
scenario file.
Alias: -topinst
-activity_waveform_clock_edge (pos | neg | auto)
Specifies the clock edge on which the analysis will begin. You can start the
analysis on the first rising edge (pos), falling edge (neg) or first edge (auto) of the
reference clock.
Default: The default is pos (meaning positive or rising edge).
-activity_waveform_clock_name clock_name
Specifies the full path name of the reference clock. The name is based on the -top
option used to generate your scenario file and is not based on the -top_instance
used to control the starting point in your testbench.
-activity_waveform_cycles_per_interval int
Specifies the number of clock cycles that would turn into one (x,y) data point in
your activity graph.
Default: 1
-activity_waveform_graph_type activity_per_cycle |
frequency_per_interval
Specifies activity_per_cycle for clock cycle mode or frequency_per_cycle for time-
based mode.
Default: activity_per_cycle
Specifies a Tcl list of group names defined in by DefineGroup commands. These
represent the instances you want to monitor.
-activity_waveform_interval_size time
Specifies the length of your interval in time steps. The time is given as an integer
followed by one of the following standard time scale indicators: s = seconds, ms =
milliseconds, us = microseconds, ps = picoseconds, fs = femptoseconds, or as =
atoseconds.
-activity_waveform_log file_name
Specifies the log file name for activity file generation.
Default: Waveform.log
Specifies the number of intervals to be analyzed.
Default: all
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-activity_waveform_start_clock_cycle int
Specifies the clock cycle number that will form the starting point for the analysis.
The combination of activity_waveform_cycles_per_interval and
activity_waveform_number_of_intervals defines the finishing clock cycle.
Default: 0
-activity_waveform_start_time time
Specifies the simulation time step that will form the starting point for the analysis.
The combination of activity_waveform_interval_size and
activity_waveform_number_of_intervals defines the finishing time step. The time
is given as an integer with the same standard time scale indicators mentioned for
-activity_waveform_interval_size.
-activity_waveform_log file_name
Specifies the name of the log file to which information is written.
Alias: -log
Default: 1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309 8517
-fsdb_output_file file_name
Specifies the name of the FSDB file. You can view the resulting file in the using
the Apache Waveform Viewer (or the Verdi™ product from SpringSoft).
simulation data.
Default: false
Default: false
Specifies the name of the PTCL file. The PTCL file is a graphical file showing
power over time. You can view the resulting .ptcl file in the using the Apache
Waveform Viewer.
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-quiet true | false

Suppresses the printing of note-level messages.
Default: false
-synlib_files file_name1 file_name2 ...
Alias: -synlib
Uses RTL simulation data for gate-level power analysis. To use this feature, you
must have generated your activity file (GAF) using a name-mapped flow. For
details, see Name Mapping Flow.
Default: false
Alias: -wait
Example for Clock Cycle Mode
GenerateActivityWaveforms -activity_file my.fsdb

-scenario_file my.scn
-top_instance top
-activity_waveform_clock_edge pos
-activity_waveform_clock_name top.clk
-activity_waveform_start_clock_cycle 20
-activity_waveform_cycles_per_interval 10
-activity_waveform_number_of_intervals 1000
-activity_waveform_graph_type activity_per_cycle
-activity_waveform_group_list { top channels memory }
Example for Time-Based Mode
GenerateActivityWaveforms -activity_file my.fsdb

-scenario_file my.scn
-top_instance top
-activity_waveform_graph_type frequency_per_interval
-activity_waveform_group_list { top channels memory }
-activity_waveform_start_time 20us
-activity_waveform_interval_size 1us
-activity_waveform_number_of_intervals 1000
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GenerateEtclFile
GenerateEtclFile
This command generates Etcl files. You can use the arguments for this command as
pt_set variables (pt_set arg_name value) in your PowerArtist command file.
Syntax
GenerateEtclFile -etcl_file file_name -etcl_start_time time

-etcl_finish_time time -etcl_log file_name
[-mixed_sim_prob_estimation true | false]
[-ptcl_output_file file_name] [-scenario_file file_name]
[-synlib_files {file_name1 file_name2 ...}]
[top_instance inst_name] [-use_rtl_sim_data true | false]
Arguments
-etcl_file file_name
Specifies the name of final etcl file to be generated.
-etcl_start_time time
Specifies the start time for the activity window you want covered by the etcl file.
Standard engineering notation applies (for example, 10ns).
-etcl_finish_time time
Specifies the end time for the activity window you want covered by the etcl file.
-etcl_log file_name
Default: GenerateEtclFile.log
Alias: -log
Specifies the name of your VCD/FSDB/IAF file that will provide the toggle
information for the Etcl file. This file may either be for the gate-level design or an
RTL design if you are using an RTLSim2Gate flow as described for the
GenerateActivityWaveforms command.
If you are using the RTLSim2Gate flow, you must also do the following:
a. Supply the name map file in your command file before the GenerateEtclFile
command. This is required to map RTL names to your gate-level netlist. This
process is described in the Name Mapping Flow section.
b. Supply the “-use_rtl_sim_data true” option (as described for that option).
Enables mixed estimation.
Default: false
Alias: -mixed
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MapRetentionCell
Specifies the name of the ptcl file. The ptcl file is a graphical file showing power
over time. You can view this file in the Apache Waveform Viewer.
Default: (none)
Alias: -scn
-synlib_files file_name1 file_name2 ...
Adds the specified file Tcl list of files to the list of .lib technology files. The asterisk
wild card is allowed, and is expanded by the shell. You can also use the
Alias: -synlib
-top_instance top_module_name
hierarchy.
Default: (none)
Alias: -topinst
Uses RTL simulation data for gate-level power analyses. To use this feature, you
must have generated your activity file (GAF file) using a name-mapped flow.
Default: false
Alias: -rtlsim2gate
MapRetentionCell
This command forces PowerArtist to consider retention cells for power analysis. To
recognize retention cells in a Liberty file, PowerArtist uses two criteria:
 It must be defined as a flop or latch in a function statement or state table; and
 It must have a power_gating_cell attribute.
Generally, retention cells are not selected for power analysis by the default cell
selection algorithm. To force PowerArtist to consider retention cells in the design, you
must supply one or more MapRetentionCell commands.
The latest MapRetentionCell command in your Tcl file supersedes earlier
MapRetentionCell commands for particular instances. This allows you to create
generic rules and then override them later on with more specific rules.
Syntax
MapRetentionCell [-instance instance_name(s)] [-net net_name(s)]

[-attribute value] [-library lib_name(s)]
-tag tag_name] [-notag true] [-exclude inst_name(s)]
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MapRetentionCell
Arguments
-instance instance_name(s)
Specifies a Tcl list of instance names, each of which may contain wild card
characters. If you do not specify the -instance or -net argument, this command will
apply to all instances in the design.
-net net_name(s)
Specifies a Tcl list of net names that will be inferred as a register or latch. Each net
name may contain wild card characters. Supplying a net name allows you to
supply specific register bits to retention cell mapping, rather than having it take
effect over an entire begin block or process statement. If you use the -net
argument you will not use the -tag or -notag argument. If you do not specify the -
instance or -net argument, this command will apply to all instances in the design.
-attribute value
Allows you to specify the value for the power_gating_cell attribute that will be
used to determine candidate retention cells.
-cell cell_name(s)
Specifies a cell name or a Tcl list of cell names to be used as retention cells. You
can not use wild cards in the cell names. Note that you can select either -attribute
or -cell, but not both.
-library lib_name(s)
Specifies a library name or a Tcl list of library names from which the cell will be
taken. You can use this option only if you also use the -cell option.
-exclude inst_name(s)
Specifies an instance name or a Tcl list of instance names that do not need to
have retention cells. You can use wild cards for the instance names.
-tag tag_name
Specifies the names of begin blocks or process statements that control which sub-
portions of an instance will be controlled by the MapRetentionCell command. If
you do not supply a tag, then all registers and latches inferred by that instance will
be controlled by the attribute setting. If you want to include hierarchical instance
children as well, then you must use wild card characters in the instance name.
The tag name may contain wild card characters as well.
-notag true
Specifies that non-retention cells be used for tagged blocks while retention cells
be used for blocks that have no tags.
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MapRetentionCell
Example 1
MapRetentionCell -instance top.block1.domain1 -attribute CLK_LOW

For instance top.block1.domain1, for its registers and latches, PowerArtist will
choose among cells that have a power_gating_cell attribute whose value is
CLK_LOW.
Example 2
MapRetentionCell -instance top.block1.domain1.subblock1 -attribute

CLK_FREE
For instance top.block1.domain1.subblock1, for its registers and latches, PowerArtist
will choose among cells that have a power_gating_cell attribute whose value is
CLK_FREE.
Example 3
MapRetentionCell -instance top.block1.domain1.subblock1

-attribute CLK_HGH -tag tag1
All registers and latches inferred in top.block1.domain1.subblock1 that were tagged
with “tag1” will be mapped to retention cells that have a power_gating_cell attribute
whose value is CLK_HIGH.
Example 4
MapRetentionCell -instance top.block1.domain2.* -attribute CLK_LOW

-notag true
For instance top.block1.domain2 and all of its hierarchical children, for any begin
block (or process) that does not have a tag, choose among cells that have a
power_gating_cell attribute whose value is CLK_LOW. All other registers and latches
that are part of named blocks should use non-retention cells.
Example 5
MapRetentionCell -instance top.block1.domain1.subblock2

-attribute CLK_HGH -tag .*
For instance top.block1.domain1.subblock2, all registers and latches that have tags
(because the wild card .* will match all tags) will use cells that have a
power_gating_cell attribute whose value is CLK_HGH.
Example 6
MapRetentionCell -net top.block1.domain1.reg_out3 -attribute

CLK_HGH
In this example, the inferred register top.block1.domain1.reg_out3 will use cells that
have a power_gating_cell attribute whose value is CLK_HGH.
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MonitorArcs
Example 7
MapRetentionCell -cell DFF2 -library typical

In this example, the cell named DFF2 from library “typical” will be used as a retention
cell.
Example 8
MapRetentionCell -instance top -attribute CLK_FREE

-exclude {top.block4.* top.#67}
This example excludes instance top.#67 and all instances inside top.block4.
Example 9
MapRetentionCell -instance top -cell DFF1

-exclude {top.block1 top.block3}
This example excludes instances top.block1 and top.block3.
MonitorArcs
This command specifies the instances and cells for which GAF creation must monitor
the arcs during pin-based power analysis.
Note that arcs are always monitored for the following instances:
 IO pads
Syntax
MonitorArcs (-cells cell_names | -instances inst_names)
Arguments
-cells cell_names
The list of cell names for which you want power arc monitoring performed. These
cell names can be found in .lib libraries. Cell names can contain wildcard
characters. Separate multiple cell names with a space. You must specify either
this option or the -instances option.
Default: *
-instances inst_names
The list of hierarchical design names for which you want power arc monitoring
performed. names can contain wildcard characters. Separate multiple instance
names with a space.
Default: *
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MonitorFast
Example
In the following example, arcs are monitored during pin-based power analysis for
instances that are always monitored, instances that begin with the characters
tst.adder and test.exor, as well as cells that begin with the characters df or ld
are monitored normally. For all other cells and instances, monitoring of arcs is
suppressed.
MonitorArcs -instances {tst.adder* tst.exor*} -cells {df* ld*}
MonitorArcs -instances {TOP.#0}
MonitorFast
This command suppresses the generation of the summary report for the top-level
instance during gate-level power analysis when you are running “CalculatePower -
analysis_type time_based”. Only instances specified in MonitorInstances will be
included in the final report and waveform files. If you are only interested in certain
instances, using this command will significantly improve the performance of the
analysis run. The power for all the instances selected will be summed and be
covered in the Total Power section of the report.
Syntax
MonitorFast -status yes | no
Arguments
-status yes | no
If set to yes, only those instances specified by the MonitorInstances command will
be monitored. If set to no (the default) the top instance will be monitored along
with the instances specified in the MonitorInstances command.
MonitorInstances
When you are running the CalculatePower -analysis_type time_based option, this
command allows you to specify instances to be monitored, by groups or instance
name(s). You must specify either -group or -name options. Only instances specified
with this command are included in the final power report and waveform files. If you
do not specify this command, PowerArtist will, by default, generate a summary report
for your top-level instance.
Syntax
MonitorInstances (-group group_name(s) | (-name instance_name(s))

[-monitor_dynamic_trace yes | no] [-monitor_static_trace yes |
no] [-all yes | no]
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MonitorInstances
Arguments
-group group_name(s)
Specifies a group name. These groups are the same clustering of instances that
you see in the power analysis summary section. The legal group names are
Register, Latch, Memory, Other, IO, Clock, and InferredBuffer. By specifying group
names, you will get information summarized for all elements in the group. You can
use a Tcl set for group_name as well. Note that if you want clock power to be
reported when using a monitor instances file, you must include “Clock” in your -
group list.
Default: All groups will be printed along with the top-level instance report.
-name instance_name(s)
Specifies the names of one or more instances that you want to monitor. The
instance could be a hierarchical instance or a vendor gate. Remember that a
vendor gate is anything that has a power model associated with it. Therefore, for
example, it could be a memory, an IO pad or a simple cell like a nand gate. You
could also use Tcl sets for instance_name(s).
-monitor_dynamic_trace true | false
Generates a separate trace for dynamic power.
Default: false
-monitor_static_trace true | false
Generates a separate trace for static power.
Default: false
-all yes | no
Monitors the instances specified with the -name option and all of its children. Note
that in addition to yes/no, you could also use true/false or 1/0. If you use this
option, you must also specify the -name option. By specifying -all and -name
together, it means that from this point on down through the design hierarchy, all
instances are to be monitored. The instances are not only hierarchical modules,
but inferred elements and instantiated library cells as well.
Example 1
MonitorInstances -group memory

This command will generate information for all memories in your design as a class
and not as individual instances.
Example 2
MonitorInstances -group {memory register}

This command will generate output for two sets of information: memories and
registers.
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MonitorToggleInstances
Example 3
MonitorInstances -group clock

This command will generate a clock report. Unless you specify a clock group, you
will see no clock summary for your design.
Example 4
MonitorInstances -name top.core1

This command will generate output information for the hierarchical instance
top.core1. All children instances will have their values included in the information
generated for top.core1.
Example 5
MonitorInstances -name {top.core.alu top.core.sram8x64_01}

This command will generate information on top.core.alu (which in this example is a
hierarchical instance} and top.core.sram8x64_01 (which in this example is meant to
have a power model in a .lib for it).
Example 6
MonitorInstances -name top1.mid1.bottom1 -all yes

This command generates report information for all of the instances that are children
of top1.mid1.bottom1.
Example 7
MonitorInstances -name top1.mid1.bottom1

This command reports a combined number for top1.mid1.bottom1, but not a
separate line item for every descendent of it.
MonitorToggleInstances
This command is used to monitor flop clock activity.
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PrintActivityData
Syntax
MonitorToggleInstances -instances instance_name(s)
Example
MonitorToggleInstances -instances {top top.core1 top.core1.u1

top.core1.t1 top.core1.r1}
PrintActivityData
Used in conjunction with the GAF creation, this command generates a file containing
a condensed representation of all the toggle information on the ports of each
hierarchical instance as well as each memory instantiated in the design. PowerArtist
defines a hierarchical instance as any instance in the design that instantiates another
instance. Memories are recognized as vendor_gates that have a complex attribute,
memory, in their corresponding .lib files or are defined as memories using the
DefineMemory command. Note that vendor_gates that are not memories (as well as
inferred instances) are not included in the file.
To generate this file, simply specify this command followed by the CalculatePower
command.
Syntax
PrintActivityData -activity_file file_name [-frequency yes]
Arguments
Specifies the name to be given to the output activity file.
-frequency yes
Specifies that the data be output as a frequency in Hertz (instead of the default
activity data). In this case, the numbers will be in scientific notation.
Example
PrintActivityData -activity_file act.tcl

This command will generate a file named act.tcl, which will contain activity data.
Format of the Output File
The activity file is comprised of a series of ModuleActivity commands. Each

hierarchical instance or memory will have a corresponding ModuleActivity command,
which has the following format:
ModuleActivity module_type instance_name port_activity
where port_activity is a Tcl set where each member of the set is a set of two
elements: the port name and the activity value.
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pt_set
Sample Activity File
ModuleActivity TOP {TOP} { {d 0.2} {q 0.2} {clk 2} {reset 0} }

ModuleActivity dff_A {TOP.flop1} { {d 0.2} {q 0.2} {clk 2} {reset 0} }
In this sample file, there are two hierarchical instances in the design: TOP and
TOP.flop1. The hierarchical instance names are enclosed in curly braces {} to
prevent Tcl from evaluating their contents. This would otherwise cause problems in
the case of escaped Verilog identifiers or certain constructs in VHDL. The module
type of TOP is TOP and the module type of TOP.flop1 is dff_A. Each instance has
four ports: d, q, clk, and reset. The activity values are: 0.2, 0.2, 2, and 0, respectively.
Sample Application that Manipulates the Activity File
Because this file has a Tcl syntax, you can build a Tcl application that implements a
ModuleActivity process that post-processes this file. A sample application is to print
this file out with some simple diagnostic information. Suppose you have a file, act.tcl,
that contained the module activity data. To print the activity data, first create a Tcl file
called, for example, myprint.tcl. The file could contain the following lines:
proc ModuleActivity {type name ports} {

puts "Type = $type, Name = $name"
foreach port $ports {
set portName [ lindex $port 0 ]
set activity [ lindex $port 1 ]
puts "Port name = $portName, Activity = $activity"
}
}
source act.tcl
Then, from within any Tcl shell including ptshell, source the Tcl file:
source myprint.tcl
This would print out the data.
pt_set
You can specify arguments listed for the CalculatePower, CreateGraph, Elaborate,
GenerateActivityWaveforms, GenerateEtclFile, ReadLibrary, ReadSDC,
ReadVerilogStartupFile, ReducePower, ReportReductions, RewriteRTL and
WriteClockGatingConstraints commands using the pt_set command. You can think of
the pt_set command as an alias for the Tcl “set” command that does basic checking
on the values of the variables that you are setting. For example:
pt_set clock_frequency 1e06

pt_set elaborate_log myelaborate.log
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pt_set
Also, you can specify your Liberty technology files as a Tcl list to the appropriate
pt_set variables:
pt_set synlib_files {../libs/hvt1.lib ../libs/lvt.lib ../libs/
retention.lib}
The pt_set command does two different types of checking.
1. If you specify a variable name that does not correspond to the list of legal
variables, it generates a warning like the following:
ptshell % pt_set suppress_warnings grbx
'suppress_warnings' is not a valid PowerArtist variable
2. If you specify a value that is not appropriate for a legal variable, it generates a
warning like the following:
ptshell% pt_set suppress_messages grbx
'grbx' is not of the required type (integer)
Also, if a file is expected to exist and is not readable, it generates a warning like the
following:
ptshell: pt_set capacitance_file foo.cap
capacitance_file: file 'foo.cap' is not readable
Specifying the pt_set command with a variable name but without an appropriate
value, will return the current value of the variable, such as:
ptshell% pt_set suppress_messages {1017 1093 1213 1217}
ptshell% pt_set suppress_messages
1017 1093 1213 1217
As with the Tcl set command, pt_set overwrites the previous value. For example:
ptshell % pt_set suppress_messages {1017 1093 1213 1217}

ptshell % pt_set suppress_messages
1017 1093 1213 1217
ptshell % pt_set suppress_messages {1275 1471 1351}
ptshell % pt_set suppress_messages
1275 1471 1351
The big advantage is that by using pt_set, if you are running similar commands one
after the other, you only have to specify the option once using pt_set. For example,
common options for two different iterations of the CalculatePower command could be
specified using the following pt_set variables:
ptshell % pt_set analysis_type average

ptshell % pt_set detailed_vertical_report true
ptshell % pt_set default_output_load 3.9e11
ptshell % pt_set use_scan_flops true
ptshell % pt_set wireload_library scmetro_cmos10lp_hvt_ff_1p1v_125c
ptshell % pt_set compress_gaf true
ptshell % pt_set start_time 6us
ptshell % pt_set finish_time 12us
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pt_reset
ptshell % pt_set gaf_file txrx.gaf

ptshell % pt_set activity_file ../sim/rtl/activities.vcd
ptshell % pt_set top_instance txrx_tst.top1
To get a list of pt_set variables, use the following command:

% ptshell –cmd “pt_set”
You can pipe the resulting list to the “more” command:
% ptshell -cmd pt_set | more
pt_reset
This command removes any prevous setting and reverts to the default value for the
specified variable.
Syntax
pt_reset variable_name
ReadLibrary
This command specifies your library files in Liberty format. If you specify such a large
number of ReadLibrary commands that the command line generated to perform an
elaboration, power calculation, power reduction or rewrite would exceed the Unix
limits on command-line size, PowerArtist automatically generates a file called
ptshell.libs.opts that contains the Liberty library names. This file then gets referenced
using the -i option to various commands.
Syntax
ReadLibrary -name file_name
Arguments
-name lib_file_name
Specifies the path name to the library file from the current working directory.
ReadParasitics
This command associates a given SPEF file with a specific hierarchical instance in
the design. The instance name must be fully rooted (that is, it must contain the top
module name). Also, in PowerArtist, periods (.) separate levels of hierarchy.
If you want to use a flow that follows SPEF back-annotation methodologies
established by Synopsys’ PrimeTime™ product, then you need to include this
command in your command file (Tcl script).
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ReadSDC
Syntax
ReadParasitics -path hierarchical_inst_name -file SPEF_file_name
Arguments
-path hierarchical_inst_name
Specifies the hierarchical path to an instance that you want to associate with the
given SPEF file.
-file SPEF_file_name
Specifies the SPEF file to be associated with the given hierarchical instance.
Example
ReadParasitics -path mydesign -file ../spef/mydesign.spef

ReadParasitics -path mydesign.mymodule0 -file ../spef/
mymodule.spef
ReadParasitics -path mydesign.myblock1 -file ../spef/myblock.spef
ReadSDC
This command parses Synopsys Design Constraints (SDC) files, version 1.7, and
generates a new command file script for use with PowerArtist. ReadSDC uses the
following SDC commands to gather information on constraints:
create_clock set_clock_transition
create_generated_clock set_ideal_network
get_clock set_ideal_transition
get_clocks set_input_transition
get_net set_load
get_nets set_max_fanout
get_pin set_propagated_clock
get_pins set_unit
get_port set_units
get_ports set_wire_load_mode
set_clock_gating_check set_wire_load_model
If you have any of the get* commands in your SDC file, you will need to specify a
power database (.pdb). These commands are used to search a power database file
for the appropriate objects and then act on them.
The ReadSDC command also parses the following commands:
set_case_analysis set_logic_one
set_logic_zero
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ReadSDC
These commands are translated into SetNetStimulus commands and placed into a
vectorless activity (.vaf) file named ReadSDC.vaf. In addition, the ReadSDC file will
add the following line to the output command file:
pt_set vectorless_activity_file ReadSDC.vaf
which points to the newly created VAF file.
After parsing the information from the supported SDC commands, ReadSDC
translates this information into equivalent PowerArtist command file format, which
uses the following commands:
 SetClockNet
 SetDefaultFanout
 pt_set default_transition_time float
 pt_set transition_time_file slopes_file
 pt_set capacitance_file load_file
 SetWireLoadMode
 SetWireLoadModel
Flow for Processing SDC Files with an Analysis Run
When you process an SDC file, generally there is not enough information extracted
to perform a correct power analysis because there is not enough clock information
extracted. For example, PowerArtist can determine the clock net name and its
frequency and whether it should be inferred or traced. However, when it is inferred
you need to specify whether or not you want clock gating performed. If clock gating
is to be performed, you need to supply clock gating constraints. Therefore, you
should use the following flow:
1. Translate your SDC file
2. Review and edit the file to correct or potentially add clock information
3. Source the resulting file in your top-level scripts using the Tcl “source” command.
You can use the arguments for the ReadSDC command as pt_set variables (pt_set
arg_name value) in your PowerArtist command file (see Alphabetical List of pt_set
Variables).
Determining Default Units
If your SDC file does not include the set_units command, PowerArtist uses the first
.lib in the Liberty search list to determine the units. Whenever you create a PDB file,
PowerArtist stores the units defined in the first .lib file. Then when you specify the
-power_db_name option to ReadSDC, PowerArtist reads in the power database,
retrieves the options used during the SDC file processing and generates messages
in the ReadSDC.log file to let you know this is occurring. You will recognize this
situation when you see messages 9669 and 9677. Message 9699 is a note that tells
you that set_units is not found in the SDC file. Additionally, message 9677 is a note
that tells you the library units being used.
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ReadSDC
Sample Notes
9669 NOTE test4.sdc, line 9: command set_units not found in SDC file(s)..
9677 NOTE test4.sdc, line 9: Using library units "-current 0.001 -time 1e-09
-capacitance 1e-12 -power 1e-06 -resistance 1000
-voltage 1".
Handling the set_max_famout SDC Command

If your SDC file contains a set_max_fanout constraint, it will be translated into a
SetDefaultFanout command. For example,
set_max_fanout 3 {myRtl2} translates to SetDefaultFanout -instance
{myRtl2} -fanout 3
Syntax
ReadSDC -sdc_files {file_name1 file_name2 ...}

-top top_inst [-sdc_command string]
[-transition_time_file file_name] [-capacitance_file file_name]
[-sdc_clocks_gated auto | true | false]
[-sdc_clocks_mode auto | infer | trace]
[-sdc_out_file file_name] [-sdc_log file_name]
[-power_db_name file_name]
Arguments
-sdc_files {file_name1 file_name2 ...}

Specifies a Tcl list of SDC files that you want to parse.
-top top_inst
Specifies the top instance in the design. By default, the analysis tools try to
determine a -top automatically. If you know the -top value, which should have
been specified for your Elaborate command, then you should specify it here.
-sdc_command string
Specifies an SDC command name that PowerArtist then evaluates before parsing
the SDC files specified with the -sdc_files option. You can use this option to add
information that is missing from the SDC files.
Specifies the output transition time file. You can specify this file in subsequent
PowerArtist sessions.
Alias: -tt
Writes out the specified file as a back-annotated inter-module wire capacitance
file. See Capacitance File Format for more information.
Default: (none)
Alias: -c
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ReadSDC
-sdc_clocks_gated auto | true | false

Controls the -gate_clock option of the SetClockNet command written in the
resulting output file. If you specify this option without a value or you do not specify
it, translation rules are applied to determine the value of the SetClockNet option;
otherwise the value of this option is copied directly to -gate_clock option of the
SetClockNet command.
-sdc_clocks_mode auto | infer | trace
Controls the -mode option of the SetClockNet command written in the resulting
output file. If you specify this option without a value or you do not specify it,
translation rules are applied to determine the value of SetClockNet option;
otherwise the value of this option is copied directly to the -mode option of the
SetClockNet command.
-sdc_out_file file_name
Specifies the name of the output command file. You can source this file in
subsequent PowerArtist sessions.
Default: ReadSDC.scr
-sdc_log file_name
Specifies the name of the log file that will collect all error, warning and note
messages generated by this command.
Default: ReadSDC.log
Reads in the specified power database file. If you want to use a PDB file, you
must specify the name of that file with this option. The is equivalent to the pt_set
power_db_name command.
Alias: -pdb
Example 1
ReadSDC -sdc_files {clocks.sdc exceptions.sdc boundry.sdc} -top

rx40 -power_db_name rx40.pdb -sdc_out_file rx.scr
This example reads in three SDC files (clocks.sdc, exceptions.sdc and
boundary.sdc) with a top instance name of “rx40”. PowerArtist opens and reads
power database rx40.pdb to validate netlist information and to support more
advanced SDC features, such as -hierarchical, wildcard matching etc.) of SDC.
Finally, it writes out rx.scr along with transition time and a capacitance file.
Example 2
ReadSDC -sdc_files design.sdc -power_db_name design.pdb

-sdc_out_file test2.out -sdc_command {set_unit -time ns
-capacitance fF}
This example sets time units in nano-seconds and capacitance units in femto Farads
(sdc 1.7 units default to MKS system). These units are applied to other SDC
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ReadVerilogStartupFile
commands such as set_ideal_transition, set_clock_transition, set_input_transition

and set_load.
Sample set_case_analysis and Their Translations
set_case_analysis 0 clk translates to SetNetStimulus -net clk -duty 0

-frequency 0
set_case_analysis 1 rst translates to SetNetStimulus -net rst -duty 1

-frequency 0
set_logic_zero en translates to SetNetStimulus -net en -duty 0

-frequency 0
set_logic_one clr translates to SetNetStimulus -net clr -duty 1 -

frequency 0
A duty cycle of 1 or 0 means that the value remains constant. A frequency of 0
reinforces that the signal is not toggling at all.
PowerArtist analyzes the create_clock and create_generated_clock commands to
create SetClockNet commands and the values for the SetNetStimulus command for
the clocks you define.
Sample create_clock Command and Its Translation
create_clock -name clk -period 50 -waveform {0 5} [get_port Pclk]

translates to:
SetNetStimulus -net {Pclk} -frequency 2e+07 -duty 0.1
ReadVerilogStartupFile
This command specifies the name of your Verilog startup file. This is the file that you
would supply to the Elaborate command using the -verilog_startup_file option. This
command is available for those users who are familiar with the way other EDA
products define their Verilog files.
Syntax
ReadVerilogStartupFile file_name
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ReducePower
ReducePower
This command performs power reduction. For details on running power reduction,
see PowerArtist Tutorial Part II: Power Reduction in the PowerArtist User Guide.
You can use the arguments for this command as pt_set variables (pt_set arg_name
value) in your PowerArtist command file.
Syntax
ReducePower -scenario_file file_name

(-vectorless_input_file file_name | -activity_file file_name)
-finish_time string -start_time string -gaf_file file_name
[-options...]
Common Options
-default_dont_use_cells file_name
process. The format of the file is as follows:
cell_name library_name
Sample File
DFFRX1 typical_13
TLATX1 typical_13
Note: this option is obsolete. You should use the SetAttribute command instead.
-default_output_load float
Sets the default output load to the specified value. This load capacitance is
applied to all primary outputs not listed in the load or wiring cap files (specified
using either the -capacitance_file or -load_file options).
Default: 0
Alias: -dl
specified.
Alias: -dt
-detailed_vertical_report true | false
Default: false
-domain_frequency_cell_selection true | false
When set to true, this option activates frequency-based cell assignment. There is
no default value for the -domain_frequency_cell_selection option. When combined
with the -frequency option to the SetClockNet command, this option determines
when frequency-based cell selection occurs. Frequency-based cell selection
occurs in either of the following two situations:
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ReducePower
 -domain_frequency_cell_selection is specified and set to true.

 -domain_frequency_cell_selection is not specified at all and -frequency is
Default: (see description)
-finish_time string
activity file.
Alias: -finish
-gaf_file file_name
by processing the -activity_file argument during an average power calculation.
The average power calculation engine then reads in this file. This argument is
required.
Default: (none)
Alias: -a
-use_existing_gaf true | false
When set to true, PowerArtist re-reads an existing GAF stimulus file during
simulation-based average power analysis. This allows you to perform what-if
experiments without re-reading your stimulus file, which can be time-consuming.
Default: false
simulation data.
Default: false
-arc_based_estimation true | false
When set to true, enables arc-based power estimation for gate-level instances in
the design. By default, PowerArtist uses pin-based power estimation, which is
significantly faster than arc-based power estimation but slightly less accurate. By
default, arcs are still monitored for the following instances:
 IO pads
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ReducePower
Additionally, even if you do use the default pin-based estimation, you can enable
arc monitoring for specific cells and instances using the MonitorArcs command.
Default: false
Specifies a PACE technology file for capacitance estimation. Capacitance
estimation using PACE overrides capacitance estimation using wire load models,
whereas other capacitance annotation methods override capacitance estimation
using PACE. For more information, see Using PACE Technology Files During
Power Analysis (Beta).
-print_missing_sim_nets true | false
Prints the names of nets that are in your scenario file but are not in your
simulation file.
Default: false
-quiet true | false
Suppresses the printing of note-level messages.
Default: false
-reduction_classes list_of_reduction_classes
Specifies the type (or “class”) of reduction to run. By default, all classes are run.
The available classes are:
 linter, which includes: Memory Power Linter, MUX Power Linter, Register
Power Linter, and Clock Enable Condition Linter
 logic, which includes: Datapath Operator Isolation
 memory, which includes: Split Memory Words, Gate Memory Clock
Note: For SplitMemoryWords to run, you must specify the following environment
variable:
PT_APPLY_SMW 1
 clock, which includes: Prism, Local Explicit Clock Enable, Low-Activity Non-
Enabled Register, and Observability Don't Care
 all, which includes all PowerBots.
If you want to exclude a class, for example, clock, you can specify this option and
simply exclude that class name from the specified list. To further fine-tune your
reduction, you can use this option in conjunction with the -skip_reduction_list
option. For example, you could do the following:
ReducePower -reduction_classes clock -skip_reduction_list prism
Given these settings, PowerArtist will only run the LEC, LNR and ODC
PowerBots.
Alias: -classes
-reduction_cpf_in_file file_name
Specifies an input file for reduction that contains multiple voltage domains and
power gating design intent constraints in the Common Power Format (CPF). For
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ReducePower
details, see Using a CPF Input Flow (Beta) in the PowerArtist User Guide.
Alias: -cpf
-reduction_cpf_output_file file_name
synthesize the design and capture all of the information required to synthesize or
place and route your design. For details, see Using a CPF Output Flow (Beta) in
the PowerArtist User Guide.
-reduction_debug_flags string
Specifies debug flags. For a list of available debug flags, see the pt_set
reduction_debug_flags variable.
-reduction_dont_touch_clocks {clock_net1 clock_net2 ...}
Specifies a list of clock domains that you want to analyze but prevent from being
automatically rewritten. This option interacts with the SetClockNet -gate_clock true
| false option. For details on the effects of this option, see Controlling Clock
Domains During Reduction.
-reduction_dont_touch_modules {module_name1 module_name2 ...}
Specifies a list of modules to exclude from reduction analysis. You cannot use wild
cards in for the module names. The names are the base module type names
before parametrization creates unique names. For example, suppose you have a
parameterized module named “block”. You then instantiate block in the following
manner:
block #(4) blk1(....);
The inferred module type name becomes block(SIZE=4). To prevent block from
being considered for reduction and rewrite, you would specify the following
command:
ReducePower -reduction_dont_touch_modules block
This also affects the rewrite process.
Alias: -dont_touch
-reduction_hierarchy none | full
Controls whether reduction opportunities are allowed to cross hierarchical
boundaries. If you set this to “full” the reduction engine will attempt to find as many
opportunities as possible that don’t cross hierarchical boundaries (for example,
Prism will break register chains at module boundaries and attempt to start a new
chain with a generated enable). If optimization across a boundary is not possible,
the opportunity is still saved for you to see in the GUI but it is not auto-accepted.
The default value for this option is “none” because RTL rewrite does not currently
make RTL changes that cross hierarchical boundaries.
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Default: none—reductions can’t cross hierarchical boundaries

Alias: -hierarchy
-reduction_log file_name
Specifies the name of the log file for reduction analysis.
Default: ReducePower.log
Alias: -log
-reduction_max_bit_width int
Specifies the maximum bit width of a register from which an enable will be
generated. Currently the only enable generation method that uses this parameter
is LNR to prevent XOR/OR trees from becoming too large.
Default: 16
Alias: -max_bit_width
-reduction_max_memory_split int
Specifies the maximum number of memory splits allowed by the SMW PowerBot.
By default, ReducePower will attempt to split a memory into two equal-sized
memories. You can increase the value of this option to allow ReducePower to
attempt to further split the original memories, although doing so could result in
significant routing congestion and area penalties. For more information, see the
detailed description of the Split Memory Words PowerBot in the PowerArtist User
Guide.
Default: 2
Alias: -max_mem_split
-reduction_memory_disable_edge_detection true | false
If you don’t want to determine if the address lines have not changed from one
read access to the next, set this option to true. The detection circuit inserts an
XOR-based circuit.
Default: false
-reduction_min_bit_width int
Specifies the minimum bit width for ungated registers. Ungated registers must be
greater than or equal to the minimum bit width value to be considered as a
candidate register. Specifies the minimum bit width for generating XOR enables as
part of the Prism powerbot.
Default: 3
-reduction_overwrite_power_db true | false
If set to true, overwrites the existing power database (.pdb) file. By default,
PowerArtist incrementally updates the reduction data for all the reductions that are
enabled without updating the average power numbers calculated from the
previous run.
Default: false
Alias: -overwrite_pdb
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-reduction_priority skew | power

Controls the way clock gating is performed in a reduction run. If you select “skew”,
PowerArtist will either include all bits of a register bank for clock gating or none.
This could reduce your power savings, but also minimizes clock skew between
bits of the same register bank. If you are concerned about minimizing clock skew,
select this option. If you select “power” PowerArtist clock gates only those bits that
save power—without regard to the impact on clock skew. This option works with
the LNR and ODC PowerBots. Note that the LEC PowerBot is always set to
“skew”. The value of this option is displayed in the header of the .red file.
Default: skew
Alias: -priority
-reduction_report_file file_name
Generates both a reduction report file and a clock gating reduction report file for
reduction analysis with the specified file name. The clock gating report will append
a “_cg” to the base name of report file name you specify. For samples of both of
these files, see Reviewing the Output Reports in the PowerArtist User Guide.
Default: (none)
Alias: -rpt
-reduction_report_options string
register or latch or memory or any other sequential device. The clock power
component is obtained from Liberty vectors modeling just a rise or fall on a
clock pin, which may or may not be qualified by a boolean expression.
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Examples are:
(01 CLK), (01 CLK || 10 CLK), (01 CLK && CS)
d Shows only new deltas on parents in power diff.
e Uses scientific notation.
i Indents hierarchy.
r Uses relative percentages in power diff section.
u Excludes vendor gates from power and area reports. Note that this option is not
available from the GUI).
v For gates, the is option replaces gate name with vendor_gate in the report.
frequency and glitch information (using the -r g option).
Default: (empty)
Alias: -r
-reduction_results_file file_name
Writes power reduction data to the specified results file. This file is needed to use
-compare_with_results option.
-reduction_topology true | false
Controls whether PowerArtist considers power when determining if a reduction
opportunity should be automatically accepted. When set to true, the algorithms for
the Prism and ODC PowerBots will not take power into consideration when
determining whether or not to accept a reduction opportunity.
Default: false—a reduction opportunity is considered only if the total power
savings is positive.
Alias: -topology
-reduction_upf_in_file file_name
Specifies a UPF file as input for power reduction analysis. This is a beta flow.
-save_clock_trees_netlist true
Generates power database schematics for the clock tree in the design.
Default: false
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-save_x_nets_file file_name
Sample Output
count.n29 1 0.000000011000
count.n46 2 0.000000034000
Note
-allowed_x_time to a value that is most appropriate for the simulation. For
example, a reasonable setting might be the period for several clock cycles.
Alias: -save_x_nets
Specifies a scenario file. If you’re in composite mode, this specifies the root from
which PowerArtist will search for other scenarios.
Default: (none)
Alias: -snc
-skip_clock_analysis true | false
Allows you to run PowerArtist without a SetClockNet command. When set to true,
the clock file is ignored. The default for this options is false. The following
conditions will print warning/error messages:
Error: Neither a SetClockNet command nor a
skip_clock_analysis option is specified. One of them is
required.
 If you set this option but you did not specify at least one SetClockNet
command, you will get the following warning message:
Warning: No SetClockNet command is specified. A
skip_clock_analysis option is specified. Therefore, clock tracing
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and inferencing analysis will be disabled. Unless the design has

clock trees instantiated, inaccurate results may occur.
 If you specify both a skip_clock_analysis option and a SetClockNet command,
Warning: A SetClockNet command and the skip_clock_analysis option
have been specified. Therefore, ignoring the skip_clock_analysis
option. Clock tracing and/or inferencing will be performed.
-skip_reduction_list reduction_type
Specifies a Tcl list of reduction types you want to skip.
Available reduction types (PowerBots) are:
cec: Clock Enable Condition Linter
doi: Datapath Operator Isolation
gmc: Gate Memory Clock
lec: Local explicit clock enable
lnr: Low-Activity Non-Enabled Register
mem: Memory Power Linter
mux: MUX Power Linter
prism: Prism
reg: Register Power Linter
smw: Split Memory Word
Default: smw (the SMW PowerBot is not run by default). If you want to run SMW,
you need to specify this option with an empty list, such as:
-skip_reduction_list { }
Furthermore, if you want to disable other PowerBots and the SMW PowerBot, you
need to list all of them explicitly, for example:
-skip_reduction_list {smw odc}
Alias: -nored
-start_time string
Starts collecting data at the specified string. If string ends with the letter “s”, it
Default: If you don’t specify -start_time, then analysis begins at the first simulation
time stamp in your activity file.
Alias: -start
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-suppress_messages {warn_num1 warn_num2 ...}

suppressed. Note that the list of message numbers you supply will overwrite the
original list.
Default: (none)
Alias: -nowarn
Alias: -synlib
-top_instance top_module_name
hierarchy. This should correspond to the module specified with Elaborate -top
Default: (none)
Alias: -topinst
Back-annotates transition times (slews) for nets and pins from the specified file.
For more information, see Transition Time File Format.
Default: (none)
Alias: -tt
When set to true, stores cell libraries by file name rather than by the logical library
name inside the Liberty file. Whenever you specify a library name, it is interpreted
as a file name rather than the name inside the .lib that has the line “library
logical_library_name {....}”. This option is required if you have multiple library
files that share the same logical library name.
Default: false
Default: false
-vectorless_input_file file_name
Reads the specified file as a Vectorless Activity File (VAF).
Alias: -vectorless_input
-vertical_report_instances {inst1 inst2 ...}
Produces a vertical report that provides summary information for the specified list
of instances. Note that vertical reports do not include instances that are reported
as part of clock tree power.
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-voltage float
Sets the design voltage to the specified value.
Default: none
Alias: -v
Default: false
Alias: -wait
Uncommon Options
#0
0$
#10
x$
#20
0$
#30
x$
#40
0$
#50
x$
#60
0$
#70
x$

simulator ticks.
Default: 10ns
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Specifies an amount of time a net can be in an Z state. If string ends with the
letter “s”, it is specified as time, otherwise it is specified in simulator ticks. The nets
that exceed the allowed time in the Z state are reported in a text file (see -
ftn_report).
Default: 100ns
Default: (none)
Alias: -c
-check_synlib_semantics true | false
Performs semantic checks on specified Liberty files.
Default: false
-compare_with_results file_name
Reads the specified result file and prints a report section showing the difference in
power between the result file and the current analysis.
Alias: -diff
-count_glitches_as_toggles true | false
In average mode, counts zero-duration glitches as toggles.
Default: false
current list of critical messages. If you want to maintain the default list and simply
add to it, you must include the message IDs that are considered critical by default.
Default: "1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309
8517"
-current_output_file file_name
default).
-debug_instances_file file_name
-xdebug_switches
...
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-disable_glitch_propagation true | false

Default: false
Alias: -g
-enhanced_vcd true | false
Reads the IAF file as an Enhanced VCD format file. See Acquiring Simulation
Data in the PowerArtist User Guide for more information about IAF and Enhanced
VCD.
Default: false
Alias: -vcde
-forced_x 0 | 1
-ftn_report_file file_name
(FTN).
Default: (none)
Alias: -ftn_report
-heartbeat string
Prints progress information during GAF file creation. he specified string (in
simulation time units) is taken as the time between emitting progress messages. If
string ends with the letter “s”, it is specified as a fraction of simulation seconds;
otherwise it is considered to be simulation ticks.
For example, if the time scale for your simulation results is 10 ns. Specifying
“pt_set heartbeat 1” will print a progress message every 10 ns of simulation time.
If you specify “pt_set heartbeat 20ns”, you will get a heartbeat message
approximately every 20 ns of simulation time.
must have simulation signal change results in your IAF file that occur
Default: (none)
-html_report_directory dir_name
Specifies a collection directory that allows for the organization of HTML reports
from various executions or designs, into a single HTML page. You can collect all
HTML reports in a central location. This option writes HTML files into the specified
directory. The top-level file is named index.html. This option must be used with the
-average_html_report_title argument.
Default: (none)
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-ignore_SPEF_C_comments true | false

Default: false
-ignore_toggles_through_x true | false
Default: false
Alias: -ix
-instance_power_threshold float
power report.
Alias: -e
-interpret_pin_caps_as min | max | avg
Instructs PowerArtist to use the rise_capacitance_range and
fall_capacitance_range attributes to calculate pin capacitances. The actual pin
capacitance values are calculated in the following manner:
For more information on how pin capacitance is calculated, see Transition
Counting on Nets.
Alias: -pin_caps
-library_defaults_file file_name
Specifies a Sequence Library Defaults (SLD) file.
-load_file file_name
Specifies a load file that contains load capacitance for any primary outputs in the
design.Alias: -l
-max_bit_width bit_width
generated. Currently the only enable generation method that uses this parameter
is LNR to prevent XOR/OR trees from becoming too large.
-max_clock_depth int
Limits forward clock-tracing depth to the number specified. Prevents excessive
time spent in forward tracing.
Default: 40
-maximum_number_of_errors int
Maximum number of errors to be printed in any given message.
Default: 50
Default: false
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option sparingly.
-no_module_net_capacitances true | false
Disables estimation of inter/intra-module net capacitances. This option only
impacts estimation, not annotation, of wire parasitics.
Default: false
Alias: -n
-no_slew_calculation true | false
An internal slew calculator is enabled by default in all power engines of
PowerArtist. This option disables this slew calculator.
Default: false
Alias: -noslewcalc
-pc_constraint_file file_name
Specifies the name of the file into which PowerArtist will write out
set_clock_gating_signals commands. You can then use this file in a synthesizer.
For information, see Rewriting Your RTL in the PowerArtist User Guide.
-reset_library_negative_power true | false
On an arc-by-arc basis, after the power computation for an arc is done, if its power
is less than 0, this option sets it to 0.
Default: false
-reset_negative_power true | false
Default: false
-stimulus_processing_passes integer
run time. The higher the integer value provided, the longer the run time and
smaller the memory footprint.
Range: 2 to 10
Alias: -split
Default: false
-voltage float
Sets design voltage to the specified value.
Default: (none)
Alias: -v
-wireload_library lib_name
Specifies the logical Liberty library name in which a power analyzer will search for
wire load models. This is useful when reading in multiple libraries that could
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RefineConfigurationParameter
contain wire load models. This option is obsolete, use the SetWireLoadModel
command instead.
RefineConfigurationParameter
This command allows you to set the specific default cell to be used for any of 9
combinations of load and frequency. This command gives you more explicit control
over your default cells than the SetConfigurationParameter command. For each cell
type, you will normally choose either to use the SetConfigurationParameter or the
RefineConfigurationParameter. If you use both, then the SetConfigurationParameter
command provides the defaults for any of the 9 ranges that are missing in the
corresponding RefineConfigurationParameter command.
Syntax
RefineConfigurationParameter load_frequency_range cell_type

cell_name library
Arguments
load_frequency_range
Specifies one of the following: LowFast, LowNormal, LowSlow, MidFast,
MidNormal, MidSlow, HighFast, HighNormal, HighSlow.
cell_type
One of the 6 required cell types or 4 optional cell types that you are defining as a
default cell.
The required cell types are:
 DefaultFlop—Default flip-flop cell without clear (you can use the
DefaultFlopWithClear instead).
 DefaultInv—Default inverter.
 DefaultMux—Default 2-input encoded multiplexor (2 data inputs, 1 select input).
 DefaultNand—Default 2-input Nand cell.
 DefaultXor—Default 2-input Xor cell.
 DefaultLatch—Default latch cell.
The optional cell types are:
 DefaultFlopWithClear—Default flip-flop cell with clear. You can use this
parameter instead of the DefaultFlop parameter.
 DefaultTriStateDriver—Default tri-state buffer (1 data input, 1 active-high enable
input).
 DefaultFullAdder—Default full adder cell (3 inputs (A, B, Cin) and 2 outputs
(Sum, Cout)).
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remap
 DefaultPassGate—Default passgate used in datapaths instead of a tri-state

driver.
cell_name
Specifies the actual cell name from a Liberty library.
library
The logical library name.
remap
This command directs GAF creation to apply the simulation waveform from the first
signal to the second signal. This command has two different syntactical forms.
Syntax 1 can be used to do a direct re-mapping of the simulation waveform. In
Maxsim (and some other SystemC simulators), control signal traces are not
represented as they would appear in an event-based RTL or gate-level simulation.
Specifically, these signal value changes may be asserted some time before the
corresponding RTL signal is to change, and the de-assertion of the these signals
may not appear in the value change dump file. Syntax 2 provides a means of
correcting the mapping.
Syntax 1
remap –from path_1.signal_1[range1] -to path_2.signal_2 [range2]
Syntax 2
remap -from path_1.signal_1[range1] -to path_2.signal_2 [range2]

[-assert_after time_value] -deassert_after time_value
-deassert_value simulation_value
Arguments
–from path_1.signal_1[range1]
Specifies the signal from which the waveform will be taken. The specified path_1
is the hierarchical scope that contains signal_1 in the VCD file. The signal must be
either a vector or a scalar. If they it is a vector, then the vector range must be
specified after the signal name.
-to path_2.signal_2 [range2]
Specifies the signal to which the waveform will be applied. The specified path_2 is
the hierarchical scope that contains signal_2 in the scenario database. The signal
must be either a vector or a scalar. If they it is a vector, then the vector range must
be specified after the signal name.
-asssert_after time_value
Delays all change records to the specified RTL signal by the specified time value.
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remap
-deassert_after time_value
-deassert_value simulation_value
If -deassert_after and -deassert_value are specified (they must be specified
together), the simulation_value will be deposited to the RTL signal by the
given time_value after the assertion occurs for each value change encountered.
If -assert_after is not specified, then the assertion occurs at the simulation time
specified in the VCD file. Note that time_value is an integer quantity of simulation
time, in the same units as appears in the VCD trace file; and simulation_value is a
valid scalar or vector simulation value.
Example 1
remap –from {arm926ej-s[0]::dahb<-->D-BUS::bslave0.addr[31:0]}

-to {CPU_BLK.inst_AHB_SYS.inst_ARM_CORE.wDHADDR[31:0]}
This example directs GAF creation to apply stimulus data from the addr signal in the
VCD file to the wDHADDR signal in the scenario file database. First, GAF creation
will check that these signals are present in the VCD and scenario file respectively.
The signals must include a bitrange specification of the form [l_index:r_index] or a
bitselect specification [index], if they refer to a vector or vector bit respectively.
As the square bracket characters ([]) have special meaning in Tcl, these must be
escaped using braces ({}) or the backslash character (\) to disable their syntax
interpretation in the Tcl interpreter.
Example 2
remap –from {arm926ej-s[0]::dahb<-->DBUS::bslave0.ctrl[4:5]}

–to {CPU_BLK.inst_AHB_SYS.inst_ARM_CORE.wDHTRANS[1:0]}
This example maps the two specified bits from the ctrl signal trace from SystemC to
the wDHTRANS wire in the scenario database.
GAF creation will allow you to map a SystemC signal or vector to any number of
HDL signals in the scenario database, but will only allow at most one SystemC signal
to be mapped to the same HDL signal.
If a required signal is not found in the VCD file or scenario database, GAF creation
will report an error and exit with error status.
Example 3
remap -from {top.AA[3:0]} -to {top.BB[3:0]} -assert_after 5

-deassert_after 10 -deassert_value b0
For this example, assume the following VCD change records, all on signal top.AA.
$dumpvars
b0 _a1
#20
b1100 _a1
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#30
b1010 _a1
#40
b0001 _a1
The following illustration shows the value changes recorded by Maxsim, and how
they are interpreted in PowerArtist, considering the effects of the assertion and de-
assertion options to the corresponding remap command.
Original Trace
top.aa
20 30 40
PT-ESL Trace
top.aa b1100 b1010 b0001
25 35 45
ReportReductions
This command generates a CSV (Comma-Separated Values) file of the reductions in
the design. This format is used for the digital storage of data structured in a table of
lists. The command separation character can be replaced with other characters such
as the + sign (the default for this command). You can use this format for bringing
data into spreadsheets or graphing tools.
Syntax
ReportReductions -power_db_name file_name

-reduction_report_csv_file file_name
[-reduction_report_csv_separator symbol]
[-reduction_report_instance instance_name | *]
[-reduction_report_log_file file_name]
[-reduction_report_module module_name | *]
Arguments
Specifies the file name of the power database file.
Alias: -pdb
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ReportReductions
-reduction_report_csv_file file_name
Specifies the name of the CSV file that will contain power analysis results.
Alias: -csv
-reduction_report_csv_separator symbol
Specifies the separator character used in the CSV file. You can use any printable
separator character; however, when choosing the separator character be mindful
of the content of the data set and the final tool into which you will import the data.
Default: , (comma)
Alias: -csv_sep
-reduction_report_instance instance_name | *
Specifies the names of instances for which you want to report power analysis
results. You can use glob-style wild card characters. If not specified, all instance
reductions will be reported.
Default: * (all)
Alias: -instance
-reduction_report_log_file file_name
Specifies the name of the log file for this command.
Default: ReportReductions.log
Alias: -log
-reduction_report_module module_name | *
Specifies the name of module for which you want to report power analysis results.
You can use glob-style wild card characters. If not specified, all instance
reductions will be reported.
Default: * (all)
Alias: -module
Example 1
ReportReductions -reduction_report_csv_file txrx.csv

-power_db_name reduction.pdb
This command creates a CSV file named txrx.csv. See the following sample file:
"Reduction/Linter"+"Module"+"Instance"+"File Name"+"Line Number"+"Total Power"
"CEC"+"upintf"+"core1.u1.#139"+"../rtl/verilog/upi.v"+"59"+"6.11584e-07"
"CEC"+"upintf"+"core1.u1.#140"+"../rtl/verilog/upi.v"+"59"+"1.83582e-05"
"CEC"+"txfsm"+"core1.t1.s1.#761"+"../rtl/verilog/txfsm.v"+"49"+"1.48148e-06"
<snip>
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Example 2
ReportReductions -reduction_report_csv_file txrx.csv

-power_db_name reduction.pdb -reduction_report_instance {*m1}
This command creates a CSV file that includes only instances that match the wild
card expression *m1. See the following sample file:
"SMW"+"mem2rp_half"+"core1.r1.dpmem.m0b.m1"+"../rtl/v/RR2P_half.v"+"43"+"0.002453"
"SMW"+"mem2rp_half"+"core1.t1.dpmem.m0a.m1"+"../rtl/v/RR2P_half.v"+"43"+"0.001630"
Example 3
ReportReductions -csv txrx.csv -power_db_name reduction.pdb

-reduction_report_module {[tr]xfsm}
This command creates a CSV file that includes only modules that match the
expression {[tr]xfsm}. See the following sample file:

"CEC"+"txfsm"+"core1.t1.s1.#761"+"../rtl/verilog/txfsm.v"+"49"+"1.48148e-06"
"CEC"+"rxfsm"+"core1.r1.s1.#1757"+"../rtl/verilog/rxfsm.v"+"39"+"4.61781e-07"
Note: The lines in the sample CSV files have been truncated on the right side to fit
the available space.
RewriteRTL
This command performs automatic rewrite of your RTL for any scheduled updates.
Generally, any options you specified to the Elaborate command that have
equivalents in the RewriteRTL command should be specified with the exact same
values. For details on how to use this command, see Rewriting Your RTL.
You can use the arguments for this command as pt_set variables (pt_set arg_name
value) in your PowerArtist command file.
Syntax
RewriteRTL –verilog_startup_file file_name -top top_module_name

-power_db_name file_name -elaborate_write_power_db true | false
[-blackbox module_names] [-case_insensitive true | false]
[-case_sensitive true | false]
[-critical_messages tcl_list_message_ids]
[-elaborate_ignore_directives tcl_list_of_values]
[-ignore_translate_off true | false]
[-ignore_translate_off_file {file_name1 file_name2 ...}
[-output_report_file file_name] [-output_rtl_dir_name dir_name]
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RewriteRTL
[-output_startup_file file_name] [-rewrite_debug_flags string]

[-rewrite_log file_name]
[-rewrite_reduction_mapping_file file_name]
[-rewrite_no_inline_modules true | false]
[-rewrite_report_file file_name] [-scenario_file file_name]
[-system_verilog true | false]
[-use_library_file_names true | false]
[-verilog_2001 true | false]
Arguments
–verilog_startup_file file_name
Specifies the Verilog startup file. The Elaborate command recognizes and
expands UNIX environment variables that appear in this startup file. You can
specify environment variables either with brace delimiters as in “${VARNAME}” or
without, as in “$VARNAME”. If you do not use brace delimiters, the variable name
is considered to end with the last alpha-numeric or underscore (_) character.
Environment variables within comments are not expanded. If there is no definition
for a variable required in the startup file, an error is reported and the program will
terminate with error status.
-top top_module_name
Specifies the top-level module name.
Default: (none)
Specifies the file name of the power database file.
Alias: -pdb
-elaborate_write_power_db true | false
Writes to the power database. When set to true, the rewrite process will update
the OpenAccess database representation of the hierarchical netlist of your design.
Default: false
Alias: -write_pdb
-black_box_modules module_names
Black-boxes the given modules, specified using a Tcl list, and their hierarchical
children.
Alias: -blackbox
-case_insensitive true | false
Uses case-insensitive name matching. By default, the scenario database is
constructed to be case sensitive if the design is entirely in Verilog, or case
insensitive if the design is VHDL or combination of VHDL and Verilog.
Default: -case_insensitive false
-case_sensitive true | false]
Uses case-sensitive name matching. By default, the scenario database is
constructed to be case sensitive if the design is entirely in Verilog, or case
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insensitive if the design is VHDL or combination of VHDL and Verilog.

Default: true
Default: 1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309 8517
-elaborate_ignore_directives tcl_list_of_values

input in;
output out;
// synopsys translate_off
assign out = in;
endmodule
-elaborate_ignore_directives {quickturn synopsys}
-ignore_translate_off true | false
Default: false
-ignore_translate_off_files file_name1 file2_name2...
Specifies a Tcl list of files in which to ignore the translate_off and translate_on
meta comments.
-output_report_file file_name
Specifies the file name containing the names of the modified files. The
output_report_file lists the file names in a simple format:
Default: output_startup_file.rpt
original_file_name new_file_name
For example, from the tutorial, a sample output_report_file is:
#
# Original_RTL_File Power_Optimized_RTL_File
#
../rtl/verilog/RR2P.v rewrite/EXTERNAL/rtl_analysis/rtl/verilog/RR2P.v
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RewriteRTL
-output_rtl_dir_name dir_name
Specifies the directory containing the rewritten RTL directory structure.
Default: ./rewrite
-output_startup_file file_name
Creates a Verilog startup file with the given name.
Default: output_rtl_dir_name/rewrite.vc
The name of the OADB power database (.pdb) file for the design. Note that you
must specify either a power database file or the scenario file (-scenario_file).
Alias: -pdb
-rewrite_debug_flags string
Prints debug information for the rewrite process. Available debug flags:
 F—prints (to your screen) information about the current processing steps
performed by rewrite.
 g—prints (to your screen) information related to failed rewrites. This will also
generate files that begin with rw_. Example files include: rw_details.txt,
rw_failed.txt, and rw_stats.txt.
-rewrite_log file_name
Writes an output log file with the given name.
Default: RewriteRTL.log
-rewrite_no_inline_modules true | false
When set true, RewriteRTL generates the pa_modules.v file for PowerBots LNR, FCE
and ODC. Depending on your design, at most, the following modules will be created:
ADS_PA_COMPARE_WITH_ZERO
ADS_PA_NEGEDGED_ADELAY
ADS_PA_NEGEDGED_DELAY
ADS_PA_NEGEDGED_SDELAY
ADS_PA_POSEDGED_ADELAY
ADS_PA_POSEDGED_DELAY
ADS_PA_POSEDGED_SDELAY
The in-lining of the functionality is switched off. When set to false (the default) you
will have module instantiations of the above in your RTL. For example,
< ADS_PA_COMPARE_WITH_ZERO pa_compare_inst( .match(pa_q_lnr_enable), .value(|(q
^ pa_q_lnr_rhs)) ) ;
---
> ìfdef SYNTHESIS
> assign pa_q_lnr_enable = (|(q ^ pa_q_lnr_rhs));
> èlse
> assign pa_q_lnr_enable = (0 !== (|(q ^ pa_q_lnr_rhs)));
> èndif
Default: false
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SetArchitecture
-rewrite_reduction_mapping_file file_name
Generates a mapping file that specifies the parameters that can be used to control
each of the reduction opportunities in RTL.
Alias: -reduction_mapping_file
-rewrite_report_file file_name
Creates a report file containing the list of original and new RTL files.
Specifies the scenario file. You must specify either this option or the
-power_db_name option.
-system_verilog true | false
Treats all files in the Verilog startup file (specified with the -verilog_startup_file
option) to be System Verilog files. System Verilog inferencing requires the System
Verilog option to PowerArtist.
Default: false
Allows two Liberty files with same library names in them to be read without any
conflict. The file names become the library names.
Default: false
-verilog_2001 true | false
Default: false
SetArchitecture
This command allows you to specify micro-architectures for adders and multipliers.
You can set them for the design as a whole, on an instance by instance basis, or for
every instance of a particular module type. You can explore power trade-offs at the
RT level by controlling these micro-architecture assignments.
Syntax
SetArchitecture (-instance instance_name | -module module_list |

-design yes) (-adder adder_name | -multiplier mult_name)
Arguments
-instance instance_name | -module module_list | -design yes

Specifies the instances to which you want the architecture applied. If you specify -
module, the architecture is applied to all instances of the specified modules.
Specify “-design yes” to apply the micro-architecture to the entire design.
-adder adder_name
Specifies the micro-architecture for adders. You have the following choices:
 ripple (slow, but low power) or
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SetAttribute
 cla (fast, but high power)

Default: ripple
-multiplier mult_name
Specifies the micro-architecture for multipliers. You have the following choices:
 booth (small, and high power): radix-4 modified booth encoding is used for
partial product generation.
 non_booth (large, slow and low power): basic shift-and-add architecture is
implemented.
Default: non_booth
Example
SetArchitecture -design yes -adder cla -multiplier booth

SetArchitecture -instance {top.dp1} -adder ripple
SetArchitecture -instance {top.dp1.#11} -adder cla
SetArchitecture -instance {top.dp1} -multiplier non_booth
SetArchitecture -instance {top.dp2.#12} -multiplier non_booth
SetArchitecture -instance {top.dp1.#12 top.#19} -multiplier
non_booth
In this example, the first command sets the design to use cla as the default adder
and booth as the default multiplier. These defaults are overridden for specific
instances by the remaining SetArchitecture commands in this example, Specifically,
top.dp1 and all of its children will use ripple adders and non_booth multipliers.
However, top.dp1.#11 will be a cla adder. Instances top.dp2.#12 will be a non_booth
multiplier as will top.#19.
In most cases, you will be specifying hierarchical instance names. This example
shows that you can assign it to inferred instances. This will not often be practical
because the next time you inference the design, the numbering may change and the
SetArchitecture commands will be out of date.
SetAttribute
Use this command to set the cell-level dont_touch or dont_use attributes. Their
values must be either true or false (to match that of the Synopsys library).
Syntax
SetAttribute [-cell cell_name] [-library lib_name(s)]

-name {attr_name} -value {attr_user_value}
Arguments
-cell cell_name
Specifies a cell name or a Tcl list of cells. Glob-style wild card patterns are
allowed. Not specifying the -cell option is identical to specifying a * wildcard.
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SetBounds
-library lib_name(s)
Specifies a library or a Tcl list of libraries. Glob-style wild card patterns are
allowed. Not specifying the -library option is identical to specifying a * wildcard.
-name attr_name
Specifies the name of the attribute. The attributes dont_touch and dont_use are
currently supported.
-value true | false
Specifies the value of the attribute—must be true or false.
Example 1
# marks all of the cells in the supplies library as dont_touch and dont_use
SetAttribute -library {my_lp} -name dont_touch -value true
SetAttribute -library {my_lp} -name dont_use -value true
# unsets some of the cells selectively
SetAttribute -cell { OX1 OX6 A1X1 A1X2 D1QX1 D1QX2 X2X4 D2X1 D2X2 D2X6 SBX1 SBX2 }
-library {my_lp} -name dont_touch -value false
SetAttribute -cell { OX1 OX6 A1X1 A1X2 D1QX1 D1QX2 X2X4 D2X1 D2X2 D2X6 SBX1 SBX2 }
-library {my_lp} -name dont_use -value false
This code example sets all of the cells in a particular library to use the dont_touch/
dont_use attributes and then unset selected cells with subsequent SetAttribute
commands.
Example 2
SetAttribute -cell * -library {my_lp} -name dont_touch -value true

SetAttribute -cell {*} -library my_lp -name dont_use -value true
This example marks all of the cells in the my_lp library as dont_touch and dont_use.
Example 3
SetAttribute -cell C* -name dont_touch -value false

SetAttribute -cell C* -name dont_use -value false
This example unsets the dont_touch attribute for all cell names starting with “C” in all
libraries.
SetBounds
This command defines the ranges for the 9 capacitance load and frequency
“buckets” that you can assign to different cell types using the
RefineConfigurationParameter command in an SLD file. For more information on the
SLD file, see the PowerArtist Library Developers Guide. If you do not use an SLD
file, then the system automatically selects cells from your libraries and assigns them
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SetBounds
to the 9 buckets. This is described in Default Behavior for Load and

Frequency later in this description.
Syntax
SetBounds -type (load | frequency) -bounds low_bound:high_bound
Arguments
-type load | frequency

Select “load” to define the low and high bounds for load capacitance or
“frequency” to define the low and high bounds for frequency. Note that you can
only specify one type per command. You would need to specify two commands to
define both load and frequency.
-bounds low_bound:high_bound
Sets a low and high bound for load (given in Farads (F)) or frequency (given in
Hertz (Hz)). Provide the low_bound and high_bound values in standard floating
point notation.
The ranges defined for load are:
— LOW = 0 to < low_bound
— MID = low_bound to high_bound
— HIGH = > high_bound
The ranges defined for frequency are:
— SLOW = 0 to < low_bound
— NORMAL = low_bound to high_bound
— FAST = > high_bound
Default Behavior for Load and Frequency
If you do not specify “-type load” then the software will determine the boundaries for
load ranges and on this basis, categorize cells in three buckets LOW, MED, HIGH.
By default, the following apply:
low_bound = 6*smallestTypicalNandLoad
high_bound = 16*smallestTypicalNandLoad
The system automatically determines the smallestTypicalNandLoad as being the
most typical input pin capacitance of a typical nand.
If you do not specify the “-type frequency”, option the software automatically
categorizes each clock as SLOW, FAST or NORMAL based on the highest clock
frequency vs. other clock frequency. That is,
 If the ratio of the frequencies of the fastest_clock/clock < 1.5 it is considered FAST
 If the ratio of the frequencies of the fastest_clock/clock > 2.5 it is considered
SLOW
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SetBuffer
 If the ratio of the frequencies of the fastest_clock/clock is >=1.5 and <= 2.5 is it
considered NORMAL
If you specify the “-type frequency” option to the SetBounds command this is
reflected in the debug messages in that you will see a line that starts with “User
Specified...”. Based on this string you can know whether the values used were user
specified or derived by the software. Note that you would set the frequency values
for each clock using the -frequency option to the SetClockNet command.
Example 1
SetBounds -type load -bounds 2e-11:5e-11

Given these values for load capacitance, the LOW range would be a positive number
less than 20 pF, the MID range would be between 20 and 50 pFs and the HIGH
range would be greater than 50 pF.
Example 2
SetBounds -type frequency 250Mhz:350Mhz

For this example, any clock that operates at a frequency lower than 250Mhz is
considered SLOW. Likewise, any clock that operates at a higher frequency than
350Mhz is FAST. Any clock operating at a frequency between the low and high
bounds is categorized as NORMAL.
SetBuffer
This command specifies buffers when inferring a buffer tree for high fanout nets. This
command is very similar to the SetClockBuffer command. Note: If you do not specify
buffers using the SetBuffer command in the clock file, but there are clock buffers set
with the SetClockBuffer command, then these buffers are used for net buffer
inferencing.
Syntax
SetBuffer -type (root | branch | leaf) -name buffer_name

-library lib_name -fanout buffer_fanout
[-wlm_scale_factor factor]
Arguments
-type root | branch | leaf

Specifies the buffer type. You must specify at least one leaf buffer or branch buffer
(in separate commands). Root buffers are optional.
-name buffer_name
Specifies the buffer model name.
-library lib_name
Specifies the Liberty logical library name containing the buffer model.
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SetCapEstimation
-fanout buffer_fanout
Specifies the maximum number of standard loads the buffer can drive. Input pins
are taken into consideration as a load. Specifies the maximum number of standard
loads the buffer can drive. If this option is not specified, the max_capacitance and
max_fanout attributes for the cell in the .lib are used to determine the number of
loads the cell can drive.
-wlm_scale_factor float
Defines the scaling factor by which the wire capacitance for a particular level is
scaled. It applies to all capacitance estimation methods including wire load models
and PACE capacitance estimation. It is a real number greater than 0. If the wire
load model says that your wire capacitance for this net would be X, specify a
value of factor*X instead of using the default.
Default: 1.0
Notes on Buffer Defaults
Missing buffers of all types (leaf, branch and root) will default to buffers of other types
in the following manner.
 If leaf buffers are required and not found in the clock file, the software will use
branch buffers if available; otherwise, it will use root buffers.
 If branch buffers are required and not found in the clock file, the software will use
leaf buffers if available; otherwise, it will use root buffers.
 If root buffers are required and not found in the clock file, the software will use
branch buffers if available; otherwise, it will use leaf buffers.
SetCapEstimation
This command instructs PowerArtist to use the default wire load model library that is
part of the PowerArtist installation for capacitance estimation. Rather than using
these defaults, you should consider using PACE models as described in Generating
PACE Technology Files (Beta) and Using PACE Technology Files During Power
Analysis (Beta).
This is useful for libraries that do not contain associated wire load information. If
PowerArtist cannot find a library containing wire load models, the analyzers will use
the following default command to ensure that wire load models will always be found:
SetCapEstimation -technology 90 -scale 1
This command will select the “default_wire_load : “SEQ_90_4;” attribute in the
seq_cap.lib.
For more information on how to use this command, see the section Using Apache
Default Wire Load Models for Capacitance Analysis.
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SetCapEstimation
Syntax
SetCapEstimation -technology technology_size [-scale scale_factor]

[-area_scale_factor scale_factor]
Arguments
-technology technology_size
Specifies the technology size from the following acceptable values: 180, 150, 130,
90, 65, or 45.
-scale scale_factor
Specifies a decimal number that is used to scale the capacitance number
retrieved from the wire load model.
Default: 1
-area_scale scale_factor
Specifies a decimal number that is used to scale the design area so that it
matches the area units in the default wire load model.
Default: 1
Example 1
SetCapEstimation -technology 90
For this example, PowerArtist will search the seqcap.lib file (which is located in
$POWERTHEATER_ROOT/sfl_lib/generic/seqcap.lib) for a wire_load_selection
table named SEQ_90_Area. Based on the area of the module (if you specified the
“enclosed” mode) or of the design (if you specified the “top” mode), PowerArtist will
locate the correct wire_load_from_area to determine the correct wire load model.
This wire load model will be of the form SEQ_150_#, where # ranges from 1 to 7.
The wire load models are built with the assumption that the areas in your .lib files are
specified using square microns. Note that you can not use this technique if your
areas are not defined in your libraries as square microns.
Example 2
SetCapEstimation -technology 45 -scale .75

In this particular case, the power analyzers will look for SEQ_45_Area, calculate the
area, determine the capacitance number and then scale that resulting value by .75.
This allows you to tune the wire load models to more closely match values you
obtained by extracting similar designs or to try out different corner values.
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SetCCommentsIgnore
SetCCommentsIgnore
Use this command to instruct PowerArtist to igmore C-style comments in the SPEF
file. A sample line that contains a C-style comment is:
*NAME_MAP
*1931 buffer/read_rc1/buf_rp_read/*suffix*/a
If you are ignoring C-style comments, the exact string is taken as the net name.
Syntax
SetCCommentsIgnore
SetCellDefaultFanout
Use this command to set the maximum fanout for a cell in the clock path. The default
fanout value is 8.
Syntax
SetCellDefaultFanout -cell cell_name -library lib_name

-fanout fanout_value
Arguments
-cell cell_name
Specifies the name of a cell in the clock path (can contain standard UNIX wild
card characters).
-library lib_name
Specifies the name of the logical library in which the specified cell exists (can
contain standard UNIX wild card characters).
-fanout fanout_value
Specifies the maximum fanout for all output pins of the specified cell. The default
fanout will be used for each output pin of the cell that does not have a maximum
fanout attribute. This value does not override a maximum fanout attribute. In the
Liberty format, this information is specified using the max_fanout attribute.
Example
SetCellDefaultFanout -cell nd*02 -library stdcell -fanout 4

This example will match cells such as ndls02 or nd0. For each output pin that is
missing, the max_fanout attribute for any cell whose name matches nd*02 in library
stdcell, will have its maximum fanout set to 4.
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SetClockBuffer
SetClockBuffer
Use this command to specify clock buffers when you want to infer a clock tree (tree
is the only topology PowerArtist supports).
Syntax
SetClockBuffer -type (root | branch | leaf | leafsplitter)

-name buffer_name -library library_name -fanout buffer_fanout
-capacitance buffer_max_capacitance_drive [-wlm_scale_factor
factor -net clock_name]
Arguments
-type (leaf | leafsplitter | root | branch)

Specifies the buffer type. At a minimum, you must specify either a leaf buffer or a
leafsplitter. Branch and root drivers are optional. A leaf splitter is a clock buffer
with two split outputs, one in the opposite phase as the other.
-name buffer_name
Specifies the buffer model name.
-library library_name
Specifies the technology library name containing the buffer model.
-fanout buffer_fanout
Specifies the maximum number of standard loads the buffer can drive. If this
option is not specified, then the max_capacitance and max_fanout attributes for
the cell in the .lib are used to determine the number of loads the cell can drive.
-capacitance buffer_max_capacitance_drive
If there is no -fanout option specified, the -capacitance value is used to calculate
the buffer count. In this case, the buffer count is calculated by dividing the
capacitance load (pin cap + wire cap) at the output by the value specified with this
option.
-wlm_scale_factor factor
Specifies the scaling factor by which the wire capacitance for a particular level is
scaled. Default value is 1.0. It is a real number 0. If the wire load model says that
your wire capacitance for this net would be X, use the value factor*X instead.
-net clock_name
Indicates that the specified buffer must be used while inferring buffers for this
particular net. If no net is specified, the buffer can be used for any net that has no
dedicated buffer of this type.
See the Transition Counting on Nets for additional information (including
examples).
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SetClockGatingRegisters
Notes on Buffer Defaults
Missing buffers of all types (leaf, branch and root) will default to buffers of other types
in the following manner.
 If leaf buffers are required and not found in the clock file, the software will use
branch buffers if available; otherwise, it will use root buffers.
 If branch buffers are required and not found in the clock file, the software will use
leaf buffers if available; otherwise, it will use root buffers.
 If root buffers are required and not found in the clock file, the software will use
branch buffers if available; otherwise, it will use leaf buffers.
SetClockGatingRegisters
You can use theis command (or equivalent) to specify registers to exclude from clock
gating. In general, you will be using this command if you want to perform correlation
studies between RTL and a synthesized gate-level netlist where you have used the
set_clock_gating_registers -exclude command (in PowerCompiler) to restrict the
registers that are clock gated. To get good correlation, you will need to perform the
equivalent operation while doing RTL power analysis. You may also want to use this
command if you know early on in your RTL design process that certain signals will
not be gated due to strict timing constraints.
Syntax
SetClockGatingRegisters -exclude_instances signal_names
Arguments
-exclude_instances signal_names
Specifies a Tcl list of hierarchical signal names to be inferred as registers in your
design. If you do not use this command, then generally, all registers that meet the
min_bit_width constraint are clock gated. You can use wild cards in the list of
signal names.
Example 1
SetClockGatingRegisters -exclude_instances {top.sub1_I.qq[0]

top.sub1_I.qq[4]}
This shows a Tcl list that includes individual register bits. All names that include the
[#] must be enclosed in {...} to pass Tcl syntax rules.
Example 2
SetClockGatingRegisters -exclude_instances {top.sub1_I.qq*}

This shows a sample wild card application. You can place this
SetClockGatingRegisters command directly into a Tcl command file.
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SetClockGatingStyle
SetClockGatingStyle
Use this command to define the attributes that control how clock gating is performed.
Syntax
SetClockGatingStyle [-min_bit_width bit_width]

[-max_bit_width bit_width] [-min_bit_width_ecg bit_width]
-clock_cell_attribute gating_cell_type
[-gating_cells gating_cell_name(s)] [-structure branch | leaf]
Arguments
-min_bit_width bit_width
Specifies the minimum number of bits a register bank must have to be considered
for clock gating.
Default: 3
-max_bit_width bit_width
Specifies a limit (maximum) on the number of register clock pins, a single inferred
clock gating cell is allowed to drive in the clock path. For details on how this option
specification is used by PowerArtist, see Clock Gating Algorithm.
-min_bit_width_ecg bit_width
Specifies the minimum number of register bank bits that must have a common
enable to be considered for enhanced clock gating. For more information, see
Performing Enhanced Clock Gating.
Default: Twice the value specified by the -min_bit_width option.
-clock_cell_attribute gating_cell_type
Sets the value of the clock_gating_integrated_cell attribute for which PowerArtist
will search to determine candidate clock gating cells. This argument is generally
required—it is optional only if the -gating_cells option is specified.
-gating_cells gating_cell_name(s)
Specifies clock gating cell(s). If this option is specified along with the
-clock_cell_attribute option, this option takes precedence.
-structure branch | leaf]
Used when you supply PACE models, this option determines whether ICGCs
should directly fanout to registers (leaf) or fanout to buffers that then drive
registers (branch). You can use this option in increase analysis accuracy if you
understand what will happen during CTS and optimization of your design. By
default, the value of this option is determined when the PACE model is created. It
is then applied to your design.
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SetClockGroups
Example 1
SetClockGatingStyle -clock_cell_attribute latch_posedge_precontrol

-max_bit_width 6
Example 2
SetClockGatingStyle -gating_cells {lib_AAA:ICGC1 lib_AAA:ICGC4}

-max_bit_width 6
SetClockGroups
This command defines a set of clocks as synchronous. Without this command, the
ODC and Prism PowerBots are unable to recognize groups of clocks as synchronous
and, therefore, may reject some opportunities as a Clock Domain Crossing (CDC)
case. By defining groups of synchronous clocks, the ODC and Prism PowerBots will
accept opportunities that cross these domains and not consider them as CDC cases.
You need to specify separate SetClockGroups commands for each group of
synchronous clocks.
Syntax
SetClockGroups -group {list_of_clocks}
Arguments
list_of_clocks
Specifies a Tcl list containing two or more clock net names. Each clock net name
may be in only one group.
Example
SetClockGroups -group {clk1 clk2}

SetClockGroups -group {clk3 clk4}
This example defines two clock groups. The clk1 and clk2 clocks are synchronous as
are clk3 and clk4. Prism and ODC will allow reduction opportunities to be pursued
between the clk1 and clk2 domains and the clk3 and clk4 domains but will consider
as a clock domain crossing any opportunity where one register is in one group and
the other is in the other group. Clock domain crossing opportunities are not
automatically accepted.
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SetClockNet
SetClockNet
Use this required command to specify a clock net in the design. If you selected the
infer mode, you will need to supply additional information with the SetClockBuffer
command.
Syntax
SetClockNet -name clock_net_name | pin_name -mode (infer | trace)

[-enhanced_cg true | false] [-exclude_pad_power true]
[-frequency float] [-gate_clock true | false]
[-hierarchical inst_name(s)]
[-instance inst_name(s)]
[-stop_at_cell cell_name(s)]
[-stop_at_instance {instance1 instance2 ...}]
[-stop_at_cell {cell1 cell2 ...}]
[-senses 1 | 2] [-trace_domain true]
Arguments
-name clock_net_name | pin_name

Specifies the name of the clock net or a pin name on a clock net in the design. In
some cases, it’s best to specify the pin name. Consider the case of a PLL. When
your system clock goes into a PLL, it is probably easier to specify clock nets to
trace by specifying the pin name of the PLL rather than the nets attached to all of
the pins.
For example, if a net named top.clk1 was attached to the PHASE1 pin of the PLL
whose instance was top.PLL, the following two SetClockNet statements perform
an equivalent operation:
SetClockNet -name top.clk1 -mode trace
SetClockNet -name top.PLL.PHASE1 -mode trace
This concept works for any instantiated element and is not restricted to PLLs.
-mode infer | trace
Declares whether the engine should infer a clock tree for the net or trace an
instantiated clock tree in the design. Note that the engine will not perform clock
gating if you specify this argument as “trace”.
-enhanced_cg true | false
When set to true, this option enables enhanced clock gating for the given clock
net. Note that you must also specify “-gate_clock true” for this option to take
effect. For more information on enhanced clock gating, see Performing Enhanced
Clock Gating.
Default: false—enhanced clock gating is not enabled.
-exclude_pad_power true
If this option is used, then the traced pads will appear in both the Clock Power
consumption and the Pad Power sections, but their power will be reported only as
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SetClockNet
Pad Power. Otherwise, they will appear in both sections and power will be
reported in both the sections.
-frequency float
Specifies the operating frequency in Hz for the specified clock. If you do not
specify this option, the clock will be considered to be a fast clock.
-gate_clock true | false
Specifies that the net should be gated. Without this option, no gating will be
performed on this net. For more information on clock gating, see Setting up Clock
Gating for Power Analysis.
Default: false—no clock gating is performed.
-hierarchical inst_name(s)
Specifies a Tcl list of hierarchical instance names. For more information on using
this option, see Hierarchical Clock Gating in the PowerArtist User Guide.
-instance inst_name(s)
Specifies a Tcl list of instance names. For more information on using this option,
see Hierarchical Clock Gating in the PowerArtist User Guide.
-senses 1 | 2
Specifies the number of clock senses that have to be routed in the design for this
net. If this net provides both a normal and inverted clock, you should specify this
number as 2. If it provides only one type of clock—either normal or inverted—
specify this number as 1.
Default: 1
-stop_at_cell cell_name(s)
Specifies a list of cell types, from your library, at which the clock tracer is to stop.
You can specify a regular expression to match multiple cell names.
-stop_at_instance inst_name(s)
Specifies a list of instances at which the clock tracer is to stop. All instances
traced up to, but not including these instances are made part of the traced clock
tree. You can specify a regular expression to match multiple instance names.
-trace_domain true
Enables the tracing of clock domains.
Example
SetClockNet -name top.clk -mode infer -frequency 200e6

In this example, the clock net, top.clk, is inferred and is operating at a frequency of
200 MHz.
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SetConfigurationParameter
SetConfigurationParameter
This command provides a simple method for setting your default cells. In addition,
you can use this command to define default wire load models, technology-specific
SLD parameters and clock buffers. However, this use has been obsoleted by other
technology and will only be described for historical completeness.
Syntax
SetConfigurationParameter cell_type cell_name library_name
Arguments
cell_type
One of the 6 required cell types or 4 optional cell types that you are defining as a
default cell.
The required cell types are:
 DefaultFlop—Default flip-flop cell without clear (you can use the
DefaultFlopWithClear instead).
 DefaultInv—Default inverter.
 DefaultMux—Default 2-input encoded multiplexor (2 data inputs, 1 select input).
 DefaultNand—Default 2-input Nand cell.
 DefaultXor—Default 2-input Xor cell.
 DefaultLatch—Default latch cell.
The optional cell types are:
 DefaultFlopWithClear—Default flip-flop cell with clear. You can use this
parameter instead of the DefaultFlop parameter.
 DefaultTriStateDriver—Default tri-state buffer (1 data input, 1 active-high enable
input)
 DefaultFullAdder—Default full adder cell (3 inputs (A, B, Cin) and 2 outputs
(Sum, Cout))
 DefaultPassGate—Default passgate used in datapaths instead of a tri-state
driver
cell_name
The actual technology library cell name.
lib_name
The logical library name containing the default cell. One SLD file can contain
references to multiple library names. You would specify the physical file locations
of these libraries using a command file (that includes the ReadLibrary command)
or a -synlib_files command option).
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SetDatapathWidth
SetDatapathWidth
This command specifies the minimum width (in bits) of a candidate register. It is used
with the Prism PowerBot.
Syntax
SetDatapathWidth width_num
Default: 8
SetDefaultFanout
Use this command to set the fanout value of an instance of a clock driver. This
command takes the highest priority when setting the fanout value. Specifically, the
priority order, from highest to lowest, for setting the fanout value is as follows:
 SetDefaultFanout command
 max_fanout of the output pin
 max_capacitance of the output pin
 default_max_fanout from the library scope
 default_max_capacitance from the library scope.
 SetCellDefaultFanout command
Syntax
SetDefaultFanout (-cell cell_name(s) | -instance inst_name(s))

-library lib_name -fanout int
Arguments
-cell cell_name(s) | -instance inst_name(s)

Specifies the cell or instance(s) to which the given fanout value will be applied.
You can use both -cell and -instance in the same command. You must specify at
least one of them.
-library lib_name
If you specified -cell, then use this option to specify the logical library name of the
library that contains the cell.
-fanout int
Specifies the cell to which the fanout value will be applied.
Examples of How Command Conflicts are Handled
Example 1
Assume the following conflict between two SetDefaultFanout commands:
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SetExcludeModules
SetDefaultFanout -cell abc -library 1.lib -fanout 2

SetDefaultFanout -instance abc.inst -library 1.lib -fanout 4
The first command sets the fanout value of cell abc to 2. If abc.inst is an instance of
cell abc the value specified in the second command (with the -instance option) will
overwrite the fanout value given by the first command. This will result in a fanout
value of 4 for abc.inst. This is true regardless the order of the commands. This is
because a -instance match takes precedence over a -cell match because instances
are more specific than cells.
Example 2
Assume the following two commands exist together:

SetDefaultFanout -cell abc* -library 1.lib -fanout 2
SetDefaultFanout -cell ab* -library 1.lib -fanout 4
In this case, the order of commands does matter. The second command will override
the first command. Specifically, all of the cells that match ab... will have their fanout
set to 4. This will also happen if the -cell option were replaced with -instance in both
commands.
If you reverse the command order, all of the cells that match *ab... * except cells that
match *abc...* will have their fanout set to 4, whereas cells that match *abc...* will
have their fanout set to 2.
SetExcludeModules
Use this command to specify a list of modules to be excluded from analysis by the
Prism PowerBot. The list of modules is a Tcl list of module names. The analysis for
candidate registers is always done across all modules. Candidate registers found in
the excluded modules list will not be reported in the results.
Syntax
SetExcludeModules {list_of_modules}
SetHighFanoutNet
You must use this command to specify the maximum fanout on a net. Any net with at
least the given number of fanouts will have a buffer tree. If no SetHighFanoutNet
command is found in the clock file, then by default “SetHighFanoutNet -fanout 9” is
applied.
Syntax
SetHighFanoutNet -fanout fanout_value
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SetIncDirPath
Example
SetHighFanoutNet -fanout 10
This command will result in buffer tree inference for all nets with fanout greater than
or equal to 10.
SetIncDirPath
This command specifies directories that can be searched to locate include files for
Verilog designs. This is used in conjunction with the CompileFile command.
Syntax
SetIncDirPath dir_name(s)
SetInstanceStimulus
Note: This command is obsolete and will be removed in the future.
This command sets the frequency, duty cycle and activity of all the input and output
ports of the instance. The instance may be either a hierarchical instance or a leaf-
level instance. If it is a hierarchical instance, then all of the ports of all instances
including leaf instances will be set to the specified values. This command is part of
the Vectorless Activity File (VAF). You do not specify this command directly in a
command file. For more information on the VAF, including a sample file, see
Vectorless Activity File Format.
Syntax
SetInstanceStimulus -instance inst_name [-frequency avg_freq]

[-duty avg_duty] [-activity activity_value]
Arguments
-instance inst_name
Specifies the name of either a leaf-level or hierarchical instance in the design.
-frequency avg_freq
Specifies the average frequency of the signals on the input and output ports. A
positive frequency value will override any value specified with the -activity option.
-duty avg_duty
Specifies the average duty cycle of the signals on the input and output ports. If the
duty cycle is not specified, all the input and output ports of the leaf-level instances
are assigned the default duty cycle (0.5).
Default: 0.5
-activity activity_value
Specifies the average activity of the signals on the input and output ports.
Default: 0.4
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SetLibrary
SetLibrary
This command defines which libraries can be used for power analysis for specified
instances. The libraries associated with an instance are inherited from its parent
instance unless explicitly overridden by this command. The root instance by default
accepts the entire set of libraries supplied using the -synlib_files command option.
The libraries are searched “first in” for cells. Libraries specified using the SetLibrary
command are searched left to right in the list as are libraries specified using a -
synlib_files command option.
Syntax
SetLibrary [-domain domain_name(s)] -instance inst_name(s)

Arguments
-domain domain_name(s)
Specifies a list of domains in which all instances use cells from the specified
library list. This option is required only if you are using the Common Power Format
(CPF)-out flow. If you use the -instance option in a CPF-out flow, it will be ignored.
Specifies a hierarchical path to a particular instance. You can also specify a Tcl list
of instance names. Each instance name may also include standard Tcl wild card
characters. Be careful when using wild cards as they could end up matching a
huge number of instances in the design. This is required for non-CPF flows.
Specifies a Liberty logical library name(s) from a library that has been specified by
either the -synlib_files command option.
Example 1
SetLibrary -instance top.block1.domain1 -library stdcell1

SetLibrary -instance top.block2.domain1 -library stdcell2
SetLibrary -instance top.block1.domain2 -library {stdcell1 rflops}
In addition to these command specifications, suppose that you have the following
-synlib_files command option to any of the commands that require libraries to be
specified:
-synlib_files libs/stdcell1_.8V.lib
-synlib_files libs/stdcell2_.8V.lib
and the opening lines of each .lib that contains the logical library name, are as
follows:
stdcell1_.8V.lib
library (stdcell1) { ...}
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SetMemoryGatingCell
stdcell2_.8V.lib
library (stdcell2) { ...}
For this example, by default, top is assigned the libraries rflops:stdcell1:stdcell2,

which are searched in that order. block1 and block2 inherit the same libraries and the
same search order. block1.domain1 only looks in library stdcell1. block2.domain1
looks in stdcell2. block1.domain2 searches both stdcell1 and rflops.
Example 2
SetLibrary -instance {top.block1.domain1 top.block2.domain*}

-library (stdcell1 rflops}
In this example, top, block1, and block2 behave as in the previous example.
top.block1.domain1 and all sub-domains of block2 are given stdcell1 and rflops.
top.block1.domain2 inherits from top.block1.
SetMemoryGatingCell
Specifies a list of clock-gating cells for the memory gating power reduction technique
performed by the Gate Memory Clock PowerBot. Each element in the Tcl list is a pair
of the logical library name separated by a colon (:) from the cell name.
In the absence of this command, GMC will take the clock-gating cell from the register
clock-gating command SetClockGatingStyle. If neither command is specified,
PowerArtist will instantiate a discrete gating circuit.
Syntax
SetMemoryGatingCell -name {lib_name1:cell_name1

lib_name2:cell_name2 ...}
Example 1
SetMemoryGatingCell -name { lib1:ICGC1

lib1:ICGC2
lib2:ICGC3 }
The lib1 and lib2 values here are logical library names specified in your Liberty files.
The cell names are from the cell definition statements. Given this command,
PowerArtist will use the ICGC1, ICGC2 and ICGC3 cells in logical libraries lib1 and
lib2 as the clock gating cells when performing memory clock gating.
SetNameMapFile
Use this command to specify the name of the name mapping file to be used when
processing your activity stimulus file while using a name mapping flow as described
in Name Mapping Flow. This command supports two formats.
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SetNetStimulus
Syntax
SetNameMapFile -map_file file_name -format conformal | pt
Arguments
-map_file file_name
Specifies either a Conformal™ “do” file or a map file containing remap commands.
-format conformal | pt
Specifies the format of the map file. Specify “pt” to directly use remap commands
with the wwgaf utility.
Example
SetNameMapFile -map_file mapFile -format pt

This command specifies a map file that includes remap commands as shown in the
following sample file:
remap -from {testbench.top1.in1} -to {top.input1}
remap -from {testbench.top1.in2} -to {top.input2}
remap -from {testbench.top1.en} -to {top.enable}
SetNetStimulus
Use this command to specify the signal frequency, duty cycle and activity for a given
net. Each net must be declared with a separate command, on a separate line. This
command is part of the Vectorless Activity File (VAF). You do not specify this
command directly in a command file. For more information on the VAF, including a
sample file, see Vectorless Activity File Format.
Syntax
SetNetStimulus -net net_name -frequency freq_value

[-duty duty_cycle] [-activity activity_value]
Arguments
-net net_name
Specifies the name of the net for which you are setting the frequency. This may be
a wild card in which case all nets matching the wild card will be set to the
appropriate values. With wild cards, the search will match all hierarchical net
names. Therefore:
-net a.b.c*
will match the following:
a.b.c1
a.b.c.d
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SetNetStimulus
Further, vectors are easily searched by specifying only the vector base name. For
example, if “d” is a vector with bits 0 to 31, specifying the following will match all
the bits of the bus:
-net a.b.c.d
Because it contains no wild cards, it would not match the following:
a.b.c.d1
-frequency freq_value
Specifies the frequency of the signal on the specified net. If a positive frequency
value is given, it overrides the value specified with the -activity option. Frequency
values should be specified in Hz; therefore, 2MGz would be 2e+06. Specify either
-frequency or -activity but not both.
-duty duty_cycle
Specifies the duty cycle of the signal on the specified net. Duty cycle values are
real numbers from between 0 and 1, inclusive. A value of 0 mans that the net is
always 0. Conversely, a value of 1 means that the net is always 1. A value of 0.5
(the default) means that a net spends 50% of its time at 0 and 50% of its time at 1.
Default: 0.5
Specifies the activity (rise and fall) of the signal on the specified net. Activity
values are real numbers from between 0 and 1, inclusive. A net that toggles once
per clock cycle would have a value of 1. A net that never toggles will have an
activity of 0. If neither frequency nor activity is specified, the net is assigned an
activity of 0.4 (the default value). Specify either -frequency or -activity but not both.
Default: 0.4
Example 1
SetNetStimulus -net top.tck -frequency 1e+08

This example sets the frequency of top.tck to 100 MHz and the duty cycle to 0.5 (the
default).
Example 2
SetNetStimulus -net top.data -frequency 1e+06 -duty .2

Assuming that data was defined as a vector, [31:0] data, then all 32 bits of data are
set to 1 Mhz and a duty cycle of .2.
Example 3
SetNetStimulus -top.a.* -frequency 1.7e+7

This example assigns a frequency of 17 MHz and a duty cycle of .5 to any
hierarchical net with a name that begins with “top.a.”.
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SetPortStimulus
Example 4
SetNetStimulus -net {top.data[5]} -frequency 1e+06

This example assigns top.data[5] a frequency of 1 Mhz. Note that if ports or net
names are bit vectors and include brackets [ ], you will have to “escape” the brackets
by enclosing the name in braces {} per standard Tcl conventions, as shown in this
example.
SetPortStimulus
Use this command to specify the duty cycle, activity, and frequency of a port of a
specified RTL inferred instance or a gate instance in the design. This command is
part of the Vectorless Activity File (VAF). You do not specify this command directly in
a command file. For more information on the VAF, including a sample file, see
Vectorless Activity File Format.
Syntax
SetPortStimulus -instance instName -port port_name

-frequency port_freq [-duty duty_cycle] [-activity
activity_value] [-type {input | output | both}]
Arguments
-instance inst_name
The name of an instance in the design. The instance may be an RTL inferred
instance or a gate-level instantiation.
-port port_name
Specifies the name of a port on the specified instance. This may be a wild card, in
which case, all ports matching the wild card will be set to the appropriate values.
-frequency port_freq
Specifies a frequency of the signal on the specified port. A positive frequency
value will override any value specified with the -activity option. Frequency values
should be specified in Hz; therefore, 2MGz would be 2e+06.
-duty avg_duty
Specifies the duty cycle of the given instance.
Default: 0.5
Specifies the activity of the signal on the specified port.
Default: 0.4
-type {input | output | both}
Specifies the direction of the port. A value of “both” means it could be either an
input or an output port.
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SetPower
Example 1
SetPortStimulus -instance top.m1 -port {ADDR[0]} -frequency 1e+6

Note that if ports or net names are bit vectors and include brackets [ ], you will have
to “escape” the brackets by enclosing the name in braces {} per standard Tcl
conventions, as shown in this example.
Example 2
You can also combine general purpose netlist commands and property commands
from SPL to perform some very useful functions. For example, suppose you want to
set the read frequency for a number of similarly named memories. Suppose further
that all of your memories were instantiated as dram followed by some integer
number. You could put the following Tcl fragment into your .vaf file:
set mems [GetInstances -name .*\.dram[0-9]*]
foreach mem $mems {
SetPortStimulus -instance $mems -read 3e+06
}
Example 3
SetPortStimulus -instance top.m1 -port clk* -frequency 1e+06

This example sets a frequency of 1 Mhz for all ports of instance top.m1 that begin
with clk* ( clkA and clkB).
Example 4
SetPortStimulus -port d* -type input -frequency 1e+6

This example sets a frequency of 1 Mhz for all input ports that begin with d.
SetPower
You can use the SetPower command to specify power values for any leaf-level
instance in your design. This command primarily targets blackboxed instances for
which there are no calculated power numbers. You may have blackboxed an
instance because you do not have a power model for the device in your technology
library. This often occurs for analog components. You may also have a very large
design that you want to break into pieces for power analysis but still have an
automatically rolled-up power number. In this latter case, you would perform the
power analysis on the sub-block, extract the power values, black-box the sub-block
in the context of your total design and then assign the values to that instance.
You can also use this command to override the computed power value for a
particular instance.
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SetPower
Syntax
SetPower (-module module_name | -instance instance_name)

[-static static_power] [-dynamic dynamic_power]
Arguments
-module module_name
Specifies a module type name or a Tcl list of module names. You can use wild
cards. PowerArtist will generate a list of hierarchical instances whose module type
name matches the module name string. You can also specify an inferred module
name which you can retrieve from an ASCII netlist or, from a power analysis
report or using a variety of different features of the user interface.
-instance instance_name
Specifies a hierarchical instance name or list of Tcl instance names. You can use
wild cards.
-static static_power
Specifies a real number >= 0 that represents the static power for the instance.
Default: 0.0W
-dynamic dynamic_power
Specifies a real number >= 0 that represents the dynamic power for the instance.
Default: 0.0W
This command supports engineering notation for the static and dynamic power
values. If you do not use engineering notation, PowerArtist assumes a default unit of
Watts.
Example 1
SetPower -module A6523 -static 5mW -dynamic 2mW

In this example, an instance of type A6523 will have its static power set to 5mW and
its dynamic power set to 2mW.
Example 2
SetPower -instance {top.U1 top.U2} -dynamic 5e-3

In this example, the two leaf-level instances, top.U1 and top.U2, will have their static
power set to 0W by default and the dynamic power set to 5mW because Watts is the
default unit.
Example 3
SetPower -module RR* -static 10uW -dynamic 30uW

In this example, all module types that start with RR and their associated instances
will be assigned the values of 10uW for static power and 30uW for dynamic power.
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SetPowerTarget
Other Impacts of the SetPower Command
The reports generated by the power analyzers will mark with an (F) any instances
with power values forced by the SetPower command (in the same way that clock
gated instances are marked with a (G)). If you display a schematic in Explorer,
PowerCanvas or PowerArtist, you will see a new property, Forced_Power_Values, in
the tool tip for any such instance.
Sample Report
3. Internal power consumption

=============================
Note: (F) after model name means power of this instance has been forced by using
the SetPower command.
Component Model Supply Static Dynamic Total
--------- ----- ------ ------ ------- -----
TOP.#26 auto CLIB8DLL.vdd 0W 0W 0W
TOP.BUFHOR.#10 or CLIB8DLL.vdd 109nW 2.13fW 109nW
TOP.BUFHOR.#11 and CLIB8DLL.vdd 125nW 1.07fW 125nW
....
TOP.BUFHOR.#21 con_inv CLIB8DLL
TOP.BUFHOR.#21 con_inv CLIB8DLL.vdd 0W 0W 0W
TOP.BUFHOR.BUFDENC_CK IVLLX5(F) CLIB8DLL.vdd 1uW 1fW 1uW
TOP.BUFHOR.BUFH27_CK IVLLX3 CLIB8DLL.vdd 284nW 4.41fW 284nW
...
SetPowerTarget
Use this command to specify power constraints for specific instances. These are
written out to the CPF output file, but are not used in any other way by PowerArtist.
Syntax
SetPowerTarget [-instance inst_name(s)]

([-static static_power] | [-dynamic dynamic_power])
Arguments
Specifies the instances for which the specified static and/or dynamic power values
apply. If you do not specify this option, the specified power value will apply to the
top-level module of the design.
-static static_power
Specifies a static power target value. You must specify either this option or the -
dynamic option (or both).
-dynamic dynamic_power
Specifies a dynamic power target value.
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SetPowerTechComments
Example
SetPowerTarget -instance {top.i1 top.i3} -static 35e-6

-dynamic 150e-6
SetPowerTarget -static 5e-3 -dynamic 7e-3
Given these commands, PowerArtist generates the following CPF commands
assuming the scope of the top-level module, top:
set_power_unit mW
set_instance i1
set_design mod1
set_power_target -leakage 0.035 -dynamic 0.15
end_design
set_instance i3
set_design mod3
set_power_target -leakage 0.035 -dynamic 0.15
end_design
set_power_target -leakage 5 -dynamic 7
Use this command to add user information/comments to your PACE model file when
you generate it. You simply specify a string to this command, which would include
the new line (\n) and tab (\t) characters. For more information on how to use this
command and an example, see Adding Comments to the PACE Model.
Syntax
SetPowerTechComments “string”
Example
SetPowerTechComments " Design= mydesign\n Lib= my_lib\n SPEF=

mydesign.poly.spef"
Given this example, when you use this PACE model, CalculatePower (or
ReducePower) will generate the following note:
wwengine: Note 9914: reading pace file power.tech

power tech information: Design = mydesign
power tech information: Lib = my_lib
power tech information: SPEF = mydesign.poly.spef
SetSpefFiles
Use this command to provide a list of SPEF file(s) to the SPEF reader for
processing. The SPEF reader performs a rapid “read” of these files to determine
their associated design names. These design names must later be referenced in
*DEFINE statements following the SPEF specification. Do not use this command if
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SetTopSpef
you are using the ReadParasitics command. You must use this command in
conjunction with a SetTopSpef command (next). It is recommend that you use the
ReadParasitics command instead of this methodology.
Syntax
SetSpefFiles file_name(s)
SetTopSpef
This command tells the SPEF reader the name of the design that forms the root of
your SPEF hierarchy. Typically, this maps to the top-level design unit in your design
hierarchy. The design name is then used to find the top-level SPEF file, which is
read. As the SPEF reader encounters *DEFINE statements, the other SPEF files are
located and read-in. This command is not required when you specify only one SPEF
file. Do not use this command if you are using the ReadParasitics command. You
must use this command in conjunction with a SetSpefFiles command (previous). It is
recommend that you use the ReadParasitics command instead of this methodology.
Syntax
SetTopSpef top_design_name
Example
SetSpefFiles {top.spef middle.spef bottom.spef}

SetTopSpef top
SetVoltageThreshold
Use this command when performing mixed-Vt power analysis to set voltage value
strings on library cells that match a given pattern. You only need to use this
command if your libraries do not categorize cells using Liberty threshold voltage
attributes. For more information on running a mixed-Vt power analysis flow, see
Running RTL Mixed-Vt Power Analysis in the PowerArtist User Guide.
Syntax
SetVoltageThreshold -group threshold_group

-pattern cell_pattern_list
Arguments
-group threshold_group
Specifies the name of a threshold voltage group.
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SetVT
-pattern cell_pattern_list
Specifies a Tcl list of patterns. The cell names in the supplied libraries matching
any of the patterns will have the threshold voltage group as specified by the -
group option.
Example
SetVoltageThreshold -group LVT -pattern {*_TL1 *_TL2}

SetVoltageThreshold -group HVT -pattern {*_TH}
This example will implement the following flow:
 In the supplied libraries, any cell names that match the patterns *_TL1 or *_TL2
will have their threshold voltage string set to LVT.
 Additionally, any cell names that match the h pattern *_TH will have their threshold
voltage string set to HVT.
Note that the SetVoltageThreshold command overrides any existing threshold
voltage string previously set for a particular group.
SetVT
This command is required when performing mixed-Vt power analysis. It assigns, for
each hierarchical instance in your design, the percentage of each type of threshold
voltage that should be used for all inferred elements in a specified instance and in all
of its children.The threshold voltage types come from the settings of the following
Synopsys Library Compiler™ attributes:
 At the library level:
default_threshold_voltage_group : "<string>" ;
 At the cell level:
threshold_voltage_group : "<string>" ;
Your libraries must be characterized with these attributes; PowerArtist uses the
supplied strings to differentiate threshold voltages for mixed-VT power analysis.
Syntax
SetVT -mode percentage -instance {instance_list}

-vt_group {threshold_group_list}
Arguments
-mode percentage
Specifies a “percentage based” mixed-VT power analysis technique. This is
currently the only technique available. This means that you can assign for each
hierarchical instance in your design, the percentage of each type of threshold
voltage that should be used for all inferred elements in that instance and in all of
its children.
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SetWireLoadMode
-instance {instance_list}
Given a list of instances, PowerArtist will assign the percentage of each type of
threshold voltage that should be used for all inferred elements in the specified
instance(s) and in all of their children.
-vt_group {threshold_group_list}
Specifies a Tcl list of Liberty cell-level threshold_voltage_group attribute values
along with their respective percentages separated by colons (:). The sum of the
percentages must be 100%. There may be any number of elements in
thethreshold_group_list.
Example
SetVT -mode percentage -instance {top.block1 top.block2}

-vt_group {HVT:70 LVT:30}
Given this example, PowerArtist will assign default cells to the children of top.block1
and block2 such that 70% of the default cells have will be HVT cells and 30% be LVT
cells. Instances that are not children of top.block1 and top.block2 will be assigned
default cells without any consideration for the threshold voltage attributes.
It is possible to assign the SetVT command hierarchically. For instance, if one of the
instances is top.block1.child1, this will override the percentage values set by the
top.block1 SetVT command.
This example assumes that the supplied libraries categorize the cells based on the
Liberty threshold voltage attributes. If they are not categorized this way, you must
use the SetVoltageThreshold command as follows.
SetVoltageThreshold -group LVT -pattern {*_TL}
SetVoltageThreshold -group HVT -pattern {*_TH}
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group
{HVT:70 LVT:30}
Given these settings, any cells from the supplied libraries that are available for
top.block1 and top.block2 and have names that match the pattern *_TL will be
treated as part of the LVT threshold voltage group. Cells that match the pattern *_TH
will be treated as part of the HVT threshold voltage group.
SetWireLoadMode
This command sets the wire load mode of the design. This command is used in
conjunction with the SetWireLoadModel command. You can use both the
SetWireLoadMode and SetWireLoadModel commands in a command file. For more
information on how this command fits in with the SetWireLoadModel command, see
Specifying Wire Load Models.
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SetWireLoadModel
Syntax
SetWireLoadMode top | enclosed
Arguments
top
Sets the same wire load model on all hierarchical instances based on the area of
the entire design.
enclosed
Sets the wire load models on all hierarchical instances based on their area values.
This is the default value.
Examples
SetWireLoadMode top
SetWireLoadMode enclosed
SetWireLoadModel
This command defines the wire load models for instances and nets. This command
is used in conjunction with the SetWireLoadMode command. You can use both the
SetWireLoadMode and SetWireLoadModel commands in a command file.
Syntax
SetWireLoadModel -name model_name -library lib_name

[-instance inst_name(s)] [-net net_name(s)]
[-scaling_factor factor]
Arguments
-name
Specifies the name of the wire load model.
-library lib_name
The logical library name which should be searched for the wire load model given
with the -name option. If you do not specify a library name, the estimators will use
the library specified using the -wireload_library command-line option. If that is not
found, then it will search all of your libraries specified using the -synlib_files
command option for a wire load model.
Specifies a hierarchical instance name or a Tcl list of instances. You may use wild
cards. For each hierarchical instance you specify, the power analyzers will set the
user wire load model on all of the instances that are in that hierarchy. All of the
nets that are fully covered by this hierarchical instance will be given the same
value.
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SetWireloadScalingFactor
-net net_name(s)
Sets the wire load model on the specified nets only. You can specify a single
hierarchical net name or a Tcl list of nets. You may use wild cards.
-scaling_factor factor
The factor by which the computed capacitance value returned from the wire load
model should be scaled.
Example 1
SetWireLoadModel -name smallsize -instance {top.l1 top.l2}

-library typical -scaling_factor .95
When PowerArtist needs a capacitance value for nets contained in instances top.l1
or top.l2, it will search for the wire load model “smallsize” in library. If found, its
capacitance value will be computed from the model then multiplied by .95.
PowerArtist will then assign the wire load model, smallsize, to top.l1 and top.l2 as
well as all their children instances.
Example 2
SetWireLoadModel -name large -net top.l1.* -library typical

For this example, all nets matching the string top.l1.* will be assigned the “large” wire
load model from the “typical” library.
Use this command to scale the wire capacitance, extracted from a wire load model.
Syntax
SetWireloadScalingFactor inst_name cap_scale_value
Arguments
inst_name
The instance for which you are setting the capacitance scale factor. The applied
capacitance scale factor will be applied to all children of this instance unless a
separate value is applied to them. If you want to define this factor globally, you
should apply it to the top module in the design.
cap_scale_value
The capacitance scale factor (can be any non-negative value).
Default: 1
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SetWireLoadSelectionTable
Example
SetWireloadScalingFactor top 10
SetWireloadScalingFactor top.i1 5
Given this example, all the instances under the top.i1 hierarchy will have a
capacitance scale value of 5. The remaining instances in the design will have a value
of 10.
Use this command to specify wire load selection tables from your Liberty files, that
the software will use to calculate net capacitances during a power analysis. In
addition to this command, the following commands also affect wire load models:
SetWireLoadModel, SetWireLoadMode, and SetCapEstimation.
wire_load_selection tables are group selections that specify the wire_load model for
various area ranges that the software uses to estimate capacitance. A typical wire
load selection table looks like the following:
wire_load_selection(SEQ_45_Area) {
wire_load_from_area(0, 8000, "SEQ_45_1");
}
The name of the selection table is SEQ_45_Area. If the area of your design is
between 75000 and 134000, then the software will use wire_load model SEQ_45_5
to estimate capacitance. An example wire load model looks like:
wire_load("SEQ_45_5") {
resistance : 0.00001 ;
capacitance : 1 ;
area : 0 ;
slope : 0.00328 ;
fanout_length(1,0.00036) ;
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TraceThruCell
}
Syntax
SetWireLoadSelectionTable -name selection_table_name

-library lib_name [-instance inst_name] [-scaling_factor float]
Arguments
-name selection_table_name
Specifies the name of the selection table in the technology library specified by the
-library argument. The software generates an error if it cannot find this table.
-library lib_name
Specifies the logical library name of one of your technology libraries. The selection
table you specified must be in this library.
-instance inst_name
Specifies the hierarchical instance name. The selected wire_load group is applied
to this instance and all of its children instances unless specifically overridden by
subsequent SetWireLoadSelectionTable commands.
Default: top instance name
-scaling_factor float
Specifies a value by which any capacitance value calculated by the selected wire
load model should be multiplied.
Default: 1 (no scaling)
Example
SetWireLoadSelectionTable -name smallsize -library typical

Specifies a selection table named “smallsize” in the library with logical name “typical”.
TraceThruCell
Use this command to specify the input-to-output path inside of a cell or to override
the existing input-to-output path specified by the timing arcs.
Syntax
TraceThruCell -name cell_name [-blackbox module_name]

-input_pins pin_list -output_pins pin_list [-library lib_name]
Arguments
-name cell_name
All instances of this particular cell type need to be traced. This may contain wild
cards.
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TraceThruInstance
-blackbox module_name
Specifies the name of a module that has been black boxed using the Elaborate
command. This may contain wild cards. Either -name or this option should be
used.
-input_pins pin_list
Specifies a Tcl list of input port names of the cell. This may contain wild cards.
-output_pins pin_list
Specifies a Tcl list of output port names of the cell. This may contain wild cards.
-library lib_name
Specifies the name of the library that contains the given cell name. This is the
logical library name rather than the physical library name unless the -
use_library_file_names option (to Elaborate, CalculatePower or ReducePower) is
in effect.
Example 1
TraceThruCell -name SCANCLKDFF -library fast90nm -input_pins SCAND

-output_pins SCANOUT
This command tells PowerArtist that for every instance of cell type SCANCLKDFF in
the design that is located in the fast90nm library, specified by the library composite
attribute in a Liberty file, if the clock tracer enters the cell instance via the SCAND
pin, trace out through the SCANOUT pin.
Example
TraceThruCell -blackbox PLL -input_pins * -output_pins *

PLL was specified using the -black_box_modules option to Elaborate. If the tracer
reaches any pin of such an instance, trace through all of its outputs.
TraceThruInstance
Use this command to specify the input-to-output path inside an instance or to
override the existing input-to-output path specified by the timing arcs.
If multiple TraceThru* commands resolve to the same instance, the first one
appearing in the clock file will take precedence. For all subsequent ones, the
following warning is issued:
wsengine: Warning 8501: Instance XYZ has already been assigned
data using the TraceThruInstance command that sets instance
name using pattern XYZ. TraceThru data will not be reset on
instance.
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WriteClockGatingConstraints
Syntax
TraceThruInstance -instance inst_name -input_pins pin_list

[-output_pins pin_list]
Arguments
-instance inst_name
Specifies the hierarchical instance name the clock tracer needs to trace through.
This may contain wild cards.
-input_pins pin_list
Specifies a Tcl list of input port names of the instance. This may contain wild
cards. If -input_pins is not specified, the following error message is issued:
wsengine: Error 8509: The command TraceThruInstance used for
instance name XYZ, must specify switch -input_pins Clock file:
test.clk
-output_pins pin_list
Specifies a Tcl list of output port names of the instance. This may contain wild
cards. If the clock tracer reaches the specified instance via any of the ports
specified in the input pin list, it will trace through to all of the ports specified in the
output pin list. Not specifying -output_pins is equivalent to specifying
-output_pins *.
Example 1
TraceThruInstance -name top.module1.* -input * -output *

For every instance underneath top.module1 in the design hierarchy, trace any input
through to any output. The instances may be inferred elements or instantiated gates.
Example 2
TraceThruInstance -name top.U1 -input CLK -output Q

Given this example, for instance top.U1, if the clock tracer reaches it via the CLK pin,
it will continue tracing with the net attached to the Q output pin.
WriteClockGatingConstraints
Use this command to generate synthesis constraints to exclude registers from clock
gating. See Generating Synthesis Constraints for more information.
Syntax
WriteClockGatingConstraints -power_db_name pdb_file

-constraints_savings float -top module_name
[-constraints_bus_naming_style string] [-constraints_log
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WriteReductionCompareFile (Beta)
file_name] [-constraints_output_file file_name]

[-constraints_synthesis_tool PC]
Arguments
-power_db_name pdb_file
Specifies the file name of the power database (.pdb) file. This is the only required
argument.
Alias: -pdb
-constraints_savings float
Specifies the target power savings that should be reached by the constraints. This
is a real number in Watts. You can use the CreateGraph command to determine
the value to use for this option.
Alias: -cumulative_savings
-top module_name
Specifies the name of the top module in the design.
-constraints_bus_naming_style string
Specifies how multi-bit register instances are named.
Alias: -bus_naming_style
-constraints_log file_name
Specifies the file name of the resulting log file.
Default: Constraints.log
Alias: -log
-constraints_output_file file_name
Specifies the file name of the resulting constraints output.
Default: output goes to the screen
Alias: -output_file
-constraints_synthesis_tool PC
Specifies the target synthesizer name. Currently, PowerArtist supports only PC
(for PowerCompiler™ from Synopsys™.
Default: PC
Alias: -synthesizer
Use this command to read-in power reductions from the reduction database (.pdb
file) and generate a rule file for the nCompare™ waveform comparison tool by
SpringSoft™. This allows you to verify the power reductions changes to your RTL.
Before you can use this command, you must first create a power database using the
ReducePower command. You can use it both before and after rewriting the RTL
(using the RewriteRTL command).
The output rule file generated by this command contains a comparison of only those
signals that are related to an implemented reduction but not affected by that
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reduction. Any mismatch in these signals will guide you to the corresponding
reduction. You do not need to start validation from the primary outputs.
For more information on verification of power reduction RTL changes, see
Performing Functional Verification of RTL Changes.
Syntax
WriteReductionCompareFile -power_db_name file_name

-top_instance sim_top_inst
-reduction_compare_output_rule_file file_name
[-reduction_compare_type rw | auto]
[-reduction_compare_golden_sim_file file_name]
[-reduction_compare_secondary_sim_file file_name]
[-reduction_compare_error_report_file file_name]
[-reduction_compare_log file_name]
Arguments
Specifies the name of the power database file.
Alias: -pdb
-top_instance sim_top_inst
Specifies the full path to the simulation top instance.
Alias: -topinst
-reduction_compare_output_rule_file file_name
Specifies the name of the output that will contain the generated rules. You will use
this file in the nCompare utility.
Alias: -output_rule_file
-reduction_compare_type rw | auto
Specifies the type of target reductions. Select “rw” to compare all rewritten
reductions or “auto” to compare all accepted reductions.
Default: rw
Alias: -type
-reduction_compare_golden_sim_file file_name
Specifies the path to the original FSDB file. If you do not specify this, PowerArtist
will use a place holder variable (set GoldenFSDB golden_fsdb_name) in the
rules file that you will later need to edit.
Alias: -golden_sim_file
-reduction_compare_secondary_sim_file file_name
Specifies the path to the new FSDB file that you get when you re-simulate your
design using the rewritten RTL. If you do not specify this option, PowerArtist will
use a place holder variable (set SecondaryFSDB fsdb_file_name) in the rule
file that you will later need to edit.
Alias: -secondary_sim_file
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WriteTechnologyFile
-reduction_compare_error_report_file error_report_file_name
Specifies the name of the file into which nCompare will output any mismatch error
messages. You can use the nce2report SpringSoft utility to generate a readable
text/html report as follows
nce2report -i error_report_file_name ...
Default: output_rule_file_name.nce
Alias: -error_report_file
-reduction_compare_log file_name
Specifies the name of the log file for this command.
Default: ReductionCompareFile.log
Alias: -log
WriteTechnologyFile
This command creates a PACE technology model file. You can use this file to
improve gate-level power accuracy. For complete details on how to create this file,
see Generating PACE Technology Files (Beta) in the PowerArtist Library
Developer’s Guide. For information on using this file in an analysis, see Using
PACE Technology Files During Power Analysis (Beta) in the PowerArtist User Guide.
Syntax
WriteTechnologyFile –top top_module_name

-power_tech_file file_name -scenario_file file_name -sdc_files
{file_name1 file_name2 ...} -spef_file file_name
-verilog_startup_file file_name [-default_transition_time float]
[-synlib_files {file_name1 file_name2 ...}]
[-multiple_license_files true | false]
[-wait_for_license true | false]
Arguments
-top top_module_name
Specifies the output file name containing technology information. You can specify
either a relative or absolute path name. You can also use an environment variable
in the path name.
Default: (none)
Alias: -scn
-sdc_files {file_name1 file_name2 ...}
Specifies a list of SDC files.
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WriteTechnologyFile
-spef_file file_name
Specifies a list of signal SPEF file(s).
-verilog_startup_file file_name
Specifies a single file containing a list of HDL files. This file is same as that used
by the -f option supplied to any Verilog simulator.
specified.
Alias: -dt
Specifies a list of liberty library files. You can also use the ReadLibrary command
to specify which Liberty libraries to read.
Default: false
Default: false
Alias: -wait
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active_edge
Alphabetical List of pt_set Variables

This section lists, alphabetically, all of the available pt_set variables. You can use
these variables in the command file, a script or directly on the command line.
active_edge
Specifies the edge of the clock that defines the start point for the first interval. This is
used for time-based power analysis.
Syntax
pt_set active_edge auto | positive | negative

Default: auto
Applies to: CalculatePower -analysis_type time_based and
activity_debug_flags
Prints debug information during any activity analysis.
Syntax
pt_set activity_debug_flags debug_values

Applies to: CalculatePower, GenerateActivityWaveforms and ReducePower
activity_file
Reads or writes the specified file as an intermediate activity file (it can be an IAF, a
VCD, or an FSDB file).
Syntax
pt_set activity_file file_name

Applies to: CalculatePower, GenerateEtclFile, GenerateActivityWaveforms,
PrintActivityData and ReducePower
activity_perform_esl_analysis
Performs Electronic System-Level (ESL) power analysis.
Syntax
pt_set activity_perform_esl_analysis true | false

Default: false
Applies to: CalculatePower
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activity_waveform_clock_edge
activity_waveform_clock_edge
Specifies the clock edge on which the analysis will begin. You can start the analysis
on the first rising edge (pos), falling edge (neg) or first edge (auto) of the reference
clock.
Syntax
pt_set activity_waveform_clock_edge pos | neg | auto

Default: pos (meaning positive or rising edge)
Applies to: GenerateActivityWaveforms
activity_waveform_clock_name
Specifies the full path name of the reference clock. The name is based on the -top
option used to generate your scenario file and is not based on the -topinst used to
control the starting point in your testbench.
Syntax
pt_set activity_waveform_clock_name clock_name

activity_waveform_cycles_per_interval
Specifies the number of clock cycles that would turn into one (x,y) data point in your
activity graph.
Syntax
pt_set activity_waveform_cycles_per_interval int

Default: 1
activity_waveform_graph_type
Specifies activity_per_cycle for clock cycle mode or frequency_per_cycle for
time-based mode.
Syntax
pt_set activity_waveform_graph_type activity_per_cycle |

frequency_per_interval
Default: activity_per_cycle
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activity_waveform_group_list
activity_waveform_group_list
Specifies a Tcl list of group names defined in a DefineGroup command. These
represent the instances you want to monitor.
Syntax
pt_set activity_waveform_group_list group_list

activity_waveform_interval_size
Specifies the length of your interval in time steps. The time is given as an integer
followed by one of the following standard time scale indicators: s = seconds, ms =
milliseconds, us = microseconds, ps = picoseconds, fs = femptoseconds, or as =
atoseconds.
Syntax
pt_set activity_waveform_interval_size time

activity_waveform_log
Specifies the log file name for activity file generation.
Syntax
pt_set activity_waveform_log file_name

activity_waveform_number_of_intervals
Defines the number of intervals to be analyzed.
Syntax
pt_set activity_waveform_number_of_intervals int | all

Default: all
activity_waveform_start_clock_cycle
Specifies the clock cycle number that will form the starting point for the analysis. The
combination of activity_waveform_cycles_per_interval and
activity_waveform_number_of_intervals defines the finishing clock cycle.
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activity_waveform_start_time
Syntax
pt_set activity_waveform_start_clock_cycle int

Default: 0
activity_waveform_start_time
Specifies the simulation time step that will form the starting point for the analysis. The
combination of activity_waveform_interval_size and
activity_waveform_number_of_intervals defines the finishing time step. The time is
given as an integer with the same standard time scale indicators described for pt_set
activity_waveform_interval_size.
Syntax
pt_set activity_waveform_start_time time

allowed_x_time
Specifies an amount of time a net can be in an X state continuously (not discrete). If
any signal is in X state (continuously) for more than the time specified with
-allowed_x_time then it is reported as WARNING 3344. For example:
#0
0$
#10
x$
#20
0$
#30
x$
#40
0$
#50
x$
#60
0$
#70
x$
Here, the total x duration is 10(20-10) + 10(40-30) + 10(60-50) + 10(70-60) = 40ns.

But the signal never remains in X state for more than 10ns of time—it changes its
value to 0. Therefore, if -allowed_x_time = 10 ns (or less) all four occurrences will be
counted. If -allowed_x_time is greater than 10ns, nothing will be counted. So here x
state means 1 x state continuously—not the entire X-state during the simulation.
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allowed_z_time
simulator ticks.
Syntax
pt_set allowed_x_time string

Default: 10ns
Applies to: CalculatePower and ReducePower
allowed_z_time
Specifies an amount of time a net can be in an Z state. If string ends with the letter
“s”, it is specified as time, otherwise it is specified in simulator ticks. The nets that
exceed the allowed time in the Z state are reported in a text file (see -ftn_report).
Syntax
pt_set allowed_z_time string

Default: 100ns
analysis_type
Performs average power analysis or time-based power analysis.
Syntax
pt_set analysis_type average | time_based

Default: average
arc_based_estimation
Enables arc-based power estimation for gate-level instances.
Syntax
pt_set arc_based_estimation true | false

Default: false
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average_cpf_in_file (Beta)
average_cpf_in_file (Beta)
Specifies an input file containing power constraints in CPF. Though the software
supports a subset of the total CPF 1.1 command set, it will read CPF files that use all
of the available commands. Commands not supported are ignored. Similarly, the
software ignores any command options that are specified but not supported. For
more information, see Using a CPF Input Flow (Beta).
Syntax
pt_set average_cpf_in_file file_name

Applies to: CalculatePower -analysis_type average
average_cpf_output_file (Beta)
Writes out CPF constraints that capture Multi Supply Voltage (MSV) and Power Shut-
Off (PSO) design intent. You can then use these constraints in other tools such as
Cadence’s RTL Compiler™. The resulting file is in ASCII format, therefore, you can
add to or modify the generated CPF commands. The commands are not expected to
capture of all the information required to synthesize the design and capture all of the
information required to synthesize or place and route your design. For details, see
Using a CPF Output Flow (Beta) in the PowerArtist User Guide.
Syntax
pt_set average_cpf_output_file file_name

average_html_report_title
Generates an HTML report file with the specified name. By default, no HTML file is
produced.
Syntax
pt_set average_html_report_title file_name

average_report_file
Writes a report file for an average power analysis with the specified file name.
Syntax
pt_set average_report_file file_name

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average_report_options
average_report_options
Specifies one or more options that determine the contents of the report file.
Syntax
pt_set average_report_options string
Available Reporting Options

Examples are:
(01 CLK), (01 CLK || 10 CLK), (01 CLK && CS)
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average_results_file
average_results_file
Writes average power results, in the netlist file format, to the given file. Note that if
you are reaching average power analysis capacity limits, do not specify this option.
Syntax
pt_set average_results_file file_name

average_upf_in_file (Beta)
Specifies a UPF file as input for an average power analysis.
Syntax
pt_set average_upf_in_file file_name

average_write_power_db
Writes out a power database (.pdb) for an average power analysis. When this option
is specified, the estimators will output the OpenAccess database representation of all
the power analysis results.
Syntax
pt_set average_write_power_db true | false

Default: false
black_box_modules
Specifies modules to be black-boxed. When specified, the Elaborate command will
not infer logic for each module/unit in the Tcl list and its corresponding hierarchical
children. The is also used by the RewriteRTL command.
You can use wild cards. For example, “-black_box_modules dw*” will mark all
modules starting with “dw” to be black boxed. The wild card matching follows the
same convention as UNIX shell wild card file name matching, specifically:
* : matches zero or any number of characters
? : matches any single character
[abc] : matches any single character within the braces, one of “abc” in this case.
Characters are matched using the case-sensitivity of the HDL language used.
Names are matched sensitive to case in Verilog, or insensitive to case in VHDL or
mixed-language designs.
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blast_regfile
Syntax
pt_set black_box_modules module1 module2 ...

Applies to: Elaborate and RewriteRTL
blast_regfile
Specifies a Tcl list of comma-separated list of 2-D arrays to bit-blast or all (all arrays
will be bit-blasted). For more information on using this option, see Controlling Array
Syntax
pt_set blast_regfile list | all

Default: none
Applies to: Elaborate
calculate_log
Syntax
pt_set calcualte_log file_name

Default: Calculate.log
capacitance_file
Syntax
pt_set capacitance_file load_file

Applies to: ReadSDC and ReducePower
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case_insensitive
case_insensitive
insensitive name matching. By default, the scenario database is constructed to be
case sensitive if the design is entirely in Verilog, or case insensitive if the design is
VHDL or combination of VHDL and Verilog.
Syntax
pt_set case_insensitive true | false

Default: false
case_sensitive
sensitive name matching. By default, the scenario database is constructed to be
case sensitive if the design is entirely in Verilog, or case insensitive if the design is
VHDL or combination of VHDL and Verilog.
Syntax
pt_set case_sensitive true | false

check_synlib_semantics
Performs semantic checks on specified .lib files.
Syntax
pt_set check_synlib_semantics true | false

Default: false
compare_with_results_file
Reads the specified result file and prints a report section showing the difference in
power between the result file and the current analysis.
Syntax
pt_set compare_with_results_file file_name

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compress_gaf
compress_gaf
Writes out a compressed .gaf file.
Syntax
pt_set compress_gaf true | false

Applies to: CalculatePower -analysis_type average and ReducePower
constraints_bus_naming_style
Specifies how multi-bit register instances are named.
Syntax
pt_set constraints_bus_naming_style string

Applies to: WriteClockGatingConstraints
constraints_log
Specifies the file name of the resulting log file from the WriteClockGatingConstraints
command.
Syntax
pt_set constraints_log file_name

Default: Constraints.log.
constraints_output_file
Specifies the file name of the resulting constraints output.
Syntax
pt_set constraints_output_file file_name

Default: output goes to the screen
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constraints_savings
constraints_savings
Specifies the target power savings that should be reached by the constraints. This is
a real number in Watts. You can use the CreateGraph command to determine the
value to use for this option.
Syntax
pt_set constraints_savings
constraints_synthesis_tool
Specifies the target synthesizer name. Currently, PowerArtist supports only PC (for
PowerCompiler™ from Synopsys™.
Syntax
pt_set constraints_synthesis_tool PC
Default: PC
count_glitches_as_toggles
In average power analysis mode, counts zero-duration glitches as toggles.
Syntax
pt_set count_glitches_as_toggles true | false

Default: false
critical_messages
summary. Note that when you specify a message ID list, it will overwrite the current
list of critical messages. If you want to maintain the default list and simply add to it,
you must include the message IDs that are considered critical by default.
Syntax
pt_set critical_messages tcl_list_message_ids

Default: "1371 1409 1425 2034 2046 2089 2818 2859 3331 3332 3344 8309 8517"
Applies to: CalculatePower, GenerateActivityWaveforms, ReducePower and
RewriteRTL
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current_output_file
current_output_file
default).
Syntax
pt_set current_output_file file_name

Default: current_output.tcl
debug_instances_file
-xdebug_switches
full_hierarchical_instance_name1
full_hierarchical_instance_name2
...
Syntax
pt_set debug_instances_file file_name

default_dont_use_cells
process. The format of the file is as follows:
cellName libraryName
Sample File
DFFRX1 typical_13
TLATX1 typical_13
Syntax
pt_set default_dont_use_cells file_name

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default_output_load
default_output_load
Sets the default output load to the specified value. This load capacitance is applied
to all primary outputs not listed in the load or wiring capacitance files.
Syntax
pt_set default_output_load float

Default: 0
default_transition_time
specified.
Syntax
pt_set default_transition_time float

detailed_vertical_report
Syntax
pt_set detailed_vertical_report true | false

Default: false
disable_glitch_propagation
Syntax
pt_set disable_glitch_propagation true | false

Default: false
domain_frequency_cell_selection
When set to true, this variable activates frequency-based cell assignment. There is
no default value for the domain_frequency_cell_selection variable. When combined
with the -frequency option to the SetClockNet command, this variable determines
when frequency-based cell selection occurs. Frequency-based cell selection occurs
in either of the following two situations:
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elaborate_ignore_directives
 “pt_set domain_frequency_cell_selection” is specified and set to true.

 “pt_set domain_frequency_cell_selection” is not specified at all and -frequency is
Syntax
pt_set domain_frequency_cell_selection true | false

Default: (see description above)
elaborate_ignore_directives

input in;
output out;
assign out = in;
endmodule
pt_set elaborate_ignore_directives quickturn
Syntax
pt_set elaborate_ignore_directives tcl_list_of_values

elaborate_log
Specifies the log for the Elaborate command.
Syntax
pt_set elaborate_log file_name

Default: Elaborate.log
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elaborate_write_power_db
elaborate_write_power_db
Writes out a Power Database (.pdb file) for use in PowerArtist. The .pdb is an
OpenAccess database representation the power analysis results.
Syntax
pt_set elaborate_write_power_db true | false

Default: false
enhanced_vcd
Reads the IAF file as an Enhanced VCD format file. See Acquiring Simulation
Data in the PowerArtist User Guide for more information about IAF and Enhanced
VCD.
Syntax
pt_set enhanced_vcd true | false

Default: falseApplies to: CalculatePower, GenerateActivityWaveforms,
ReducePower
etcl_file
Specifies the name of final ETCL file to be generated by the GenerateEtclFile
command.
Syntax
pt_set etcl_file file_name

Applies to: CalculatePower -analysis_type time_based and GenerateEtclFile
etcl_finish_time
Specifies the end time for the activity window you want covered by the etcl file.
Standard engineering notation applies (for example, 10ns). The start and end time
are written to a temporary Tcl file that contains the following command which is the
file name supplied to the -tcl option.
studio_state_setup_time_based start_time end_time etcl_file_name
Syntax
pt_set etcl_finish_time time

Applies to: GenerateEtclFile
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etcl_log
etcl_log
Specifies the name of the output log file for the GenerateEtclFile command.
Syntax
pt_set etcl_log
Default: GenerateEtclFile.log
etcl_start_time
Specifies the start time for the activity window you want covered by the etcl file.
Syntax
pt_set etcl_start_time time

finish_time
Stops collecting data at the specified string. If string ends with the letter “s”, it is
specified as time, otherwise it is specified in simulator ticks.
Syntax
pt_set finish_time time

Default: (none)
flop_clock_activity
Monitors the activity of clock pins in registers in your design. The
file_name_prefix specifies the prefix you want to use for flop clock activity output
files (for example, “fca”).
Syntax
pt_set flop_clock_activity file_name_prefix

Applies to: CalculatePower -analysis_type time_based
force_stimulus_processing
VCD file processing typically takes a significant amount of time for any meaningful
size design. If you want to do some what-if experiments without re-reading your
stimulus file, you have to set this argument to “false”. When set to true (the default)
your stimulus file gets re-read during a simulation-based, average power analysis.
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forced_x
Syntax
pt_set force_stimulus_processing true | false

Default: true
forced_x
Replaces X with a binary value of 1 or 0 wherever they occur while reading a VCD or
FSDB simulation trace file.
Syntax
pt_set forced_x 0 | 1
fsdb_output_file
Specifies the name of the FSDB file. The FSDB file is a graphical file showing power
over time. You can view the resulting .ptcl file using the Apache Waveform Viewer (or
the Verdi™ product from SpringSoft).
Syntax
pt_set fsdb_output_file file_name

Applies to: CalculatePower and GenerateActivityWaveforms
ftn_report_file
(FTN).
Syntax
pt_set ftn_report_file file_name

gaf_file
Reads or writes the specified global activity file (GAF).
Syntax
pt_set gaf_file file_name

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gate_level_netlist
gate_level_netlist
Directs PowerArtist to regard the design as a gate-level netlist. This has the following
 During compilation, Elaborate will ensure that the design is a gate-level netlist. If
RTL operators are encountered (other than direct assignments of one signal to
another), then a warning is printed and the operators are removed from the
design.
 During either average or time_based power analysis, PowerArtist will skip default
cell selection for RTL operators. If all simulation activity has been directly recorded
and, vectorless, pin-based, or mixed probabilistic analysis is not required, then
power analysis skips activity propagation for additional run time efficiency.
Syntax
pt_set gate_level_netlist true | false

Default: false
Applies to: Elaborate and CalculatePower
graph_class
Specifies the type of reduction data that should be examined for plotting. Currently,
this variable only supports the “clock” value. This will generate graph data related to
clock gating opportunities. You must specify this variable when running the
CreateGraph command.
Syntax
pt_set graph_class clock

Default: clock
Applies to: CreateGraph
graph_log
Specifies the log file name containing any messages generated by the CreateGraph
command.
Syntax
pt_set graph_log file_name

Default: CreateGraph.log
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graph_output_file
graph_output_file
Specifies the PTCL file name containing graph data for the CreateGraph command.
If you don’t specify this option, the PTCL is output to the log file, which by default is
named CreateGraph.log.
Syntax
pt_set graph_output_file ptcl_file_name

Default: Output goes to the CreateGraph.log file
graph_type
Specifies the form of the graph to be generated by the CreateGraph command.
Currently, the graph type supports only “power_savings”. This generates a
cumulative power savings curve as a function of the number of RTL reduction
opportunities.
Syntax
pt_set graph_type power_savngs

Default: power_savngs
heartbeat
Prints progress information during GAF file creation. The specified string (in
For example, if the time scale for your simulation results is 10 ns. Specifying “pt_set
heartbeat 1” will print a progress message every 10 ns of simulation time. If you
specify “pt_set heartbeat 20ns”, you will get a heartbeat message approximately
every 20 ns of simulation time.
must have simulation signal change results in your IAF file that occur approximately
every heartbeat.
Syntax
pt_set heartbeat string

Default: none
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html_report_directory
html_report_directory
This option writes HTML files into the specified directory. The top-level file is named
index.html. This option must be used with the average_html_report_title variable.
Syntax
pt_set html_report_directory dir_name

ignore_SPEF_C_comments
Syntax
pt_set ignore_SPEF_C_comments true | false

Default: false
ignore_toggles_through_x
Syntax
pt_set ignore_toggles_through_x true | false

Default: false
ignore_translate_off
Syntax
pt_set ignore_translate_off true | false

Default: false
ignore_translate_off_files
Specifies a Tcl list of files for which to ignore translate_off and translate_on meta
comments.
Syntax
pt_set ignore_translate_off_files {file1 file2...}

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instance_power_threshold
instance_power_threshold
power report.
Syntax
pt_set instance_power_threshold float

Default: 0
interpret_pin_caps_as
Instructs PowerArtist to use the rise_capacitance_range and fall_capacitance_range
attributes to calculate pin capacitances. The actual pin capacitance values are
calculated in the following manner:
For more information on how pin capacitance is calculated, see Transition Counting
on Nets.
Syntax
pt_set interpret_pin_caps_as min | max | avg

Default: (none)
interval_size
Specifies the number of intervals into which the simulation will be broken. For more
information on the usage of this option and an example, see the description of the
pt_set statistics variable.
Syntax
pt_set interval_size float

library_defaults_file
Specifies a Sequence Library Defaults (SLD) file.)
Syntax
pt_set library_defaults_file file_name

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list_required_traces
list_required_traces
Generates a file containing a list of nets that must be monitored (recorded) to ensure
an accurate power analysis. The resulting file will contain one net name per line. This
file is used in a Palladium flow. For more information, see Acquiring Simulation Data
in Palladium Flows.
Syntax
pt_set list_required_traces file_name

load_file
Reads the specified back-annotated load capacitance file. See Capacitance File
Format for more information.
Syntax
pt_set load_file file_name

lower_case_vhdl
Generates lower-case names for VHDL.
Syntax
pt_set lower_case_vhdl true | false

Default: false
macro_directories
Specifies a Tcl list of directories that contain power macro models. The Elaborate
command searches these directories in the order listed, and the default directory is
searched last.
You can use the power-aware models in these directories to replace HDL models
without modifying your design source. See the Getting Your Design into
PowerArtist chapter in your user guide for more information about power macros.
Syntax
pt_set macro_directories {directory1 directory2...}

Default: $POWERTHEATER_ROOT/pthdl_src/macros
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max_clock_depth
max_clock_depth
Limits the forward clock-tracing depth to the number specified. Prevents excessive
time spent in forward tracing. Very rarely would you encounter a clock depth greater
than the default. You should only need to use this variable when you get a 1441
warning.
Syntax
pt_set max_clock_depth int

Default: 40
max_time_stamps
Specifies the maximum number of time stamps printed in the report for each instance
or class of instances defined in the monitor file. The time stamps correspond to the
times when the power was the highest for those instances.
Syntax
pt_set max_time_stamps integer

Default: 10
maximum_number_of_errors
Specifies the maximum number of errors to be printed in any given message.
Syntax
pt_set maximum_number_of_errors integer

Default: 50
min_regfile_bit_count
Specifies a minimum bit count (words x length) of 2-D arrays to be preserved as
register files or latch files. For more information on using this option, see Controlling
Array Inferencing in the PowerArtist User Guide.
Syntax
pt_set min_regfile_bit_count integer

Default: 32
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min_regfile_word_count
min_regfile_word_count
Specifies a minimum word count 2-D arrays to be preserved as register files or latch
files. For more information on using this option, see Controlling Array Inferencing in
the PowerArtist User Guide.
Syntax
pt_set min_regfile_word_count integer

Default: 32
min_regfile_word_length
Specifies a minimum word length of 2-D arrays to be preserved as register files or
Syntax
pt_set min_regfile_word_length integer

Default: 3
mixed_sim_prob_estimation
simulation data.
Syntax
pt_set mixed_sim_prob_estimation true | false

Default: false
Applies to: CalculatePower, Elaborate, GenerateActivityWaveforms and
ReducePower
mode_file
Reads the specified mode control file. For modal analysis, you must run
CalculatePower with this option. For more information on the mode file, see Mode
File Format. Note that this variable cannot be used with the gate_level_netlist
variable (or -gate_level_netlist option to CalculatePower).
Syntax
pt_set mode_file file_name

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multiple_license_files
multiple_license_files
Allows PowerArtist licenses to be served by FlexLMTM license servers.
Syntax
pt_set multiple_license_files true | false

Default: false
Applies to: all commands, it is a global setting
multiple_testbench_control_file
Calculates an averaged power number based on multiple GAF files that were
generated using different testbenches. These GAF files are specified via a control file
you specify as an argument to this variable. Each GAF must be written for the same
design (top level), but cover different portions of the design, or supply different vector
sets. The testbenches do not need to be of equal length or mutually exclusive, but
they are required to have the same top instance.
Syntax
pt_set multiple_testbench_control_file control_file_name

no_default_macros
Instructs Elaborate to not search for macros in the directory specified with the
macro_directories variable only—not the default macros in the default
$POWERTHEATER_ROOT/pthdl_src/macros directory.
Syntax
pt_set no_default_macros true | false

no_maximum_error_list
Removes any limit on the number of messages that can be printed. You should use
this option sparingly.
Syntax
pt_set no_maximum_error_list message_num1 message_num2 ...

Applies to: Elaborate, CalculatePower and ReducePower
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no_module_net_capacitances
no_module_net_capacitances
When set to true, disables analysis of inter/intra-module net capacitances.
Syntax
pt_set no_module_net_capacitances true | false

Default: false
no_slew_calculation
An internal slew calculator is enabled by default in all power engines of PowerArtist.
This variable disables this slew calculator.
Syntax
pt_set no_slew_calculation true | false

Default: false
num_clock_cycles
Sets the interval size as a number of clock cycles for RTL time-based analysis. The
interval size is the period of the block into which PowerArtist will split the simulation.
It is recommended that you choose an interval greater than 1% of the total simulation
time.
Syntax
pt_set -num_clock_cycles int

Default: 0
Applies to: CalculatePower -analysis_type time_based and ReducePower
output_ascii_netlist
Writes the netlist data to the specified ASCII file.
Syntax
pt_set output_ascii_netlist file_name

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output_current
output_current
Writes out current information to the waveform files instead of power numbers. You
might want to use this feature, for example, if you were looking for di/dt changes for
voltage drop analysis.
Syntax
pt_set output_current true | false

Default: false
output_rtl_dir_name
Specifies the directory containing the rewritten RTL directory structure.
Syntax
pt_set output_rtl_dir_name
Default: ./rewrite
Applies to: RewriteRTL
output_startup_file
Creates a Verilog startup file with the given name.
Syntax
pt_set output_startup_file file_name

Default: output_rtl_dir_name/rewrite.vc
parameter_maps
Assigns values to different parameters for a top-level VHDL or Verilog module. For
example, suppose you have the following Verilog (or equivalent VHDL fragment:
module top(in,out);
parameter size=2;
input [size-1:0] in;
output [size:0] out;
assign out = in+1;
endmodule
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parameter_maps
You could override the size parameter by adding the pt_set parameter_maps
variable in your command file:
pt_set parameter_maps size=4

Elaborate
When PowerArtist elaborates the Verilog design, size would be set to 4. If you have
multiple parameters you want to override, you could use multiple instances of the
pt_set parameter_maps variable or include multiple values with a Tcl list of
name=value pairs. For example:
pt_set parameter_maps p1=4
pt_set parameter_maps p2=5
accomplishes the same operation as:
pt_set parameter_maps p1=4 p2=5
You can also use the pt_set parameter_maps variable to set generics. Take, for
example, the following VHDL fragment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS
GENERIC(SIZE : integer);
PORT ( AA, BB, TT : IN STD_LOGIC_VECTOR(SIZE-1 downto 0);
CC : OUT STD_LOGIC_VECTOR(SIZE-1 downto 0));
END TOP;
ARCHITECTURE A0 OF TOP IS
BEGIN
CC <= BB AND TT;
END A0;
Given this fragment, you could add the following lines to your command file to set the
SIZE parameter:
pt_set parameter_maps SIZE=4

Elaborate
Syntax
pt_set parameter_maps name=value

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pc_constraint_file
pc_constraint_file
Specifies the name of the file into which PowerArtist will write out
set_clock_gating_signals commands. You can then use this file in a synthesizer. For
information, see Rewriting Your RTL in the PowerArtist User Guide.
Syntax
pt_set pc_constraint_file file_name

Applies to: ReducePower
peak_cycle_file
Generates an output file that contains the commands required to generate the Etcl
(.etcl) file. An Etcl file saves the primary inputs and register state information for a
given point in time. It can be used by CoolTime when calculating dynamic voltage
drop analysis. If the “pt_set peak_cycle_processing_mode” variable is set to “auto”,
then this file will contain the studio_state_setup_time_based command, and is
passed on to the GenerateEtclFile command for generating an etcl file; otherwise,
the file will contain peak power information for each clock cycle.
Syntax
pt_set peak_cycle_file file_name

Default: pcf.tcl
peak_cycle_processing_mode
Selects the processing mode for generating an etcl file.
 auto: the time-based engine will automatically determine the clock cycle with the
highest power and will run CalculatePower with the correct options to generate the
required etcl file. If multiple cycles have the same power, then the first one that
occurs in time will be selected.
 interactive: the GUI will generate a peak cycle file. When power analysis
completes, you will be taken to another GUI page that allows you to interactively
scan the power on each clock cycle and choose the cycle of interest. Once you
complete this step, PowerArtist generates the required etcl file.
Syntax
pt_set peak_cycle_processing_mode auto | interactive

Default: auto
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peak_waveform_file
peak_waveform_file
Generates an output file that contains peak power information for all clock cycles.
Syntax
pt_set peak_waveform_file file_name

power_db_name
Reads in the specified power database file. If you want to use a PDB file, you must
specify the name of that file with this option.
Syntax
pt_set power_db_name file_name

Applies to: CalculatePower, CreateGraph, ReadSDC, ReducePower, RewriteRTL
and WriteClockGatingConstraints
power_tech_file (Beta)
Specifies a PACE technology file for capacitance estimation. Capacitance estimation
using PACE overrides capacitance estimation using wire load models, whereas other
capacitance annotation methods override capacitance estimation using PACE. For
more information, see Using PACE Technology Files During Power Analysis (Beta) in
the PowerArtist User Guide and Chapter 9, Generating PACE Technology Files
(Beta) in the PowerArtist Library Developer’s Guide.
Syntax
power_tech_file file_name
Applies to: CalculatePower, ReducePower and WriteTechnologyFile
preserve_regfile
Specifies either a Tcl list of 2-D arrays to preserved or all (all arrays will be
preserved). For more information on using this option, see Controlling Array
Syntax
pt_set preserve_regfile list | all

Applies to: Elaborate and ReducePower
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print_missing_sim_nets
print_missing_sim_nets
Prints the names of nets that are in your scenario file but are not in your simulation
file.
Syntax
print_missing_sim_nets true | false

Default: false
ptcl_output_file
Specifies the name of the PTCL file generated by the GenerateActivityWaveforms
command. You need to specify this variable (or the equivalent command option to the
GenerateActivityWaveforms command) to name the PTCL file. The PTCL file is a
graphical file showing power over time that you can view using the Apache
Waveform Viewer.
Syntax
pt_set ptcl_output_file file_name

quiet
Suppresses the printing of Note-level messages.
Syntax
pt_set quiet true | false

Default: false
Applies to: all command file commands
reduction_classes
Specifies the type (or “class”) of reduction to run. By default, all classes are run. The
available classes are:
 linter, which includes: Memory Power Linter, MUX Power Linter, Register Power
Linter, and Clock Enable Condition Linter
 logic, which includes: Datapath Operator Isolation
 memory, which includes: Split Memory Words, Gate Memory Clock
 clock, which includes: Prism, Local Explicit Clock Enable, Low-Activity Non-
Enabled Register, and Observability Don't Care
 all, which includes all PowerBots.
If you want to exclude a class, for example, clock, you can specify this option and
simply exclude that class name from the specified list. To further fine-tune your
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reduction_compare_error_report_file
reduction, you can use this option in conjunction with the skip_reduction_list variable.
For example, you could do the following:
pt_set reduction_classes clock

pt_set skip_reduction_list prism
Given these settings, PowerArtist will only run the LNR and ODC PowerBots.
Syntax
pt_set reduction_classes linter | logic | memory | clock | all
reduction_compare_error_report_file
Specifies the name of the file into which nCompare will output any mismatch error
messages. You can use the nce2report SpringSoft utility to generate a readable text/
html report as follows:
nce2report -i error_report_file_name ...
Syntax
pt_set reduction_compare_error_report_file file_name

Applies to: WriteReductionCompareFile (Beta)
reduction_compare_golden_sim_file
Specifies the path to the original FSDB file against which the new FSDB (with the
new RTL) file will be compared by the WriteReductionCompareFile command.
Syntax
pt_set reduction_compare_golden_sim_file file_name

reduction_compare_log
Specifies the name of the log file for the WriteReductionCompareFile command.
Syntax
pt_set reduction_compare_log file_name

Default: false
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reduction_compare_output_rule_file
reduction_compare_output_rule_file
Specifies the name of the output rule file to be generated by the
WriteReductionCompareFile command.
Syntax
pt_set reduction_compare_output_rule_file file_name

reduction_compare_secondary_sim_file
Specifies the name of the rewritten FSDB file against which the golden FSDB file is
to be compared.
Syntax
pt_set reduction_compare_secondary_sim_file file_name

reduction_compare_type
Specifies the types of power reductions to compare. You can select either “rw” to
compare all rewritten reductions or “auto” to compare all accepted reductions.
Syntax
pt_set reduction_compare_type rw | auto

reduction_cpf_in_file (Beta)
Specifies an input file for reduction that contains multiple voltage domains and power
gating design intent constraints in the Common Power Format (CPF). For details,
see Using a CPF Input Flow (Beta) in the PowerArtist User Guide.
Syntax
pt_set reduction_cpf_in_file file_name

reduction_cpf_output_file (Beta)
Off (PSO) design intent. You can then use these constraints in other tools such as
Cadence’s RTL Compiler™. The resulting file is in ASCII format, therefore, you can
add to or modify the generated CPF commands. The commands are not expected to
capture of all the information required to synthesize the design and capture all of the
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reduction_debug_flags
information required to synthesize or place and route your design. For details, see
Using a CPF Output Flow (Beta) in the PowerArtist User Guide.
Syntax
pt_set reduction_cpf_output_file file_name

reduction_debug_flags
Specifies debug flags to be applied during a reduction run.
Syntax
pt_set reduction_debug_flags debug_flags

The following flags are available:
@—writes out debug information to an ASCII file for the GMC PowerBot.
+—writes out debug information to an ASCII file for the ODC PowerBot.
&—writes out debug information to an ASCII file for the DOI, LNR, MUX, REG,
MEM, CEC and SMW PowerBots.
# —writes out debug information to an ASCII file for the Prism PowerBot.
The following numeric flags print information to the screen for different PowerBots.
h—prints details of the SMW analysis
0—prints details of the ODC constraints analysis phase
2, 6, 7—prints details of the LEC analysis
2, 4, 5—prints details of the LNR analysis
8—prints details of the ODC power estimation phase
For details on the information that is generated using these debug flags, see the
descriptions of the PowerBots in the Examining and Implementing Power
Reduction Opportunities chapter in the PowerArtist User Guide.
reduction_dont_touch_clocks
Specifies a list of clock domains that you want to analyze but prevent from being
automatically rewritten. This option interacts with the SetClockNet -gate_clock true |
false option. For details on the effects of this option, see Controlling Clock Domains
During Reduction.
Syntax
pt_set reduction_dont_touch_clocks {clock_net1 clock_net2 ...}
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reduction_dont_touch_modules
reduction_dont_touch_modules
Specifies a list of modules to exclude from reduction analysis. You cannot use wild
cards in for the module names. The names are the base module type names before
parametrization creates unique names. For example, suppose you have a
parameterized module named block. You then instantiate block in the following
manner:
block #(4) blk1(....);
The inferred module type name becomes block(SIZE=4). To prevent block from
being considered for reduction and rewrite, you would specify the following
command:
pt_set reduction_dont_touch_modules block
This also affects the rewrite process.
Syntax
pt_set reduction_dont_touch_modules
reduction_hierarchy
Controls whether reduction opportunities are allowed to cross hierarchical
boundaries. If you set this to “full” the reduction engine will attempt to find as many
opportunities as possible that don’t cross hierarchical boundaries (for example,
Prism will break register chains at module boundaries and attempt to start a new
chain with a generated enable). If optimization across a boundary is not possible, the
opportunity is still saved for you to see in the GUI but it is not auto-accepted. The
default value for this option is “none” because RTL rewrite does not currently make
RTL changes that cross hierarchical boundaries.
Syntax
pt_set reduction_hierarchy none | full

Default: none
reduction_html_report_title
Generates an HTML report file with the specified name. By default, no HTML file is
produced.
Syntax
pt_set reduction_html_report_title file_name

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reduction_log
reduction_log
Specifies the name of the log file for reduction analysis.
Syntax
pt_set reduction_log file_name

Default: ReducePower.log
reduction_max_bit_width
generated. Currently the only enable generation method that uses this parameter is
LNR to prevent XOR/OR trees from becoming too large.
Syntax
pt_set reduction_max_bit_width int

Default: 16
reduction_max_memory_split
Specifies the maximum number of memory splits allowed by the SMW PowerBot. By
default, ReducePower will attempt to split a memory into two smaller-size memories.
You can change this value to a higher number to allow the SMW PowerBot to
attempt to further split the original memories.
Syntax
reduction_max_memory_split int
Default: 2
reduction_min_bit_width
Specifies the minimum bit width for ungated registers. Ungated registers must be
greater than or equal to the minimum bit width value to be considered as a candidate
register. Specifies the minimum bit width for generating XOR enables as part of the
Prism PowerBot.
Syntax
pt_set reduction_min_bit_width
Default: 3
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reduction_overwrite_power_db
reduction_overwrite_power_db
If set to true, overwrites the existing power database (.pdb) file. If not set, PowerArtist
incrementally updates the reduction data for all the reductions that are enabled
without updating the average power numbers calculated from the previous run.
Default: false
Syntax
pt_set reduction_overwrite_power_db true | false
reduction_priority
Controls the way clock gating is performed in a reduction run. If you select “skew”,
PowerArtist will either include all bits of a register bank for clock gating or none. This
could reduce your power savings, but also minimizes clock skew between bits of the
same register bank. If you are concerned about minimizing clock skew, select this
option. If you select “power” PowerArtist clock gates only those bits that save
power—without regard to the impact on clock skew. This option works with the LNR
and ODC PowerBots. Note that the LEC PowerBot is always set to “skew”. The value
of this option is displayed in the header of the .red file.
Syntax
pt_set reduction_priority skew | power

Default: skew
reduction_report_csv_file
Specifies the name of the output CSV file generated by the ReportReductions
command.
Syntax
pt_set reduction_report_csv_file file_name

Applies to: ReportReductions
reduction_report_csv_separator
Specifies the separator to be used in the CSV report file.
Syntax
pt_set reduction_report_csv_separator
Default: ,
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reduction_report_file
reduction_report_file
Writes a report file for power reduction analysis with the specified file name.
Syntax
pt_set reduction_report_file file_name

reduction_report_instance
Specifies the names of instances for which you want to report power analysis results.
You can use glob-style wild card characters. If not specified, all instance reductions
will be reported.
Syntax
pt_set reduction_report_instance inst_name

Default: * (all instances)
reduction_report_log_file
Specifies the name of the log file generated by the ReportReductions command.
Syntax
pt_set reduction_report_log_file file_name

Default: ReductionReport.log
reduction_report_module
Specifies the name of module for which you want to report power analysis results.
You can use glob-style wild card characters. If not specified, all instance reductions
will be reported.
Syntax
pt_set reduction_report_module
Default: *
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reduction_report_options
reduction_report_options
Specifies a list of reporting options.
Syntax
pt_set reduction_report_options string
Available Reporting Options

Examples are:
(01 CLK), (01 CLK || 10 CLK), (01 CLK && CS)
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reduction_report_type
reduction_report_type
Reports reduction information in terms of the power savings you can achieve
(power_savings) or how difficult it will be to achieve the savings
(reduction_vs_effort).
Syntax
pt_set reduction_report_type power_savings | reduction_vs_effort

reduction_results_file
Writes power reduction data to the specified results file. This file is needed to use
compare_with_results_file variable.
Syntax
pt_set reduction_results_file file_name

reduction_threshold
Limits the display to only those reductions that would save more than the specified
percentage of total power.
Syntax
pt_set reduction_threshold percent_pwr_savings

Default: 0.001
reduction_topology
Controls whether PowerArtist considers power when determining if a reduction
opportunity should be automatically accepted. When set to true, the algorithms for
the Prism and ODC PowerBots will not take power into consideration when
determining whether or not to accept a reduction opportunity.
Syntax
pt_set reduction_topology true | false

Default: false—a reduction opportunity is considered only if the total power savings
is positive.
Apache Design, Inc.

reduction_upf_in_file (Beta)
reduction_upf_in_file (Beta)
Specifies a UPF file as input for power reduction analysis.
Syntax
pt_set reduction_upf_in_file file_name

reference_clock
Specifies the reference clock that controls when a clock starts and the length of its
period.
Syntax
pt_set reference_clock
reset_library_negative_power
On an arc-by-arc basis, after the power computation for an arc is done, if its power is
less than 0, this option sets it to 0.
Syntax
pt_set reset_library_negative_power true | false

Default: false
reset_negative_power
Syntax
pt_set reset_negative_power true | false

Default: false
rewrite_debug_flags
Prints debug information for the rewrite process.
Syntax
pt_set rewrite_debug_flags string

The following options are available:
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rewrite_log
F—prints (to your screen) information about the current processing steps
performed by rewrite.
g—prints (to your screen) information related to failed rewrites. This will also
generate files that begin with rw_. Example files include: rw_details.txt,
rw_failed.txt, and rw_stats.txt.
rewrite_log
Writes an output log file with the given name.
Syntax
pt_set rewrite_log file_name

Default: RewriteRTL.log
rewrite_no_inline_modules
When set true, RewriteRTL generates the pa_modules.v file for PowerBots LNR,
FCE and ODC. Depending on your design, at most, the following modules will be
created:
ADS_PA_COMPARE_WITH_ZERO
ADS_PA_NEGEDGED_ADELAY
ADS_PA_NEGEDGED_DELAY
ADS_PA_NEGEDGED_SDELAY
ADS_PA_POSEDGED_ADELAY
ADS_PA_POSEDGED_DELAY
ADS_PA_POSEDGED_SDELAY
The in-lining of the functionality is switched off. When set to false (the default) you
will have module instantiations of the above in your RTL. For example,
< ADS_PA_COMPARE_WITH_ZERO pa_compare_inst( .match(pa_q_lnr_enable), .value(|(q ^

pa_q_lnr_rhs)) ) ;
---
> ìfdef SYNTHESIS
> assign pa_q_lnr_enable = (|(q ^ pa_q_lnr_rhs));
> èlse
> assign pa_q_lnr_enable = (0 !== (|(q ^ pa_q_lnr_rhs)));
> èndif
Syntax
pt_set rewrite_no_inline_modules true | false

Default: false
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rewrite_reduction_mapping_file
rewrite_reduction_mapping_file
Generates a mapping file that specifies the parameters that can be used to control
each of the reduction opportunities in RTL.
Syntax
pt_set rewrite_reduction_mapping_file file_name

rewrite_report_file
Creates a report file containing a list of original and new RTL files.
Syntax
pt_set rewrite_report_file file_name

saif_file
Specifies a SAIF file to use for power analysis instead of a VCD or FSDB. For details
on this flow, see Analyzing Average Power Using a SAIF File.
Syntax
pt_set saif_file file_name

save_clock_trees_netlist
Generates power database schematics for the clock trees in the design.
Default: false
save_x_nets_file
Sample Output
count.n29 1 0.000000011000
count.n46 2 0.000000034000
The first column is the signal name. The second column is the number of times the
signal transitions to an X state. The third column is the cumulative time spent by the
signal in the X state. You can use the -allowed_x_time option to set the tolerance of
X detection, that is, the allowable time span beyond which signals stuck at X get
reported. You can sort this file by any of the three columns using the UNIX “sort”
utility, for example:
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scenario_file
Syntax
pt_set save_x_nets_file file_name

scenario_file
which PowerArtist will search for other scenarios.
Syntax
pt_set scenario_file file_name

Applies to: CalculatePower, Elaborate, GenerateActivityWaveforms and
GenerateEtclFile
sdc_files
Specifies a Tcl list of SDC files that you want to parse.
Syntax
pt_set sdc_files sdc_file(s)

Applies to: ReadSDC
sdc_log
Specifies the name of the log file that will collect all error, warning and note
messages generated by this command.
Syntax
pt_set sdc_log file_name

Applies to: ReadSDC
sdc_out_file
Specifies the name of the output ptshell script. You can specify this file in subsequent
Syntax
pt_set sdc_out_file file_name

Applies to: ReadSDC
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set_load_file
set_load_file
Reads a Tcl list of file names as supplied load on internal nets or pins in the design.
Syntax
pt_set set_load_file file_name1 file_name2 ...

show_reduction_net_name
Shows net names for register reductions.
Syntax
pt_set show_reduction_net_name true | false

Default: false
skip_clock_analysis
Allows you to run PowerArtist to without a SetClockNet command. When set to true,
the clock file is ignored. The default for this options is false. The following conditions
will print warning/error messages:
Error: Neither a SetClockNet command nor a skip_clock_analysis
option is specified. One of them is required.
 If you set this option but you did not specify at least one SetClockNet command,
Warning: No SetClockNet command is specified. A skip_clock_analysis option is
specified. Therefore, clock tracing and inferencing analysis will be disabled.
Unless the design has clock trees instantiated, inaccurate results may occur.
 If you specify both a skip_clock_analysis option and a SetClockNet command, you
will get the following warning message:
Warning: A SetClockNet command and the skip_clock_analysis option have been
specified. Therefore, ignoring the skip_clock_analysis option. Clock tracing and/or
inferencing will be performed.
Syntax
pt_set skip_clock_analysis true | false

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skip_reduction_list
skip_reduction_list
Specifies a Tcl list of reduction types (PowerBots) you want to skip.
Syntax
pt_set skip_reduction_list reduction_type

Available reduction types are:
cec: Clock Enable Condition Linter
doi: Datapath Operator Isolation
gmc: Gate Memory Clock
lec: Local explicit clock enable
lnr: Low-Activity Non-Enabled Register
mem: Memory Power Linter
mux: MUX Power Linter
prism: Prism
reg: Register Power Linter
smw: Split Memory Word
Default: smw (the SMW PowerBot is not run by default) If you want to run SMW, you
need to specify this option with an empty list, such as:
pt_set skip_reduction_list { }
Furthermore, if you want to disable other PowerBots and the SMW PowerBot, you
need to list all of them explicitly, for example:
pt_set skip_reduction_list {smw odc}
spef_file
Specifies a SPEF file. This file is used to back-annotate the pin and internal net
capacitance values. For details see, Back-Annotating Capacitance Using SPEF.
Syntax
pt_set spef_file file_name

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start_time
start_time
Starts collecting data at the specified string. If string ends with the letter “s”, it is
specified as time, otherwise it is specified in simulator ticks.
Syntax
pt_set start_time string

Default: (none)
statics_threshold
Specifies that PowerArtist monitor only static vectors with power greater than the
specified percentage. For RTL designs with huge numbers of instantiated gates,
using this option will improve both the run time and memory usage. Values of 5 to 20
percent are usual, 0 to 50 percent is allowed. You should rarely have to use this
option in PowerArtist
Default: 0
Syntax
pt_set statics_threshold
statistics
Specifies that PowerArtist capture register activity statistics for use in the CoolTime
product. CoolTime requires register activity information for a vectorless
instantaneous voltage drop analysis. Given the “pt_set statistics register_activity”
variable, CalculatePower reports the “peak” register activity over your chosen
simulation duration. This means that you also have to supply an interval size that is
used to break your simulation up into N intervals. This peak activity is output in your
Example:
pt_set statistics register_activity
CalculatePower -start_time 10ns -finish_time 1ms
-interval_size 20e-09
follows:

You can then supply the Peak Register Activity (.7 in this example) to CoolTime. The
Note also records the start and end time of the peak interval.
Apache Design, Inc.

stimulus_processing_passes
Syntax
pt_set statistics register_activity

run time. The higher the integer value provided, the longer the run time and smaller
the memory footprint.
Syntax
pt_set stimulus_processing_passes integer

Range: 2 to 10
suppress_messages
Specifies a Tcl list of warning numbers to be suppressed. This will override the
default warning message list.
Syntax
pt_set suppress_messages {warn_num1 warn_num2 ...}

Applies to: CalculatePower, Elaborate and ReducePower
synlib_files
Adds the specified file or Tcl list of files to the list of .lib technology files. The asterisk
wild card is allowed, and is expanded by the shell.
Syntax
pt_set synlib_files file_name1 file_name2 ...

Applies to: Elaborate, GenerateActivityWaveforms and GenerateEtclFile
system_verilog
Treats all files in the Verilog startup file (specified with the verilog_startup_file
variable) to be System Verilog files. System Verilog inferencing requires the System
Verilog option to PowerArtist.
Syntax
pt_set system_verilog true | false

Default: false
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tag_blocks
tag_blocks
Tags registers with the surrounding block name. These tags will be used later in the
MapRetentionCell command to control retention cell default cell selection.
Syntax
pt_set tag_blocks true | false

Default: false
time_based_cpf_in_file (Beta)
Specifies an input file containing power constraints in CPF. Though the software
supports a subset of the total CPF 1.1 command set, it will read CPF files that use all
of the available commands. Commands not supported are ignored. Similarly, the
software ignores any command options that are specified but not supported. For
more information, see Using a CPF Input Flow (Beta).
Syntax
pt_set time_based_cpf_in_file file_name

time_based_cpf_output_file (Beta)
Off (PSO) design intent.
Syntax
pt_set time_based_cpf_output_file file_name

time_based_report_file
Writes a report file for time based power analysis with the specified file name.
Syntax
pt_set time_based_report_file file_name

Apache Design, Inc.

time_based_report_options
Specifies reporting options for time-based power analysis. You can specify the
following options:
M—Outputs retention flops of the library cell to which the inferred instance mapped.
V—Reports power dissipation per power supply.
Syntax
pt_set time_based_report_options string

time_based_upf_in_file (Beta)
Specifies an input file in UPF 1.0. For details how to use this option, see Using a
UPF Input Flow (Beta).
Syntax
pt_set time_based_upf_in_file file_name

time_based_write_power_db
Writes out a Power Database (.pdb) for use in the PowerArtist GUI. When this option
is specified, the time-based power analyzer will output the OpenAccess database
representation of all the power analysis results.
Syntax
pt_set time_based_write_power_db true | false

top
Syntax
pt_set top library_name.design_unit_name

Applies to: Elaborate, ReadSDC, RewriteRTL, WriteClockGatingConstraints and
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top_instance
top_instance
hierarchy. This should correspond to the module specified with Elaborate -top. For
example, if your testbench is called “bench” and it instantiates the top module as
“dut”, specify “pt_set top_instance bench.dut”. Note that this is not supported by the
Elaborate command.
Syntax
pt_set top_instance top_module_name

transition_time_file
Specifies the output transition time file. You can specify this file in subsequent
Syntax
pt_set transition_time_file file_name

Applies to: ReadSDC and CalculatePower
unlimit_interval_size
Allows you to specify an interval size smaller than 1ns for time-based power
analysis.
Syntax
pt_set unlimit_interval_size true | false

Default: false
use_library_file_names
Normally all Liberty cells are found using logical names. When set to true,
PowerArtist stores cell libraries by file name. This allows two Liberty files with same
logical library names in them to be read without any conflict. This tells Elaborate,
CalculatePower and ReducePower to find the cells by their physical file names which
will always be unique. Then any command in the system that has a -library option
will find cells using the physical file name.
Syntax
pt_set library_file_names true | false

Default: false
Applies to: Elaborate, CalculatePower, ReducePower and RewriteRTL
Apache Design, Inc.

use_non_scan_flops
use_non_scan_flops
During power analysis, PowerArtist searches the library for non scan flip-flop
definitions for use as default cells.
Syntax
pt_set use_non_scan_flops true | false

Default: false
use_rtl_sim_data
Tells PowerArtist to run average power analysis with name mapping. This flow maps
as many of your RTL net names as possible into gate-level equivalent names. This is
described in the Name Mapping Flow in the PowerArtist User Guide.
Syntax
pt_set use_rtl_sim_data true | false

Default: false
Applies to: CalculatePower -analysis_type average, GenerateActivityWaveforms and
GenerateEtclFile
use_scan_flops
Syntax
pt_set use_scan_flops true | false

Default: false
vectorless_input_file
Reads the specified file as a Vectorless Activity File (VAF) and run s a vectorless
average power analysis.
Syntax
pt_set vectorless_input_file file_name

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verilog_2001
verilog_2001
Syntax
pt_set verilog_2001 true | false

Default: false
verilog_startup_file
Reads in the specified startup file. The Elaborate command recognizes and expands
UNIX environment variables that appear in this startup file. You can specify
environment variables either with brace delimiters as in “${VARNAME}” or without, as
in “$VARNAME”. If you do not use brace delimiters, the variable name is considered
to end with the last alpha-numeric or underscore (_) character. Environment
variables within comments are not expanded. If there is no definition for a variable
required in the startup file, an error is reported and the program will terminate with
error status.
Syntax
pt_set verilog_startup_file file_name

vertical_report_instances
Produces a vertical report that provides summary information for the specified list of
instances. Note that vertical reports do not include instances that are reported as
part of clock tree power.
Syntax
pt_set vertical_report_instance {inst1 inst2 ...}

vertical_report_sort_mode
Sorts the vertical report when it is generated by the vertical_report_instances
variable.
Syntax
pt_set vertical_report_sort_mode (alphabetical | power)

Default: alphabetical
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voltage
voltage
Sets the design voltage to the specified value.
Syntax
pt_set voltage float

wait_for_license
Waits for a PowerArtist license to become available and doesn’t exit. For more
information, see Waiting for a Feature License.
Syntax
pt_set wait_for_license true | false

Default: false
Applies to: all commands; this applies a global setting
wireload_library
Specifies the library in which the power analyzer will search for wire load models.
This is useful when reading in multiple libraries that could contain wire load models.
Note: the lib_name argument is the name of the library in your .lib file—not the file
name of the library.
Syntax
pt_set wireload_library lib_name

work_library
Specifies the work library of the top design unit.
Syntax
pt_set work_library lib_name

zero_delay
Specifies that the activity file was generated by a simulator in zero-delay mode. See
the Zero Delay Simulation section in the PowerArtist User Guide for details.
Syntax
pt_set zero_delay true | false

Default: false
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dcd
Open Access Database Access Utilities

The utilities documented in this section allow you to access your OpenAccess
Database (OADB) to retrieve and manipulate many different kinds of data. See the
Writing OpenAccess Database Applications section in the PowerArtist User Guide for
details on how to write OADB applications that use these utilities. The utilities
available fall into the following categories: Design Navigation Utilities (this page),
Netlist Traversal Utilities, Design Query Utilities, Analysis Reporting Utilities,
Reduction Reporting Utilities and Power Database Mapping Utilities.
Design Navigation Utilities

These utilities mimic Unix directory traversal (cd) and listing (ls) utilities and allow
you to navigate through the design hierarchy and list design contents. For more
information, see Using the Design Navigation Utilities in the PowerArtist User Guide.
dcd
This utility sets the current design directory to the specified design directory.
Syntax
dcd design_directory
Returns
-1 if the specified design directory is invalid, otherwise, 0
Example (using the tutorial design)
dcd /top
This sets your current design directory to be /top. /top is an absolute path.
dcd core1
If you have first specified the “dcd /top” command followed by this command, this
sets your current design directory to be /top/core1—core1 is a relative path.
dpush
dpop
The dpush and dpop utilities work analogously to the pushd and popd Unix
commands. dpush pushes the current working directory to a directory stack and then
sets the current working directory to be the design directory. dpop pops the directory
stack and makes the current design directory be the directory that was on the top of
the design stack.
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dirs
Syntax
dpush design_directory
dpop design_directory
Returns
dpush returns -1 if the design directory is invalid, otherwise, 0

dpop returns 0 if operation succeeds, -1 if it does not
Example
dcd /top
dpush core1/j1
# the current working directory is /top/core1/j1
dpop
# the current working directory is /top
# the directory stack is empty
dirs
This utility lists the design directory stack.
Syntax
dirs
Returns
A Tcl set of design directory names with the stack top directory name as index 0.
Example
full_chip_ptshell % dcd /top

0
full_chip_ptshell % dpush core1

0
full_chip_ptshell % dpush r1
0
full_chip_ptshell % dirs
/top/core1 /top
full_chip_ptshell % dpwd
/top/core1/r1
This series of commands shows you how to use the dirs command.
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dpwd
dpwd
This utility lists the current working directory.
Syntax
dpwd
Returns
The directory name corresponding to the current working directory.
dls
This utility lists the contents of the design directory.
Syntax
dls [pattern] [-p | -pi | -po] [-n] [-i | -iH | -iL] [-l] [-help | -h]
Arguments
pattern
Specifies a pattern of element names to be matched. You can use standard glob-
style wild cards.
[-p | -pi | -po]
Shows different types of ports: -p (all), -pi (input ports only), or -po (output ports
only)
[-n]
Shows the nets in this design.
[-i | -iH | -iL]
Shows the specified type of instances: -i (all instances) -iH (hierarchical instances
only) or -iL (leaf instances only).
[-help | -h]
Prints a help message for this utility.
Returns
The standard output will look similar to the following:
/top/core1/j1
(i) tck (i) tms (i) trst (i) tdi
(o) tdo (n) tck (n) tms (n) trst
(n) tdi (n) tdo (n) #2327 (n) 0
(n) ireg[63:0] (n) intermediate (L) #2329 (L) #2328
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show
The first line is the current design directory name. The remaining lines are the
objects (nets, ports and instances) local to the current design directory. The ()
indicates the type of object:
 i(nput port)
 o(utput port)
 n(et)
 H(ierarchical instance)
 L(eaf instance)
show
This utility shows pseudo-Verilog for the specified instance path or module. The
pseudo-Verilog is a structural netlist representation of all the elements in the
specified design object. This opens a vi session (or the editor set by environment
variable $EDITOR) in an xterm. If you do not specify an argument to this command,
then the current working directory will be displayed.
Syntax
show [inst_path_or_module_name]
Example
Using the analysis/full_chip tutorial, if you specify the following set of commands:
dcd /top/core1/r1/s1
show
vi will start up with the pseudo-Verilog displayed for the current working directory.
The screen will look like the following as the receive channel finite state machine,
rxfsm, is displayed.
module rxfsm(clk, nreset, match, frame, ndevsel, en_rxwrd, en_rxmsg, push);

input clk;
input nreset;
input match;
input frame;
output ndevsel;
output en_rxwrd;
output en_rxmsg;
output push;
<snip>
#unencoded_mux#,1,1,1,1,3 #415(
.select[2](#361), .select[1](#363), .select[0](#381),
.a_in[0](1), .b_in[0](#365), .c_in[0](frame),
.out[0](#380)
Apache Design, Inc.

getAssociatedNet
);
#unencoded_mux#,1,1,1,1,3 #414(
.select[2](#362), .select[1](#397), .select[0](#364),
.a_in[0](1), .b_in[0](frame), .c_in[0](#368),
.out[0](#376)
);
#register#,4,4,1,1 #413(
.clock[0](clk), .reset[0](nreset), .dout[3](ndevsel),
.dout[2](en_rxwrd), .dout[1](en_rxmsg), .dout[0](push),
.din[3](#390), .din[2](#391), .din[1](#392),
.din[0](#394)
);
<snip>
endmodule
To see the same result, you could type:

show /top/core1/r1/s1
Netlist Traversal Utilities
getAssociatedNet
This utility returns the path name for the net associated with the specified pin path.
Syntax
getAssociatedNet pin_path
Arguments
pin_path
A pin path name for which the associated net’s path name will be returned.
Example
set netPath [getAssociatedNet /top/core1/clk]

puts $netPath
An example output sent to stdout may be:
/top/clk
Apache Design, Inc.

getConnectedPins
getConnectedPins
This utility returns a list of pins connected to the specified net.
Syntax
getConnectedPins net_path
Example
set connected_pins [getConnectedPins $net]

puts $fp "Net = $net"
puts $fp "Connected Pins = $connected_pins"
Pin = /top/Pupdin[24]
Connected Pins = {/top/Pupdin[24]} /top/udi44/P
Notice how the connected pins returned is a Tcl set. To handle [] in vectored pins,
such pin paths are enclosed in {}.
getSrcPin
This utility returns the path name of the driving source pin of the specified pin or net.
If multiple source pins are found, a warning is issued and the path name of the first
pin is returned. Only pins of leaf instances and primary input ports are listed.
Syntax
getSrcPin pin_or_net_path
Example
set srcPin [getSrcPin /top/core1/t1/l1/#1245/clock]

puts $srcPin
/top/core1/t1/l1/clk
While you, as an end user, may not be typing in a specific inferred leaf element, an
application you write could certainly query a name like that.
getSinkPins
This utility returns a list of path names of the sink pins driven by the specified pin (or
net). Only pins of leaf instances and primary output ports are listed.
Syntax
getSinkPins pin_or_net_path
Apache Design, Inc.

getFanout
Example
getSinkPins /top/core1/r1/s1/match
Run from the full-chip tutorial, this command returns the following:
{/top/core1/r1/s1/#417/b_in[0]} {/top/core1/r1/s1/#419/in[0]}
getFanout
This utility returns a list of path names of fanout endpoints from a specified pin.
Fanout endpoints are either flop input pins or primary output ports. These endpoints
are the terminating points of paths from the start pin.
Syntax
getFanout –pin pin_path [-levels num]

[-gothru instance_gothru_command]
[-command endpoint_satisfaction_command]
Arguments
-pin pin_path
Specifies the path name of the pin from which PowerArtist will return a list of
fanout endpoints.
-levels num
Specifies the number of logic levels to traverse. Inferred logic instances like
unencoded multiplexors may be very complex. They however only account for one
logic level even though when synthesized they may account for many more levels
of synthesized logic.
Default: 1; specifying -1 will traverse as many levels of logic as needed to reach
an endpoint.
-gothru instance_gothru_command
Specifies a command (default is isCombinational) that would be applied to the
logic instance in the path. Traversal will continue if this command is satisfied, and
stop otherwise. For example, if you want the traversal to go through all LATCH
instances, use “-gothru isLatch”.
-command endpoint_satisfaction_command
Specifies a command to be applied on the incident pin for endpoint satisfaction.
For example, if you want to trace fanout to the select pins of all MUX instances,
use “-command isSelectPin”.
Apache Design, Inc.

getFanin
Example
getFanout -pin /top/Pclk -levels 1
# INFO: 27 paths terminating in 27 endpoints

{/top/core1/r1/d1/#1072/clock[0]} {/top/core1/r1/dpmem/m0a/#221/in[0]} ...
getFanout -pin /top/Pclk -levels -1
# INFO: 56 paths terminating in 46 endpoints

{/top/core1/r1/d1/#1072/clock[0]} /top/core1/r1/dpmem/m0a/m1/CLKA ....
Notice how by traversing all the end points specified using -levels -1 you reach more.
getFanin
This utility returns a list of path names of fanin startpoints from a specified pin.
Startpoints are either flop output pins or primary input ports.
Syntax
getFanin –pin pin_path [-levels num]

[-gothru instance_gothru_command]
[-command endpoint_satisfaction_command]
Arguments
-pin pin_path
Specifies the path name of the pin from which PowerArtist will return a list of fanin
startpoints.
-levels num
Specifies the number of logic levels to traverse. Inferred logic instances like
unencoded multiplexors may be very complex. They however only account for one
logic level even though when synthesized they may account for many more levels
of synthesized logic.
Default: 1; specifying -1 will traverse as many levels of logic as needed to reach
an startpoint.
-gothru instance_gothru_command
Specifies a command (default is isCombinational) that would be applied to the
logic instance in the path. Traversal will continue if this command is satisfied, and
stop otherwise. For example, if you want the traversal to go through all LATCH
instances, use “-gothru isLatch”.
-command startpoint_satisfaction_command
Specifies a command to be applied on the incident pin for startpoint satisfaction.
For example, if you want to trace fanin but stop at the select pins of all MUX
instances, use “-command isSelectPin”.
Apache Design, Inc.

getFlops
Design Query Utilities
getFlops
This utility returns a list of flop instance paths. The returned flops may be either
inferred registers or instantiated gate instance flops.
Syntax
getFlops [-inst inst_path] [-module module_name]

[-clock pin_or_net_path] [-cell cell_name]
[-cg inferred | instantiated | both | none] [-width num]
[-op eq | gt | lt | ge | le]] [-help | -h]
Arguments
-inst inst_path
Returns flops in the specified hierarchical instance.
-module module_name
Returns flops in the specified module. The module should be a module that can
be inferred and, therefore, not be a leaf instance.
-clock pin_or_net_path
Returns flops reached in the fanout of the specified clock pin or clock net.
-cell cell_name
Returns flops of the given gate name. You can specify a glob-style regular
expression.
-cg inferred | instantiated | both | none
Allows you to control which types of flops to return. You can filter for clock gated
flops that either had inferred, instantiated or either integrated clock gating cells or
for no clock gating. If you do not specify the -cg operand, then this criteria is not
considered.
-width num [-op eq | gt | lt | ge | le]]
Specifies the width (in bits) of a returned flop. The optional argument -op specifies
a condition that must be met. For example, if you specify:
-width 3 -op gt
this command returns only flops that are greater than 3 bits wide.
If no -width option is specified, the default is to return all the flops. If a width option
is specified without a -op argument, then the default operand is eq which means
equal.
Default: All flops are returned, -op default is eq (equals the specified num width)
-help | -h
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getModule
Example
getFlops -inst /top/core1/r1/s1 -width 2

/top/core1/r1/s1/#412
This example returns all registers with a width of 2 bits on the d input that are local to
/top/core1/r1/s1. In this case, there is one.
getModule
Returns the module name of the instance.
Syntax
getModule inst_path
Example
getModule /top/core1/r1/s1
This returns the module string “rxfsm” for the instance /top/core1/r1/s1:
rxfsm
getModulePorts
This utility returns bit-blasted port names of the module in the form of a list of tuples
{bit_port_name dir}.
Syntax
getModulePorts inst_path_or_module_name
Example 1
getModulePorts /top/core1/r1/s1
{clk input} {nreset input} {match input} {frame input} {ndevsel
output} {en_rxwrd output} {en_rxmsg output} {push output}
The legal directions are “input”, “output” and “inputOutput”.
Example 2
getModulePorts /top/core1/r1/s1/#412
{clock[0] input} {reset[0] input} {dout[1] output} {dout[0] output} {din[1] input} {din[0]
input}
This example shows how you can apply this command to inferred instances. Each bit
of a bus is represented as a separate tuple.
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getModuleNets
getModuleNets
This utility returns a list of net name paths that are local to the specified instance or
module.
Syntax
getModuleNets inst_path_or_module_name
Example 1
getModuleNet /top/core1/r1/s1
/top/core1/r1/s1/#401 /top/core1/r1/s1/#400 /top/core1/r1/s1/#399
...
By specifying a hierarchical instance name, you will get the full path name to all nets
local to that particular instance.
Example 2
getModuleNets rxfsm
rxfsm/clk rxfsm/nreset rxfsm/match ... rxfsm/#400 rxfsm/#399 ...
By supplying a module name, you will get the relative path name to all ports and nets
local to the module.
getModuleInsts
This utility returns a list of instances of the specified instance path or module name.
Names are relative to the specified instance path or module name.
Syntax
getModuleInsts inst_path_or_module_name
Example 1
getModuleInsts rxfsm
#422 #421 #420 #419 #418 #417 #416 #415 #414 #413 #412 #411 #410
...
When you specify a module type name, this command returns a list of all the
instances local to that module.
Example 2
getModuleInsts /top/core1/r1/s1
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getInstsOfModuleType
#422 #421 #420 #419 #418 #417 #416 #415 #414 #413 #412 #411 #410
...
When you specify a hierarchical instance, this command returns all instances local to
the instance.
getInstsOfModuleType
This utility returns a list of instance path names with the specified module type name.
You can specify either a Verilog module type name or an inferred instance name.
Syntax
getInstsOfModuleType module_name
Example 1
getInstsOfModuleType rxfsm
/top/core1/r1/s1
This means that the one example of the Verilog module type rxfsm in the tutorial is /
top/core1/r1/s1.
Example 2
dcd /top/core/r1/s1
dls
full_chip_ptshell % dls
/top/core1/r1/s1
(i) clk (i) nreset (i) match (i) frame
(o) ndevsel (o) en_rxwrd (o) en_rxmsg (o) push
(n) clk (n) nreset (n) match (n) frame
(n) ndevsel (n) en_rxwrd (n) en_rxmsg (n) push
(n) #401 (n) #400 (n) #399 (n) #398
<snip>
(L) #409 (L) #408 (L) #407 (L) #406
(L) #405 (L) #404 (L) #403 (L) #402
full_chip_ptshell % getModule #403

#or#,2,1
full_chip_ptshell % getInstsOfModuleType #or#,2,1

/top/core1/t1/f1/#1253 /top/core1/r1/s1/#403 ...
This example, which uses the full-chip tutorial design, demonstrates how you can
use OADB utilities to look for specific inferred instance types.
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getPinDirection
getPinDirection
This utility returns a direction of the pin as input, output or inputOutput.
Syntax
getPinDirection pin_path
Example
getPinDirection /top/core1/r1/s1/clk
input
getRelatedPins
This utility returns a list path names of related pins of this combinational instance pin.
Syntax
getRelatedPins pin_path
Example 1
getRelatedPins {/top/core1/u1/#1340/out[0]}
{/top/core1/u1/#1340/in[1]} {/top/core1/u1/#1340/in[0]}
#1340 is an and gate in the tutorial. Querying for the related pins of the output pin
returns the two inputs pins. You can then run the following command:
getRelatedPins {/top/core1/u1/#1340/in[0]}
{/top/core1/u1/#1340/out[0]}
Querying for the related pins of the input pin in[0] returns the output pin.
getPropVal
This utility returns the value of the specified property for the given object path (pin,
net or instance). If you do not specify a property, all properties are returned.
Syntax
getPropVal obj_path [property]
Arguments
obj_path
Specifies an object path for which the value of the specified property (or all
properties) will be returned. The object patch can also be a module type name.
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getPropVal
property
Specifies a property name as a tuple {property_name value}. The properties
that are returned for each instance type are found in the section, PowerArtist
Netlist Properties in the PowerArtist User Guide.
Example 1
getFlops
# INFO: Collecting list of Registers: done.

# INFO: Processing 30 Registers: 30/30
/top/core1/j1/#1956 /top/core1/p1/#1941 /top/core1/p1/#1940 /top/core1/p1/#1939 /
top/core1/r1/f1/#1256 /top/core1/r1/f1/#1255 /top/core1/r1/f1/WRCNTR/#252 /top/
core1/r1/f1/RDCNTR/#252 /top/core1/r1/s1/#413 /top/core1/r1/s1/#412 /top/core1/r1/
d1/#1072 /top/core1/t1/f1/#1256 /top/core1/t1/f1/#1255 /top/core1/t1/f1/WRCNTR/#252
/top/core1/t1/f1/RDCNTR/#252 /top/core1/t1/l1/#997 /top/core1/t1/l1/#996 /top/core1/
t1/d1/#1072 /top/core1/t1/s1/#343 /top/core1/t1/s1/#342 /top/core1/s1/#1864 /top/
core1/s1/#1863 /top/core1/s1/#1862 /top/core1/s1/#1861 /top/core1/s1/#1860 /top/
core1/u1/#1349 /top/core1/u1/#1348 /top/core1/u1/#1347 /top/core1/u1/#1346 /top/
core1/u1/#1345
#+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
You can then use the getPropVal on a returned flop (see the highlighted text above).
getPropVal /top/core1/j1/#1956
{Static_Power 1.157743e-08} {Dynamic_Power 0.000000e+00} {Total_Power 1.157743e-08}

{File_Name ../design_data/rtl_source/jtst.v} {Line_Number 14} {Clock_Gated None}
{File_Type 2} {Forced_Power_Values 0} {Optimized 0}
Example 2
getPropVal DP512x32
{Func_Type 11} {File_Name mem.alfcell512} {Line_Number 1}
{Area 2.191939e+05} {File_Type 1}
This example finds the module named DP512x32 and returns the module properties.
Func_Type 11 is a memory. File_Type 1 means the definition is found in a Liberty
technology file.
See the Module Properties section in the PowerArtist User Guide for module
property definitions.
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isRoot
isRoot
This utility determines if the specified instance or module is the root design root.
Syntax
isRoot inst_path_or_module_name
Returns
1 if the given instance or module is a root design root

0 if the given instance or module is not a root design root
Example
isRoot /top
1
isLeaf
This utility determines if the specified instance or module is a leaf.
Syntax
isLeaf inst_path_or_module_name
Returns
1 if the given instance or module is a leaf

0 if the given instance or module is not a leaf
Example 1
dcd /top/core1/r1/s1
isLeaf #420
1
Instance #420 is an inferred element number in the /top/core1/r1/s1 hierarchical
instance.
Example 2
isLeaf /top/core1/r1/s1/#420
1
This case shows you can supply an absolute path name for the instance.
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isFlop
Example 3
If the specified instance is an instantiated element like a memory or is part of a gate-

level netlist, it will return 1 as well. You can query a memory from the tutorial by
specifying:
isLeaf /top/core1/r1/dpmem/m3/m1
This command returns the following:
1
isFlop
This utility determines if the specified instance or module is a flop.
Syntax
isFlop inst_path_or_module_name
Returns
1 if the given instance or module is a flop

0 if the given instance or module is not a flop
Example
isFlop /top/core1/s1/#1862
1
isLatch
This utility determines if the specified instance or module a latch.
Syntax
isLatch inst_path_or_module_name
Returns
1 if the given instance or module is a latch

0 if the given instance or module is not a latch
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isMemory
isMemory
This utility determines if the specified instance or module is a memory.
Syntax
isMemory inst_path_or_module_name
Returns
1 if the given instance or module is a memory

0 if the given instance or module is not a memory
isSequential
This utility determines if the specified instance or module is a flop, latch or memory.
Syntax
isSequential inst_path_or_module_name
Returns
1 if the given instance or module is a flop, latch or memory

0 if the given instance or module is not a flop, latch or memory
isComb
This utility determines if the specified instance or module is a combinational device. If
a module or an instance is not a sequential device, then it is identified as a
combinational device.
Syntax
isComb inst_path_or_module_name
Returns
1 if the given instance or module is not a sequential devices.

0 if the given instance or module is a sequential device.
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isConnect
isConnect
This utility determines if the specified instance or module is a connect primitive,
buffer or inverter.
Syntax
isConnect inst_path_or_module_name
Returns
1 if the given instance or module is a connect primitive, buffer or inverter

0 if the given instance or module is not a connect primitive, buffer or inverter
isPin
This utility determines if the specified path is a pin.
Syntax
isPin obj_path
Returns
1 if the given instance or module is a pin

0 if the given instance or module is not a pin
getCGs
This utility returns a list of integrated clock gating cells (ICGCs).
Syntax
getCGs [-enable enable_pin_path] [-inst inst_path]

[-module module_name] [-clock pin_or_net_path]
[-cell cell_name]
[-width num] [-op eq | gt | lt | ge | le]] [-help | -h]
Arguments
-enable enable_pin_path
Lists ICGCs driven by the fanout of the given enable pin.
-inst inst_path
Lists ICGCs inside the given hierarchical instance.
-module module_name
Lists ICGCs inside all instances of the specified non-leaf module.
-clock pin_or_net_path
Lists ICGCs clocked by the fanout of the specified pin or net.
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getCGs
-cell cell_name
Lists ICGCs of the given cell_name type. You can use a regular expression.
-width num [-op eq | gt | lt | ge | le]]
Specifies the width (in bits) that a clock gated register must meet before it is
considered as a candidate for locating its associated ICGC. The optional
argument -op specifies a condition that must be met. For example, if you specify:
-width 3 -op gt
this command returns only ICGCs whose associated clock registers are greater
than 3 bits wide.
If no -width option is specified, the default is to return all ICGCs. If a width option
is specified without a -op argument, then the default operand is eq which means
equal.
Default: All ICGCs are returned, -op default is eq (equals the specified num width)
-help | -h
Example 1
getCGs -inst /top/core1/r1

Run from the full-chip tutorial, this command finds all the ICGCs that clock gate
registers in r1.
Example 2
getModule /top/core1/r1/
Run from the full-chip tutorial, this command returns the following module name:
rxchan
You can then use this module name with the getCGs command:
getCGs -module rxchan
/top/core1/r1/f1/RDCNTR/#251 /top/core1/r1/d1/#1071
This shows that the exact same ICGC is returned if you search for it by the module
name. You would get more instances if rxchan were instantiated multiple times.
Example 3
getCGs
Run from the full-chip tutorial, this command returns all ICGCs in the design:
/top/core1/r1/f1/RDCNTR/#251 /top/core1/r1/d1/#1071 /top/core1/t1/
f1/WRCNTR/#251 /top/core1/t1/d1/#1071 /top/core1/s1/#1859 /top/
Apache Design, Inc.

getRegisterCGs
core1/s1/#1858 /top/core1/s1/#1857 /top/core1/s1/#1856 /top/

core1/s1/#1855 /top/core1/u1/#1344
Example 4
getCGs -width 16 -op gt

This only returns ICGCs that clock gate registers greater than 16 bits wide. Run from
the full-chip tutorial, this command returns the following:
/top/core1/r1/d1/#1071 /top/core1/t1/d1/#1071 /top/core1/s1/#1859
/top/core1/s1/#1858 /top/core1/s1/#1857 /top/core1/s1/#1856 /
top/core1/s1/#1855 /top/core1/u1/#1344
getRegisterCGs
This utility returns a list of clock gating instances gating the register.
Syntax
getRegisterCGs reg_inst_path
getCGRegisters
This utility returns the register instances being gated by the specified clock gating
instance. Each returned instance is a tuple; the first element is the full path to the
register, the second is the enable sense when the register is gated. The value is
either neg or pos. For instance, if the code is:
if (enable)
out = in;
This is a neg sense enable.
If (!enable)
out = in;
This is a pos sense enable.
Syntax
getCGRegisters cg_inst_path
Example
getCGRegisters /top/core1/r1/d1/#1071
{/top/core1/r1/d1/#1072 pos}
In this case, the #1071 was discovered using the query in one of the examples for
getCGs. This command then found the registers gated by #1071 which is a register
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reportPath
bank, 1072#. The returned tuple also indicates tat this enable is a pos enable
register.
Analysis Reporting Utilities

You can use the utilities in this section to report various types of information.
reportPath
This utility reports power along the specified path.
Syntax
reportPath -from src_pin_path -to dst_pin_path

[-command node_data_command] [-out report_file_name]
[-help | -h]
Arguments
-from src_pin_path -to dst_pin_path

Specifies the source and destination pins of the path for which you want to get the
power.
-command node_data_command
Specifies the command to get data from each node.
Default: getPower.
-out report_file_name
Specifies the name of an output file to which the power information will be printed.
-help | -h
reportPower
Returns the power associated with a given instance or all instances in a given
module.
Syntax
reportPower {-inst inst_path | -module mod_name}

[-collate true | false] [-mode pa | reference] [-levels level]
[-category register | latch | logic | memory | net | clock | pad | ibp]
[-sort_by category[:type] [-unit W | mW | uW | nW]
[-out output_file_name]
Arguments
-inst inst_path
Specifies the path name to a particular instance.
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reportPower
-module mod_name
Specifies the module name. You must specify either -inst or -module.
-collate true | false
When set to true, the output data will be collated.
Default: true
-mode pa | reference
Specifies the compatibility of the output power data. You can select either ‘pa’ (to
produce output that is compatible with PowerArtist) or ‘reference’ (to produce
output that is compatible with other gate-level reference power tools).
Default: pa
-levels level | all
Specifies the number (as an int) of nested levels of instances for which to
summarize the power. If you specify ‘all’ then all instances will be summarized.
Default: 0—do not summarize the power of the children of the current level
-category register | latch | logic | memory | net | clock | pad | ibp
Specifies the category(ies) for which to generate power data. The ‘ibp’ mode
reports inferred buffer power data and is applicable only with the ‘-mode reference’
setting. You can specify more than one category (-category latch logic)
Default: all categories are included
-sort_by category[:type]
Sorts the returned information by the given category and type. For category, you
can specify any of the categories listed under the -category option (register, latch,
etc.). For type, you can specify static, dynamic or load.
Example: -sort_by register:load
-unit W | mW | uW | nW
Specifies the unit for the output power values.
Default: W (watts)
-out output_file_name
Writes the report to the specified file name. If you do not specify -out, the output
will be printed to stdout.
Example 1
reportPower -inst /top

This example generates a power summary for just the /top instance as shown in the
following sample output:
Instance: /top
Power Unit: W
Category Static Dynamic Total
-------------------------------------------------
register 4.35705e-06 7.02941e-04 7.07298e-04
latch 0.00000e+00 0.00000e+00 0.00000e+00
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reportPower
logic 4.41875e-02 7.51179e-01 7.95367e-01

memory 3.80580e-03 1.58462e-02 1.96520e-02
net 1.47127e-07 2.42758e-04 2.42905e-04
clock 1.39378e-07 4.29214e-04 4.29353e-04
-------------------------------------------------
Subtotal 4.79979e-02 7.68400e-01 8.16398e-01
Example 2
reportPower -inst /top/core1 -category register

This example outputs the register power for the /top/core1 instances in the default
units of Watts. Run from the tutorial, this command returns the following:
Instance: /top/core1
Power Unit: W
-------------------------------------------------
register 4.35705e-06 7.02941e-04 0.00070729805
-------------------------------------------------
Subtotal 4.35705e-06 0.000702941 0.00070729805
0
Example 3
reportPower -inst /top/core1/r1 -levels 1 -unit mW

This example shows the impact of the -unit and -levels options. Asking for 1 level will
summarize the power for all hierarchical children of the instance /top/core1/r1.
Inferred leaf instances are not included. Run from the tutorial, this command returns
the following:
Instance: /top/core1/r1
Power Unit: mW
-------------------------------------------------
register 0.001 0.030 0.031
latch 0.000 0.000 0.0
logic 0.001 0.056 0.057
memory 1.903 7.357 9.26
net 0.000 0.110 0.11
clock 0.000 0.033 0.033
-------------------------------------------------
Subtotal 1.905 7.586 9.491
Instance: /top/core1/r1/dpmem
Power Unit: mW
-------------------------------------------------
register 0.000 0.000 0.0
<snip>
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reportPower
clock 0.000 0.006 0.006

-------------------------------------------------
Subtotal 1.904 7.506 9.41
Instance: /top/core1/r1/p1
Power Unit: mW
-------------------------------------------------
register 0.000 0.000 0.0
<snip>
clock 0.000 0.000 0.0
-------------------------------------------------
Subtotal 0.0 0.002 0.002
<snip>
Gate-level instantiations are included as can be seen in the next example:
Example 4
reportPower -inst /top/core1/r1/dpmem -levels 1 -unit mW

Run from the tutorial, this command returns the following:
Instance: /top/core1/r1/dpmem
Power Unit: mW
-------------------------------------------------
register 0.000 0.000 0.0
latch 0.000 0.000 0.0
logic 0.001 0.035 0.036
memory 1.903 7.357 9.26
net 0.000 0.108 0.108
clock 0.000 0.006 0.006
-------------------------------------------------
Subtotal 1.904 7.506 9.41
<snip>
Instance: /top/core1/r1/dpmem/m1
Power Unit: mW
-------------------------------------------------
register 0.000 0.000 0.0
latch 0.000 0.000 0.0
logic 0.000 0.000 0.0
memory 0.434 0.403 0.837
net 0.000 0.019 0.019
clock 0.000 0.000 0.0
-------------------------------------------------
Subtotal 0.434 0.422 0.856
<snip>
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reportCGEfficiency
In the tutorial design, m1 is an instance of a DP256x32 memory.
Example 5
reportPower -inst /top -levels 0

Since -levels 0 is equivalent to not supplying the -levels option at all, this example
returns the same result at Example 1.
reportCGEfficiency
This command generates a comprehensive report of all inferred and instantiated
ICGCs in the design. You must first source the power database (.pdb file) for the
design before running this command.
You can use this report to determine the effectiveness of the ICGCs and determine
which enables should be possibly strengthened or removed. You can use the report
to rank the enables by sorting the data in multiple ways. In addition, this report
provides a detailed view of the clock network with respect to the ICGCs.
This command works in conjunction with the getCGs command which returns a list of
ICGCs in the design.
Syntax
reportCGEfficiency [–wrapper_module_info { {module_name1

[enable_port_name1]} {module_name2 [enable_port_name2]} …}]
[-cg_list cg_inst_list] [-cols column_list]
[-out report_file_name] [-sort_by clock_power | enable_eff]
[-format csv] [-help | -h]
Arguments
-wrapper_module_info {{module_name1 enable_port_name1}

{module_name2 enable_port_name2} …}
Specifies a Tcl set of sets. You can specify one or more pairs where each pair is of
the form {modName enablePortName}. The modName is the name of the wrapper
module that infers or instantiates an ICGC. The enablePortName is the clock
enable port of the wrapper module. If you do not specify this option and if the
ICGC is instantiated, PowerArtist will use the leaf-level ICGC instance to report
attributes such as file name. If you do not specify an enablePortName,
PowerArtist attempts to determine the clock enable port from the wrapper module.
It will generate an appropriate warning message if it is not able to determine the
enable port.
You can use wild cards for the module_name. You may want to use a wild card if
you have a naming convention for your ICGC module names and want to specify
a portion of the module name and then use a wild card for the characters that
vary. You can also use wild cards with the enable_port_name.
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reportCGEfficiency
-cg_list cg_inst_list
This is a list of ICGCs you for which you wish to calculate their clock gating
efficiency. The list would typically be created using the getCGs or getRegisterCGs
commands.
Default: get all ICGCs
-cols column_list
Determines the columns that are displayed in the report/table. Each column
represents a property of the ICGCs. When you specify -cols, the default column
list is overwritten (rather than augmented). Therefore, if you want to add a column
to the columns already displayed, you need to specify all of the columns, not just
the new one. You can specify any of the following column options: cg_inst,
cg_type, flop_bits, direct_flop_bits, ct_icgc_cnt, enable_net, enable_sense,
enable_duty_cycle, enable_efficiency, enable_cum_eff, clock_net, clock_power,
clock_freq, rtl_info, file, and line. For details on each of the columns in the output
file, see Output Report Contents and Format.
Default: -cols cg_inst cg_type enable_duty_cycle enable_cum_eff clock_power
clock_net enable_efficiency enable_net file line clock_freq gated_clock_freq
-sort_by clock_power | enable_eff
Sorts the returned information by clock power or enable efficiency.
-out report_file_name
Specifies the name of the output file in which the report is to be written.
Default: Writes the output to the screen.
-format csv
Specifies the format to be used for writing the report. This option will be extended
to support other formats in the future and defaults may change at that time. To
ensure that your scripts continue to work, please specify “-format csv” with this
routine though it is optional.
Default: csv
-help | -h
Prints help information (syntax) for this command.
Example
set cg_inst_list [getCGs -clock /top/Pclk]

reportCGEfficiency -sort clock_power -out Pclk_CGE.rpt
-cg_list $cg_inst_list
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reportCGEfficiency
Output Report Contents and Format
This command prints a detailed report for every ICGC in the design. The following
table lists each of the unique fields in this report by default.
Field/Column Header -cols option Description
*Inst Name cg_inst The full hierarchical path name of the

ICGC instance. If the ICGC is inferred
by a feedback mux driving a register,
the name of the mux instance will be
provided.
*Gater Type cg_type Indicates whether this ICGC is already

in the HDL or will be created by
synthesis later. It will contain one of the
two values: “inferred” or “instantiated”
Flop Bits flop_bits The number of flop bits for the ICGC
Dir Flop Bits direct_flop_bits The number of direct flop bits for the
ICGC
*En Duty enable_duty_cycle The percentage of the time the ICGCs

enable is high.
*ICGCs ct_icgc_cnt The number of ICGCs in the clock tree

that implements this clock-gate. If the
clock-gate is an instantiated ICGC, this
number will be 1.
*Cum En Eff enable_cum_eff The efficiency of the clock tree at this

level including the savings of all
downstream ICGCs. This is computed
as:
1 – (Sum of clock toggles at each
downstream sequential element/(clock
toggle at this ICGC’s input clock pin *
number of downstream sequential
elements))
*Dwns Clk Power clock_power The sum of the power burned in the
clock tree from this ICGC to the power
burned by each downstream sequential
element’s clock pin. This represents the
maximum additional clock power that
would be saved if this ICGC’s enable
were completely turned off.
*Pr Clock clock_net Name of the root clock of this ICGC’s

clock pin
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reportCGEfficiency
Field/Column Header -cols option Description
*En Eff enable_efficiency (1 – output_clock_frequency/

input_clock_frequency)
1 means that the enable completely
deactivates the downstream clock
network.
0 means that the enable always leaves
the ICGC transparent.
If the input clock frequency is 0, the
ICGC is not needed because its input
clock is already disabled. If this
happens, you will see the string
“redundant” in the value of the field.
*En Net enable_net The hierarchical name of the enable

net, if available. If it is an expression,
the driving expression, if available, will
be provided. If it is a complex
expression involving a datapath, the
driving expression may not be
available; in that case, the inferred net
name is provided.
En Sense enable_sense The sense of the enable_net signal. If

the sense is "pos", data gets clocked
when the enable_net is high. If the
sense is "neg", data gets clocked when
the enable_net is low.
RTL Info rtl_info Lists the “file_name:line_number” for

the ICGC
*File file The name of the HDL file where the

ICGC is instantiated or inferred
*Line line The HDL file line number where the

ICGC is instantiated or inferred
*In Freq clock_freq Input clock frequency of this ICGC
*Out Freq gated_clock_freq Output clock frequency of this ICGC
Note: The column headers marked with an * are those that are generated by default
(without having to specify the -cols option).
The report is in CSV format. The first line (which takes up two lines in the following
sample report) contains the column headers.
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readReductions
Sample Report
"Inst Name","Gater Type","En Duty","Cum En Eff","Dwns Clk Power","Pr Clock","En Eff.","En

Net","File","Line","In Freq","Out Freq"
"core1.s1.#1819","inferred","1.00","0.00","3.09e-05","clk","0.00","core1.s1.en_wdtmr","./
design_data/rtl_source/stats.v","94","6.60e+07","6.60e+07"
"core1.u1.#1308","inferred","0.42","0.58","2.57e-05","clk","0.58","core1.u1.#1303","./
design_data/rtl_source/upi.v","46","6.60e+07","2.75e+07"
"core1.s1.#1822","inferred","0.54","0.46","1.69e-05","clk","0.46","core1.s1.en_txwrd","./
"core1.s1.#1823","inferred","0.46","0.54","1.43e-05","clk","0.54","core1.s1.en_txmsg","./
Reduction Reporting Utilities

PowerArtist provides two reduction reporting utilities that you can use to collate
multiple reduction reports: readReductions and collateReductions. These utilities
work off of data generated by PowerArtist’s ReportReductions command. You will
need to use the following flow:
1. Elaborate the design using the Elaborate command.
2. Perform a power reduction analysis using the ReducePower command.
3. Generate a .csv file of the reductions using the ReportReductions command.
4. Optionally iterate steps 2 and 3 using different stimulus files to obtain reduction
data over a variety of different operating modes and conditions.
5. Run the readReductions utility once reading all CSV files generated in the
sequence of steps 2-4.
6. Run the collateReductions command to read in the CSV files you created during
step 5 and generate a formatted report. This report allows you to determine the
best reductions to implement over all of the ReducePower scenarios you ran in
step 3.
readReductions
Reads one or more .csv report files generated by the ReducePower command. It
builds up an in memory representation of these files which may then be further
processed by the collateReductions command. You can only execute this command
once. Successive runs of readReductions restarts the analysis.
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collateReductions
Syntax
readReductions -csv list_of_csv_files [-delim delimiter]
Arguments
-csv list_of_csv_files
This is a Tcl list of CSV files created by the ReportReductions command.
-delim delimiter
Specifies a CSV field separator. By default, the field separator is + to match the
default for the ReducePower command.
Example 1
readReductions -csv CSVs/example.csv

This reads and loads into memory the csv file CSVs/example.csv, created by
ReportReductions, using a + to separate the fields
Example 2
readReductions -csv scn1.csv scn2.csv -delim ","

This reads two CSV files and uses a comma to break the file into fields.
collateReductions
This command reads in CSV files and generates a collated report based on the data
filter options you specify. There are five data filters you can apply. If none of these
options are specified, the default is to operate over all data points.
Syntax
collateReductions [-file csv_file_name] [-inst instance_path]

[-module module_name]
[-redn LNR | ODC | LEC | GMC | SMW | MUX | FCE] [-top number]
[-group_by {file | module | inst | redn}+]
[-out output_file_name]
Arguments
-file csv_file_name
Selects only the data from the specified CSV file.
-inst instance_path
Selects only the data for the specified instance.
-module module_name
Selects only the data for the specified module.
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collateReductions
-redn LNR | ODC | LEC | GMC | SMW | MUX | FCE

Selects only the data for the specified reduction.
-group_by {file | module | inst | redn}+
Specifies one or more key words that determine how the selected data will be
grouped (put into buckets). Data in each bucket is then collated to compute the
average and maximum power savings.
Default: module redn. Using this setting, the reduction data is grouped into
buckets such as: [mod1,LNR], [mod2,LNR], [mod1,ODC], [mod2,ODC], etc.
-out output_file_name
Outputs the data into the specified file.
Default: output goes to stdout
Example
readReductions -csv ../Data/CSV/sim1.csv ../Data/CSV/sim2.csv ../

Data/CSV/sim3.csv
collateReductions -group_by inst -top 20
This example produces a report similar to the following sample:
#--------------------------------------------------------------------------------------------------
-
# Group by: inst, Sort by: power/tot
# CSV File IDs: F0 = ../Data/CSV/sim1.csv, F1 = ../Data/CSV/sim2.csv, F2 = ../Data/CSV/sim3.csv
# power/avg hit power/max line csv power/tot cnt power/tot cnt power/tot cnt GroupID
#-------------------------------------------------------------------------------------------------
1.217e-04 3 1.218e-04 104 F1 1.215e-04 1 1.218e-04 1 1.218e-04 1 fsm.#44448:W=2
6.761e-05 3 9.561e-05 24 F1 5.266e-05 1 9.561e-05 1 5.455e-05 1 fsm.#44446:W=36
5.907e-05 3 6.356e-05 53 F1 5.612e-05 1 6.356e-05 1 5.752e-05 1 transmit.#5730:W=22
4.792e-05 3 5.067e-05 20 F1 4.243e-05 1 5.067e-05 1 5.064e-05 1 fsm.#44428:W=16
4.451e-05 3 4.458e-05 2 F1 4.441e-05 1 4.458e-05 1 4.455e-05 1 fsm.#44254:W=14
3.160e-05 3 9.520e-05 82 F1 6.556e-05 2 7.001e-05 2 5.403e-05 2 receive.#1231:W=32
3.078e-05 3 3.376e-05 68 F1 2.889e-05 1 3.376e-05 1 2.970e-05 1 transmit.#5750:W=11
2.930e-05 3 2.939e-05 105 F1 2.911e-05 1 2.939e-05 1 2.939e-05 1 fsm.#44449:W=7
The field descriptions are:

 power/avg: average power saved computed across all occurrences of this
reduction opportunity
 hit: # of CSV files (representing simulation scenarios) that triggered this reduction.
This can range from 0 to the total number of .csv files. The more files that
contained this opportunity, the more universally applicable the modification is.
 power/max: maximum power saved in any one CSV file for this opportunity.
 line: the reduction opportunity number in the CSV file listed under the CSV
heading. You can find it by editing the CSV file and going to line+1 where the +1
accounts for the header record in the CSV file.
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pa2oa
 csv: the CSV file containing the maximum savings opportunity. The code F# will
be used rather than the actual file name. The code is listed in the report header:
# CSV File IDs: F0 = ../Data/CSV/sim1.csv, ... F2 = ../Data/CSV/sim3.csv
Then there are two columns listed for each CSV file ordered left to right—F0 to F(N-
1). In the sample report, these column pairs are color coded into groups. The blue
group represents the F0 file, the green group represents the F1 file and the orange
group represents the F2 file. Each of these groups has two values/columns:
 power/tot: the total power saved for this reduction opportunity
 cnt: number of listings of the reduction opportunity in the associated CSV file.The
count may be greater than one due to the fact that the containing instance may be
instantiated multiple times or multiple reductions may be applicable to the same
register.
The final field comes next.
 GroupID: this is the
module_name.inferred_instance_number:register_width. This tells you
which module in the design contains the reduction opportunity, the inferred
register number impacted by this opportunity and how many bits wide it is.
Generally, the larger the number of bits, the larger the total savings.
Power Database Mapping Utilities

These utilities map names and objects between the PowerArtist namespace and the
power database namespace defined by OpenAccess. You mostly likely will not need
to use these utilities unless you are using API provided as part of the standard
OpenAccess distribution. Utilities also exist that translate power database utilities to
netlist names more closely associated with industry standard synthesis tools.
pa2oa
This utility converts a PowerArtist name to a power database name.
Syntax
pa2oa pa_name
Example
Specifying:
pa2oa /top/core1
Will return:
#2ftop#2fcore1
End user names can’t necessarily be represented directly in the power database.
Examples are /’s. These need to be turned into escaped characters. In this example,
“#2f” is the representation for / in OpenAccess.
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oa2pa
oa2pa
This utility converts a power database name to the equivalent PowerArtist name.
Syntax
oa2pa oa_name
oa2nl
This utility converts a power database name to a netlist name.
Syntax
oa2nl oa_name
nl2pa
This utility converts a netlist name to a PowerArtist name.
Syntax
nl2pa nl_name
Example
In the tutorial, if you specify:

nl2pa /top/core1/clk
It will return:
core1.clk
pa2nl
This utility converts a PowerArtist name to a netlist name.
Syntax
pa2nl pa_name
Example
In the tutorial, if you specify:

pa2nl core1.clk
It will return:
/top/core1/clk
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nl2oa
nl2oa
This utility converts a netlist name to a power database name.
Syntax
nl2oa nl_name
getObject
This utility returns the power database object for the specified the object path. The
specified object can be either a module, pin or net name or an instance path.
Syntax
getObject object_path
getOccObject
This utility returns the power database occurrence object for the specified object
path. The specified object can be either a module, pin or net name or an instance
path.
Syntax
getOccObject object_path
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ptoa::convertDBName
Legacy Flow OpenAccess Database Tcl API Commands

The Tcl API calls in this section are part of the legacy flow for accessing common
data from an OpenAccess Database (OADB). These may be used interchangeably
with utilities described in the OpenAccess programming documentation. These APIs
are written by Apache Design, Inc. and are not meant to be used by other
applications.
It is recommended that you use the newer Open Access Database Access Utilities
which are described in the Writing OpenAccess Database Applications in the
PowerArtist User Guide. These utilities, which include reportPath, reportPower,
reportCGEfficiency, collateReductions, readReductions and others, are much easier
to use because they require little knowledge of the OpenAccess database storage
mechanisms.
You need to pass OA object names to Tcl APIs. For help on OA naming style, please
see your OA programmers guide. The name mapping rules are available in the
online OA documentation package you get with the PowerArtist software by selecting
Topics > Programmers Guide > Name Mapping > Name Mapping Rules.
ptoa::convertDBName
This routine converts the names from the OpenAccess namespace to a PowerArtist
namespace and vice-versa. The Open Access naming conventions are different from
those in PowerArtist. This means that when you locate an object using one of the
oa:: routines, the name of the object will often have escaped characters in it. To
make these names understandable, you need to convert the names from the
OpenAccess namespace to a PowerArtist namespace.
You must perform a similar transformation when you want to search the OpenAccess
database for names you would typically be using in PowerArtist. For instance,
PowerArtist uses a dot ('.') to separate elements in a hierarchical path. OpenAccess
uses a forward slash ('/'). PowerArtist uses the pound sign ('#') in names for inferred
objects. These need to be escaped in OpenAccess. The convertDBName routine
transforms names in either direction. By default, it assumes that the name is an OA
name that must be converted to a PowerArtist name. You need to specify the -to_oa
option if you want to convert a PowerArtist name to an OA name.
Syntax
ptoa::convertDBName name [-to_oa]
Options
name
The name you want to convert. By default you are converting an OA name to a
PowerArtist name.
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ptoa::getCGInfo
-to_oa
Indicates that you want to convert a PowerArtist name to an OA name.
Returns
The converted string in the target namespace format.
Example 1
set netName [oa::getPathName $localOccurrence]

# Extract all properties
set allProps [ptoa::getPropVal $localOccurrence *]
if { $allProps != "" } {
puts "Net Name = [ptoa::convertDBName $netName]"
puts "$allProps"
} else {
puts "No properties found for net: [ptoa::convertDBName $netName]"
}
The oa::find routines expect names in the OpenAccess namespace. This means that
if you want to find a name like a[5].b.c[7], this would have to be converted into a
name that OpenAccess understands. The ptoa:: routines in this release all take
names in the PowerArtist namespace. Therefore, you do not have to call
convertDBName before you pass a name string to them.
Example 2
set oaName [ptoa::convertDBName #connect_inv#,1,1 -to_oa}

puts "oaName = $oaName"
This example will generate the following output:

oaName = #23connect_inv#23#2c1#2c1
ptoa::getCGInfo
This routine returns the total number of register bits that are clock gated for a module
or a hierarchical instance.
Syntax
ptoa::getCGInfo (-module module_name | -inst

hierarchical_inst_name)
[-cg_type (inferred | instantiated | both)]
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ptoa::getClockPower
Options
-module module_name
Specifies the module for which you want to retrieve the number of clock gated
registers. All instances of that module are summed up. It is not the count of the
number of registers gated in the module definition.
-inst hierarchical_inst_name
Specifies a hierarchical instance for which you want to retrieve the number of
clock gated registers.
-cg_type (inferred | instantiated | both)
Specifies whether you want to have the count for inferred ICGCs, instantiated
ICGCs or both. If you specify this option, you must supply one of inferred,
instantiated or both.
Default: inferred
Neither -module nor -inst support wild cards.
Returns
The number of register bits as an integer.
Example
The following example uses the -inst argument:
set elems {"m1" "m2" "m2.b1" "m2.b2"}

foreach elem $elems {
set count [ptoa::getCGInfo -inst $elem]
puts -nonewline $logFile [format " %-24s " $elem]
puts -nonewline $logFile [format "%12s" "inferred"]
puts -nonewline $logFile [format "%12d" $count]
puts $logFile ""
}
By default, it is returning the count of the number of inferred instances. An example

that uses this command can be found in the distribution kit in the examples/
OpenAccess/cgRegInfo.tcl file.
ptoa::getClockPower
This routine returns the clock power for a module or a hierarchical instance.
Syntax
ptoa::getClockPower (-module module_name |

-inst hierarchical_instance_name) -hierarchy true | false
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ptoa::getClockPower
Options
-module module_name | -inst hierarchical_instance_name

Specifies either a module name or a hierarchical intance for which you want to
retrieve the clock power. If you specify a module, all instantiations of that module
are added together to return one value. If you specify a hierarchical instance
name, it cannot be an inferred instance or an instantiated gate-level instance,
such as a memory. You cannot use wild cards with this routine.
-hierarchy true | false
When the value is set to true, clock power is accumulated for nested hierarchical
instances. When set to false, clock power is accumulated only for registers in the
current hierarchical instance.
Default: true
Clock Power Calculation
Clock power is calculated in the following manner:

 For an instance, only registers that are immediate children of the instance are
considered in the clock power. This means that clock power is not inherited from
nested hierarchical children.
 The clock power numbers consider power due to inferred buffer trees, traced
instances in the clock tree and traced net power in the clock tree. It does not
contain clock power dissipated within the boundaries of the register.
 Clock trees crossing hierarchical boundaries have their power apportioned out to
various hierarchical instances. For example, suppose that a clock tree is shared
between two instances. The power will be apportioned in the following manner:
— The total leaf-level load (Z) on the clock tree is the sum of the total register load
for instance 1 (X) and the total register load for instance 2 (Y). Therefore, Z =
X+Y.
— The total power (P) allocated to instance 1 is X/Z. The total power allocated to
instance 2 is Y/Z.
 If a module is instantiated 5 times, then the total clock power for that module is the
sum of the clock power for all of its instances.
Returns
The power as a floating point number in Watts.
Example
An example that uses this command can be found in the distribution kit in the
examples/OpenAccess/getClockPower.tcl file. This example also shows how to get
the clock power for all modules or all instances.
Apache Design, Inc.

ptoa::getFunctionTypeName
ptoa::getFunctionTypeName
This routine returns the string for the function type for an occurrence instance and
applies only to leaf instances.
 at the RT level, if it is an inferred element, it will return the inferred type name as a
string. The legal values are: or, nor, xor, xnor, nand, and, connect, connect_inv,
adder, mult, decoder, mux21, unencoded_mux, tri, register, latch, regfile, latchfile.
 at the gate level (or an instantiated gate level instance at the RT level
a. if it can determine the function of the cell from the corresponding .lib, it will
return the corresponding boolean function or, nor, xor, xnor, nand, xnand,
register, latch.
b. if it can’t determine the function, it will return its module type name (or VHDL
architecture name).
 at the RT level, if it is a hierarchical instance, it will return the module type name
(or VHDL architecture name).
Syntax
ptoa::getFunctionTypeName occurrenceInstance
Example
set funcType \
[ptoa::getFunctionTypeName $occurrenceInstance]
puts " FuncType: $funcType"
This example generates the following output:

FuncType: register
Returns
A character string representing the function type.
ptoa::getInsts
This routine returns an iterator that can be walked using the getNext command. It
returns a list of instances that match one of an optional Tcl set of instance types that
may be further filtered by a wild card path name.
Syntax
ptoa::getInsts {[-type type [-name full_name_wild_card]}
Apache Design, Inc.

ptoa::getModules
Options
-type memory | pad | register | latch | adder | multiplier | mux |

decoder | comparator | and | or | |nor | xor | invertor | buffer
Specifies the type of instance from the above list.
-name full_name_wild_card
Specifies the full path name of the instance. Glob-style wild card characters are
supported.
Returns
A handle to the iterator. See also ptoa::getNext and ptoa::releaseIterator.
Example
set occurenceInstance [ptoa::getInsts -name core1.u1.#140]

set funcType \
ptoa::getModules
This routine returns a Tcl list of the non-inferred module names in the design.
Therefore, it returns the module name for hierarchical instances and instantiated
gate instances. Each module name occurs once in the Tcl list even if the module is
instantiated multiple times.
Syntax
ptoa::getModules
Returns
A Tcl list of module names.
Example
You can find an example that uses this command in the distribution kit in the
examples/OpenAccess/getClockPower.tcl file.
ptoa::getNets
This routine returns an iterator that can be walked using the ptoa::getNext command.
It returns a list of nets that match a wild card path name. In a hierarchical design, the
same net gets passed through the ports of the design and has many different names
depending on where you are in the hierarchy. The getNets routine will only output the
results for one unique name for that net, which is the highest up point in the
hierarchy of your design.
Apache Design, Inc.

ptoa::getNext
Syntax
ptoa::getNets [-name full_name_wild_card]
Options
full_name_wild_card
The full path name of the net. Glob-style wild card characters are supported.
Returns
A handle to the iterator. See also ptoa::getNext.
Example
set iter [ptoa::getNets {core1.u1.#140.clock[0]}
ptoa::getNext
This routine returns an OADB handle to the next element in the iterator. If you want
to reset the iterator and point back to the first element, then specify the -reset option.
Syntax
ptoa::getNext iter_obj_handle [-reset]
Options
iter_obj_handle
The handle to the iterator object returned by ptoa::getNets or ptoa::getInsts
commands.
-reset
Resets the iterator and returns the status.
Returns
An OADB handle to the object.
Example
set iter [ptoa::getNext {core1.u1.#140.clock[0]}

set first_net_obj [ptoa::getNext $iter]
Apache Design, Inc.

ptoa::getObject
ptoa::getObject
This routine returns an OADB handle to an object that matches a given search
criteria. You specify the type of object you are looking for and the full path name to
that object.
Syntax
ptoa::getObject -type (inst | pin | net) | -name full_name
Options
-type inst | pin | net

Specifies the type of object for which you are searching in the netlist.
-name full_name
Specifies the full path name of the net, instance or pin without wild cards.
Returns
An OADB handle to the object.
Example
set inst_obj [ptoa::getObject -type inst {core1.u1.#140}

This example returns an OADB handle to the core1.u1.#140 instance.
ptoa::getProductVersion
This routine returns the current product version.
Syntax
ptoa::getProductVersion
ptoa::getPropVal
This routine returns properties attached to an OADB object.
Syntax
ptoa::getPropVal object_handle property_name
Options
object_handle
The handle to the OADB object.
property_name
The name of the property you want return. “*” will return all properties. For a list of
available property names, see PowerArtist Netlist Properties.
Apache Design, Inc.

ptoa::releaseIterator
Returns
One of two possible types of values. If you supply a property name, it will return the
value. If you supply “*”, then a Tcl “list of lists” containing all the properties will be
returned. The form of the list is { {prop1 value_1} {prop2 value_2}...}
Example
set inst_obj [ptoa::getObject -type inst {core1.u1.#140}

set properties [ptoa::getPropVal $inst_obj “*”]
This example collects all properties of hierarchical instance core1.u1.#140.
ptoa::releaseIterator
This command releases an iterator created by the getInsts, getNets or getPins
commands.
Syntax
ptoa::releaseIterator iter_handle
Options
iter_handle
The handle to the iterator returned by getInsts, getNets or getPins commands.
Returns
A status
Example
set iter [ptoa::getNext {core1.u1.#140.clock[0]}

ptoa::releaseIterator $iter
ptoa::reportClockEnableEfficiency
This routine generates a comprehensive report of all inferred and instantiated ICGCs
in the design. You can use this report to determine the effectiveness of the ICGCs
and determine which enables should be possibly strengthened or removed. You can
use the report to rank the enables by sorting the data in multiple ways. In addition,
this report provides a detailed view of the clock network with respect to the ICGCs.
Syntax
ptoa::reportClockEnableEfficiency [–wrapper_module_info {
{module_name1 [enable_port_name1]} { module_name2
[enable_port_name2]} …}] [-output_file file_name] [-format csv]
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Options
-wrapper_module_info { {module_name1 enable_port_name1}

{module_name2 enable_port_name2} …}
Specifies a Tcl set of sets. You can specify one or more pairs where each pair is of
the form {modName enablePortName}. The modName is the name of the wrapper
module that infers or instantiates an ICGC. The enablePortName is the clock
enable port of the wrapper module. If you do not specify this option and if the
ICGC is instantiated, PowerArtist will use the leaf-level ICGC instance to report
attributes such as file name. If you do not specify an enablePortName,
PowerArtist attempts to determine the clock enable port from the wrapper module.
It will generate an appropriate warning message if it is not able to determine the
enable port.
You can use wild cards for the module_name. You may want to use wild card if
you have a naming convention for your ICGC module names and want to specify
a portion of the module name and then use a wild card for the characters that
vary. You can also use wild cards with the enable_port_name.
-output_file file_name
Specifies the name of the output file in which the report is to be written.
Default: Writes the output to the screen.
-format csv
Specifies the format to be used for writing the report. This option will be extended
to support other formats in the future and defaults may change at that time. To
ensure that your scripts continue to work, please specify “-format csv” with this
routine though it is optional.
Default: csv
Output Report Contents and Format
This command prints a detailed report for every ICGC in the design. The following
table lists each of the unique fields in this report.
Field/Column Header Description
Inst Name The full hierarchical path name of the ICGC instance. If the ICGC
is inferred by a feedback mux driving a register, the name of the
mux instance will be provided.
Gater Type Indicates whether this ICGC is already in the HDL or will be
created by synthesis later. It will contain one of the two values:
“inferred” or “instantiated”
En Duty The percentage of the time the ICGC’s enable is high.
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Field/Column Header Description
Cum En Eff The efficiency of the clock tree at this level including the savings
of all downstream ICGCs. This is computed as:
1 – (Sum of clock toggles at each downstream sequential
element/(clock toggle at this ICGC’s input clock pin * number of
downstream sequential elements))
Down Clk Power The sum of the power burned in the clock tree from this ICGC to
the power burned by each downstream sequential element’s clock
pin. This represents the maximum additional clock power that
would be saved if this ICGC’s enable were completely turned off.
Pr Clock Name of the root clock of this ICGC’s clock pin
En Eff (1 – output_clock_frequency/input_clock_frequency)
1 means that the enable completely deactivates the downstream
clock network.
0 means that the enable always leaves the ICGC transparent.
If the input clock frequency is 0, the ICGC is not needed because
its input clock is already disabled. If this happens, you will see the
string “redundant” in the value of the field.
En Net Hierarchical name of the enable net, if available. If it is an

expression, the driving expression, if available, will be provided. If
it is a complex expression involving a datapath, the driving
expression may not be available; in that case, the inferred net
name is provided.
File The name of the HDL file where the ICGC is instantiated or
inferred
Line The HDL f

ile line number where the ICGC is instantiated or inferred
In Freq Input clock frequency of this ICGC
Out Freq Output clock frequency of this ICGC
The report is in CSV format. The first line (which takes up two lines in the following
sample report) contains the column headers.
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Sample Report
"InstName", "GaterType", "En Duty", "CumEnEff", "DwnsClkPower", "PrClock", "EnEff.", "EnNet",

"File", "Line", "InFreq", "OutFreq"
"ICGC_I","instantiated","1.00","0.25","1.03e-02","Clock","0.00","Enb","test.v", "52",
"1.00e+08","1.00e+08"
"#NN","inferred","0.50","0.50","1.03e-02", "Clock", "0.50","Ena","test.v","43","1.00e+08",
"4.98e+07"
Sample API Usage

For a sample API Tcl script, see $POWERTHEATER_ROOT/example/OpenAccess/
setResults.tcl.
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make_mti_mapfile
Additional Utilities
make_mti_mapfile
ModelSim creates a file that includes the logical library names and the locations of
the compiled simulation libraries. The file created during ModelSim processing is
called vsystem.ini. This utility examines .ini files and generates a map file. To operate
correctly, the ModelSim binary must be in your executable search path because the
interface executes some Mentor-supplied programs during operation.
For example, assume you are running ModelSim. Your current working directory
contains the top-level vsystem.ini file, you are using the PowerArtist standard VHDL
87 compatible libraries, and you want all files to be compiled locally. In this case, run
the following:
make_mti_mapfile
If you are running ModelSim but you are in a different directory than the one that
contains the vsystem.ini file and you want to use VHDL 93, run the following
command:
make_mti_mapfile -input ../../mylib/vsystem.ini -std 93
Arguments
-dir path
The physical file name for the logical library lib1 is ww_lib1. This file is created in
your current working directory. Use the -dir option to specify an alternative
directory location.
-f
Indicates that you want to use your simulator-supplied IEEE, STD, SYNOPSYS, and
VITAL libraries. It is recommended that you do not use this option, but use the
PowerArtist libraries by default.
-h
Provides a brief help message for the command and options.
-input path
Indicates the location of the vsystem.ini file. This is very important. This can be
any UNIX path name. Thus, if you are unable to run this program in the directory
containing your top-level vsystem.ini file, you can execute make_mti_mapfile in
another directory.
Default: ./vsystem.ini.
-o
Supplies the name of the resulting map file.
Default: mapfile.mti.
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ptFsdb2VcdPlus
-prog name
The make_mti_mapfile program needs to access the vmap command that MTI
(Mentor) supplies.
-quiet true | false
Default: false
-std 87 | 93
Indicates the language standard you want to follow. The legal values are 87 and
93. If you do not use -f and you want to use the PowerArtist-supplied VHDL 93
compatible libraries, set this value to 93.
Default: 87
Example 1
You are running ModelSim. Your current working directory contains the top-level
vsystem.ini file. You are using the PowerArtist standard VHDL 87 compatible
libraries. You want all files to be compiled locally. Enter:
make_mti_mapfile
Example 2
You are running ModelSim. You are in a different directory than the one that contains
the vsystem.ini file. You want to use VHDL 93.
make_mti_mapfile -input ../../mylib/vsystem.ini -std 93
ptFsdb2VcdPlus
This utility converts an FSDB file to a VCDe file. For details of the VCDe file, see
VCDe File Format. Also see the Generating a VCDe File from an FSDB File section
in the PoweArtist-XP User Guide.
Syntax
ptFsdb2VcdPlus -in fsdb_file_name -out vcde_file_name

-topinst top_inst_name -start start_time_for_analysis
-finish finish_time_for_analysis
Arguments
-in fsdb_file_name
Specifies the name of the FSDB file you are converting to VCDe.
-out vcde_file_name
Specifies the name of the output VDCe file.
-topinst top_inst_name
Specifies the name the top instance in the design.
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ptLibraryCheck
-start start_time_for_analysis
Specifies the start time for the analysis. Note that this is equivalent to the -
start_time option to CalculatePower.
-finish finish_time_for_analysis
Specifies the finish time for the analysis. Note that this is equivalent to the -
finish_time option to CalculatePower.
ptLibraryCheck
If you are concerned about the quality of your power libraries that you intend to use
for power analysis, you should check them using the library checker. The PowerArtist
library checker is invoked using the ptshell ptLibraryCheck utility. Two classes of
checks are available: library completeness and library data quality.
Library completeness checks include checking for:
 Missing power models for input pin transitions
 Missing pins in state dependencies
Library quality checks include checking for:
 Unreasonably large parameter values that exceed user-defined thresholds.
Checks are made for energy, current, capacitance, power, and slew values.
 Large gaps between tables indexes for slew, capacitance, and energy
 Large energy variations between different power arcs of cell models
 Negative total energy values for a valid sequence of cell pin transitions
Use the command options to control the checks that are performed. By default,
ptLibraryCheck will perform all checks.
Syntax
ptLibraryCheck -synlib lib1.lib[:lib2.lib ...]

[-no_large_cap] [-no_large_current] [-no_large_energy]
[-no_large_power] [-no_large_slew] [-no_large_values]
[-no_missing_pins] [-no_pin_model] [-no_large_gaps]
[-no_large_var] [-max_cap] [-max_current] [-max_energy]
[-max_power] [-max_slew] [-state_energy_factor]
[-table_gap_factor]
Arguments
-synlib lib1.lib[:lib2.lib ...]

Specifies a list of Synopsys format libraries to check. Use a colon (':') to separate
the library names. This argument is required.
-no_large_cap
Disables checking for unreasonably large capacitance values.
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ptLibraryCheck
-no_large_current
Disables checking for unreasonably large current values.
-no_large_energy
Disables checking for unreasonably large energy values.
-no_large_power
Disables checking for unreasonably large power values.
-no_large_slew
Disables checking for unreasonably large slew values.
-no_large_values
Disables all checking for unreasonably large parameter values.
-no_missing_pins
Disables checking for missing pins in state dependency.
-no_pin_model
Disables checking for missing power models for input pin transitions.
-no_large_gaps
Disables checking for large gaps between table values.
-no_large_var
Disables checking for large state-to-state energy value variations.
-max_cap float
Specifies a value above which capacitance is reported as unreasonable.
Default: 100pF
-max_current float
Specifies a value above which current is reported as unreasonable.
Default: 100mA
-max_energy float
Specifies a value above which energy is reported as unreasonable.
Default: 100pJ
-max_power float
Specifies a value above which power is reported as unreasonable.
Default: 100uW
-max_slew float
Specifies a value above which slew is reported as unreasonable.
Default: 10nS
-state_energy_factor float
Specifies a factor above which variations between state energies are reported
Default: 100
-table_gap_factor float
Specifies a factor above which gaps between table values are reported.
Default: 100
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wwgaf
wwgaf
The wwgaf utility reads simulation activity files. Running the CalculatePower
command automatically runs wwgaf and this is the method you will most often use;
however, there may be times when you want to run wwgaf as a separate utility.
Syntax
wwgaf -a file_name -iaf file_name -start string -finish string

-interval_size float -scn file_name -topinst top_inst_name
[-allowed_x_time string] [-allowed_z_time string]
[-compress_gaf true | false] [-forced_x 0 | 1]
[-ftn_report file_name] [-heartbeat string]
[-save_x_nets file_name] [-split integer]
[-statistics register_activity] [-vcde true | false]
Arguments
-a file_name
by processing the -iaf argument. When you run the average power calculation
engine, it reads in this file. This argument is required.
Default: (none)
-iaf file_name
Specifies an input stimulus file generated due to a functional simulator run. The
file may be in FSDB, VCD or IAF (generated by Apache PLI routines) format. You
must specify either -activity_file or -vectorless_input_file for an average power
analysis.
#0
0$
#10
x$
#20
0$
#30
x$
#40
0$
#50
x$
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wwgaf
#60
0$
#70
x$

simulator ticks.
Default: 10ns
Specifies an amount of time a net can be in an Z state. If string ends with the
letter “s”, it is specified as time, otherwise it is specified in simulator ticks. The nets
that exceed the allowed time in the Z state are reported in a text file (see -
ftn_report).
Default: 100ns
-compress_gaf true | false
Writes out a compressed .gaf file compressed using wwgzip (which is the gzip
shipped with PowerArtist).
Default: false
-finish string
activity file.
-forced_x 0 | 1
-ftn_report file_name
(FTN).
Default: (none)
-heartbeat string
Prints progress information during GAF file creation. he specified string (in
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wwgaf
For example, if the time scale for your simulation results is 10 ns. Specifying
“pt_set heartbeat 1” will print a progress message every 10 ns of simulation time.
If you specify “pt_set heartbeat 20ns”, you will get a heartbeat message
approximately every 20 ns of simulation time.
must have simulation signal change results in your IAF file that occur
Default: (none)
-interval_size float
Specifies a number of intervals into which the simulation will be broken during a
time-based power analysis. For more information on the usage of this option and
an example, see Controlling Your Time-Based Power Analysis. Note that you
need to either specify -interval or -reference_clock and -num_clock_cycles.
Default: false
-save_x_nets file_name
Sample Output
count.n29 1 0.000000011000
count.n46 2 0.000000034000
Note
-allowed_x_time to a value that is most appropriate for the simulation. For
example, a reasonable setting might be the period for several clock cycles.
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wwgaf
-scn file_name
which PowerArtist will search for other scenarios. This argument is required.
Default: (none)
-split integer
run time.
Range: 2 to 10
Specifies that PowerArtist capture register activity statistics for use in the
CoolTime product. CoolTime requires register activity information for a vectorless
instantaneous voltage drop analysis. Given the “-statistics register_activity” option,
CalculatePower reports the “peak” register activity over your chosen simulation
duration. This means that you also have to supply an interval size that is used to
break your simulation up into N intervals. This peak activity is output in your
Example:
wwgaf -statistics register_activity -start 10ns -finish 1ms
-interval_size 20e-09
follows:

You can then supply the Peak Register Activity (.7 in this example) to CoolTime.
The Note also records the start and end time of the peak interval. Currently, there
is no support for the -statistics and -interval_size options from the PowerCanvas.
-topinst top_module_name
hierarchy. This should correspond to the module specified with Elaborate -top
Default: (none)
Alias: -topinst
-vcde true | false
Reads the IAF file as an Enhanced VCD format file. See Acquiring
Simulation Data in the PowerArtist User Guide for more information about IAF
and Enhanced VCD.
Default: false
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wwvmkr
Automatic Spawning of wwgaf

If disk space is limited, you can use PowerArtist’s auto-spawning feature to avoid
storing large IAF files on disk. This feature automatically spawns the wwgaf utility
during simulation. This utility is shared with the CalculatePower command. Keep in
mind that as result of auto-spawning, there will be no disk image of the IAF file,
therefore, you will not be able to do a “what-if” analysis.
This feature is available for the VPI interface for NC-Verilog, and the FLI interface for
ModelSim. It is not enabled by default, because it requires a change in the
PowerArtist flow; the scenario file must be created before you run simulation. To
enable this feature, use the following procedure:
1. Create a command file that includes the Elaborate command to generate a
scenario file.
2. Run the wwgaf utility on the command line with the following options: -scn, -iaf
and -a. For example:
wwgaf -scn mydesign.scn -iaf - -a activities.gaf
The single dash (-) is interpreted to mean “pipe the IAF to wwgaf”. Your command
file must exist in the directory where you run the simulation; otherwise, it will not
be found by the spawned program. You can add any other options to wwgaf such
as -start and -finish.
3. Run your simulation.
Try a short simulation first, to make sure things are working. If things are working,
you will see the output from wwgaf intermingled with the output from the simulator,
and you will have an activities.gaf file when the simulator exits. If things are not
working, then you can examine the simulation output and the wwgaf log file, if any,
to see what went wrong.
wwvmkr
The PowerArtist wwvmkr program takes a map file—created either by hand, an
automated process or by make_mti_mapfile—and builds makefiles that you use to
compile your design. It also creates a script called wwcompile that you use to run
make on the generated makefiles. You do not execute this script directly, instead you
will execute ptCompileScript, which calls this script. This process supports the
Elaborate flow.
The wwvmkr program builds a series of make files that dictate the order in which
your VHDL files must be compiled.
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wwvmkr
Arguments
-b
Disables default binding rules and enforces VHDL-87 LRM binding. This option
is very important. The wwvmkr program follows conventions established by
the VHDL simulators from Model Technology (V-System) and Cadence (NC
VHDL) with respect to bindings. In these simulators, if you have a library lib1
statement, it is equivalent to having an additional use lib1.all statement added
immediately after it by default. This is the default binding behavior. To prevent this
behavior, add the -b switch on the command line.
-c "xxx"
Specifies ptCompileScript compiler options. To make the system follow VHDL 87
guidelines, use
-c "-k 87e"
Note that the ptCompileScript options must be in quotes because there are
spaces within the option.
Default: "-k 93e"
-d path
Defines the directory to contain your Makefiles. The default is your current working
directory.
-e file_name
Specifies an exclude file name.
Default: wwvmkr.xld.
-h
Provides a brief help message for the command and options.
-m map_file
Supplies a map file created manually or by one of the make_*_mapfile interfaces.
-s vhdl_file_extentions
Supplies a colon-separated list of VHDL source file extensions to be used when
matching file names.
Default: vhd:vhdl:87
The 87 extension is used to distinguish between the different versions of the STD
and IEEE packages required for VHDL 87 and VHDL 93. If you are compiling for
VHDL 93 you will need to specify this option with 93 in the list of extensions.
-v
Displays verbose messages. This option could be useful in determining the cause
of circular dependencies in your VHDL source.
-w lib_name
Specifies the top-level library representing work. This must be supplied and acts
as a “seed.” From the files being compiled into this specified library, wwvmkr
determines all subsequent dependencies.
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ptCompileScript
Example 1
wwvmkr -m mapfile.mti -w work

This example builds the Makefiles in your local working directory, following VHDL 93
rules. The top-level logical library is work (this is case insensitive). The map file was
created by the make_mti_mapfile program using the default output.
Example 2
wwvmkr -m mapfile -d makefiles -w work -s vhd:93 -c "-k 93e"

This example builds the Makefile in the sub-directory makefiles, following the VHDL
93 rules. The top-level logical library name is work and the map file name is mapfile.
Note the use of the -s option to ensure the correct version of the std_logic_1164
package is used.
ptCompileScript
This utility executes “make” on all of your Makefiles, determines all of the libraries
and files used in your design, and writes them out to a file in the order in which they
must be analyzed. The output of ptCompileScript is by default ptSourceFiles.tcl. This
is a Tcl file that contains the following sections:
 Definitions of all of the standard libraries and the source files that define them.
 AddLibrary commands that map logical library names to physical libraries. A
typical AddLibrary command would be:
AddLibrary WORK /system/u/demouser/work
 CompileFile commands, providing file names, libraries, and VHDL standards (87/
93) to apply when compiling. A typical CompileFile command would be:
CompileFile -file test.vhdl -library /system/u/demouser/work -
87 yes
These commands are written so that they support the legacy flow of pre-compiled
libraries. CompileFile can simply skip the physical-to-logical mapping and accept a
logical library name:
CompileFile -file test.vhdl -library WORK -87 yes
Note that the library name in this case must match a logical library name
previously defined in an AddLibrary command. For complete syntax for the
ptSourceFiles.tcl file, see ptSourceFiles.tcl File Format.
The output of ptCompileScript is then used as the value of the -compile_script
argument to the Elaborate command to determine which files to analyze, elaborate,
and infer.
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pt_copy_pdb
Syntax
ptCompileScript [-c] [-o output_file] [-v]
Arguments
-c
Directs ptCompileScript to omit the default VHDL packages that otherwise are
compiled into the STD, IEEE, and SYNOPSYS libraries. This allows you to
replace the location or contents of these packages with your own.
-o output_file
Specifies an output file name.
Default: ptSourceFiles.tcl
-v
This option prints verbose messages.
pt_copy_pdb
For your use model, there may be a situation where you are working on a very large
design and want to allow it to be modified by several different designers. You want
each designer to be able to edit the same power database (.pdf) to make design
decisions. Because they need exclusive access to the power database to make the
edits, a designer will have to first copy the .pdb to a private directory, make the
desired changes in the private copy. They will then need to manually merge the
changes into a master database to perform an automatic rewrite of all changes at
one time.
You can use the pt_copy_pdb utility to copy the master power database file to a
private area. During the copy process, this utility erases any existing lock files on the
.pdb file.
Syntax
pt_copy_pdb -to dir_name [-from pdb_file] [-create true | false]

[-overwrite true | false] -debug -help
Arguments
-to dir_name
Specifies a writable UNIX directory to which the copied of the pdb will be written.
This argument is required.
-from pdb_file
Specifies the name of an existing, readable pdb file. If -from is not specified and
there is a single pdb file in the current working directory, that pdb file will be used
to locate the OpenAccess database. If there are multiple pdb files in the current
working directory, you must use the -from option.
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pt_copy_pdb
-create true | false

When set to yes, the target directory specified using the -to option will be created
automatically.
Default: false
-overwrite true | false
When set to yes, a pdb file in the target directory that matches the -from name will
be deleted and then overwritten automatically.
Default: false
-debug
Turns on debug tracing.
-help
Prints a detailed help message.
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pt_copy_pdb
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259
Chapter 4
File Formats 4
Introduction
This chapter describes some of the file formats for side files that you may want to
use with your PowerArtist run.
The following file formats are described in this chapter:
 Capacitance File Format
 Transition Time File Format
 Sequence Library Defaults File Format
 SPEF File Format
 Etcl File Format
 Mode File Format
 Global Activity File Format
 Auxiliary GAF File
 Verilog Startup File Format
 Vectorless Activity File Format
 ptSourceFiles.tcl File Format
Net Name Matching for External Files

Several PowerArtist commands allow you to supply a net name as an input. If other
EDA vendor tools generate these files, the algorithm those tools use for a net name
might not match the net name that PowerArtist expects. There are several possible
reasons for the mismatch:
 If a net traverses various levels of the design hierarchy, the node it represents
could be represented by more than one signal in the design.
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CHAPTER 4 — File Formats PowerArtist™ Reference Manual 260
Capacitance File Format
 PowerArtist prepends the name of the top module type to the beginning of all of its
nets. Some tools do not do this.
 Some tools consider pound signs, dots, and other special characters as illegal.
They often precede these characters in the net name with a backslash.
 Some tools specify nets by supplying a hierarchical instance name followed by a
port name.
To locate a net name in an external file, PowerArtist uses several searching rules,
listed here by order of precedence.
1. Try to find an unmodified net name as the “highest” hierarchical net in the design.
2. If the net name does not begin with the top module type name, prepend the top
module type name and try again.
3. If there are back slashes in the net name, remove them and try again.
4. Try to find the net as an instance name followed by a port name.
Capacitance File Format

PowerArtist can back-annotate capacitances from a file instead of using its own
estimates. These capacitance values are stored in a capacitance file, which uses the
file extension .cap. The format for each line in the capacitance file is:
net_name capacitance [termination_resistance [termination_voltage]]
where net_name is a fully qualified HDL path name and capacitance values are listed
in farads. This capacitance is the net or wiring capacitance, excluding the
capacitance of pins being driven by the net. The estimators add the pin capacitances
to the values that you specify.
The two optional termination fields can be used to specify external termination
parameters for drivers with open source or drain. The resistance field specifies (in
Ohms) the value of the resistor used for pull-up or pull-down. For a pull-down
resistor, the voltage field can be either set to 0 or omitted. For a pull-up resistor, the
voltage field must be specified (in V).
In the following example, the capacitances are specified in a file named
busconall.cap. This file specifies a load of 1.5 pF for the internal signal select[3] and
30 pF is specified for the internal clock clk. For a pin pad, the load cap of 3 pF is
specified, as well as the 1 KOhm termination tied to an external supply of 3.3 V.
buscon.corelogic.select[3] 1.5e-12
buscon.corelogic.clk 30e-12
buscon.corelogic.pad 3e-12 1000 3.3
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Transition Time File Format
See Net Name Matching for External Files for a description of the rules used to
match net names in a scenario file to net names in the capacitance file.
Transition Time File Format

PowerArtist can backannotate transition times (slews) for nets and pins from a file.
The values are supplied via a transition time file, which typically uses the file
extension .tt. The format for each line in the transition time file is:
net_name transition_time [r|f]
where net_name is a fully qualified HDL path name and transition time values are
listed in seconds. Transition times can be specified for nets and pins separately. Rise
or fall transition times are annotated by using r or f modifiers. If a modifier is not
used, an average transition time is assumed.
In the following example, the transition times are specified in file named busconall.tt.
This file specifies a slew of 0.15 ns for the internal signal select[3]. A value of 0.05 ns
is specified for the internal clock clk.
buscon.corelogic.select[3] 1.5e-10
buscon.corelogic.clk 50e-12
match net names in a scenario file to net names in the transition time file.
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Sequence Library Defaults File Format
Sequence Library Defaults File Format

The Sequence Library Defaults (SLD) file is an ASCII file you can use to specify
default clock buffers and their parameters, a default transition time value
(DefaultTransitionTime), default wire load mode, and more. You should rarely have a
need to use SLD files. This file (which has a .sld extension) accepts two commands:
SetConfigurationParameter and RefineConfigurationParameter.
For more information on the SLD file, see Creating SLD Files in the PowerArtist
Library Developers Guide.
Escaping Library Names

You must escape library names that have non-alphanumeric characters in the .sld
file. For example, an .sld file like
SetConfigurationParameter DefaultFlop DefFlop \generic.cells

SetConfigurationParameter DefaultNand DefNand \generic.cells
...
will yield errors when running a tool such as wwalflint. For it to work, the .sld file
needs to look like the following:
SetConfigurationParameter DefaultFlop DefFlop \\generic.cells

SetConfigurationParameter DefaultNand DefNand \\generic.cells
...
Specifying Default Cells

Optionally, you can use the SLD file to specify default cells; however, this method is
not recommended. By default, PowerArtist automatically searches the libraries you
provide for the most appropriate versions of the cells whenever it needs to map an
inferred instance to a power model. This default method usually provides better
power results. If you choose to specify default cells in an SLD file, PowerArtist will
use the power properties of the specified default cells in the PowerArtist RTL power
models.
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SPEF File Format
SPEF File Format

The -spef_file option to CalculatePower is used to back-annotate the pin and internal
net capacitance values. In power calculation methodology, capacitive load is an
important parameter for all the pins/nets of a design. The command is needed to
support the capacitance specification format for back-annotating net capacitances
extracted from the SPEF file into PowerArtist.
This format is mutually exclusive with capacitance back-annotated files, which
means that the -spef_file option is mutually exclusive with the -capacitance_file
option. PowerArtist will return an error if both -spef_file and -capacitance_file options
are given at the same time. If you specify both the -spef_file and -load_file (load cap)
options at the same time, PowerArtist will take internal wire cap values from the
SPEF. For output pins, it will take the sum of the wire cap values from the SPEF file
and load capacitance values from .cap
(-capacitance_file) file. The SPEF file also accepts the net name mapping format.
In the .spef file lumped capacitance for all of the nets are available from D_NET
statements. The structure of D_NET is represented as
*D_NET net_name total_net_capacitance
Syntax of Net Name Mapping
*NAME_MAP
*2 net
*D_NET *2 3.48108
match net names specified in your SPEF files with their equivalent names in your
scenario file.
Apache Design, Inc.

Etcl File Format
Etcl File Format

This file is generated by the GenerateEtclFile command. The Etcl file (.etcl) contains
net activity information which is used for voltage drop analysis in CoolTime (or
CoolPower). This file contains one curr_set_net_events command for each net in the
design and one curr_etcl_info command.
curr_etcl_info
This command specifies the size of the Etcl window. The Etcl window size (in
nanoseconds) is the difference between the Etcl start and end times.
Syntax
curr_etcl_info [-clock clock_name] -window size
Arguments
-clock clock_name
Specifies the name of the reference clock when using a clock-based Etcl
generation (rather than time-based).
-window size
Specifies the window size for the Etcl file, in nanoseconds.
Example
curr_etcl_info -window 40
This example sets the Etcl window size to 40 nanoseconds.
curr_set_net_events
This command applies a series of time-stamped events to a net. The events listed
describe every change in the net’s value over the time period t1->t2. The time period
is specified internally by the studio_state_setup_time_based command which is
generated by pttbengine. If you are using a command-line flow to generate the Etcl
file, you would need to manually create this command (see the CoolTime User Guide
for more information on this flow).
Syntax
curr_set_net_events {net_name} start_state event_list
Arguments
net_name
The net/primary input to which the events apply. The net names will be enclosed
in curly braces.
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Etcl File Format
start_state
The initial state of the net. Possible values: 0, 1, X, Z.
event_list
The syntax of the event list is: { { time state } ...}. For example, { {3.2 1} {4.4 0} }.
For the signals that toggle over the time period t1 to t2, the time of the events will
be with respect to the start time (t1) specified in the
studio_state_setup_time_based command and must be in the nanoseconds. This
is true even if the VCD file does not have a timestamp at the specified start time.
The finish time (t2) is inclusive, meaning that if there is a timestamp for a net at
time t2 in the VCD file, then it will be present in the generated event-list for that
signal.
For all signals that do not toggle over the time period t1->t2, the
curr_set_net_events statement will have the following format:
curr_set_net_event {net_name} start_state {}
The set of curly braces, which represent an empty Tcl list, denotes no toggles.
Example
curr_set_net_events {din} 0 { {1.1 1} {2.3 0} }

This example starts net din at 0 and generates a rising edge at 1.1 and a falling edge
at 2.3.
For information on how to generate an Etcl file, see Generating Etcl Files for
CoolTime in the PowerArtist User Guide.
Sample Etcl File
curr_set_net_events {z} 0 { {5 1} {15 0} }

curr_set_net_events {d} 1 {}
curr_set_net_events {y} 0 {}
curr_set_net_events {c} 0 { {0 1} {10 0} {20 1} }
curr_set_net_events {b} 1 {}
curr_set_net_events {a} 0 {}
curr_etcl_info -window 20
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Mode File Format
Mode File Format

A mode file contains design-specific information that the tools use to execute several
power analyses corresponding to different operational modes of the design. The
mode file combines these results into one or more reports.
Syntax of the Mode File
$mode "boolean_expression"
$report file_name
$result file_name
Arguments
$mode boolean_expression
This required keyword assigns a name to the operational mode you are defining.
The boolean_expression can be a single signal name or a combination of signals
in the design. The signal’s hierarchical name is, in this case, with respect to the
top most scope (or testbench scope) in the VCD—not the design’s “top” name.
You can use any of the standard boolean operators.
$report file_name
Writes the results of the analysis to the specified report file name. This file is in
ASCII format. This is an optional keyword.
$result file_name
Writes a result file, with the specified file name, for the preceding $mode
definition. This is an optional keyword. This file is for back-ward compatibility and
is not meant for you to review.
Sample 1: Mode File using Simple Signal Names
$mode txrx_tst.top1.rx_rq
$report receive.rpt
$result receive.res
$mode txrx_tst.top1.tx_rq
$report transmit.rpt
$result transmit.res
This mode file will result in modes named txrx_tst.top1.rx.rq and txrx_tst.top1.tx_rq. It
writes individual report files named receive.rpt and transmit.rpt (for the receive and
transmit signals). In addition, it generates result files similarly named receive.res and
transmit.res.
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Mode File Format
Sample 2: Mode File using Boolean Operators
$mode "!(test.tmp || test.en)"

$report tmp_en_high.rpt
This sample file will result in a mode named "!(test.tmp||test.en)". The results of the
analysis will be written to tmp_en_high.rpt. The system will be in that mode
whenever the expression !(test.tmp || test.en) evaluates to true. The GAF file will be
broken into sections corresponding to each mode. The section will be delimited by
the following record:
$mode percent mode_name
For example, you will see a line that looks like the following in the GAF file:
$mode 0.0498 "!(test.tmp&&test.en)"
This means that during the entire simulation duration, the system spent 4.98% of the
time in this mode.
For more information on using mode files during power analysis, see
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Global Activity File Format
Global Activity File Format

The global activity file (GAF) describes the simulation activity for each net in the
design, as well as observed counts for dynamic power vectors and duty cycle static
power vectors. The GAF file is created by the “CalculatePower -analysis_type
average” analysis. The following example illustrates its format:
Version 2010.1
SimTime 3e-06
StartTime 0us
FinishTime 3us
$options
f_block.ainput 0.2 1 0
f_block.ltout 0.6 3 3
f_block.diin 0.6 4 3
f_block.fpads_0.(!A&&DI&&LT) 0.5 2
f_block.fpads_0.(01DI~>10LT&&A) 0 6
The version record indicates that this file was created by the 2010.1 release of
PowerArtist. The elapsed simulation time is three micro-seconds as defined by the
SimTime entry. StartTime and FinishTime lines contain the data about the start and
the finish time of wwgaf processing, and correspond to the -start and -finish options
of wwgaf. The $options record indicates the beginning of an options section. In this
example the section is empty. The remaining records are of two forms:
net_name duty_cycle rising_transitions falling_transitions
For net transition data, the net name field is the full hierarchical name of a “real net”
in the design, as in the case of f_block.ainput. The duty cycle field is the percentage
of time that the signal was high during simulation. The two toggle fields list the
number of times that the signal transitioned up and down during the simulation.
vector_name duty_cycle vector_count
For vector data, the name of the vector is formed by concatenating the name of the
instance and the vector expression, stripped of spaces. For static vectors, such as
(!A&&DI&&LT), only the duty cycle field is taken into account. The duty cycle of a
vector corresponds to the fraction of the simulation time when the vector expression
was true. For dynamic vectors such as (01DI~>10LT&&A), only the count field is
used (duty cycle is always 0). The count field contains the number of times the vector
condition was matched during the simulation.
match net names in a scenario file to net names in the global activity file.
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Auxiliary GAF File
Auxiliary GAF File

The auxiliary GAF file (.sgaf) is created by the ReducePower command. This file
contains activity data collected during linter reduction analysis. For the purpose of
performing wasted power calculations, toggles are separated into the following
classes:
 used toggles: toggles for which there was a meaningful impact
 wasted toggles: toggles that had no impact and therefore represent wasted power
A GAF (.gaf) stores both the used and wasted toggles as part of a total toggle count.
In contrast, the linters store only the used toggles in the .sgaf file.
The .sgaf file has a similar format to the GAF file, which is described in the previous
section. The one difference is that the auxiliary GAF file does not contain the GAF
header, which contains information about the version of the software used to
generate the GAF file, the simulation time, the start and end time of the analysis and
the options used. Also, unlike the GAF, the auxiliary GAF can include inferred nets.
The auxiliary GAF contains a separate section for each power linter:
 $mux (denotes the start of the MUX linter section)
 $cec (denotes the start of the CEC linter section)
 $reg (denotes the start of the REG linter section)
 $mem (denotes the start of the MEM linter section)
The data lines in each of the section describe the used toggles on the participating
nets and use the following syntax.
Syntax
net_name duty_cycle rise_toggles fall_toggles
Example
$cec
top1.#0 0 45 45
In this example, net top1.#0 had 45 rise and 45 fall “used” toggles. Note that the duty
cycle will be always 0. (It is only included in this file so that the normal GAF reader in
the engine can read this file.)
Sample File
$mux
mp.mp_dbg_rdata[31] 0 0 0
<lines removed for brevity>
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Auxiliary GAF File
mp.pbd_rdata[31] 0 832 739

mp.pbd_rdata[30] 0 916 613
mp.pbd_rdata[29] 0 355 256
$reg
mp.dbg_mp_addr_wdata[31] 0 0 0
mp.pbd_rdecode_val 0 2338 2338
mp.pbd_wdecode_val 0 1415 1415
mp.rst_core 0 0 0
mp.ac1_an1_addr[6] 0 4 3
mp.ac1_an1_addr[5] 0 4 3
mp.ac1_an1_addr[4] 0 2236 2236
mp.ac1_an1_addr[3] 0 4469 4469
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Verilog Startup File Format
Verilog Startup File Format

A startup file tells the Verilog compiler which Verilog files must be loaded for your
design. The file format for the startup is identical to the startup file used by Verilog
simulators (as used with the -f command-line option). You can use the same startup
file for both the PowerArtist RTL inferencing as well as Verilog simulations (with the
exception that testbench information should be stripped out). The PowerArtist startup
file may contain the entries illustrated by the following simple example.
core.v
logic.v
datapath.v
top.v
-v asic_lib.v
-y /user/tools/libraries/lca500k/verilog
The -v option specifies a file of library cells and the -y option specifies a directory of
library cells. Note that the listing of the Verilog modules is order-independent.
Comments can be placed and begun with either double forward slash as in Verilog,
or with a semi-colon. The Verilog convention of forward slashes and asterisks is also
supported, as shown in the following examples.
// this is a comment
; this is also a comment
/* this is also a comment */
The following additional Verilog command-line options are also supported:
+libext+
+incdir+
+define+
Any unsupported compile option, such as -a or +maxdelays, is ignored if it is present

in the startup file used for Verilog simulation. Multiple Verilog options are allowed on
one line for more compatibility with Verilog. For more information on these options
see the Verilog-XL Reference Manual.
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Vectorless Activity File Format
Vectorless Activity File Format

The Vectorless Activity File (VAF) contains the data that you must use for the gate-
level vectorless power analysis feature. Whereas a GAF contains information that
you get from a simulator, the VAF contains information about net frequencies that
you must define yourself. The VAF is a Tcl-based file that is comprised of object
definitions using the SetNetStimulus and SetPortStimulus commands. The following
sample file illustrates the format of the VAF.
# Clocks:
#
# Name Frequency (Hz) Duty Cycle (Default: 0.5)
#
SetNetStimulus -net rxchan.clk -frequency 6.6e+07
SetNetStimulus -net rxchan.pci_clk -frequency 6.6e+07
#
# Primary IOs:
#
#
SetNetStimulus -net {rxchan.din[0]} -frequency 1.40451e+07
<snip>
#
# Other Nets:
#
#
SetNetStimulus -net {rxchan.wr_addr[0]} -frequency 1.75861e+07
# Memories:
#
# Name Avg. Frequency(Hz) of Local Nets
#
SetInstanceStimulus -instance rxchan.dpmem.m0.m1 -frequency 2.76e+07

This file is used in the block-level analysis tutorial in the PowerArtist User Guide. For
details, see PowerArtist Tutorial Part 1: Power Analysis.
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ptSourceFiles.tcl File Format

This Tcl file is generated by ptCompileScript and contains the following sections:
Section 1
global ptcsStdLibraries
This line defines a global variable that will be used by the remaining Tcl commands in
the file.
Section 2
set ptcsStdLibraries(LIBRARY_NAME,dependency) {list_of_libraries}
This is where you define the standard libraries the VHDL language expects and their
interdependencies. The library name is one of the standard libraries and must be in
capital letters. The standard libraries are STD, SYNOPSYS and IEEE. The space-
separated list_of_libraries specifies the libraries that must be compiled before this
library can compile. This list might be empty. For libraries that are part of the
PowerArtist standard distribution, these are the following lines that get generated:
set ptcsStdLibraries(STD,dependency) {}
set ptcsStdLibraries(SYNOPSYS,dependency) {STD}
set ptcsStdLibraries(IEEE,dependency) {STD SYNOPSYS}
This says that STD must be compiled before SYNOPSYS which must be compiled
before IEEE.
Section 3
This section contains a list of files that must be compiled into each of the standard
libraries.
Syntax
set ptcsStdLibraries(library_name) {list_of_file_names}
}
The list_of_file_names is a Tcl list. The files are located by searching for them in the
$POWERTHEATER/pthdl_src directory.
Example
set ptcsStdLibraries(STD) {
standard.vhd
textio.vhd
}
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This means the library, STD, has compiled into pthdl_src/standard.vhd and pthdl_src/
textio.vhd.
Section 4
This section consists of AddLibrary commands that define all of the logical-to-
physical name mappings for all of your libraries in use in your VHDL design. The
AddLibrary commands are not used for Verilog files. A typical AddLibrary command
would be:
AddLibrary WORK /system/u/demouser/work
Section 5
This is the most complex portion of the file. This section accepts both the
SetIncDirPath and the CompileFile commands. If you are using ptSourceFiles.tcl to
supply the names of your Verilog source files rather than the traditional Verilog
startup file, you may have to specify directories that can be searched for include files.
This is done through the SetIncDirPath command. The CompileFile command
defines how to compile each of the source files in your design. VHDL compilation
has strict rules that must be followed. You must indicate the target library into which
the file will be compiled. If a file must be compiled before another one to meet VHDL
semantic rules, its CompileFile command must occur earlier in the file.
For example, suppose you have the following Verilog source file fragments:
In file “design.v”:
ìnclude "macros.v"
module top(ÀA, bb, cc);
input ÀA, bb;
output cc;
wire tt;
sub u0 (ÀA, bb, tt);
endmodule
In file “sub.v”:
ìnclude "macros.v"
module sub(pp, `QQ, rr);
input pp, `QQ;
output rr;
assign rr = pp & `QQ;
endmodule
And assume the design.v should get its macros.v file from sub-directory include1
while sub.v gets its macros.v file from include2.
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PowerArtist Configuration Files
A properly setup ptSourceFiles.tcl file would be:

SetIncDirPath ./include1
CompileFile -type verilog -file design.v
SetIncDirPath ./include2
CompileFile -type verilog -file sub.v
Each SetIncDirPath completely overwrites the previous value. If a file needs to

include files from multiple directories, you would do something like:
SetIncDirPath dir1 dir2 dir3
CompileFile -type verilog -file design.v
This would search for files included by design.v in dir1, then dir2, then dir3.
PowerArtist Configuration Files

In your home directory, PowerArtist create files that store the current state of your
session. These files are located in the ~/.config/ApacheDesignInc directory. You
should never edit this file since it is created and updated by the PowerCanvas. If you
delete these files, PowerArtist will start with default UI settings for window sizes,
positions etc.
Sample PowerArtist.conf File
[Average_Power_Analysis]
geometry=@Rect(166 164 778 544)
[HDL_Inferencing]
geometry=@Rect(219 253 664 472)
[MainWindow]
SchemColorGroup=actionColorSchematicPower
TreeColorGroup=actionColorTreePower
TreeFilterGroup=actionFilterNothing
TreeSortGroup=actionSortTreeName
actionAutoHidePins=true
actionColoriseDataNets=false
actionColoriseSelectNets=false
actionDisplayGates=false
actionDisplayInferredInstances=false
actionDisplayRegisters=false
actionHierarchy=true
actionIgnoreSelectCones=true
actionSchematic=true
actionSchematicLegend=false
actionTreeLegend=false
actionWaveform=false
geometry=@Rect(120 100 672 461)
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VCDe File Format
mainViewSplitter=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xfc\0\0\0\x92\x1\0\0\
0\x6\x1\0\0\0\x2)
[PTQTreeView]
net_table_1=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\0
<snip>
[Pin_Net_Info]
geometry=@Rect(470 211 400 300)
[PowerArtist-XP_-_Console]
geometry=@Rect(23 23 584 318)
[RTL_Inferencing]
[Time_Based_Power_Analysis]
[Vector_Analysis]
VCDe File Format

This section describes in detail the Enhanced VCD (VCDe) format. Table 3 lists the
major terms used in this section.
Table 3 Terminology
VCDe format Apache Design’s extension to standard VCD (Value

Change Dump) format for handling complex VHDL data
types.
VCDe interface Interface used by Apache Design Power Tools to

generate and use VCDe format and during power
analysis.
Scenario file Apache Design Power Tools design database format.
Intermediate Activity File (IAF) Apache Design Power Tools format for simulation activity
data.
VCDe Format Definition

The VCDe format as it applies to PowerArtist is an extension to the standard VCD
format that supports monitoring of activities for complex VHDL data types. The
standard VCD format was designed for Verilog simulators and never intended to
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VCDe File Format
support VHDL-specific data types. Activity data on objects of these data types would
be lost in the Standard VCD approach or the standard Intermediate Activity File (IAF)
approach. The Enhanced VCD format preserves names and structures for these
complex objects, thereby allowing PowerArtist to match activities on these objects
with the corresponding objects in the Scenario database.
VCDe Interface Definition

The VCDe interface to PowerArtist consists of the following:
 A VPI/FLI interface to a VHDL simulator that allows for writing out the VCDe
format in the generated IAF file.
 The ability to read a VCDe format IAF file into PowerArtist.
Supported VHDL simulators are:
 Modelsim (Mentor)
 NC-VHDL (Cadence)
The complex data types that are supported via the VCDe interface are as shown in
Table 4.
Table 4 Supported Data Types
Type
Classification Description Modelsim NC-VHDL
Discrete Enumerations Yes Yes
Integers Yes Yes
Composite Unconstrained arrays Yes Yes
Constrained arrays Yes Yes
Records Yes Yes
Combinations of the above Arrays of records, for Yes Yes

example
Floating Point No No
Physical No No
Example
The following example demonstrates how a VHDL record is handled in the VCDe
format.
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VCDe File Format
A record declared in VHDL:
package my_pack is
type my_record is
record
field1 : integer;
field2 : bit_vector ( 0 to 1 );
end record;
end my_pack;
VCDe types declared in the resulting IAF file:
$type BIT enum '0' '1' $end

$type BIT_VECTOR__[0:1] array 2 1 BIT [0:1] $end
$type MY_RECORD record 2
INTEGER FIELD1,
BIT_VECTOR__[0:1] FIELD2
$end
The above type declaration for MY_RECORD (and the name conventions) in the
VCDe format match the scenario file declaration of MY_RECORD, allowing
PowerArtist to attribute accurate activity to the record for power calculation purposes.
In contrast, the standard VCD format has no provision for composite data type like
records, and would prevent PowerArtist from matching simulation activity on
MY_RECORD to the scenario database. The net result of such a mismatch would be
that no power would be attributed due to any activities on MY_RECORD. This may
lead to inaccuracy, especially if the use of such data types is prevalent in the design.
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279
Chapter 5
PowerArtist Error Messages 5
Introduction
This chapter lists error messages that PowerArtist can generate. The messages are
organized according to what section of the tools generated the message.
The messages are classified in increasing levels of severity:
1. NOTE. Specifies the state the tool is in so that you can monitor the tool’s progress.
2. WARNING. Indicates that a condition has been found, that while probably not
catastrophic, will negatively affect the quality of results.
3. ERROR. Indicates that a condition has been encountered that prevents the tool
from continuing execution.
4. FATAL. Indicates that the tool has entered an abnormal state. Contact Apache
Design’s customer service whenever a fatal condition is encountered.
The following table indicates by number which section of the toolset is responsible
for generating different message numbers.
Table 5 Error Message Ranges and Their Source
Error # Range Description
1000-1099 Indicate fundamental problems that the tools experience related to the
machine configuration, licensing, and/or file protections.
1100-1199 Generated during the Verilog compilation process and pertain to

problems in the source Verilog.
1200-1399 Generated by the PowerArtist average power calculation engine to

indicate errors, warnings or notes during the power calculation process.
1400-1499 Internal database messages that can be generated if the HDL being
analyzed contains semantic errors.
1500-1599 Generated during the process of reading files such as the internal
SFL_LIB.DAT file.
1800-1899 Generated by the simulation process during a Verilog simulation run.
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CHAPTER 5 — PowerArtist Error Messages PowerArtist™ Reference Manual 280
Introduction
Table 5 Error Message Ranges and Their Source
Error # Range Description
2000-2199 Generated by the GAF reader and may indicate problems in your VCD
file or setup.
2400-2599 Generated during the VHDL compilation process and pertain to

problems in the source VHDL.
2600-2699 Generated by the PowerCanvas in situations where invalid data is

encountered.
2800-2899 Generated by the Elaborate command
3200-4499 Generated by the simulator interfaces
7000-7099 Generated by the RewriteRTL command
7700-7799 Generated during path tracing
8100-8199 Generated by the PowerCanvas GUI
8400-8499 Generated during time-based power analysis (CalculatePower)
8500-8599 Generated during average power analysis (CalculatePower)
9000-9099 Generated by the ReducePower command
9300-9599 Generated during power database (.pdb) generation
9600-9699 Generated by ptshell
9700-9799 Generated by the RewriteRTL command
9800-9899 Generated by the ICGC wrapper
9900-9999 Generated by during the PACE model generation and/or implementation

process
10000-10999 Generated by Verilog
20000-20999 Generated by VHDL
30000-30999 Related to the Elaborate netlist database
45000-45099 Generated during power database (.pdb) generation.
Critical Messages
Warnings and Errors can be classified as “critical”. A critical message is any
message where the reported problem may have a significant impact on either
performance of the software or accuracy of results. These messages are
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Introduction
summarized in the table that PowerArtist prints in the log after an executable is
complete (see the following sample).
wwgaf: Summary of warnings, errors, and suppressed messages:

|---------|---------|---------|---------|
| Type| Number| Printed| Suppr. |
|---------|---------|---------|---------|
| Warning| 2152 | 1 | 0 |
| Warning| 5408 | 1 | 0 |
| Warning| 5410 | 0 | 28 |
| Warning| 3345 | 1 | 0 |
|---------|---------|---------|---------|
wwgaf: Summary of *critical* messages:

|---------|---------|---------|---------|
| Type| Number| Printed| Suppr. |
|---------|---------|---------|---------|
| Warning| 3344 | 1 | 0 |
|---------|---------|---------|---------|
wwgaf: Completed successfully with 4 warning(s)
In this example, there is one critical warning. The Suppr. (suppressed) column lists
warning messages for which the -nowarn option has been set.
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Introduction
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283
Chapter 6
Advanced Usage Tips 6
Using LSF
You can use the Load Sharing Facility (LSF) in either batch or interactive mode in
PowerArtist.
For batch mode, you can simply submit jobs using bsub, for example:
bsub -Rsol8 ptshell -tcl Elaborate.tcl
The command you use could easily be a complex Tcl script.
You can use one of two methods to submit interactive jobs.
Method 1
The first method is to spawn an X-terminal, for example:
bsub -Rsol8 xterm
This opens up an xterm window in which you can set the environment variables
necessary to run PowerArtist and type ptshell.
Do not attempt to run PowerArtist using either the -I or -Is switches to LSF. For
example:
bsub -Rsol8 -Is ptshell
will spawn the job, but you will not be able to enter any commands. If you type:
bsub -Rsol8 -I ptshell
you will not get the ptshell prompt, but you will be able to enter Tcl commands such
as Elaborate.
Method 2
The second method is to submit jobs using the lsrun command which is specifically
designed for interactive job submittal using LSF. For example:
lsrun ptshell
This will then give you an active ptshell with a prompt at which you can submit further
commands.
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CHAPTER 6 — Advanced Usage Tips PowerArtist™ Reference Manual 284
Using LSF
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285
Appendix A
Supported Sys. Verilog, Verilog 2001 & VHDL

Constructs A
All designs make use of a design language to create simulation models as well as to
act as the source for a gate-level synthesizer. PowerArtist needs to be able to handle
both types of data. It needs to be able to successfully parse RTL code that is meant
to be input to a simulator and it must be able to inference RTL code that is meant to
be input into a gate-level synthesizer as well as a simulator. This appendix describes
the SystemVerilog, Verilog 2001 and VHDL constructs supported by PowerArtist.
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APPENDIX A — Supported Sys. Verilog, Verilog 2001 & VHDL Constructs PowerArtist™ Reference Manual 286
SystemVerilog Support
The following table lists the constructs that are supported (parsed and inferenced).
Description Parse Inference
Literals structure literals Y Y
unsized literal ('0', '1', 'x', 'z') Y Y
Data Types logic (4-value) data type Y Y
integer data types (int, bit) Y Y
User-defined types (typedef) Y Y
Structures (packed) Y Y
Structures (unpacked) Y Y
Enumerations Y Y
Unions (packed) Y Y
Integer data types Y Y
Casting Y Y
Void data types Y Y
Arrays Arrays (packed) Y Y
Arrays (unpacked) Y Y
Array querying ($length, $left, $right, Y Y

$low, $left,
$right, $low, $high, $increment,
$dimensions)
Data Declaration Scoping Y Y
Constants Y Y
Variables Y Y
Operators Structure fields ("." Operator)
Auto-operators (+= -= ++ -- &= |= ^=, Y Y

<<= >>=
<<<= >>>=)
Procedural Statements unique/priority if statement Y Y
unique/priority case, casex, casez Y Y

statements
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Description Parse Inference
Matching end block name Y Y
Process always_comb Y Y
always_latch Y Y
always_ff Y Y
Tasks and functions void functions Y Y
all types as legal task/function Y Y

argument types
return statement in functions Y Y
logic default task/function argument Y Y

type
input default task/function argument Y Y

direction
Assertions Propagated to netlist Y Y
Hierarchy All types as legal module ports Y Y
$root Y Y
implicit .name and .* port connections Y Y
Interfaces Interface as signal container & module Y Y

port replacement
Interface modports Y Y
Interface ports Y Y
Parameterized interfaces Y Y
Interface tasks & functions (no import Y Y

or modport
Array instantiation of interfaces Y N
Generic interface Y N
System tasks and functions Expression Size system function Y Y

($bits)
Compiler directives Macro arguments in strings Y Y
Misc. For(int i=0; ….) Y Y
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Verilog 2001 and VHDL Support
Verilog 2001 and VHDL Support

PowerArtist parses all Verilog 2001 and VHDL constructs. PowerArtist will
successfully inference all Verilog 2001 and VHDL constructs that are recognized as
being synthesizable by industry standard gate-level synthesizers.
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289
Appendix B
Listing of Commands, Variables and Utilities B

This appendix contains a comprehensive alphabetical listing of all commands and pt_set variables that
you can use in your PowerArtist command file.
active_edge compress_gaf etcl_file

activity_debug_flags constraints_bus_naming_style etcl_finish_time
activity_file constraints_log etcl_log
activity_perform_esl_analysis constraints_output_file etcl_start_time
activity_waveform_clock_edge constraints_savings finish_time
activity_waveform_clock_name constraints_synthesis_tool flop_clock_activity
activity_waveform_cycles_per_interval count_glitches_as_toggles force_stimulus_processing
activity_waveform_graph_type CpfIncludeFile forced_x
activity_waveform_group_list CreateDomain fsdb_output_file
activity_waveform_interval_size CreateGraph ftn_report_file
activity_waveform_log CreateVirtualSupply gaf_file
activity_waveform_number_of_intervals critical_messages gate_level_netlist
activity_waveform_start_clock_cycle curr_etcl_info GenerateActivityWaveforms
activity_waveform_start_time curr_set_net_events GenerateEtclFile
AddLibrary current_output_file getAssociatedNet
allowed_x_time dcd getCGRegisters
allowed_z_time debug_instances_file getCGs
analysis_type default_dont_use_cells getConnectedPins
arc_based_estimation default_output_load getExtendedName
average_cpf_in_file (Beta) default_transition_time getFanin
average_cpf_output_file (Beta) DefineGroup getFanout
average_html_report_title DefineHalfMemScalingFactor getFlops
average_report_file DefineLibAlias getInstsOfModuleType
average_report_options DefineMemActivityThreshold getModule
average_results_file DefineMemory getModuleInsts
average_upf_in_file (Beta) detailed_vertical_report getModuleNets
average_write_power_db dirs getModulePorts
black_box_modules disable_glitch_propagation getObject
blast_regfile dls getOccObject
calculate_log domain_frequency_cell_selection getPinDirection
CalculatePower dpop getPropVal
capacitance_file dpush getRegisterCGs
case_insensitive dpwd getRelatedPins
case_sensitive Elaborate getSinkPins
check_synlib_semantics elaborate_ignore_directives getSrcPin
collateReductions elaborate_log graph_class
compare_with_results_file elaborate_write_power_db graph_log
CompileFile enhanced_vcd graph_output_file
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APPENDIX B — Listing of Commands, Variables and Utilities PowerArtist™ Reference Manual 290
graph_type pa2oa reduction_max_memory_split

heartbeat parameter_maps reduction_min_bit_width
html_report_directory pc_constraint_file reduction_overwrite_power_db
ignore_SPEF_C_comments peak_cycle_file reduction_priority
ignore_toggles_through_x peak_cycle_processing_mode reduction_report_csv_file
ignore_translate_off peak_waveform_file reduction_report_csv_separator
ignore_translate_off_files power_db_name reduction_report_file
instance_power_threshold power_tech_file (Beta) reduction_report_instance
interpret_pin_caps_as preserve_regfile reduction_report_log_file
interval_size print_missing_sim_nets reduction_report_module
isComb PrintActivityData reduction_report_options
isConnect pt_copy_pdb reduction_report_type
isFlop pt_reset reduction_results_file
isLatch pt_set reduction_threshold
isLeaf ptcl_output_file reduction_topology
isMemory ptCompileScript reduction_upf_in_file (Beta)
isPin ptFsdb2VcdPlus reference_clock
isRoot ptLibraryCheck RefineConfigurationParameter
isSequential ptoa::convertDBName remap
library_defaults_file ptoa::getCGInfo reportCGEfficiency
list_required_traces ptoa::getClockPower reportPath
load_file ptoa::getFunctionTypeName reportPower
lower_case_vhdl ptoa::getInsts ReportReductions
macro_directories ptoa::getModules reset_library_negative_power
make_mti_mapfile ptoa::getNets reset_negative_power
MapRetentionCell ptoa::getNext rewrite_debug_flags
max_clock_depth ptoa::getObject rewrite_log
max_time_stamps ptoa::getProductVersion rewrite_no_inline_modules
maximum_number_of_errors ptoa::getPropVal rewrite_reduction_mapping_file
min_regfile_bit_count ptoa::releaseIterator rewrite_report_file
min_regfile_word_count ptoa::reportClockEnableEfficiency RewriteRTL
min_regfile_word_length quiet saif_file
mixed_sim_prob_estimation ReadLibrary save_clock_trees_netlist
mode_file ReadParasitics save_x_nets_file
MonitorArcs readReductions scenario_file
MonitorFast ReadSDC sdc_files
MonitorInstances ReadVerilogStartupFile sdc_log
MonitorToggleInstances ReducePower sdc_out_file
multiple_license_files reduction_classes set_load_file
multiple_testbench_control_file reduction_compare_error_report_file SetArchitecture
nl2oa reduction_compare_golden_sim_file SetAttribute
nl2pa reduction_compare_log SetBounds
no_default_macros reduction_compare_output_rule_file SetBuffer
no_maximum_error_list reduction_compare_secondary_sim_file SetCapEstimation
no_module_net_capacitances reduction_compare_type SetCCommentsIgnore
no_slew_calculation reduction_cpf_in_file (Beta) SetCellDefaultFanout
num_clock_cycles reduction_cpf_output_file (Beta) SetClockBuffer
oa2nl reduction_debug_flags SetClockGatingRegisters
oa2pa reduction_dont_touch_clocks SetClockGatingStyle
output_ascii_netlist reduction_dont_touch_modules SetClockGroups
output_current reduction_hierarchy SetClockNet
output_rtl_dir_name reduction_html_report_title SetConfigurationParameter
output_startup_file reduction_log SetDatapathWidth
pa2nl reduction_max_bit_width SetDefaultFanout
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SetExcludeModules voltage
SetHighFanoutNet wait_for_license
SetIncDirPath wireload_library
SetInstanceStimulus work_library
SetLibrary WriteClockGatingConstraints
SetMemoryGatingCell WriteReductionCompareFile (Beta)
SetNameMapFile WriteTechnologyFile
SetNetStimulus wwgaf
SetPortStimulus wwvmkr
SetPower zero_delay
SetPowerTarget
SetSpefFiles
SetTopSpef
SetVoltageThreshold
SetVT
SetWireLoadMode
SetWireLoadModel
show
show_reduction_net_name
skip_clock_analysis
skip_reduction_list
spef_file
start_time
statics_threshold
statistics
suppress_messages
synlib_files
system_verilog
tag_blocks
time_based_cpf_in_file (Beta)
time_based_cpf_output_file (Beta)
time_based_report_file
time_based_upf_in_file (Beta)
time_based_write_power_db
top
top_instance
TraceThruCell
TraceThruInstance
transition_time_file
unlimit_interval_size
use_non_scan_flops
use_rtl_sim_data
use_scan_flops
vectorless_input_file
verilog_2001
verilog_startup_file
vertical_report_instances
vertical_report_sort_mode
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PowerArtist™ Reference Manual 293
Index
A file format 260 enhanced_vcd 34, 92

capacitance_file 33, 77, 91 ESL power analysis
active_edge 22
case_insensitive 57, 101 remap command 96
activity_debug_flags 22, 59, 90
case_sensitive 53, 57, 101 Etcl file format 264
activity_file 22, 59, 63, 249
check_synlib_semantics 33, 91 etcl_file 63
activity_perform_esl_analysis 32
clock nets file etcl_finish_time 63
activity_waveform_clock_edge 60
specifying buffers 112 etcl_log 63
activity_waveform_clock_name 60
specifying clock gating style 114 etcl_start_time 63
activity_waveform_cycles_per_inter
specifying maximum fanout for
val 60
clock cells 111
activity_waveform_graph_type 60
commands, alphabetical listing 289
F
activity_waveform_group_list 60 file formats
compare_with_results 91
activity_waveform_interval_size 60 capacitance 260
compare_with_results_file 33
activity_waveform_log 60, 61 duty cycle 68, 261
compress_gaf 24, 249, 250
activity_waveform_number_of_inter
constraints_bus_naming_style 140 global activity 68, 261
vals 60 message log 68, 271
constraints_log 140
activity_waveform_start_clock_cycl mode 68
constraints_output_file 140
e 61 Sequence Library Defaults (.sld)
constraints_synthesis_tool 140
activity_waveform_start_time 61 262
CoolTime
allowed_x_time 32, 90, 249 stimulus 271
register activity generation Tcl 49
allowed_z_time 33, 91, 249, 250 29, 88, 249, 252
analysis_type 22 transition time 261
count_glitches_as_toggles 34, 91 Verilog startup 271
arc_based_estimation 22, 81 critical_messages 34, 53, 61, 91, 102
arcs monitoring 67 file name mapping
cumulative_savings 140 logical to physical 260
average_cpf_in_file 23 current_output_file 34, 91 files
average_cpf_output_file 33
external
average_html_report_title 33
D net name matching 17, 259
average_report_file 23
debug_instances_file 34, 91 finish_time 25, 81, 249, 250
average_report_options 23
default_dont_use_cells 24, 80 flop_clock_activity 25
average_results_file 33
default_output_load 25, 80 forced_x 34, 92, 249, 250
average_upf_in_file 24
default_transition_time 15, 25, 80, 143 fsdb_output_file 25, 61
average_write_power_db 24
detailed_vertical_report 25, 80 ftn_report_file 35, 92, 249, 250
disable_glitch_propagation 34, 92
B
domain_frequency_cell_selection G
black_box_modules 53, 101 25, 80 gaf_file 26, 81
blast_regfile 53 duty cycle file format 68, 261 gate_level_netlist 26, 54
block-level components
global activity file format 68, 261
extracting from HDL design 13
bus frequency 9 E graph_class 42
elaborate_ignore_directives 53, 102 graph_log 42
elaborate_log 54 graph_output_file 42
C graph_type 42
elaborate_write_power_db 54, 101
calculate_log 24 energy, definition 1
capacitance
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INDEX PowerArtist™ Reference Manual 294
H num_clock_cycles 27 reduction_upf_in_file 86
heartbeat 35, 92, 249, 250 reference_clock 27
html_report_directory 35, 92 O relative frequency information
file format 271
output_ascii_netlist 58
remap command 96
I output_current 37
reset_library_negative_power 37, 94
ignore_SPEF_C_comments 35, 93 output_report_file 102
reset_negative_power 38, 94
ignore_toggles_through_x 35, 93 output_rtl_dir_name 103
rewrite_debug_flags 103
ignore_translate_off 54, 102 output_startup_file 103
rewrite_log_file 103
ignore_translate_off_files 54, 102 rewrite_no_inline_modules 103
instance_power_threshold 35, 93 P rewrite_report_file 104
interpret_pin_caps_as 36, 93 PACE technology files, specifying
27, 82 S
L parameter_maps 55
saif_file 27
library_defaults_file 36, 93 pc_constraint_file 94
save_clock_trees_netlist 27, 86
peak_cycle_file 37
list_required_traces 54 save_x_nets_file 28, 87, 249, 251
load_file 36, 93 peak_cycle_processing_mode 37
scenario file 13
lower_case_vhdl 57 power
scenario_file
component hierarchy 6
28, 56, 60, 64, 87, 104, 142, 249, 2
definition 1
M 52
dynamic 2, 7
sdc_clocks_gated 78
macro_directories 57 static 4, 8
sdc_clocks_mode 78
make_mti_mapfile command power_db_name 42, 78, 101, 103, 140
sdc_command 77
examples 246 power_tech_file 27, 82, 142
sdc_files 77, 142
max_bit_width 93 preserve_regfile 58
sdc_log 78
max_clock_depth 36, 93 print_missing_sim_nets 27, 82
sdc_out_file 78
max_time_stamps 36 ptcl_output_file 27, 61, 64
seed vector format 264
maximum_number_of_errors 36, 93 ptLibraryCheck command 247
Sequence Library Defaults (.sld) file
message log file format 68, 271
format 262
micro-architectural inferencing 13 Q SetCellDefaultFanout command
min_regfile_bit_count 57
quiet 27, 58 111, 138
min_regfile_word_count 57
SetClockGatingStyle command 114
min_regfile_word_length 57
R SetClockNet command 116
mixed_sim_prob_estimation
skip_clock_analysis 28, 87
26, 61, 63, 81 reduction_classes 82
skip_reduction_list 88
mode file format 68 reduction_cpf_in_file 82
spef
mode_file 26 reduction_cpf_output_file 83
file format 263
monitoring arcs 67 reduction_debug_flags 83
spef_file 29, 143
multiple_license_files reduction_dont_touch_clocks 83
split 252
36, 58, 61, 93, 142, 143 reduction_dont_touch_modules 83
start_time 29, 88
multiple_testbench_control_file 26 reduction_hierarchy 83
stimulus file format 271
reduction_max_bit_width 84
stimulus_processing_passes 38, 94
N reduction_max_memory_split 84
suppress_messages 29, 58, 89
reduction_min_bit_width 84
nets synlib_files 30, 56, 62, 64, 143
reduction_overwrite_power_db 84
name matching for external files system_verilog 56, 104
reduction_priority 85
17, 259
reduction_report_file 85
transition counting 9 T
no_default_macros 58 reduction_report_log_file 84
no_maximum_error_list 36, 58, 94 reduction_report_options 85 tag_blocks 56
no_module_net_capacitances 37, 94 reduction_results_file 86 Tcl file format 49
no_slew_calculation 37, 94 reduction_topology 86 time_based_cpf_in_file 30
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time_based_cpf_output_file 38 Z
time_based_report_file 30 zero_delay 32
time_based_report_options 30
time_based_upf_in_file 30
time_based_write_power_db 30
top 56, 77, 101, 140, 142
top_instance 30, 60, 64, 89, 252
transition counting on nets 9
transition times
automatic calculation 15
file format 261
transition_time_file 31, 77, 89
U
unlimit_interval_size 38
use_existing_gaf 31, 81
31, 89, 101, 104
use_non_scan_flops 38
use_rtl_sim_data 31, 62, 64
use_scan_flops 31, 89, 94
V
VAF (Vectorless Activity File)
format details 121, 124, 126, 272
variables
alphabetical listing of all 289
vectorless_input_file 31, 89
Verilog startup file format 271
verilog_2001 56, 104
verilog_startup_file 56, 101, 143
vertical_report_instances 31, 89
vertical_report_sort_mode 31
voltage 38, 90, 94
W
wait_for_license
32, 58, 62, 90, 142, 143
wireload_library 38, 94
work_directory 58
wwgaf
generating register activity
29, 88, 249, 252
wwgaf conversion utility
automatic spawning 253
wwvmkr command
examples 255
options 254, 256
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PowerArtist 1

Software Release 2011.1.3

© 2011 Apache Design, Inc.

© 2011 Apache Design, Inc. All rights reserved.

Trademarks and Registered Trademarks

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© 2011 Apache Design, Inc.

CHAPTER 1 Energy and Power Analysis

CHAPTER 3 Command Reference

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Design Navigation Utilities............................................................................ 199

CHAPTER 4 File Formats

CHAPTER 5 PowerArtist Error Messages

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CHAPTER 6 Advanced Usage Tips

APPENDIX A Supported Sys. Verilog, Verilog 2001 & VHDL Constructs

APPENDIX B Listing of Commands, Variables and Utilities

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Energy and Power Analysis 1

Energy and Power Fundamentals

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Figure 1 Simple Circuit Capacitance

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Figure 2 Simple Static Circuit

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Ptotal = (2 •10-12 • 5.252 • 2 • 15 •106 / 2) + (1 • 10-3 • 5.25)

Etotal = Edyn + Est

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Power Component Hierarchy

Ptotal = Pdynamic + Pstatic

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Dynamic Power Component

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Static Power Component

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Transition Counting on Nets

Table 1 How GAF Creation Counts Transitions

X -> 0 Counts as a transition

X -> 1 Counts as a transition

0 -> X Does not count as a transition

1 -> X Does not count as a transition

0 -> Z Does not count as a transition

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Table 1 How GAF Creation Counts Transitions

1 -> Z Does not count as a transition

Z -> 0 Counts as a transition

Z -> 1 Counts as a transition

If you use the -ignore_toggles_through_x option to CalculatePower, transitions to the

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Duty Cycle Calculation

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Value Changes of a Signal with Tag '-'

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This generates two new sub-modules, #1 and #2.

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Default Transition Time Calculator