Digital Lab Manual V2.1
Digital Lab Manual V2.1
Digital Lab Manual V2.1
DL7211
The Digital Lab may also be used for testing circuits and making projects related to digital
electronics.
DC Power
Pulse Generator
Pulser Switches
8-Bits Data Switches
Logic Probe
Digital Display
Mode Selector
8-Bits LED Display
14 Additional Experiment Boards
Technical Specification:
8-Bits LED Display : When the input to this block is high the LED
will glow red and when low the LED will
glow green, there will be no display for an
open input.
The trainer is equipped with a built in DC power supply, when the ON/OFF switch is set to
ON the LED will be lit indicating that there is power to the trainer.
When +V and -V potentiometer of DC power block are in the fully clockwise position, full
voltage +15V and -15V is obtained, the +V and -V potentiometer can be varied to get variable
positive and negative supply from +3V to +15V and -3V to -15V. When +V potentiometer is
varied, CMOS voltage level will be varied proportionally, so whenever CMOS mode is used,
carefully check the +V potentiometer position.
The frequency potentiometer of the pulse generator is used for the fine setting of frequency of
pulse. The range switch is used to vary frequency from 10Hz to 1MHz in six steps.
Frequency below 10Hz can be obtained by the frequency potentiometer. Pulser switches are
momentary switches, as long as these are pressed, indicated outputs are obtained. When the
8-bits data switches are in position 1 they will give a high output and in zero position will
give a low output. When the ON/OFF switch of digital probe is turned ON the digital display
will be illuminated.
When TTL/CMOS switch is switched to ‘TTL’ or ‘CMOS’ position the outputs of the pulse
generator, pulse switches, 8-bits data switches, inputs of the digital probe and 8-bits LED
display will meet either the high or low level of ‘TTL or CMOS’.
Introduction:
DL01 is a Logic Gates experiment board. All logic gates are incorporated on a single board
for verification of their truth table and comparison. It can be used as stand-alone unit with
external power supply or can be used with the DL7211 Digital Lab which has built in power
supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display, 8
bits LED display
Theory:
A Logic gate is a digital circuit with one or more input but only one output. AND, OR,
NAND, NOR, NOT, EX-OR gates are some examples of logic gates. Each gate has one or
two binary input variable designated by X & Y and one binary output variable Z. The logic
diagram and truth table of logic gates is shown in experiment section.
OR Gate: The OR Gate has two or more inputs and one output.
This operation is represented by a plus sign e.g. X +Y= Z is read X or Y is equal to Z
meaning that Z=1 if X=1 or if Y=1 or if both X=1 & Y=1. If both X=0 & Y=0 then Z=0. The
output voltage of OR gate is high if any or all of the input voltages are high that is +5 V or
logic 1 (TTL level is used). Logic equation is Z = X+ Y (X & Y are inputs & Z is output.)
AND Gate: The AND gate has two or more than two inputs. This operation is represented by
a dot or by absence of an operator e.g. X.Y=Z or XY=Z is read X AND Y is equal to Z. The
logical operation AND is interpreted to mean that Z=1 if and only if X=1 and Y=1 otherwise
Z=0
NOT gate: The NOT gate has one input and one output. This operation is represented by
prime (bar). For example X’= Z is read “X not equal to Z” meaning that Z is what X is not. In
other words if X=1, then Z=0 but if X= 0 then Z=1.
NAND Gate: The NAND gate has two inputs & one output. The NAND function is a
compliment of the AND function. The bubble on output represents inversion after ANDing.
The logic equation is Z= (X.Y)’. The output is high if any of the input is low.
NOR Gate: The NOR gate has two or more inputs and one output. The NOR function is
complement of OR function .The output is low if any input is high.
EX-OR Gate: The Exclusive OR gate has two inputs and one output. The output is high if
and only if the two inputs i.e. X & Y are different i.e. If X=1 & Y=0 or X=0 & Y=1 otherwise
output will be low. The logic equation is XY’+X’Y= X⊕Y=Z.
Note: Truth tables and logic diagrams are shown in Experiment Section.
Apparatus Required:
X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
OR Gate
X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
AND Gate
X Y Z
0 0 1
0 1 0
1 0 0
1 1 0
NOR Gate
X Z
0 1
1 0
NOT Gate
X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
X Y Z
0 0 0
0 1 1
1 0 1
1 1 0
EX-OR Gate
Procedure:
1. Connect +5 V and ground to their indicated position on DL01 experiment board from
external DC power supply or from DC power block of Digital Lab Main Board
DL7211.
2. Connect inputs 00, 01, 10, 11 as per truth table to pin X and Y of AND gate.
7400 7402
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Introduction:
DL02 is a Universal Gate NAND/NOR experiment board that has been designed to show that
logic operations like AND, OR, NOT can be performed using NAND and NOR gate. The
board can be used as stand-alone unit with external power supply or can be used with Digital
Lab 7211 which has built in power supply, pulse generator, pulser switches, 8 bits data
switches, logic probe, 8 bits LED display.
Theory:
NAND & NOR gates are said to be Universal gates because any digital system can be
implemented with them. It is only need to show that logic operations AND, OR, NOT can be
implemented with NAND & NOR gates.
The implementation of AND, OR, NOT operation with NAND gate is shown in Logic
diagram in Experiment section. The NOT operation is obtained from one two input NAND
gate. The inputs of NAND gate are shorted to get NOT operation. The AND operation
requires two NAND gates. The first produces the inverted AND, and second acts as an
inverter to produce Normal output. The OR operation is achieved through a NAND gate with
additional inverters in each input.
The NOR function is dual of the NAND function. All procedures and rules for NOR logic
form a dual of the corresponding procedures and rules developed for NAND logic. The
conversion of NOR to AND, OR, NOT is shown Logic diagram in Experiment section. NOT
operation is obtained from one, 2 input NOR gate with the inputs shorted. The OR operation
requires two NOR gates. The first produces the inverted-OR and the second acts as an inverter
to obtain normal output. The AND operation is achieved through a NOR gate with additional
inverters at each input. The logic diagram and truth table of logic gates is shown in
experiment section
Object: To study implementation of AND, NOT and OR function with NAND and NOR
gate.
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1=+5 V& logic 0= GND)
X
X
X Z
Y
Z Z
Y
X
X
X Z
Y
Z Z
Y
X Y Z X Y Z
0 0 0 0 0 0
X Z
0 1 1 0 1 0
0 1
1 0 1 1 0 0
1 0
1 1 1 1 1 1
NOT Gate OR Gate AND gate
Procedure:
1. Connect +5 V and ground to their indicated position on DL02 from external DC power
supply or from DC power block of Digital Lab 7211.
2. Connect inputs 00, 01, 10, 11 as per truth table to pins X and Y of OR gate
3. Switch ON the power supply.
4. Observe output Z of gate on multi-meter or on logic probe or on LED display of Digital
Lab 7211 and prove truth table.
5. Repeat above steps for remaining logic gates.
7400
X Z
0 1
1 0
7402
Introduction:
DL03 is an EX-OR Gate Implementation experiment board. This is useful for students to study
application of logic gates to implement EX-OR function. It can be used as stand-alone unit with
external power supply or can be used with Digital Lab 7211 which has built in power supply, pulse
generator, pulser switches, 8 bits data switches, logic probe, 8 bits LED display.
Theory:
The Exclusive-OR (EX-OR) is a logic block that compares a bit of data. When the bits are alike, the
EX-OR output is 0 and when the bits are not alike, EX-OR output is 1. With inputs X & Y, EX-OR
equation is Z = X’.Y +X.Y’=X Y.
Z= (X Y) W= X (Y W) =X Y W.
This implies the possibility of using exclusive-OR gates with three or more inputs. Although there
are many ways of implementing EX-OR, two logic diagrams are shown in the experiment section. In
the first method four NAND gates are used to implement the EX-OR function. The inputs to the first
stage NAND gate are X & Y and the output is (XY)’.
X and (XY)’ are inputs to upper NAND gate of second stage. Its output is [X. (XY)’]’=X’+XY
(Demorgan’s theorem (X.Y)’=X’+Y’).The inputs to second NAND gate are Y & (XY)’. It’s output
is (Y’+X.Y). Similarly output of last stage NAND gate is [(X’+XY). (Y’+XY)]=X’Y+Y’X. In the
second method 2 NOT gates, 2 AND gates and 1 OR gate are used. Inputs to I NAND gate are X &
Y’ and output is XY’ similarly outputs of II NAND gate is X’Y. These two outputs are inputs to OR
gate. It’s output is Z= X’Y+Y’X.
Note: Truth tables and logic diagrams are shown in Experiment Section.
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
Y
Fig I
Y
Fig II
X Y Z
0 0 0
0 1 1
1 0 1
1 1 0
EX-OR Gate
1. Connect +5 V and ground to their indicated position on DL03 experiment board from external
DC power supply or from DC power block of Digital Lab 7211.
2. Connect inputs 00, 01. 10, 11 as per truth table to pins X and Y of EX-OR gate shown
in Fig I.
3. Switch on the power supply.
4. Observe output Z of gate on multi-meter or on logic probe or LED display of Digital
Lab 7211 and prove truth table.
5. Repeat above steps for Fig II.
Datasheet
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7432 7408
Introduction:
DL04 is a Demorgan’s Theorem experiment board. This experiment board has been designed to
prove Demorgan’s Theorem with simple Boolean logic equations. It can be used as stand-alone unit
with external power supply or can be used with DIGITAL LAB 7211 which has built in power
supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display, 8 bits LED
display.
Theory:
Demorgan’s theorem permits conversion of logic from OR/NOR to AND/NAND and AND/NAND
to OR/NOR.
It says that the complement of a sum equals the product of complements. Fig 4a is the graphical
meaning of Demorgan's first theorem. The L.H.S of equation I represents NOR gate & R.H.S of
equation I represents bubbled AND gate.
Fig4a
Equation I shows that the NOR gate is equivalent to bubbled AND gate.
It says complement of a product equals the sum of the complements. Fig 4b is the graphical meaning
of Demorgan’s second theorem. L.H.S of equation II represents output of a NAND gate. RHS of
equation II represents output of bubbled OR gate. Thus equation II represents NAND gate is
equivalent to a bubbled OR gate.
Apparatus Required:
X+Y
X Y X+Y (X’.Y’)’
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
X.Y
X+Y = (X’.Y’)’
Fig I
X.Y
X Y (X’+Y’) X.Y
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1
X+Y
X.Y= (X’+Y’)’
Fig II
Procedure:
1. Connect +5V and ground to their indicated position on DL04 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Connect inputs 00, 01, 10, 11 to inputs X and Y of logic circuit shown in Fig I. as per truth
table given.
3. Switch on the power supply.
4. Observe outputs (X’.Y’)’, (X+Y) on multi-meter or on logic probe or LED display of Digital
Lab 7211 and prove truth table.
5. Repeat above steps for logic circuit of Fig II
7404 7402
7400
Introduction:
DL05 is an EX-OR Gate Application experiment board. This experiment board has been designed to
study logic circuits such as parity generators, binary word comparator implemented using EX-OR
gate.
All logic circuits incorporated on a single board for verification of their truth table. It can be used as
stand-alone unit with external power supply or can be used with Digital Lab 7211 which has built in
power supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display,
8 bits LED display.
Theory:
Parity Generator:
A parity bit is a scheme for detecting errors during transmission of binary information. A parity bit is
an extra bit included with a binary message to make the number of 1’s either odd or even. The
message, including the parity bit, is transmitted and then checked at the receiving end for errors. An
error is detected if the checked parity doesn’t correspond to one transmitted. The circuit that
generates the parity bit in the transmitter is called a Parity Generator.
Consider a three-bit message to be transmitted with an odd parity bit as shown in truth table for the
odd parity generator in Experiment section. The three bits X 0, X1, X2 constitute the message and are
the inputs to the circuit. The parity bit Y is output. For odd parity the bit Y is generated so as to make
the total number of 1’s odd (including Y). From truth table Y=1 When the number of 1’s in X0 X1 X2
is even. So the functions for Y can be expressed Y= (X0 X1) oX2.
The Logic diagram for the odd parity generator is shown in Experiment section. It consists of two
2-input exclusive OR gate and a NOT gate. The three bit message and parity bit are transmitted to
their destination where they are applied to parity checker circuit. An error occurs during transmission
if the parity of four bits received is even. Since the binary information transmitted was originally
odd. The output of parity checker should be 1 when number of 1’s in the four inputs is even.
Similarly for even parity, the bit Y is generated so as to make the total number of 1’s even (including
Y) when number of 1’s in X0 X1 X2 is odd (Refer truth table). So the function for Y can be expressed
as
Y= X0 X1 X2.
Logic diagram & truth table for the even parity generator is shown in Experiment section.
A binary word comparator is a combinational circuit that compares two numbers X and Y and
determines whether they are equal or not. The binary variable Z that indicates whether X is equal to
Y or not, specifies the outcome of the comparison. There are two numbers X & Y with four digits
each as shown in truth table for Binary word comparator in Experiment section.
X= X0 X1 X2 X3
Y= Y0 Y1 Y2 Y3
The two numbers are equal if all pairs of significant digits are equal i.e. X0=Y0, X1=Y1, X2=Y2,
X3=Y3. When the inputs to each EX-OR gates are equal i.e. either both are 0 or both are 1, output of
EX-OR gate will be 0. This will make the output of NOT gates 1 and so the output variable Z=0.
Whenever inputs to EX-OR gate are unequal i.e. one input is 1 and other is zero or vice versa then
output Z=1. Output Z is active low i.e. low output indicates the two numbers X and Y are equal &
high indicates that they are unequal.
Apparatus Required:
X0
X1
X0
X1
X2
X2 Y
Y
X0
Y0
X1
Y1
Z
X2
Y2
X3
Y3
Procedure:
1. Connect +5V and ground to their indicated position on DL05 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Connect inputs to pins X0, X1, X2 of odd parity generator as shown in logic diagram as per
truth table.
3. Switch ON the power supply.
4. Observe output Y on multi-meter or on logic probe or on LED display of Digital Lab
7211 and prove truth table.
5. Repeat steps 2, 3 & 4 for even parity generator and binary word Comparator and
prove truth table. (Refer logic diagram and truth table).
7404 7400
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Introduction:
DL06 is a Code Conversion experiment board. This experiment board has been designed to study
code converters used for translating from code to code. It can be used as stand-alone unit with
external power supply or can be used with Digital Lab 7211 which has built in power supply, pulse
generator, pulser switches, 8 bits data switches, logic probe, Digital Display, 8 bits LED display.
Theory:
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes by different digital system. It is sometimes necessary to use the output of
one system as the input to another. A conversion circuit must be inserted between the two systems
if each uses different codes for the same information. Thus, a code converter is a circuit that makes
the two systems compatible even though each uses a different binary code.
The binary number system is a system that uses only the digits 0 & 1 as codes. To represent a group
of 2n distinct element in a binary code requires a minimum of n bits. This is because it is possible to
arrange n bits in 2n distinct ways. Although the minimum number of bits required to code 2n distinct
quantities is n, there is no maximum number of bits that may be used for binary code .For example,
a group of four distinct quantities can be represented by a two bit code, with each quantity assigned
one of the following bit combination: 00, 01,10,11. A group of eight elements requires a three bit
code, with each element assigned to one and only one of the following 000, 001, 010, 011, 100,
101,110, 111. (Refer table 6.1)
Gray code (Reflected code) is shown in Table 6.1. Numbers in the Gray code change by only one
bit as it proceeds from one number to the next. For example in going from decimal 7 to 8, the Gray
code number changes from 0100 to 1100; these numbers differ only in MSB. So it is with the entire
Gray code; every number differs by only one bit from the preceding number.
Table 6.1
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
B0
G0 G0
B0
B1
G1 G1
B1
B2
G2 G2
B2
B3 G3 B3
G3
Decimal B3 B2 B1 B0 Decimal G3 G2 G1 G0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 0 0 0 1
2 0 0 1 0 2 0 0 1 1
3 0 0 1 1 3 0 0 1 0
4 0 1 0 0 4 0 1 1 0
5 0 1 0 1 5 0 1 1 1
6 0 1 1 0 6 0 1 0 1
7 0 1 1 1 7 0 1 0 0
8 1 0 0 0 8 1 1 0 0
9 1 0 0 1 9 1 1 0 1
10 1 0 1 0 10 1 1 1 1
11 1 0 1 1 11 1 1 1 0
12 1 1 0 0 12 1 0 1 0
13 1 1 0 1 13 1 0 1 1
14 1 1 1 0 14 1 0 0 1
15 1 1 1 1 15 1 0 0 0
1. Connect +5 V and ground to their indicated position on DL06 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Connect inputs B0, B1, B2, B3 as per truth table 6.2 to Binary to Gray code converter
as shown in figure 6.1.
3. Switch ON the power supply.
4. Observe output G0, G1, G2, G3 on multi-meter or on LED Display of Digital Lab
7211
5. Repeat above step for remaining inputs and prove truth table.
6. Repeat above steps for Gray to Binary code converter and prove truth table.(Refer fig
6.2.& table 6.3)
Datasheet:
7486
Introduction:
DL07 is a Code Conversion experiment board. This experiment board has been designed to study
BCD to Excess-3 code converter. It can be used as stand-alone unit with external power supply or
can be used with Digital Lab 7211 which has built in power supply, pulse generator, pulser
switches, 8 bits data switches, logic probe, 8 bits LED display.
Theory:
The availability of a large variety of codes for the same discrete elements of information results
in the use of different codes by different digital system. It is sometimes necessary to use the
output of one system as the input to another. A conversion circuit must be inserted between the
two systems if each uses different code for the same information. Thus, a code converter is a
circuit that makes the two systems compatible even though each uses a different binary code.
BCD is an abbreviation for binary-coded decimal. Binary codes for decimal digits require a
minimum of four bits. The BCD code expresses each digit in a decimal number by its nibble
equivalent. Weights are assigned to binary bits according to their positions. The weights in the
BCD codes are 8, 4, 2, and 1.
For example, the bit assignment 0110 can be interpreted by the weights to represent the decimal
digit 6 because (0 × 8) + (1 × 4) + (1 × 2) + (0 ×1) = 6. Table 7.1 shows BCD code.
The excess-3 code is an important 4-bit code used with BCD numbers. To convert any decimal
number in to its excess-3 form, add 3 to each decimal digit, and then convert the sum to a BCD
number. To convert decimal 5 to an excess-3 number, first add 3 to decimal digit:
5
+3
8
8 = 1000
To convert BCD to Excess-3, add 0011 to BCD code. Refer fig 7.1 and table 7.1.
Table 7.1
Object: To study and verify BCD to Excess-3 code conversion circuit and prove its truth table.
Apparatus Required:
B0 E0
B1 E1
B2 E2
B3 E3
Decimal B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Table 7.2
1. Connect +5 V and ground to their indicated position on DL07 Experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Connect inputs B0, B1, B2, B3 as per truth table 7.2 to BCD to Excess-3 code
converter as shown in figure 7.1
3. Switch ON the power supply.
4. Observe output E0, E1, E2, E3 on multi-meter or on LED display of Digital Lab
7211.
5. Repeat above steps for remaining of inputs and prove truth table.
Datasheet:
7404
7432 7408
Introduction:
DL08 is a Binary Adder-Subtractor experiment board. This experiment board has been designed
to study Binary adder and subtractor circuits. It can be used as stand-alone unit with external
power supply or can be used with Digital Lab 7211 which has built in power supply, pulse
generator, pulser switches, 8 bits data switches, logic probe, digital display, 8 bits LED display.
Theory:
Half Adder:
The combinational circuit that performs the addition of two bits is called a half adder. This
circuit has two binary inputs and two binary outputs. The input variable X, Y designate the
augends and addend bits, the output variables Sh, Ch produces the sum and carry. The logic
diagram and truth table are shown in experiment section. The Boolean equation is
Sh = X’.Y +X.Y’= XY
Ch = X.Y
Full Adder:
The circuit that performs the addition of three bits (two significant bits and a previous carry)
is called a full adder. It consists of three inputs X, Y, Z. Two of the input variable, denoted by
X and Y, represents the two significant bits to be added. The third input, Z, represents the
carry from the previous lower significant position. The output Sf gives the value of the least
significant bit of sum and Cf gives the output carry. The logic diagram for 3-bit full adder is
shown in Experiment section.
The full adder introduced above forms the sum of two bits and a previous carry. Two binary
numbers of n bits each can be added in parallel by means of Binary parallel adder. Consider
two 2 bit numbers Y0 X0, Y1 X1
Y0 X0 Y0 X0
+ Y1 X1 = Y1 X1
SUM C0 S1 S0
It can also be constructed with two full adders in cascade, with the output carry from one full
adder connected to the input carry of the next full adder. An n bit parallel adder requires n full
adder.
The truth table and logic diagram for 2 bit binary parallel adder is shown in experiment section.
A half subtractor is a combinational circuit that subtracts two bits and produces their difference .It
has two inputs X, Y. X is minuend and Y is subtrahend. The output bits are designated by Bh, Dh.
Dh is difference bit and Bh is borrow bit (generates the binary signal that informs the next stage
that a 1 has been borrowed).The logic diagram and truth table for 2 bit Half subtractor is shown
in Experiment section.
Dh =X’Y+XY’= XY
_
Bh = XY
Object: To study and verify truth table for the following digital circuits:
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
X
X Y Ch Sh S
h
Y
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0 C
h
X Y Z Cf Sf
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1 Z
0 1 1 1 0 S
f
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0 C
h
1 1 1 1 1 C
f
S0
X1
C0
Y0
S1
Y1
Y0 X0 Y1 X1 C0 S1 S0
0 0 0 1 0 0 1
0 1 0 1 0 1 0
0 1 1 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 1 0 1
X
D
h
Y X Y Bh Dh
0 0 0 0
0 1 1 1
1 0 0 1
B
h 1 1 0 0
7432 7408
7404
Introduction:
DL09 is an Encoder-Decoder experiment board. This experiment board has been designed to
study 8 to 3 line Encoder and 3 to 8 Line Decoder circuit and verify their truth table. It can be
used as stand-alone unit with external power supply or can be used with Digital Lab 7211 which
has built in power supply, pulse generator, pulser switches, 8 bits data switches, logic probe,
digital display, 8 bits LED display.
Theory:
Discrete quantities of information are represented in digital systems with binary codes. 2 n distinct
elements can be represented by a binary code of n bits. An encoder has 2n input lines and n output
lines. The output lines generate the binary code for the 2n input variables.
Fig 9.1 shows 8 to 3 line encoder. It consists of eight inputs D0-D7, and three outputs X, Y, Z that
generates the corresponding binary number. X is MSB. It is constructed with OR gates whose
inputs can be determined from the truth table 9.1.
The encoder in fig 9.1 assumes that only one input line can be equal to 1 at any time. The circuit
has eight inputs and could have 28 = 256 possible input combinations. Only eight of these
combinations have been considered. The other input combinations are don’t-care conditions.
A decoder is a digital function that produces a reverse operation from that of an encoder. A
decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. Fig 9.2 shows 3 to 8 line decoder. The three inputs X, Y, Z
are decoded in to eight outputs D0-D7, each output representing one of the minterms of the three
input variables. The three inverters provide the complement of the inputs and each one of the
eight AND gate generates one of the minterms. Truth table 9.2 shows different input
combinations for 3 to 8 line decoder.
Object: To study the following circuit and verify their truth table.
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
D0
D1 X
D2
D3
Y
D4
D5
D6
Z
D7
Fig 9.1
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Table 9.1
D1
Z
D2
Y D3
D4
X
D5
D6
D7
Fig 9.2
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Table 9.2
Procedure:
1. Connect +5V and ground to their indicated position on DL09 from external DC
power supply or from DC power block of Digital Lab 7211.
2. Connect inputs D0-D7 as per truth table 9.1 to 8 to 3 line encoder circuit as shown in
fig 9.1
3. Switch ON the power supply.
4. Observe output X, Y, Z on multi-meter or on LED display of Digital Lab 7211 and
prove truth table.
5. Connect inputs X, Y, Z as per truth table 9.2 to 3 to 8 line decoder circuit of fig 9.2
6. Observe output D0-D7 on multi-meter or on LED display of Digital Lab 7211 and
prove truth table.
7. Repeat above steps for remaining input.
7432
7411
Introduction:
Theory:
Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. There are 2n input lines and n selection lines
whose bit combinations determine which input is selected.
A 4 to 1 line multiplexer is shown in fig 10.1. Each of the four input lines, D0 to D3 is applied to
one input of an AND gate. Selection lines S1, S0 are decoded to select a particular AND gate.
When S1, S0 = 10. The AND gate associated with input D2 has two of its inputs equal to 1 and
third input connected to D2. The other three AND gates have at least one input equal to 0, which
makes their output equal to 0.The OR-gate output is now equal to the value of D2, thus providing
a path from the selected input to the output.
A multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output line. Whenever any input is selected which is in form of clock
pulse all other inputs should be at zero level i.e. logic 0.
A de-multiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of a specific output line is controlled
by the bit values of n selection lines. 1to 4 line de-multiplexer is shown in fig 10.2 The single
input variable D has a path to all four outputs, but the input information is directed to only one of
the output lines, as specified by the binary value of the two selection lines S1 and S0. If the
selection lines S1 S0 = 10 output D2 will be same as the input value D, provided D =0 while all
other outputs are maintained at 1. For D=1 all outputs are at high level. Clock pulse given to D
input can be obtained at output lines through selection lines S1 S0.
Table 10.1 and 10.2 shows truth table for 4 to 1 line multiplexer and 1 to 4 line de-multiplexer.
Object: To study the following circuit and verify their truth table.
• 4 to 1 line multiplexer.
• 1 to 4 line de-multiplexer
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
D0
D1
D2
D3
S1
S0
Fig 10.1
D0 D1 D2 D3 S1 S0 Z
1 0 1 0 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 1
1 0 1 0 1 1 0
Table 10.1a
D0
D1
D2
S1 D3
S0
D
Fig 10.2
D S1 S0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Table 10.2 a
D S1 S0 D0 D1 D2 D3
I 0 0 I 1 1 1
I 0 1 1 I 1 1
I 1 0 1 1 I 1
I 1 1 1 1 1 I
I (Clock Pulse of 1 KHz)
Table 10.2 b
1. Connect +5 V and ground to their indicated position on DL10 from external DC power
supply or from DC power block of Digital Lab 7211.
2. Switch ON the power supply.
3. Connect inputs D0-D3 as per truth table 10.1a to 4 to 1 line multiplexer. circuit as
shown in fig 10.1
4. Observe output, Z on multi-meter or on LED display of Digital Lab 7211 and prove
truth table.
5. Repeat step 3 and 4 for table 10.1 b. Observe results on oscilloscope
6. Connect input D as per truth table 10.2a to 1 to 4 line de-multiplexer circuit as shown
in fig 10.2
7. Observe output D0-D3 on multi-meter or on LED display of Digital Lab 7211 and
prove truth table.
8. Repeat steps 2 & 3 for table 10.2 b and observe output on oscilloscope.
7404
7432
7411 7412
Introduction:
DL11 is a Flip-Flop experiment board. All Flip-flops are incorporated on a single board for
verification of their truth table and comparison. This experiment board has been designed to study
R-S, J-K, D, T flip-flops. It can be used as stand-alone unit with external power supply or can be
used with Digital Lab 7211 which has built in power supply, pulse generator, pulser switches, 8 bits
data switches, logic probe, digital display, 8 bits LED display.
Theory:
Flip-flops are binary cells capable of storing one bit of information. A Flip-flop has two outputs,
one for the normal value and one for complement value of the bit stored in it. A flip-flop circuit can
maintain a binary state indefinitely (as long as power is supplied to the circuit) until directed by an
input signal to switch states.
Clocked RS Flip-flop:
Clocked RS Flip-flop shown in fig 11.1 consists of two NOR gates and two AND gates. The input
S and R are set and reset input and output Q and Q’ are normal and complement output. The input
CP is input for giving clock pulse. Flip-flop will change state only when CP goes from 0 to 1.
The output of two AND gates remain at 0 as long as the clock pulse CP is 0, regardless of the S and
R input values. When the clock pulse goes to logic high level i.e. 1, information from the S and R is
allowed to reach the basic flip-flop. The set state is reached with S=1, R= 0, and CP=1.( for set
state, Q =1 and for reset state, Q=0 )To change to the clear state, the inputs must be S= 0, R=1,
CP=1. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily
go to 0. When the pulse is removed, the state of flip-flop is indeterminate, i.e., either state may
result, depending on whether the set or the reset input of the basic flip-flop remains a 1 longer
before the transition to 0 at the end of the pulse. The characteristics table is shown in experiment
section along with logic diagram.
D Flip-flop:
The logic symbol and characteristics table for D flip-flop is shown in fig 11.2. It has only one data
input (D) and clock input (CP). The outputs are labelled Q and Q’. The data (0 or 1) at the input D
is delayed one clock pulse from getting to output Q. SD and CD are active low input (Negative
edge trigger) to set and reset the flip-flop i.e. these inputs will be effective when logic 0 is applied.
A D Flip-flop is a bi-stable circuit whose D input is transferred to the output after a clock pulse is
received.
J-K Flip-flop:
A J-K flip-flop is refinement of R-S flip-flop in that the indeterminate state of the RS type is
defined in the JK type. Inputs J, K is used to set and clear the flip-flop. When both J, K are high
simultaneously, the flip-flop switches to its complement state, that is, if Q = 1, it switches to Q= 0,
and vice versa. A CP signal which remains a 1(While J=K=1) after the outputs have been
complemented once will cause repeated and continuous transitions of the output. To avoid this
undesirable operation, the clock pulse must have a time duration which is shorter than the
propagation through the flip-flop.
The JK flip-flop shown above behaves like an R-S flip-flop, except when both J and K are 1, the
clock pulse is transmitted through one AND gates only- the one whose input is connected to the
flip-flop output which is presently equal to 1 .Thus, if Q=1, the output of the upper AND gate
become 1 upon application of a clock pulse, and the flip-flop is cleared .If Q’ =1, the output of
lower AND gate becomes a 1 and the flip-flop is set. In either case, the output state of the flip-flop
is complemented.
T Flip-flop:
The T flip-flop is a single input version of the JK flip-flop. As shown below, the T flip-flop is
obtained from a JK type if both inputs are tied together .The designation T shows ability of flip-flop
to toggle. Regardless of the present state of the flip-flop, it assumes the complement state when the
clock pulse occurs while input T is logic 1.
• R-S
• D
• J-K
• T
Apparatus Required:
R-S Flip-flop
Fig 11.1
CP Q S R Q (t+1)
Transition
0→1 0 0 0 0
0→1 0 0 1 0
0→1 0 1 0 1
0→1 0 1 1 Indeterminate
0→1 1 0 0 1
0→1 1 0 1 0
0→1 1 1 0 1
0→1 1 1 1 Indeterminate
CP Q J K Q (t+1)
Transition
1→0 0 0 0 0
1→0 0 0 1 0
1→0 0 1 0 1
1→0 0 1 1 1
1→0 1 0 0 1
1→0 1 0 1 0
1→0 1 1 0 1
1→0 1 1 1 0
Fig 11.3 J-K Flip-flop
CP Q T Q(t+1)
Transition
1→0 0 0 0
1→0 0 1 1
1→0 1 0 1
1→0 1 1 0
1. Connect +5 V and ground to their indicated position on DL11 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Switch on the power supply.
3. Connect inputs 0, 0, 0 to S, R, CP pins of R-S flip-flop.
4. Measure output Q (Present state).
5. Connect input 1 to CP.
6. Measure output Q .It is next state Q (t+1) for input 0, 0.
7. Repeat above steps for remaining inputs. (Before transition of clock pulse from 0 to 1, output
is present state and after transition output is next state )
8. Connect 1, 0 to pins SD and CD of D flip-flop to clear the output Q.
9. Connect 1, 1 to pins SD and CD of D flip-flop.
10. Connect inputs as per truth table for D flip-flop and prove truth table.
11. Connect output Q’ to Input D of D Flip-flop.
12. Connect a TTL clock pulse of 2 KHz to CP input.
13. Observe output Q on Oscilloscope. It will be 1 KHz.
14. Connect 1, 0 to pins SD and CD of JK flip-flop to clear the Output Q.
15. Repeat steps of D flip-flop to prove truth table of JK flip-flop.
16. Connect input 1, 1 to J, K pins of JK flip-flop and 1, 1 to SD, CD.
17. Connect a TTL clock pulse of 2 KHz to CP input.
18. Observe output Q on Oscilloscope. It will be 1 KHz.
19. Repeat above steps to prove truth table for T flip-flop.
7402
7408
7476
Vcc =+5 V, CK= clock input (active low), PR= to set output (active low), CK= to clear output
(active low), Q & Q’ are normal and complement output.
Introduction:
DL12 is a Shift Register experiment board. This experiment board has been designed to study 4
Bit Serial in-Parallel out Shift Register and verify truth table. It can be used as stand-alone unit
with external power supply or can be used with Digital Lab 7211 which has built in power
supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display, 8 bits
LED display.
Theory:
A register is a group of binary storage cells suitable for holding binary information. A group of
flip-flops constitute a register, since each flip-flop is a binary cell capable of storing one bit of
information. An n-bit register has a group of n flip-flops and is capable of storing any binary
information containing n bits. In addition to the flip-flops, a register may have combinational
gates that perform certain data processing tasks like when and how new information is transferred
in to the register.
A register capable of shifting its binary information either to the right or to the left is called a
shift register. The logical configuration of a shift register consists of a chain of flip-flops
connected in cascade, with the output of one flip-flop connected to the input of next flip-flop. All
flip-flops receive a common clock pulse, which causes the shift from one stage to the next.
The 4 bit serial in –parallel out shift register is shown in fig 12.1.The Q output of a given flip-
flop is connected to the D input of the flip-flop at its right. Each clock pulse shifts the contents of
the register one bit position to the right. The serial input determines what goes into the leftmost
flip-flop during the shift. The serial output is taken from the output of rightmost flip-flop prior to
the application of pulse. The register shifts its contents with every clock during the positive edge
of the pulse transition. There are parallel outputs Q0-Q3 with Q3 as LSB. MC is active high
clock input i.e. data will shift to right on positive edge of clock pulse.
MR is master reset input (active low i.e. negative edge trigger) to flip-flops to reset or clear
output Q0-Q3 globally.
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
MR MC Input Q0 Q1 Q2 Q3
0 1 1 or 0 0 0 0 0
1 0 1 1 1 0 0 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 1 0
1 0 1 0 0 1 0 1
0 1 = transition from logic 1 to logic 0
(Positive Edge trigger)
Table 12.1
1. Connect +5 V and ground to their indicated position on DL12 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Switch ON the power supply.
3. Clear the outputs Q0-Q3 by Connecting + 5V (logic 1) to MC input and ground or 0V
(logic 0) to MR input of shift register of fig 12.1 as per truth table 12.1.
4. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 0.
5. Connect logic 1 to MR input and logic 0 to MC input.
6. Connect input 1 to shift register as per truth table 12.1
7. Connect logic 1 to MC input.
8. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 1 0 0 0.
9. Repeat step 5, 6, 7 for different inputs as per truth table 12.1 and verify truth table.
SN74164
Function Table :
Introduction:
DL13 is a 4-Bit Synchronous Binary Counter experiment board. This experiment board has been
designed to study 4 Bit Synchronous Binary Up Counter and verify truth table. It can be used as
stand-alone unit with external power supply or can be used with Digital Lab 7211 which has built
in power supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display,
8 bits LED display.
Theory:
A sequential circuit that goes through a prescribed sequence of states upon the application of input
pulses is called a counter. A counter that follows the binary sequence is called a binary counter. An n-
bit binary counter consists of n flip-flops and can count in binary from 0 to 2n -1. State transitions in
clocked sequential circuits occur during a clock pulse; the flip-flops remain in their present states if
no pulse occurs. Counters come in two categories: ripple counters and synchronous counters. In a
ripple counter, the flip-flop output transition serves as a source (i.e. clock) for triggering other flip-
flops, i.e. CP inputs of all flip-flops (except the first) are triggered not by the incoming pulses but
rather by transition that occurs in other flip-flops. In a synchronous counter, the input pulses are
applied to all CP inputs of flip-flops.
Observe truth table of 4 bit synchronous binary Up counter as shown in fig 13.1, the flip-flop in the
lowest-order position is complemented with every pulse so J and K inputs must be maintained at
logic 1. A flip-flop in any other position is complemented with a pulse provided all the bits in the
lower-order position are equal to 1, because the lower-order bits (when all ones) will change to 0’s on
the next count pulse. Refer truth table. The binary count dictates that the next higher-order bit be
complemented.
If the present state of a 4-bit counter is Q3Q2Q1Q0 =0011, the next count will be 0100. Q0 is always
complemented.Q1 is complemented because the present state of Q0 =1. Q2 is complemented because
the present state of Q1Q0=11 but Q3 is not complemented because the present state of Q2Q1Q0 =011,
which does not give an all 1’s condition.
The CP terminal of all flip-flops is connected to a common clock pulse source. The first stage Q0 has
its J and K equal to1. The other J and K inputs are equal to 1 if all previous low order bits are equal to
1 and the count is enabled. The Chain of AND gates generate the required logic for the J and K inputs
in each stage.
As shown in figure MS is master set input which sets output of flip-flops to logic 1, when
connected to logic 0. MCD is master reset input which resets or clears output when connected to
logic 0. Q3, Q2, Q1, Q0 are outputs of flip-flops where Q0 is LSB.CP is clock pulse input. It will
trigger flip-flops on negative edge i.e. +5 V to 0 transition (10).
Apparatus Required:
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
Fig 13.1
MS MCD CP Q3 Q2 Q1 Q0
0 1 0 1 0 0 0 0
1 1 1 10 0 0 0 1
2 1 1 10 0 0 1 0
3 1 1 10 0 0 1 1
4 1 1 10 0 1 0 0
5 1 1 10 0 1 0 1
6 1 1 10 0 1 1 0
7 1 1 10 0 1 1 1
8 1 1 10 1 0 0 0
9 1 1 10 1 0 0 1
10 1 1 10 1 0 1 0
11 1 1 10 1 0 1 1
12 1 1 10 1 1 0 0
13 1 1 10 1 1 0 1
14 1 1 10 1 1 1 0
15 1 1 10 1 1 1 1
Truth Table 13.1
Q0 is LSB
1. Connect +5V and ground to their indicated position on DL13 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Switch ON the power supply.
3. Connect logic 1(+5 V) to CP and MS input.
4. Clear the outputs Q0-Q3 by Connecting logic 0 (Gnd or 0V) to MCD input of 4 bit
synchronous counter of fig 13.1 as per truth table.
5. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 0.
6. Connect logic 1 to MCD and MS inputs.
7. Connect logic 1 to CP input.
8. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 0.
9. Connect logic 0 to CP input.
10. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 1.
11. Make CP terminal to transit from 1 to 0 (10) and observe next state of counter as
shown in truth table for counter and prove truth table.
12. Repeat step10 until last state 1111 appear.
7476
Note: Pull up resistance of 1k is required in Open collector output ICs to get output.
Introduction:
DL14 is a 4-Bit Binary Ripple Counter experiment board. This experiment board has been designed
to study 4 Bit Binary Ripple Up/Down Counter and verify truth table. It can be used as stand-alone
unit with external power supply or can be used with Digital Lab 7211 which has built in power
supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display, 8 bits
LED display.
Theory:
A sequential circuit that goes through a prescribed sequence of states upon the application of input
pulses is called a counter. A counter that follows the binary sequence is called a binary counter. An
n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n -1. State transitions in
clocked sequential circuits occur during a clock pulse; the flip-flops remain in their present states if
no pulse occurs. Counters come in two categories: ripple counters and synchronous counters. In a
ripple counter, the flip-flop output transition serves as a source (i.e. clock) for triggering other flip-
flops, i.e. CP inputs of all flip-flops (except the first) are triggered not by the incoming pulses but
rather by transition that occurs in other flip-flops. In a synchronous counter, the input pulses are
applied to all CP inputs of flip-flops.
A binary ripple up counter as shown in fig 14.1 consists of a series connection of complementing J-K
flip-flops, with the normal output of each flip-flop connected to the CP input of the next higher-order
flip-flop. It will count from 0000 to 1111. The LSB flip-flop receives the incoming count pulses. The
lowest order bit Q0 must be complemented with each count pulse. Every time Q0 goes from 1 to 0, it
complements Q1.Every time Q1 goes from 1 to 0, it complements Q2 and so on. The flip-flop change
one at a time in rapid succession, and the signal propagates through the counter in a ripple fashion.
Ripple counters are also called asynchronous counter.
Fig 14.1
In binary down counter as shown in fig 14.2 complement output of each flip-flop is connected to the
CP input of the next higher-order flip-flop. It will count from 1111 to 0000. Lowest order bit must be
complemented with every count pulse. Any other bit in the sequence is complemented if its previous
lower-order bit goes from 0 to 1.
If clock pulse of frequency f is applied to CP terminal of LSB flip-flop then output frequency at Q0,
Q1, Q2, Q3 will be f /2, f/4, f/ 8, f/16 as shown in figure SD is set input which sets output of flip-
flops to logic 1, when connected to logic 0 (Gnd.). CD is clear/reset input which resets or clears output
when connected to logic 0. Q3, Q2, Q1, Q0 are outputs of flip-flops where Q0 is LSB.CP is clock pulse
input. It will trigger flip-flops on negative edge, i.e. +5 V to 0 transition (10).
Apparatus Required:
1. Digital board DL14.
2. DC Power Supply +5 V from external source or 7211 Digital lab.
3. Oscilloscope, Digital Multi-meter or Digital Lab 7211.
Logic Diagram & Truth Table: (Logic 1= +5V & Logic 0= GND)
Fig 14.3
Q to SD CD CP Q3 Q2 Q1 Q0
CP
0 short 1 0 1 0 0 0 0
1 short 1 1 10 0 0 0 1
2 short 1 1 10 0 0 1 0
3 short 1 1 10 0 0 1 1
4 short 1 1 10 0 1 0 0
5 short 1 1 10 0 1 0 1
6 short 1 1 10 0 1 1 0
7 short 1 1 10 0 1 1 1
8 short 1 1 10 1 0 0 0
9 short 1 1 10 1 0 0 1
10 short 1 1 10 1 0 1 0
11 short 1 1 10 1 0 1 1
12 short 1 1 10 1 1 0 0
13 short 1 1 10 1 1 0 1
14 short 1 1 10 1 1 1 0
15 short 1 1 10 1 1 1 1
Procedure:
1. Connect +5V and ground to their indicated position on DL14 experiment board from
external DC power supply or from DC power block of Digital Lab 7211.
2. Switch ON the power supply.
UP counter
3. Connect normal output of flip-flop to CP input of next flip-flop.
4. Connect logic 1(+5 V) to CP and SD input.
5. Clear the outputs Q0-Q3 by Connecting logic 0 (Gnd or 0V) to CD inputs of fig 14.3.
6. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 0.
7. Connect logic 1 to MCD and MS inputs.
8. Give Logic 1 to 0 transition (+5 V to Gnd.) to CP input.
9. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 0 0 0 1
10. Repeat step 8 and observe output and verify truth table for fig 14.1.
Down counter
11. Connect complement output of flip-flop to CP input of next flip-flop.
12. Connect logic 1(+5 V) to CP and CD input.
13. Set the outputs Q0-Q3 by Connecting logic 0 (Gnd or 0V) to SD inputs fig 14.3
14. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 1 1 1 1
15. Connect logic 1 to CD and SD inputs.
16. Give Logic 1 to 0 transition (+5 V to Gnd) to CP input.
17. Observe output on multi-meter or on LED display of Digital Lab 7211.
It will be 1 1 1 0
18. Repeat step 16 and observe output and verify truth table for fig 14.2
19. Connect clock pulse of 3 KHz to CP input and observe outputs on oscilloscope.
7476
Note: Pull up resistance of 1k is required in Open collector output ICs to get output.
List of Components:
Components Quantity
Logic Diagrams:
X X X
O O O
Y Y Y
X X
O O IN OUT
Y Y
Input Output
X O
0 1
1 0
NOT Gate
Procedure:
AND gate
1. Connect +5 V to pin no. 14 of IC 7408 and connect ground to pin no. 7 (refer IC pin
diagram)
2. Apply 0 (0 V) to pin no. 1 and 2 of IC 7408 shown in figure as per truth table.
3. Connect output of AND gate i.e. pin no. 3 to input of logic probe or 8 bits LED
display.
4. Switch ON the instrument.
5. Observe output of gate on 8 bits LED display.
6. Outputs can also be observed on oscilloscope.
7. Repeat steps 2, 3, and 4 for different input combination.
8. Verify truth table.
NAND gate
1. Connect +5 V to pin no. 14 of IC 7400 and ground to pin no. 7 (Refer IC pin
diagram) :
2. Apply 0 (0 V) to pin no. 1 & 2 of IC 7400 shown in figure as per truth table.
3. Connect output of NAND gate i.e. pin no.3 to input of logic probe or 8 bits LED
display.
4. Switch On the instrument.
5. Observe output.
6. Repeat Step 2, 3, and 4 for different input combinations.
NOR gate
1. Connect + 5 V to pin no. 14 of IC 7402 and connect ground to pin no. 7
2. Apply 0 (0V) to pin no. 2 and 3 of IC 7402 as per truth table.
3. Connect output of NOR gate i.e. pin no. 1 to input of logic probe or 8 bits LED
display.
4. Repeat step 4, 5, 6 of NAND gate.
EX-OR gate
1. Connect +5V to pin no. 14 of IC 74136 and connect ground to pin no.7
2. Apply 0 (0V) to pin no. 1 and 2 of IC 74136 as per truth table.
3. Connect output of EX-OR gate i.e. pin no. 3 to input of logic probe or 8 bits LED
display.
4. Repeat step 4, 5, and 6 of NAND gate.
NOT gate
1. Connect +5 V to pin 14 and ground to pin no.7 of IC 7404.
2. 0 (0V) to pin no. l of IC 7404 as per truth table.
3. Observe output on 8 bits LED display or Logic Probes.
• Half Adder
• Full Adder
• Two bit binary parallel adder,
.
Half Adder:
Component Quantity
Logic Diagram:
Truth Table:
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Procedure:
Logic diagram:
Component Quantity
Truth Table:
Input Output
Input l Input 2 Sum
Carry Carry
X Y Ci C0 S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 I 1
Component Quantity
Logic Diagram
S.N A1 A0 B1 B0 C01 S1 S0
1 0 0 0 1 0 0 1
2 0 1 0 1 0 1 0
3 0 1 1 1 1 0 0
4 1 0 1 0 1 0 0
5 1 0 1 1 1 0 1
Procedure:
1. Make connections as shown in figure.
2. Connect +SV to pin no. 14 and ground to pin no.7 of ICs.
3. See IC Pin diagram.
4. Connect 0 (OV) and 1(+5 V) to inputs A1, AO, B1, BO of adder shown as per truth
table
5. Switch ON the instrument.
6. Observe outputs S 1, SO and CO on 8 bits LED display.
7. Outputs can also be observed on oscilloscope.
8. Repeat steps 4 and 6 for other input combinations.
9. Verify truth table.
Full adder can be implemented using two half Adder. Adders are studied and truth tables are
verified.
Object: To study 2 bit binary subtractor (Half subtractor) List of components required:
Component Quantity
Logic Diagram:
Truth Table:
Procedure:
Components Quantity
Logic Diagram:
Truth Table:
Component Quantity
Logic Diagram:
Truth Table:
Components Quantity
Logic Diagram:
Truth Table:
B3 B2 B1 BO E3 E2 E1 EO
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 l 1 1 0
1 1 0 0 1 1 1 1
Component Quantity
Logic Diagram:
Truth Table:
Present
Input l Input 2 Next State
state
Q S R Q(t+l)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 In determinant
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 In determinant
Clocked RS Flip-Flop
Q D Q (t+1)
0 0 0
0 1 1
1 0 0
1 1 1
D Flip-Flop
Present
Input Next state
state
Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
T Flip-Flop
Present
Input Input Next State
state
Q J K Q(t+l)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
J K Flip-flop
1. Make connections as shown in figure for each flip-flop one by one. (Refer pin
diagram of ICs)
2. Connect +5 V to pin no. 14 and ground to pin no. 7 of ICs.
3. Connect pulser switch output (¥) to clock input CP of flip-flop
4. Connect input 1 or 0 to inputs of flip-flops as per truth table shown.
5. Switch ON the instrument.
6. Press Pulser switch to get output.
7. Observe outputs on 8 bits LED display or logic probe.
8. Repeat above steps 4, 5 and 6 for other input combinations.
9. Verify truth tables.
Observations:
Components Quantity
Resistance 330 S2 1
Crystal 1 MHz 1
Capacitor
0.00 1 MF 1
100 PF 1
IC 7404Hex Inverter 1
Logic Diagram:
Procedure:
Crystal oscillator frequency depends solely on crystal dimensions and independent of any
other parameter.
Components Quantity
Logic Diagram:
Procedure:
A4 A3 A2 A1 A4 A3 A2 A1
0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0
0 0 1 0 1 1 0 1
0 0 1 l 1 1 0 0
0 1 0 0 1 0 1 1
0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 0 0
1 0 0 0 0 1 1 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 1 1
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 1 0 0 0 0
Components Quantity
IC 7474 D flip-flop 2
IC 7408 2 input AND Gate 2
IC7404 Hex Inverter 2
Logic Diagram:
Truth Table:
Flip-flop
AND gate required for
Sequence Output
output
A B C E
1 0 0 0 0 A'E'
2 1 0 0 0 AB'
3 1 1 0 0 BC'
4 1 1 1 0 CE'
5 1 1 1 1 AE
6 0 1 1 1 AT
7 0 0 1 1 BT
8 0 0 0 1 C'E
Result:
Components Quantity
IC 7474D flip-flop 1
Logic Diagram:
Truth Table:
A B C D
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
Flip-flops Output Table
Procedure:
Component Quantity
Logic Diagram:
Truth Table:
D0 D1 D2 D3 D4 DS D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Components Quantity
Logic Diagram:
Truth Table:
x y z D0 D1 D2 D D4 DS D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 1 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Component Quantity
Procedure:
Truth Table:
E S0 S1 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 I 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Procedure:
Components Quantity
Logic Diagram:
Procedure:
Pulse width at
S.No Capacitance
terminal 6
1 0 MF
2 0.001 MF
3 0.022 MF
4 0.033 MF
Result:
The width of output at point 3 is longer than that at A because it takes capacitor C time to
charges up to the threshold voltage of gate 2.
Object: To study method of interfacing CMOS logic family with TTL logic family.
Introduction:
The CMOS logic family can be operated at the same power supply voltage as TTL but with a
sacrifice in speed. To operate the CMOS family at its maximum speed requires operation with
Vdd equal to 15V. To interface with TTL requires a level shifting device.
CMOS logic elements can easily drive other CMOS elements because of their high input
resistance. However, most CMOS logic elements cannot provide the current required by a
single load of the medium-power TTL series. To satisfy this current requirement requires high
current CMOS buffer element.
Component Quantity
Logic Diagram:
Result:
7400 7402
Quad 2-Input NAND Gate Quad 2-Input NOR Gate
7404 7406
HEX Inverter HEX Inverter Buffer/Driver
(with open-collector high voltage output)
7408 7411
Quad 2-Input AND Gate Triple 3-Input AND Gate
74107 74LS136
Dual JK Flip-Flop Quad 2-Input EXCLUSIVE-OR Gate
4001B 4050B
Quad 2-Input NOR Gate HEX Non-Inverting Buffer