Analog Integrated Circuit
Analog Integrated Circuit
Analog Integrated Circuit
Integrated
Circuits
Chapman & Hall
Solid State Science and Engineering Series
Michael N. Kozicki, Series Editor
Arizona State University
Edwin W.Greeneich
Associate Professor
Department of Electrical Engineering
Arizona State University
AII rights reserved . No part of this book covered by the copyright hereon may be reproduced or used in
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2 3 4 5 6 7 89 10 XXX 01 00999897
Page
Preface ix
v
vi Contents
Linearization 186
Applications 188
CMOS Transconductance Amplifier 191
Problems 194
References 201
4 Feedback and Compensation of Feedback Amplifiers 203
4.1 Basic Feedback Concepts 203
Gain Stabilization 204
Reduction in Distortion 205
Increased Bandwidth 206
4.2 Feedback Circuit Example 208
Input Resistance 211
Output Resistance 212
4.3 Feedback Configurations 213
Series Voltage 215
Shunt Voltage 223
Series Current 230
Shunt Current 239
4.4 Dual-Loop Feedback 244
Series Current-Shunt Voltage 247
Series Voltage-Shunt Current 258
4.5 Stability of Feedback Amplifiers 264
Gain and Phase Relationship 264
4.6 Compensation of Feedback Amplifiers 270
Compensation Methods 271
Problems 284
References 294
5 Translinear Circuits 295
5.1 Translinear Circuit Classes 295
Transconductance Linear with Current 295
Transconductance Linear with Voltage 302
5.2 Analog Functions with Translinear Circuits 305
Vector Magnitude 305
Two-Quadrant Squarer 306
Absolute Value 308
Analog Multipliers 309
5.3 Trigonometric Functions with Translinear Circuits 322
5.4 Gilbert Gain Cell 327
Problems 328
References 335
Index 337
PREFACE
Analog Integrated Circuits deals with the design and analysis of modem
analog circuits using integrated bipolar and field-effect transistor technologies.
This book is suitable as a text for a one-semester course for senior level or
first-year graduate students as well as a reference work for practicing engin-
eers. Advanced students will also find the text useful in that some of the
material presented here is not covered in many first courses on analog circuits.
Included in this is an extensive coverage of feedback amplifiers, current-mode
circuits, and translinear circuits. Suitable background would be fundamental
courses in electronic circuits and semiconductor devices.
This book contains numerous examples, many of which include commercial
analog circuits. End-of-chapter problems are given, many illustrating practical
circuits.
Chapter 1 discuses the models commonly used to represent devices used in
modem analog integrated circuits. Presented are models for bipolar junction
transistors, junction diodes, junction field-effect transistors, and metal-oxide-
semiconductor field-effect transistors. Both large-signal and small-signal
models are developed as well as their implementation in the SPICE circuit-
simulation program.
The basic building blocks used in a large variety of analog circuits are
analyzed in Chapter 2; these consist of current sources, dc level-shift stages,
single-transistor gain stages, two-transistor gain stages, and output stages. Both
bipolar and field-effect transistor implementations are presented.
Chapter 3 deals with operational amplifier circuits. The four basic op-amp
circuits are analyzed: (1) voltage-feedback amplifiers, (2) current-feedback
amplifiers, (3) current-differencing amplifiers, and (4) transconductance ampli-
fiers. Selected applications are also presented.
In Chapter 4 feedback amplifiers are discussed. A detailed analysis pro-
cedure for various feedback configurations is developed and numerous
examples of feedback circuits are presented. Stability considerations and
methods for compensation of feedback amplifiers are also discussed.
ix
x Preface
Chapter 5 deals with translinear circuits; these are circuits that exploit the
linear relationship between the transconductance of a transistor and either its
current or voltage. Applications of translinear circuits include implementation
of analog functions and generation of trigonometric functions. These circuits
find use in communications, signal processing, and control systems.
Chapter 1
In the analysis, design and simulation of integrated circuits, models are used
to represent the electrical behavior of the devices in the circuit. Consequently,
the accuracy to which the actual circuit performance is predicted depends
directly on the suitability and accuracy of the models used to represent the
devices. It is important that the circuit designer understand the limitations and
range of applicability of the device models and the approximations used in their
derivation.
In this chapter we discuss the models commonly used to represent devices
in analog integrated circuits: bipolar junction transistors, junction diodes, junc-
tion field-effect transistors, and metal-oxide-semiconductor field-effect transis-
tors. Included will be models as implemented in the circuit simulation program
SPICE.
Emitter
Metal
N + Burled leyer
p. Substrate
S 1
Figure 1-1 Cross-sectional view of an npn bipolar integrated-circuit transistor.
The active portion (also tenned the intrinsic portion) of the transistor is the
vertical N+ IP IN- layer structure shown beneath the emitter metallization. A
one-dimensional representation of this intrinsic device portion is shown in Fig.
1-2(a). Under nonnal operation, the emitter-base junction is forward biased and
the collector-base junction is reverse biased. In this configuration, carriers
(electrons for an npn transistor) are injected into the base by virtue of the
forward bias on the emitter junction. These carriers move by a combination of
drift and diffusion through the base to the collector junction, where, due to the
reverse bias on this junction, are swept into the collector region, giving rise to
a current in the collector. This current, originating in the emitter, is thus
controlled predominantly by the emitter-base junction bias and accounts for this
structure being an active (transistor) device.
Figure 1-2(b) shows the circuit symbol for an npn transistor and the sign
convention for voltages and currents. Under nonnal operation (in which the
device is operating in the forward-active region), Vbe is positive, Vbc is negative,
and currents flow in the directions depicted in the figure. A one-dimensional
representation of the intrinsic portion of a pnp transistor is shown in Fig. 1-2(c)
and its circuit symbol is illustrated in Fig. l-2(d). For apnp transistor operating
in the forward-active region, Vbe is negative, Vbc is positive, and currents flow in
the directions depicted.
A relatively simple, but yet adequate for many cases, large-signal model for
the bipolar transistor is the Ebers-Moll model [1]. It describes the transistor
1.1 Bipolar Junction Transistor 3
E E
emlner emlner
N+ p+
N" p'
C C
(a) (c)
c
r c
c
fc
Vbc + +
Vbc
+ +
B B
+ +
----+ +--
Ib Vbe Ib Vbe
fe fe
E E
(b) (d)
currents in terms of the two pn junction currents and their respective junction
voltages and is illustrated in Fig. 1·3. The emitter-base and collector-base
junction currents are given by
(1-1)
where hs and Ics are the reverse saturation currents of the emitter-base and
collector-base junctions, respectively and kT /q is the thermal voltage.
4 Chapter 1 - Models for Integrated-Circuit Devices
emitter collector
- c
E
I C
qVIE/kT qVa:/kT
IEF;IES(e -I) iCR;iCS(e -I)
<a)
V BE VFr:;
+ +
-
E
IE
URICR IlFI EF
-
C
I C
IB t B
<b)
Figure 1-3 (a) Emitter and collector junction currents used in the Ebers-Moll
model of the bipolar transistor. (b) Common-base Ebers-Moll static model of an
npn transistor.
The total collector current (Id is comprised of the collector junction current
(leR) and the fraction of the emitter junction current (lEF) reaching the collector.
This current arises from the carriers injected from the emitter into the base and
their subsequent transport through the base to the collector. This fraction is
denoted aF and represents the ratio of the collector to emitter current when the
transistor is operating in the normal (forward-active) mode of operation; that
is, with the emitter-base junction forward biased and the collector-base junction
reverse biased. Typical values for aF in modem integrated-circuit transistors are
0.98-0.995. With reference to the circuit model shown in Fig. 1-3(b), the
terminal collector current is
(1-3)
Likewise, the total emitter current (Id is comprised of the emitter junc-
tion current (hF) and the fraction aR of the collector junction current reaching
the emitter. aR represents the ratio of the emitter to collector current when
the transistor is operating in the inverse (reverse-active) mode of operation
(collector-base junction forward biased and emitter-base junction reverse
biased). Owing primarily to the large difference in the impurity doping
concentrations in the emitter and collector regions of the transistor, aR is
1.1 Bipolar Junction Transistor 5
smaller than CXF, with typical values ranging from 0.5 to 0.9. From Fig. 1-
3(b),
IE = IEF - cxRlcR (1-4)
Applying Kirchoff's current law for the base current (IB = IE - Ie) gives
IB = (1 - cxF)IEF + (1 - CXR)lCR (1-5)
It can be shown from reciprocity conditions applied to the emitter and
collector junctions [2] that
cxFIEs = CXR Ics = Is (1-6)
where Is the saturation current of the BJT and is given as
- qDBn~ AE
I s- (1-7)
QB
DB is the diffusion constant for minority carriers in the base (electrons for an
npn, holes for a pnp), ni is the intrinsic carrier concentration of the semicon-
ductor, AE is the area of the emitter-base junction, and QB is the number of
majority carrier charges per unit area in the base (holes for an npn, electrons
for a pnp). Typical values for Is in an integrated-circuit transistor range from
about 10 - 17 A for a small-geometry, low-current device to 10 - 15 A for a large device
such as might be used in the output stage where large currents are required.
Using Eq. (1-6) in Eqs. (1-3) and (1-4) gives for the Ebers-Moll equations:
Ie=!s(eqVBE'kT _l)_~(eqVBClkT -1) (1-8)
CXR
IE_Is
-- e
(qVBE/kT - 1) - I s (qVBclkT
e - 1) (1-9)
CXF
These equations describe the large-signal behavior of the bipolar transistor and,
as such, there is no restriction on either the magnitude or polarity of the
junction voltages. They can thus be used to describe transistor operation in
four regions of operation:
(i) Forward-active. Here, the emitter-base junction is forward biased (VBE posi-
tive for an npn, negative for a pnp) and the collector-base junction is reverse
biased (VBC negative for an npn, positive for a pnp). If the reverse bias on the
collector junction is at least several kT /q in magnitude, then the exp (qVBC /kT)
terms in Eqs. (1-8) and (1-9) are much smaller than - 1 and can be neglected.
This gives for forward-active region:
Ie = !s(eqVBE/kT - 1) +~ (1-10)
CXR
(1-11)
6 Chapter 1 - Models for Integrated-Circuit Devices
Equation (1-11) can be used in Eq. (1-10) to express the collector current
in terms of the emitter current:
(1-12)
where
( 1-13)
leo is the collector current obtained with the emitter open circuited (h = 0). At
room temperature (27"C), leo is small (typically in the range of 10 - 13 A-IO - 10 A) and
can usually be neglected. However, for silicon, leo doubles for about every 8°C
increase in temperature and so may not be negligible at high temperatures.
Normally in the forward-active mode the base-emitter bias is at least several
kT/q in value so that exp(qVsElkT) is »1. Neglecting the - 1 and Is terms in
Eqs. (1-10) and (1-11) gives
Ie = Is eqV'E/kT (1-14)
and
- -Is
IE -e
qVBElkT
(1-15)
CXF
(1-17)
(iii) Saturation. Here, both junctions are forward biased and hence both are
injecting carriers into the base. Each junction acts both as an emitter and
collector, and the net behavior can be described by a superposition of forward-
active and reverse-active modes.
1 .1 Bipolar Junction Transistor 7
For IVBEI ::::?>kT/q and IVBCI ::::?>kT/q, again neglecting the reverse leakage cur-
rent,
- I qVBElkT
I c- se - -Ise qVBclkT (l-18)
aR
( 1-19)
~R is the reverse common-emitter current gain, -IE lIB at VBE = 0 and is related
to the reverse common-base current gain UR as
UR
~R=- (1-26)
} - UR
12
I
Ib =100 I1A
10
8
7 80 I1A
fl 60 I1A
6
rr 40llA
4
If 20llA
2 I'
Ib = 0
o
-2
-1.0 -0.5 0.0 0.5 1.0
Vee (volts)
Figure 1-5 Simulated common-emitter output characteristics for an npn transistor
at 27° C. Device parameters are Is = 2 x 10 -16 A, JlF = 100, and JlR = 10.
1.1 Bipolar Junction Transistor 9
B o-----+---~----~
E
Figure 1-6 Common-emitter Ebers-Moll large-signal model of an npn transistor.
(1-27)
(1-28)
CjE (0) and CjC (0) are the values of the emitter-base and collector-base junction
capacitances at zero bias (VBE = 0 or VBC = 0), <!>E and <!>c are the emitter-base and
collector-base junction barrier potentials, and mE and me are the emitter-base and
collector-base junction gradient factors. For a uniformly doped step junction,
m is ~, whereas for a linearly graded junction, m is ~. In practice, actual junctions
will have a value for m between these values, the specific value dependent on
the particular impurity dopant concentration profile. It is common to choose
either ~ or ~ to represent a given junction, the choice being made based on
whether the junction doping profile appears closer to a step grade or to a linear
grade. In SPICE [4], if the Ebers-Moll model is used, the value for m is fixed
aq.
10 Chapter 1 - Models for Integrated-Circuit Devices
Equations (1-27) and (1-28) are written for an npn transistor, where VBE and
VBC are negative for reverse bias. For a pnp transistor, use VEB and VCB in Eqs. (1-27)
and (1-28), respectively.
To prevent infinite values for the junction capacitances at forward voltages
equal to the junction barrier potentials, SPICE limits the forward bias for
which Eqs. (1-27) and (1-28) are used to Fe</>e and Fe<l>e, where Fe is a factor
between 0 and 1 (SPICE default = 0.5). For forward biases larger than these
values, the junction capacitances are modeled by a linear extrapolation:
(1-29)
(1-30)
Charge storage due to the mobile carriers injected into the neutral regions
of the transistor are modeled by the diffusion capacitances CDE and Coc. CDE
represents the capacitance associated with injection at the emitter junction and
CDC represents the capacitance associated with injection at the collector junction.
(1-31)
where 'T F is the forward transit time across the neutral base region from emitter
to collector, and 'TR is the reverse transit time across the neutral base region
from collector to emitter. Under reverse bias, the diffusion capacitance is small
compared to the junction capacitance and is usually neglected.
Base-Width Modulation
Ie
Early effect [5]) can be seen from Eqs. (1-7) and (1-14), which combine to
give
(1-33)
for the collector current in the forward-active region. Recall that QB is the
number of majority carrier charges per unit area in the base and is equal to
the volume density of this charge times the width of the neutral base region.
A reduction in base-width reduces QB and thereby increases le.
For modeling purposes, a linear fit to the output characteristics is often made.
The extrapolated curves then intersect the negative VCE axis at a point which is
defined as the Early voltage, VA, as shown in Fig. 1-7. Using this parameter, the
slope of the collector current-voltage characteristics is given by
ale le(O)
(1-34)
aVCE VA
where [dO) is the value of the collector current at VCE = 0, given by Eq. (1-14).
It should be remarked that a similar effect occurs for a transistor operated in
the reverse-active mode. Here, the base width is modulated by the reverse bias
on the emitter-base junction, and the increase in current with collector voltage
is characterized by the reverse Early voltage, VB' The corresponding model
parameters in SPICE for the forward Early voltage and the reverse Early
voltage are VAF and VAR, respectively.
Equation (1-34) defines the output conductance which can be incorporated
into the large-signal model for the forward-active region, shown in Fig. 1-8
for both common-emitter and common-base configurations. In Fig. 1-8,
VA VA
Ro = [dO) = Is eqVBElkT (1-35)
12 Chapter 1 - Models for Integrated-Circuit Devices
B 0----, c
Ro
(a)
Ro
E C
4-
IF IF
IXF
B
(b)
Figure 1-8 (a) Large-signal static common-emitter model for forward-active re-
gion; (b) common-base model.
(1-36)
(a) (b)
Figure 1-9 Example common-emitter amplifier circuit: (a) current driven; (b)
voltage driven.
and
Vo = 15 - (0.591 mA)(lOkfl) = 9.09V
Figure 1-9(b) shows the same amplifier circuit driven by a voltage source.
Determine and sketch (a) IB as a function of the input, V in , for V in ranging from
o to 1 V and (b) Vo as a function of V in . Take room temperature, kT/q = 26mV.
Here, VBE = Vino so
IB = _I S eqVi,lkT = 5 X 10 -16
e Vi' 10.026 = 5 X 10- 18 e V lO.026 A
m
~F 100
This result is plotted in Fig. 1-IO(a). Note the steep increase in base current
with base-emitter voltage for VBE beyond about 0.7 V. This is, of course, due to
the exponential current-voltage characteristic. As an approximation to the circuit
model, the base-emitter voltage is often taken to be constant for a transistor
operating in the active region. For a silicon bipolar transistor operating at room
temperature this voltage, denoted V BE (on), is typically in the range of 0.7-0.8 V.
For the voltage drive (b),
Ie = Is eqV"lkT ( I + ~:)
which combined with Va = Vee - IeRc gives
15 - (5 X 10 - 12) e Vm /0.026
I + (l X 10 13) e Vi,1O.026
This result is plotted in Fig. 1-IO(b) for the portion of the curve labeled "for-
ward-active region." At V in equal to approximately 0.75 V the transistor enters
the saturation region (both emitter and collector junctions are forward-biased)
14 Chapter 1 - Models for Integrated-Circuit Devices
20
15
I., (IIA) 10
o
)
0.0 0.2 0.4 0.6 0.8 1.0
Vin (volts)
(a)
20
15
Forward.active\
region .....,
5
~ Satura'lion
region
o
0.0 0.2 0.4 0.6 0.8 1.0
Vin (volts)
(b)
Figure 1-10 (a) Base current and (b) output voltage as a function of Vln for
example common-emitter amplifier circuit.
and the collector-to-emitter voltage, VeE (and hence Vo in this example), saturates
at a small value, typically 0.1-0.2 V, as illustrated in the figure. Also note that
for V in less than about 0.6 V the output remains high (at Vee), even though the
transistor is still operating in the forward-active region. This is because the
collector current at these base-emitter voltages is small such that IcRc <t:: Vee.
+
vbe Vee
+
VBE
(a)
Cit
i b -+ r lt
0
b
+
rIt v1
(b)
Figure 1-11 (a) Decomposition of transistor currents and voltages into dc and
small-signal components. (b) Common-emitter small-signal equivalent circuit
model.
gm the transconductance and its value is seen to depend linearly on the collector
dc bias current.
Figure 1-8(a) and Eq. (1-37) can be used to determine the variation in base
current with base-emitter voltage.
d (lFI?>F)
g = dh
-- I =---=- (1-38)
rr dVbe ""~o dVbe
The approximation here is that ?>F remains constant for small-signal variations
in Vbe, which is generally true. Hence, the small-signal base resistance is
r = - =?>F
- (1-39)
rr grr gm
The small-signal output resistance ro results from the variation in collector
current with collector bias voltage (Early effect). Using Eq. (1-36),
r.,. models the variation in base current with collector bias voltage:
r.,. is typically a very large resistance and in most cases is neglected in the
small-signal model.
The capacitance Crr is the diffusion capacitance CDE in parallel with the emitter-
base junction capacitance CjE :
Generally, the diffusion capacitance is much larger than the junction space-
charge capacitance so that Crr is usually much larger than C.,..
An alternate form of the common-emitter small-signal model is the com-
mon-base configuration illustrated in Fig. 1-12. Here, the input is applied to
the emitter and the output is taken at the collector. In application to a circuit
in which a transistor is connected in a common-base configuration, this form
of the model is often more convenient to analyze. Either form of the model
is valid, however, and may be used irrespective of the particular circuit
1.1 Bipolar Junction Transistor 17
ro
9m v1
e C
4- 4-
ie v1 ic
Cit C~
ib f b r~
Figure 1-12 Common-base small-signal equivalent circuit model.
(1-44)
(1-45)
Equating Eqs. (1-44) and (1-45) gives the value of the small-signal emitter
resistance
1 (XF
re=---I- -g-m-(l-+-l/-~-F) = -g-m (1-46)
gm+-
rTf
The fabrication process for integrated circuit transistors introduces other circuit
elements (parasitics) in addition to those associated with the intrinsic portion
of the device. Figure 1-13 illustrates the origin of these parasitic elements for
an npn transistor. Table 1-1 identifies each element.
A simplified model which combines the principal parasitic elements affect-
ing circuit performance is illustrated in Fig. 1-14. With reference to Fig. 1-13,
rE = R";, rB = R; + R B, rc = RCI + RBL + RC2 + R;. In addition, C;c and C~c
can be combined with Cjc . Typical values for the parasitic resistances in an
integrated circuit BIT range from a few ohms for rE to a few hundred ohms
for rB and rc. The ohmic emitter resistance rE is often neglected; rB and rc can be
18 Chapter 1 - Models for Integrated-Circuit Devices
Base Collector
p+
m ,
CBS :
,,
~ _ _ _ _ _ _ _ .! Cb
c+ IC
, IC
r-------------------------------------- - ------ --- ~
,
RBl
N+
Substrate
,,
!--- substrate
intrinsic transistor
Figure 1-14 Simplified equivalent circuit which retains the principal parasitic
elements.
neglected if they are small in relation to the other resistances in the base circuit
and collector circuit, respectively.
i in{<o)
(a)
Cil c .-i c
ro Ccs
ac short
(b)
Figure 1-15 (a) Circuit for determining the common-emitter cutoff frequency fT.
(b) Small-signal equivalent circuit, neglecting rE, rc, r ", and R bias•
circuit used to determine this cutoff frequency is shown in Fig. 1-15(a) and the
corresponding small-signal equivalent circuit is shown in Fig. 1-15(b). From Fig.
1-15(b), the small-signal current gain [denoted f3 (jw)] is found to be
(1-47)
20 Chapter 1 - Models for Integrated-Circuit Devices
Figure 1-16 Magnitude of the small-signal short-circuit current gain versus fre-
quency.
At low frequencies, ~ (jw) ~ gm r", = ~F. Because C", is usually much larger than
CJJ., the second term in the numerator of Eq. (1-47) (which represents the feed-
forward current in CJJ.,) is small and can be neglected. Thus,
~ (jw) = ~F (1-48)
1 + jw r", (C'" + CJJ.)
The variation in the magnitude of the small-signal current gain with frequency
is illustrated in Fig. 1-16. The comer frequency w~ is the frequency at which
!~ (jw)! is down by 3 dB (1[2) from the low-frequency value ~F. From Eq.
(1-48),
(1-49)
(1-50)
(1-51)
(1-52)
1.1 Bipolar Junction Transistor 21
1
27t'tp
~ ~ ~ _ - - r - - - - Eqn. (1-53)
actual
~----------------------.IC
IT = 2~ [-k:-::T=----I---]
+
- ( CjE+ Cje) TF
(1-53)
q1c
The cutoff frequency is seen to increase with collector current at low currents
due to the increased charge and discharge rates of CjE and CIL" At high currents,
IT is dominated by the base transit time TF and according to Eq. (1-53) ap-
proaches a constant value 1/2'ITTF' In practice, the neutral base width of a
bipolar transistor widens at high currents (Kirk effect [6]), causing an increase
in TF with current and a subsequent fall-off in IT at high currents. This behavior
is illustrated in Fig. 1-17.
yielding
rn =-=
I3F 150
=7.81kO
gm 19.2mAN
The output resistance from Eq. (1-40) is
VA 100 V
ro=-= =200kO
Ie 0.5 rnA
and from Eq. (1-41), the collector-base resistance is
r lL = I3Fro = (150)(200kO) = 30MO
From Eq. (1-42), the small-signal base-emitter capacitance is
Cn = gmTF + CjE = (19.2 X 10 -3 AN)(32 X 10 12 s) + 0.2 X 10 -12 F
= 8.14 X 1O- 13 F = 0.814pF
and, finally, from Eq. (1-42), the small-signal collector-base capacitance is
19.2mAN = 3.34GHz
(21T)(0.814 + 0.1) pF
Any of the pn junctions that comprise the bipolar transistor structure may be
used as an integrated-circuit junction diode: the base-emitter junction, the
base-collector junction, and the collector-substrate junction all produce viable
diodes, each with differing characteristics [7]. The most common diode struc-
ture for analog integrated circuits is produced by connecting the base and
collector terminals of an npn transistor, as illustrated in Fig. 1-18(a). There are
good reasons for fabricating diodes in this form: With the base and collector
shorted, V BC = 0; from Eq. (1-8), we have for the diode
(1-54)
1.3 Junction Field-Effect Transistor 23
(a) (b)
Figure 1-18 (a) Integrated-circuit junction diode formed from an npn transistor.
(b) Small-signal equivalent circuit.
The diodes are fabricated concurrently with the npn transistors, and thus they
both have identical reverse saturation currents (Is), except as scaled by their
respective emitter areas [see Eq. (1-7)]. Hence, for example, if an equal-area
diode and bipolar transistor are connected in a circuit in which VD and VBE are
equal, then the diode current and the collector current of the transistor will be
the same (neglecting transistor base current and Early effect). This behavior
(as we shall see later) can be quite useful in analog circuits.
The small-signal equivalent circuit of the junction diode is shown in Fig.
1-18(b). Directly from the small-signal bipolar transistor model (Fig. 1-12) we
have
1
rd = re11ro=- (1-55)
gm
and
(1-56)
(bottom gate)
N + BUlled layer
p. Substrate
Device Characteristics
Figure 1-20 illustrates the active region of the p-channel JFET with normal
biases applied. The thickness of the depletion region surrounding the gate-
channel pn junction is determined by the voltage across the junction, in this
case being a function of the gate-source bias (VGs ) and the drain-source bias (VDS).
VGS is normally positive and V DS is negative, resulting in a reverse-biased gate
junction. This produces essentially zero gate current-just a small reverse-bias
junction leakage current. The undepleted portion of the p-type layer provides
Source Drain
depletion
region +
VDS(neg)
Bottom Gate
Figure 1-20 Active region of a p-channel JFET with normal biases applied. The
reverse bias on the gate-channel junction is largest at the drain end of the channel
and smallest at the source end, resulting in a variation in the thickness of the
conducting channel region.
1.3 Junction Field-Effect Transistor 25
the conducting channel, whose thickness (and hence its conductance) is con-
trolled by both V GS and V DS ' Drain current ID flows out of the drain terminal.
With reference to Fig. 1-20, several operating points are worthy of note: As
VGS is increased, the thickness of the depletion layer increases, narrowing the
conducting channel. At a sufficiently large value of VDS the depletion layer will
extend completely through the channel to the bottom-gate pn junction. Because
VDS is negative, the reverse voltage across the gate-channel junction is smallest
at the source end of the channel and is largest at the drain end of the channel.
Thus, if the channel is depleted at the source end, then the entire channel
region will be depleted (pinched off) and no conduction will occur. The
transistor will be turned off. For the p-channel device depicted in Fig. 1-20,
this occurs at a gate-source voltage of
(1-57)
For V DS less than VDs,t the drain current in the JFET is controlled by both V GS and
V DS ; for V DS greater than VDS(sat), the drain current is relatively independent of V DS
and depends mainly on VGS. To keep the gate-channel junction reverse biased,
the maximum gate-source voltage is zero and thus the maximum drain current
occurs for V GS = O. At V DS = VDs'h this maximum current is denoted I Dss and for a
uniformly doped channel region is given by
(1-59)
26 Chapter 1 - Models for Integrated-Circuit Devices
lD
-----~--
\
-- ---- ------ lOSS
1\
saturation
1\
,
,
where
(1-60)
ID = loss [2 ( I - V os ) (
Vp -
Vos )
Vp -
(
-
Vos )
Vp
2] (1-61)
ID = loss ( I -
Vas
Vp
)2 (1-62)
I+-- L ---+I
channel length
(a) (b)
Figure 1-22 D1ustration of channel length modulation in a JFET. (a) At Vns = VDsab
the channei is pinched off just at the drain end of the channel. (b) For Vns > VDsa" the
channel pinch-off point moves back toward the source, resulting in an effective
channel length L I that is less than the geometrical channel length L.
ID = loss ( 1 -
VGS
Vp
)2( 1 - Vos)
VA (1-63)
------ -.
----~ ----------
________+-_____
.................. ... ......
:::::~ ... - - - - .
..;;..;;.:.:..:..ii.J Vos
1
VA= - "I
Figure 1-23 Actual characteristics of a p-channel JFET illustrating the effects of
channel-length modulation. The finite slope in the drain current is characterized
by the Early voltage VA.
28 Chapter 1 - Models for Integrated-Circuit Devices
D D
tId tId
+ +
G Vds G Vds
+ +
VgS VgS
S S
(a) (b)
Figure 1-24 Circuit symbols and sign conventions for (a) p-channel and (b)
n-channel JFET.
and the drain current characteristics in the saturation region are thus expressed
as
VGS)2
lD = loss ( 1 - V p (1 + >'Vos) (1-64)
Figure 1-24 shows the circuit symbols and sign conventions for p-channel
and n-channel JFETs. For an n-channel JFET, the pinch-off voltage is negative
and the parameter >. is positive; in normal operation, the gate-source voltage
is negative, the drain-source voltage is positive, and current flows into the
drain terminal. Thus, Eqs. (1-61) and (1-64) may be used to model the n-
channel characteristics provided Vos < VGS - Vp for operation in the triode region
and Vos 2:: VGS - Vp for operation in the saturation region.
Large-Signal Model
The large-signal static model of an n-channel JFET is shown in Fig. 1-25. With
negative gate voltage, the gate-source and gate-drain pn junctions are reverse
biased, resulting in negligible gate current and lD = los. In the SPICE simulation
program, the large-signal static drain current is modeled as
0 for VGS - Vro<O
(
los= I3Vod2(VGs~Vro)-Vos](I+>'Vos) for VGS-Vro>Vos>O (1-65)
I3(VGS -Vro ) (1 +>'Vos) for Vos2::VGS-Vro>O
where Vro (threshold parameter) = Vp and is taken as negative for both p- and
n-channel JFETs. The parameter 13 is given as
loss
13 = V~ (1-66)
1.3 Junction Field-Effect Transistor 29
Go
0 for V GS $. V P
1
IDs = IDSS [2 (1-V Gs /V;) (-VDs/Vp)-(VDSNp)2]) for V GCVp>VDS>O
IDss(1-VGsNp) (1 + AV Ds) for VDS2::VGS-Vp
It may be readily shown that the two forms given in Eqs. (1-64) and 0-65)
for operation in the saturation region are equivalent. The SPICE model adds
the channel-length modulation term (1 + AVDs ) to the characteristic for operation
in the triode region to avoid a discontinuity in the drain current at VDS = VGS - Vm.
In practice, of course, there is no channel-length modulation in this region; the
error, however, is small.
EXAMPLE. Figure 1-26 shows a simple common-source JFET circuit. Deter-
mine the drain current In and the output voltage Va. The transistor parameters
are Vp = - 5 V, IDss = 1.5mA, and A = 0.03 V-I.
Not known is the operating region of the device. VGS = - 2 V> Vp , so the
JFET is not turned off. It is, therefore, operating in either the triode or
saturation region. We will assume initially that it is in saturation and see if
the results are consistent with that assumption.
From Eq. (1-64)
V DO (+10 V)
(5 kO)
2V
+
yielding
ID = I Dss (1 - V GS IVp)2 [1 + A(VDD - IDR D)]
Solving for ID gives
L - IDss(l- VGSIVp)2(1 + AVDD ) (1.5)(1 - 2/5)2[1 + (0.03)(10)] =Q619mA
D 1 + AIDss R D(1 - VGSIVp)2 1 + (0.03)(1.5)(5)(1 - 2/5)2
and
Vo = 10 - (0.649) (5) = 6.75 V
Here, Vos = Vo = 6.75 V > VGS - Vp = 3 V, so the device is operating in the satura-
tion region.
EXERCISE. Determine the value for RD in the previous example for which
the JFET just enters the triode region. (Ans. 11.9 kO)
(1-67)
(1-68)
1.3 Junction Field-Effect Transistor 31
CGO
D
r d
I GO - - .
+
G
--.
I9
lOS
I GS--'
CGS
S + Is
where CGS (0) and CGD (0) are the zero-bias values of the gate-source and gate-drain
junction capacitances, respectively, and m is the junction grading coefficient.
In SPICE, m is set to 0.5 and cannot be changed.
For a p-channel JFET model, reverse the two diodes and the current source,
reverse the directions of the terminal currents in Fig. 1-27, and change the
signs in the denominators of Eqs. (1-67) and (1-68) from minus to plus.
Figure 1-28 shows the small-signal equivalent circuit for a JFET operating
either in the triode or saturation region. The transconductance is found from
Eqs. (1-61) and (1-64):
(1-70)
32 Chapter 1 - Models for Integrated-Circuit Devices
C GO
i 9 -. ...-i d
g
0
C GS
1+v1
I
gm v 1 ro
d
r =-- (1-71)
o hID
The values of CGS and CGD are detennined from Eqs. (1-67) and (1-68), evalu-
ated at the dc operating point.
,
__ J
·
p+ p+ I ;
,,
.·,,
.,I ) __________ -' N
N- CSBG N GDBG
- - 1 ,
"
· \
I
I
\.------------------------------------------------~'
;, p CGSS ::
Substrate
Figure 1-29 Principal parasitic circuit elements associated with an integrated-
circuit JEFT.
1.3 Junction Field-Effect Transistor 33
Drain
Gate COBG
I
I
intrinsic ;;t----+---,
trans istor rS CGSS
t---------i r----o Substrate
Source
elements for a p-channel JFET: CSBG is the capacitance between the source and
bottom gate, CDBG is the capacitance between the drain and bottom gate, and CGSS
is the capacitance between the bottom gate and substrate.
In practice, only the top gate is driven, which gives the highest frequency
response [10). The bottom gate can either be connected to a separate dc bias
voltage or connected directly to the source terminal; for the latter, the JFET
including the parasitic elements can be represented as shown in Fig. 1-30.
(1-72)
where in the last term the feed-forward current in CGD has been neglected in
relation to gm' From Eq. (1-72), the unity-gain frequency is found to be
f T-- gm (1-73)
21T (CGS + CGD)
EXAMPLE. Determine the cutoff frequency for an n-channel JFET operating
at ID = 1 rnA and VDS = 5 V. The device parameters are IDss = 1.5 rnA, Vp = - 3 V,
34 Chapter 1 - Models for Integrated-Circuit Devices
id
d 4--
i in ro CDBG
'---"""'""----+--~___'_____-..---J\
S ac short
Figure 1-31 Small-signal circuit for determining cutoff frequency /T of the JFET.
The parasitic source and drain resistances, rs and rD, are normally small compared
to lIg m and are neglected here.
A = 0.Q2 V-I, Cos (0) = 0.25 pF, and Coo (0) = 0.1 pF. For this device, <!>i = 0.8 V and
m=~.
From Eq. (1-64), the gate-source voltage, assuming operation in the satura-
tion region, is
depoSited oxide
grown oxide
P well
N" epl
N+ Substrate
Device Characteristics
Figure 1-33 illustrates the active region of the n-channel MOSFET with normal
biases applied. With zero voltage applied to the gate, there is no conducting
channel between the N+ source and drain regions; * the device acts like two
back-to-back pn junctions and only a small reverse-leakage current flows from
• There is a class of MOSFET devices in which a conducting channel exists even in the absence
of an applied gate voltage. These are called depletion-mode devices and a negative gate voltage
(positive for p-channel devices) is required to turn them off.
36 Chapter 1 - Models for Integrated-Circuit Devices
VGS (pOS)
oj.
channal
Source Drain +
VOS(pos)
depletion
region
1 - - - - .:
-- - - - 'I_
14
..1 - - - - - L - - - --'i
.. r---- -- -
"'.I
Body
Figure 1-33 Active region of an n-channel MOSFET with normal bias applied.
(1-74)
where VTO is the threshold voltage for V BS = O. The parameter 'Y is given as
(1-75)
C~x is the capacitance per unit area of the gate-oxide region, given by
' - tox
Cox--- (1-76)
tox
1.4 Metal-Oxide-Semiconductor Field-Effect Transistor 37
where fox is the dielectric permittivity of the oxide and tox is its thickness. <\>p is the
Fermi potential of the semiconductor, given by
kT (NA)
<\>p=-ln - (1-77)
q ni
With VGS > VTH, a conducting channel exists and the drain current ID increases with
increasing drain voltage VDS • As VDS is increased, the potential in the channel
increases, being largest at the drain end of the channel. When VDS = V GS - VTH , the
voltage across the gate oxide at the drain (VGD = VGS - VDS ) is no longer large enough
to create the n-type inversion layer and the channel is pinched off at that point.
This value of drain voltage, denoted VDsab is given by
ILnChx W 2
VDsat = 2L (VGS - VTH ) (1-79)
where ILn is the electron mobility in the channel, and Wand L are the channel
width and length dimensions, respectively (as illustrated in Fig. 1-33).
For values of V DS less than VDsab the drain current is well approximated by
ID =
ILnChx W (
L VGS - VTH - 2"1)
V V
DS DS (1-80)
for VDS < VGS - VTH and describes operation in the triode region [11]. Note that the
drain current is proportional to the channel width - channel length ratio W IL;
this is analogous to the variation in collector current with emitter area AE in a
bipolar transistor.
For VDS larger than VDsab the device is operating in the saturation region and the
current is given by
(1-81)
for VDS 2:: VGS - VTH • In Eq. (1-81) we have included the channel-length modulation
parameter A, which models the narrowing of the inversion channel length as VDS
is increased beyond VDsat • Figure 1-34 illustrates the I-V characteristics for an
n-channel MOSFET. In a p-channel MOSFET, VTH is negative (positive for a
depletion-mode device), VGS and VDS are negative, and current flows out of the drain.
Figure 1-35 illustrates the circuit symbols and sign conventions for n-channel
and p-channel MOSFETs.
38 Chapter 1 - Models for Integrated-Circuit Devices
ID
actual
ideal
I Dsat _ I V GS
saturation
cutoff
VDsat
G o-:-i
+
VgS
S S
n-channel p-channel
(a)
+ +
S S
n-channel p-channel
(b)
Figure 1-35 Circuit symbols and sign conventions for n-channel and p-channel
MOS transistors. (a) Normal symbols for body connected to source. (b) Symbols
for separate body connection.
1.4 Metal-Oxide-Semiconductor Field-Effect Transistor 39
i
In the SPICE simulation program, the drain current is modeled as
KP
L
_W2
XJI
(VGS - VTH - ~2 VDS) VDS (1 + X- VDS ) for VGS - VTH > VDS > 0
ID =
KP W 2
2 L-2X (VGS-VTH) (1 +X-VDS) for VDS2::VGS-VTH>0
]I (1-82)
KP is the transconductance parameter and is equal to f.1n Cbx. XjI is the distance by
which the gate electrode overlaps the source and drain regions (2Xjl = LG - L in
Fig. 1-33), and L is the gate length (labeled LG in Fig. 1-33). The threshold voltage
VTH is modeled after Eq. (1-74) using the zero-bias threshold voltage parameter V ro
and the body-effect parameter"y. Alternately, in place of"y, the channel mobility
f.1n (f.1p for the p-channel), oxide thickness tax, and channel doping concentration N A
(N D for the p-channel) may be used as model parameters.
f.1n C oxL
I W(
Vbias - VTH - 21 VD ) V D
R=-------- 1 = 952D
(100 X 10 6 AN2) (10.5 Y)
40 Chapter 1 - Models for Integrated-Circuit Devices
--,----
61 0 ideal R
actual
1V
(a) (b)
Figure 1-36 (a) Linear resistor example. (b) Ideal versus actual characteristic.
MOSFET Capacitance
There are numerous capacitances associated with the MOSFET structure; the
origin of these capacitances is illustrated in Fig. 1-37. The total gate-to-source
capacitance CGS is comprised of
CGS = C~s + cgs (1-83)
where C~s is the gate-oxide capacitance associated with the source region of the
intrinsic transistor structure and is modeled as [12]
G
s D
L------i~
B
Figure 1-37 Origin of principal capacitances associated with a MOSFET.
1.4 Metal-Oxide-Semiconductor Field-Effect Transistor 41
cgs is the parasitic capacitance resulting from the overlap of the gate and source
and is given by
(1-85)
In SPICE, the gate-to-source per unit-length capacitance C GSO is used, so
(1-86)
where
CGSO = C~xL (1-87)
The total gate-to-drain capacitance CGD is comprised of
C GD = C~D + cgD (1-88)
I
where C~D is the gate-oxide capacitance associated with the drain region of the
intrinsic transistor structure and is modeled as [12]
-
' W'T{l
C ox L - [ V GS - VTH
2 (VGS - V TH ) - V DS
]2}.tnode regIOn
.
C1GD- (1-89)
= 0 saturation region
cgD is the parasitic capacitance resulting from the overlap of the gate and drain
and is given as
(1-90)
In SPICE, the gate-to-source per unit-length capacitance C GDO parameter is used,
giving
(1-91)
where
(1-92)
C SB and C DB represent the pn junction capacitances formed between the source and
body (substrate), and the drain and body regions, respectively. They can be
modeled as
(1-93)
and
C (V ) - CDB(O) (1-94)
DB DB - (1 + VDB/<pi)l!2
where C SB (0) and C DB (0) are the zero-bias capacitances of the source-body and
drain-body pn junctions, respectively.
42 Chapter 1 - Models for Integrated-Circuit Devices
Included in the SPICE model is the capacitance between the gate and body
formed by the overlap of the gate oxide beyond the intrinsic region in the width
(W) dimension. This parasitic capacitance is modeled as
Figure 1-38 shows the small-signal equivalent circuit for a MOSFET operating
either in the triode or saturation region. The transconductance is found from Eqs.
(1-80) and (1-81):
for V DS < Vas - VTH
2ID
gm=---- ( 1-97)
Vas - V TH
where we have made use of Eq. (1-81) and assumed that A V DS « 1. Note that the
transconductance is proportional to the square root of the drain current; contrast
i 9 ----+ C GD +- i d
g
O----I4---~'r--4~-----4~----~~
+ d
CGS v1
J
s
CS B 1=
b
Figure 1-38 Small-signal equivalent circuit for a MOSFET.
1.4 Metal-Oxide-Semiconductor Field-Effect Transistor 43
this with the bipolar transistor in which g m is linearly proportional to the collector
current-see Eq. (1-37).
The small-signal output resistance is determined from Eqs. (1-80) and (1-81):
The unity-gain cutoff frequency iT for the MOSFET is similar to that for the
JFET:
f T-- gm (1-99)
271" (Cos + COD)
Using Eq. (1-96) for gm in the saturation region (and assuming AVDS < l),fT can be
expressed as
f T-- (1 X)
/-Ln (Vos - VTH)
forVDS2':VOS-VTH (1-100)
471"L2 3 + {I
where Eqs. (1-83) - (1-85) and Eqs. (1-88) - (1-90) have been used for the
capacitances Cos and COD' Equation (1-100) indicates that the high-frequency be-
havior of a MOSFET varies as the square of the channel length L; a fabrication
process that reduces the channel length has a significant effect on device, and
hence circuit speed.
EXAMPLE. A MOSFET with a channel length L of 3 /-Lm has a unity-gain
cutoff frequency iT of 800 MHz. A new fabrication process allows the channel
length to be reduced to 2 /-Lm. Determine the new cutoff frequency, assuming
that X jl remains at 1 /-Lm.
From Eq. (1-100)
1 31 )
(3/-L m ) 2 ( 3+
(2/-Lm)
2( 1 1)
3 +2
= 1.8
giving
iT= (1.8) (800 MHz) = 1.44GHz
44 Chapter 1 - Models for Integrated-Circuit Devices
Problems
1 1 Ie
-+--
kT UR I3R IB
VCE(sat) = - I n
q lIe
1---
I3F IB
(b) What is VCE(sat) for Ie~O?
(c) At a constant base current IB, what is Ie for VCE(sat) ~ O?
1.3 For the transistor in Problem 1.2, determine and sketch a plot (using log
scales) of the magnitude of the common-emitter small-signal current gain
as a function of frequency from 1 MHz to 10 GHz.
1.4 Using the common-base small-signal equivalent circuit (Fig. 1-12), find
the frequency w" at which the short-circuit common-base current gain
(Ui e ) (jw) is down by 3 dB from the low-frequency value UF. Neglect the
output resistance roo
1.5 Figure 1-39 illustrates two ways of implementing a two-diode string using
npn transistors. Derive the forward-bias I-V characteristic for the two
configurations, assuming identical transistors and that 13 F ~ 1. At a constant
forward-bias current, which diode string has the largest voltage drop V?
v v
(a) (b)
Voo (+10 V)
+
Vi n =1 V
(3 kU)
1.11 Determine ID and Vo in the circuit of Fig. 1-41. The MOSFET parameters
are/JopCbxW1L=200/JoAN2, VTH = -2V,and)"= -0.02V- I .
46 Chapter 1 - Models for Integrated-Circuit Devices
Voo (+5 V)
(6 kO)
V S S(-5 V)
Determine and sketch the small-signal equivalent circuit for this transistor
used in a circuit with VGS = 2.5 V, V DS = 3V, and VSB =0. Take f..Ln = 6OOcm2 /
V-s and <l>i = 0.8 V.
1.13 A useful figure-of-merit for a transistor which relates its gain and bias
current is the transconductance/current ratio gmlI. (a) Determine this fig-
ure-of-merit for a bipolar transistor (operating in the forward-active re-
gion) gmlIc and for a MOSFET (operating in the saturation region) gmlID.
Compare the two at room temperature, taking VGS - VTH = 1 V for the MOS-
FET. (b) An n-channel MOSFET is to be designed to give the same
transconductance as a BJT, both operating at a current of 1 rnA. Deter-
mine the channel width W required to achieve this transconductance; the
fabrication process gives L = 1.5 f..Lm and tox = 6Onm. Take f..Ln = 6OOcm 2 N-
s and Eox = 3.45 X 10 - 13 Flcm. Is this a realistic size for a modem integrated-
circuit device?
1.14 Determine the I-V characteristic for each of the two MOSFET "diode"
connections illustrated in Fig. 1-42. The two NMOS transistors in Fig.
1-42(a) are identical and both the NMOS and PMOS transistors are
enhancement mode devices. Use J3n = f..Ln C~x Wn/Ln and VTH to represent the
NMOS transistors, and J3p = f..LpC~x Wp /Lp and VTp = VTH to represent the PMOS
transistor. For each ot the two configurations sketch the I-V characteristic
for V>O.
1.15 The induced charge per unit area in the channel of a MOSFET is given by
QCH (x) = C~x [VGS - VTH - V(x)]
where V(x) is the channel potential equal to zero at the source end (x = 0)
References 47
(a) (b)
Figure 1-42 (a) Series NMOS and (b) series PMOS and NMOS for Problem 1.14.
dV= ID dx
WlLnQ~H(X)
C~S = dQcH
dVGS
show that the gate-to-source capacitance in saturation given in Eq. (1-84)
results.
Hint: In saturation, take V DS = VGS - VTH and use Eq. (1-79) for I D•
References
I. J.J Ebers and J.L. Moll, "Large-Signal Behavior of Junction Transistors," Proc. IRE,42, 1761
(1954).
2. R.S. Muller and T.!. Kamins, Device Electronics for Integrated Circuits, 2nd ed., Wiley, New
York, 1986.
3. P. Antognetti and G. Massobrio (eds.), Semiconductor Device Modeling with SPICE, McGraw-
Hill, New York, 1988.
48 Chapter 1 - Models for Integrated-Circuit Devices
current
reference current mirror gain stage output stage
,-------., t-----------~ -------, ... -------.
•
,••
•
•
•
•
•
•
•
•
•
• out
•
•
•
•
•
•
current sources •
•
,, .________________ ~------~---L----. :•
-------, ,-------, ~-------.
Figure 2-1 A two-stage operational amplifier circuit illustrating its component
circuit blocks.
49
50 Chapter 2 - Analog Integrated-Circuit Blocks
I ref + I ref +
I D1 t
M1
(a) (b)
Figure 2-2 Basic current mirror (a) using BJTs and (b) using MOSFETs.
Current sources provide currents that are relatively constant and independent of
device parameters and voltage; they can also be made relatively independent of
temperature and power-supply variations as well. In analog circuits, current
sources are used for dc biasing and as load elements in amplifier stages. In a
current-source circuit, a reference current in one branch is reproduced or mir-
rored in another branch; hence, these circuits are also called current mirrors.
Figure 2-2(a) shows the basic current mirror fashioned with bipolar transistors.
In the circuit, both transistors have the same base-emitter voltage. Thus, if the
transistors are identical and the output transistor Q2 is operating in the forward-
active region, then the collector currents of the two transistors will be equal
(neglecting Early effect) and the output current 12 will be approximately equal to
the reference current I ref • For each transistor, operating in forward active, we have
from Eq. (1-36)
(2-1)
The transistor saturation current Is is proportional to emitter area [see Eq. (1-7)].
In an integrated-circuit process, the two transistors (and others) are fabricated
simultaneously and, hence, will have identical values of Is, except as scaled by
their respective emitter areas (designer specified); they will also have other
closely matched device parameters, such as current gain ~F and Early voltage VA'
In the current mirror, we have for QI and Q2 at equal VBE ,
lei IC2
(2-2)
A 1 (1 + VBEIVA ) A 2 (l + VCE2 IVA )
2.1 Current Sources 51
(a) (b)
Figure 2-3 Output current characteristics of (a) the BJT current and (b) the
MOSFET current mirror of Fig. 2-1.
where Al and Az are the emitter areas of QI and Qz, respectively. In the circuit,
which used in Eq. (2-2) gives for the output of the current source
The output characteristic of the basic BJT current mirror are illustrated in Fig.
2-3(a).
EXAMPLE. Find the output current at Va = lOV of the simple current source
shown in Fig. 2-4. Except for emitter areas, the transistors are identical with
I3F=100 and VA=50V. Az=&AI. Take VBE =VBE(on)=O.7V. Repeat the
calculation if base current and the Early effect are neglected.
From the circuit,
Vee (+ 15 V)
I ref ..
where j = 2, 3, ... , N,
Vee
I ref ..
This technique is commonly used in analog circuits where several bias cur-
rents are required-see Fig. 2-1 for example. As additional current-source tran-
sistors are added, however, additional base current must be supplied by the
reference current, which detracts from the reference transistor's collector current
[Cl. This can lead to significant error, especially for low-beta transistors. The use
of base-current compensation-to be discussed later in this section--can reduce
this error.
For the MOS version of the current mirror [Fig. 2-2(b)], the drain current in
saturation is given by Eq. (1-81):
(2-7)
Here, [ref = [Dl, which when combined with Eq. (2-7), yields
In the MOS current mirror, the output current scales with the channel width-
to-channel length ratios W IL of the transistors. Normally, the channel length L
is fixed for a given fabrication process and the channel width dimension W is
varied.
[ _ V DD - Vas
ref - R
V DD (+ 15 V)
v: -
GS -
V
TH
+ j 2/ref
fJ..nC~x(WIL)1
which combined with the previous equation yields a quadratic equation in I ref :
15 ( 1 + (0.02) (5) )
12 = 10 (0.750 rnA) I + (0.02)(3.74) = 1.15 rnA
A primary source of error in the basic current mirror of Fig. 2-2(a) arises from
the finite base currents, which results in ICI differing from Iref-by a factor of
[1 + (1 + A2 IA I) 113 F]' In high-beta transistors (say 100 or greater), this difference
is small; however, with smaller gain devices (such as with lateral pnp transis-
tors), the difference can be significant. The base-current error can be reduced
by adding current gain to the reference transistor Q I, as illustrated in Fig. 2-7.
The difference between I ref and I CI is now equal to the base current of Q3, which is
less than IBI + I B2 • Assuming identical transistors, except for emitter areas, we have
h3 IBI IB2
I ref = ICl + IB3 = ICI + - - - = ICI + - - - + - - - (2-9)
I3F+ 1 I3F+ 1 I3F+ 1
With Ie = I3FIB and, neglecting the Early effect, IC2 = (A 2IA I)/Ch this leads to
I =1 [ 1+ I3F(I3F
1 (1+ -
A2)] (2-10)
ref CI + 1) Al
Vee
I ref +
(2-11)
1 ~~ Iref(
2 =
1+ 2
11
[3F+[3F
( A'))(:::~::~~)
1+-
AI
(2-12)
For a reasonably large value of beta, the base-current terms can be neglected,
giving
(2-13)
A second source of error in current sources arises from the finite output resis-
tance of the current-source transistors, which results in a variation in output
current with voltage, as depicted in Fig. 2-3; this variation in current with
voltage is characterized by the effective output resistance of the current source
Ro. In the simple current source using the basic current mirror, this output
resistance is simply the output resistance ro of the transistors. Several modifica-
tions to the basic current mirror can provide current sources with increased
output resistance; one example is the cascade current source, illustrated in Fig.
2-8 for bipolar transistors. In this circuit, Q3 and Q4 form a basic current mirror,
and a second mirror stage consisting of QI and Q2 is added in series. In this
connection, Q2 and Q4 form a common-base : common-emmiter cascode pair;
56 Chapter 2 - Analog Integrated-Circuit Blocks
Vee
I ref t
IC3 = hi - I (2-15)
1 + 2/f3F - C4
Using
(2-16)
leads to
1 1
I - I - I (2-17)
2 - ref 4 ( 1 ) - ref 1 + 4/f3F
1 +- 1 +-
f3F f3F
which shows a factor-of-2 improvement in beta sensitivity over the simple
current source.
The output resistance Ro of the cascode current source is calculated from its
small-signal equivalent circuit, shown in Fig. 2-9. In this calculation, a small-
signal test current ix is applied to the output port of the current source and the
2.1 Current Sources 57
R
r e1
r02 +
Vx
,+ test current
ix
r e3 r04
Figure 2-9 Small-signal equivalent circuit of the cascode current source for cal-
culating output resistance.
resulting response Vx is measured; the ratio of the two vx/i x then gives RD.' With
reference to Fig. 2-9, several points are worthy of note: The current in r04 is small
relative to the current gm4 V4 and, because r04 is not connected to the output, will be
neglected; the reference current resistance R is usually much larger than the
emitter resistance re and will be neglected; r ,,4, which is in parallel with re3' is the
larger of the two by a factor of [3 F + 1 and can be neglected; all four collector
currents are approximately equal; thus, reI = re3, both denoted reo and gm2 = gm4, both
denoted gm. With these approximations, the simplified equivalent circuit in Fig.
2-10 results.
• An equally valid method is to use a test voltage Vx and measure the response current i x•
58 Chapter 2 - Analog Integrated-Circuit Blocks
Summing the currents at the node connecting the emitter of Q2 and the
collector of Q4 gives
ix =gm V4+ v
r",+2r,
=gmV4+~=gm(V4+~)
r", ~F
(2-18)
(2-20)
The last term on the right-hand side of Eq. (2-20) is r ",/2, which is much smaller
than ~ F r 02 12, and is neglected; also ~ F 12 ~ 1, yielding
Vx ~F
R =-=-r2 (2-21)
o ix 2 0
The output resistance of the cascode current source is thus a factor of ~F12
greater than that of the simple current source.
Another current source that achieves a high output resistance is the Wilson
current source [1], illustrated in Fig. 2-11. In this configuration, the diode-
connected reference transistor Q3 operates as a negative feedback element in the
I ref.
IC1 t
output circuit of the source, which tends to stabilize the output current 12 to lref.
To see this, suppose that the output voltage of the source is raised, causing 12 to
increase; this, in turn, increases la and thereby V BE3 , causing ICI to increase. This
increase in ICI subtracts from I ref, causing 1m to decrease, thereby decreasing
la. The output current thus remains nearly constant, giving a high output resis-
tance. A small-signal analysis of the circuit gives an output resistance of
I3F (2-22)
R o " = '2- r 2
0
for I3F~ 1. This gives a factor-of-I3F improvement over the basic current source.
EXAMPLE. Determine the current and output resistance of the Wilson current
source of Fig. 2-11 with Vee = 18 V and R = 10 kil. The transistors are identical
with I3F = 100 and VA = 75 V. Take VBE(on) = 0.7 V.
The reference current is
Vee
I ref +
Figure 2-12 Improved Wilson current source. With this circuit, V CEI = V CE3. so a pre-
cise match between I C1 and I C3 is obtained.
side of the current source, as illustrated in Fig. 2-12. With this arrangement, leI and
IC3 are made equal and, neglecting the output resistance ofQ2, 12 is exactly equal to l ref •
Both versions of the Wilson current source can be implemented in MOS
technology as well; Fig. 2-13(a) illustrates an NMOS Wilson current mirror and
Fig. 2-13(b) illustrates the improved current mirror with NMOS transistors. A
small-signal analysis of either circuit gives for the output resistance
(2-25)
I ref + I ref +
(a) (b)
Figure 2-13 (a) NMOS Wilson current mirror. (b) Improved Wilson current
mirror using NMOS •.
2.1 Current Sources 61
One drawback to the MOS Wilson current source is the minimum output
voltage required to keep both M2 and M3 operating in the saturation region; for
identical transistors, this minimum voltage is equal to 2Vos - VTH • In some
applications, this can severely limit the dynamic range of the current source,
especially with low power-supply voltages.
(2-26)
kT (/CI2)
VBEI •2 = -In --' (2-27)
q I SI ,2
kT
1 =~I [ 1 + q AI 12
In(~
lref) 1
(2-28)
2 R 2 ref ref I
IR
I ref t
+
• ix
(2-30)
(2-32)
and
(2-33)
2.1 Current Sources 63
(2-35)
If I3Fro2 ~ (RdlRref + r",2), then the second term on the right-hand side of Eq. (2-35)
is negligibly small, yielding
Ro = (1 + I3FR2
+
RI11Rref R2 + r",2
) ro2 (2-36)
EXAMPLE. Find the output current and output resistance of the resistor-
ratioed current source of Fig. 2-14 with Vee = 10 V, R I = 1 kil, R2 = 4 kil, and
Rref = lOkil. Take for the transistors, I3F = 100, VA = 75 V, lSI = 5 X 10 -16 A,
IS2 = 2.5 X 10 -16 A, and AI = 2A 2 •
which, used in Eq. (2-28), gives an initial value for 12 of 215.7 jJ.A. Using this
value in Eq. (2-27), gives
215.7X 10-6)
VBE2 = 0.0261n ( 16 V = 0.715 V
2.5 X 10
which is used in Eq. (2-26) to obtain an updated value for VBEI :
VBE1 = VBE2 + 12R2 - IrefR I = 0.715 V + (0.2157 rnA) (4kil) - (0.8455 rnA) (1 kil)
=0.732V
This value is used in Eq. (2-29) to obtain a new value for lref of 0.8425 rnA. A
second iteration cycle is sufficient, giving the final values:
lref = 0.8426 rnA, 12 = 215.0jJ.A
VBE1 = 0.732 V, VBE2 = 0.714 V
64 Chapter 2 - Analog Integrated-Circuit Blocks
~ = 0.2150mA = 0.2552
I rer 0.8426 rnA
which is close to the value of 0.25 predicted by Eq. (2-30).
For the output resistance,
VA2 75 V
ro2 =- = = 348.8 kfl
12 0.215mA
and
r 2=
7r I3F = 100 = 12.1 kfl
gm2 0.215 rnA 10.026 V
which, combined in Eq. (2-36), gives
Figure 2-16 shows a special case of the resistor-ratioed current source in which
the resistor in the emitter leg of QI is omitted. This configuration, called the
Widlar current source [2], is useful in providing very low output currents, but
without a commensurately low reference current, which would require a large
(and therefore impractical) reference resistance. Setting R I equal to zero in Eq.
(2-28) gives for the output current of the Widlar current source;
12 = kT In (~ lrer) (2-37)
qR 2 AI 12
Vee
I ref.
where
I - Vee - V BEI
ref - R (2-38)
ref
Likewise, setting R I = 0 in the anaiysis previously carried out for the resistor-
ratioed current source gives for the output resistance of the Widlar current
source:
R a -- (1 + I3FR2 .) ra2 ~
~
( 1
+ gm2 R 2 ) ra2 (2-39)
reI IIR ref + R2 + r,,2 1 + gm2R2/13F
where in the second equation we have neglected rei in comparison with r,,2 and
assumed that I3 F::'P 1. Further, if gm2R2 ~ I3F, then
(2-40)
VBE!
kT
=-In - (10) (2-42)
q lSI
An added benefit of this stage is the relatively high input resistance provided
by the emitter follower which reduces the loading at the output of the previous
stage to which it connects; most level-shift stages employ an emitter follower
(or source follower with MOS transistors) buffer as part of the level-shift
circuit.
66 Chapter 2 - Analog Integrated-Circuit Blocks
(a)
(c)
Figure 2-17 DC level-shift stages using the base-emitter voltage drop: (a) single
VBE emitter follower; (b) multiple VBE diode string; (c) VBE multiplier.
Vee
kT (/0)
VSE=-ln - (2-48)
q Is
Composite npn-pnp Level-Shift Stage
Both npn and pnp transistors can be combined to form level-shift circuits [3].
Figure 2-19 shows a commonly used stage. With approximately equal base-
emitter voltages for QI and Q2, the voltage at node a is equal to VI> and the
current in R I is (Vee - VI) IR I, which equals leI + I E2; neglecting base currents,
leI = 10 and h2 = 12. The level-shifted voltage Vz is equal to 12R z, which yields
R2
V2 = -(Vee - VI) - loR2 (2-49)
RI
68 Chapter 2 - Analog Integrated-Circuit Blocks
Vee
This level-shift stage has a non unity voltage gain (A v = - R2 IR I) unless R I and
R2 are made equal. If R2 is eliminated, the circuit becomes a voltage-controlled
current source with
(2-50)
Figure 2-20 shows two commonly used level-shift stages using NMOS tran-
sistors. Transistor M I operates as a source follower and M2 provides the bias
current. The level shift is equal to Vas" and as long as V I :5 (VDD + VTH ), M,
operates in the saturation region. Using Eq. (1-81), neglecting channel-length
modulation (X. = 0), we have for the circuit of Fig. 2-20(a):
1-
(2-51)
(WILh
1+ 1+
(WIL) I
For (WIL)z« (WIL)" the radical terms in Eq. (2-51) are negligible and the
level shift is approximately
V 2 = VI - VTH (2-52)
For the special case in which (WIL), = (WILh, the circuit functions as a voltage
divider with
(2-53)
2.3 Single-Transistor Gain Stages 69
Voo Voo
(a) (b)
Figure 2-20 NMOS source follower level-shift stages.
V\
Vbias ::; -~r==== + -~r====- VTH (2-54)
(WILh (WILh
1+
(WIL) \ (WIL) \
and the level shift is
V2 = V\ - (1- (WILh
(WIL) \
)v
TH-
(WILh
---'---- Vbias
(WIL) \
(2-55)
Single transistors, combined with either resistive or active loads, produce the
simplest circuits which can provide useful amplification in analog circuits.
Although more complex circuits can provide improved characteristics, these
basic single-transistor gain stages are utilized in certain portions of many
analog integrated circuits. The three singie-transistor configurations utilizing
bipolar and fieid-effect transistors are briefiy discussed in this section, each of
which has a particular set of input resistance, output resistance, and gain
characteristics.
70 Chapter 2 - Analog Integrated-Circuit Blocks
Vee
load element
Figure 2-21 Common-emitter gain stage with resistances added in the base and
emitter legs. Ri and R. represent the small-signal equivalent input and output resis-
tances, respectively. rl. is the smal-signal equivalent resistance of the load element.
(2-58)
where
(2-59)
2.3 Single-Transistor Gain Stages 71
and
I = V (I + Vee)
!3F(Vi - be ) (2-61)
e RB + (!3F + I)RE VA
The two-port equivalent circuit shown in Fig. 2-22 may be used to represent
the small-signal behavior of the common-emitter stage. The small-signal input
resistance Ri can be obtained directly from Eq. (2-59):
dVi dVbe
Ri=-=--+RB+(!3F+ I)RE (2-62)
dh dh
(2-63)
Ri=RB+r1T(I+gmRE) (2-64)
(2-66)
72 Chapter 2 - Analog Integrated-Circuit Blocks
ro +
The output resistance re seen looking into the collector of the CE transistor is
evaluated from the small-signal test circuit shown in Fig. 2-23; this circuit is
the same as that used to evaluate the output resistance of the resistor-ratioed
current source (Fig. 2-15) with (rei + RI)IIR,ef = RB and R2 = R E. From Eq. (2-36)
re =(I+ R B
I3FRE
+ RE + r 1T
)ro (2-68)
then for Vi < VBE(on), the transistor is off and the output voltage is at VCC. As Vi
increases, Va (and hence the collector voltage VJ decreases; when Vbc becomes
positive, the transistor enters the saturation region, giving Vo = VCE(sat). This occurs
at an input voltage
(2-72)
(2-73)
(2-74)
Vo
v CC 4-....:o;:.:,ff.:..-....
sat
V CE(satrf - - - -- -~ -- - -- - -- - I
I I
VBE(on) Vi(sat)
Figure 2-25 Output voltage versus input voltage for resistive-loaded CE stage.
From a practical sense, the voltage gain of the resistive-loaded gain stage is
limited by the load resistor, Rc in the circuit of Fig. 2-24. Large gains require
2.3 Single-Transistor Gain Stages 75
Vee
I ref. +----0 Vo
large resistance values, which, in turn, require a sizable chip area. The output
resistance of a transistor can be utilized as an effective load element, replacing
a fixed resistive load. Figure 2-26 shows a common-emitter gain stage with
an active load provided by a pnp current-source transistor, Qz; the effective
load resistance is roz, which when combined with the output resistance rol of the
CE transistor QI provides a high overall output resistance for the stage.
For the collector current of transistor QI in Fig. 2-26,
(2-78)
where the pnp Early voltages, VAZ and VA3 , are taken as positive quantities. Now,
VecZ = Vee - Vo and Vec3 = Veb3 • Neglecting base current, we have le3 = lref' and
assuming that VA3 ~ Veb3 , Eq. (2-78) becomes approximately
0 1 off, O 2 sat
Vcc - VCE2(sat) +---.....
Vcc o 1 ,Q 2 active
Q 1 sat, Q 2 active
:\
VCE1 (sat) --------~'-------------
+-----~------- .... Vi
Figure 2-27 Output voltage versus input voltage for active-loaded CE stage.
(2-81)
(2-82)
If the npn and pnp Early voltages are equal, then at this operating point,
Vo = Vcc l2.
The small-signal voltage gain with no load connected to the output can be
obtained by differentiating Eq. (2-80):
(2-83)
2.3 Single-Transistor Gain Stages 77
A = _ 1 ((lOOV)(lOOV)) = _ 1923
v O.026V lOOV+lOOV
Figure 2-28(a) shows a common-source (CS) gain stage using NMOS transis-
tors. Here, a "diode"-connected transistor (M 2) is used as a nonlinear resistive
element, which eliminates the additional process steps required to fabricate
separate integrated-circuit resistors. The voltage transfer characteristic is
sketched in Fig. 2-28(b). For Vi < VTH , transistor MI is off, transistor M2 is in
saturation (at negligibly small current), and the output voltage is at V DD - VTH • As
Vi is increased above VTH , MI turns on, operating inti ally in the saturation region;
M2 operates always in saturation. Because M2 presents a relatively low value of
effective load resistance to the CS transistor Mj, the effects of channel-length
modulation can be neglected; in this region of operation,
and
(2-88)
(WIL) I V - V (2-89)
(WILh ( i TH)
78 Chapter 2 - Analog Integrated-Circuit Blocks
Vo
Voo
Voo !--------------------
M 1 off, M 2 sat
Voo- VTH f--"",
I
T--- -----
I
I
V OS(sat) ~
I
VTH Vi(sat)
(a) (b)
Figure 2-28 (a) Common-source gain stage with saturated transistor load. (b)
Output voltage versus input voltage.
The output voltage is seen to vary linearly with the input voltage; the approxi-
mate small-signal voltage gain can be obtained from the slope of this charac-
teristic:
dVo (WIL)!
A =-= (2-90)
v dVi (WILh
Thus, for a voltage gain greater than unity, (W IL)! must be made larger than
(W ILh; usually, M! is made with a short channel length (L) and a wide channel
width (W), and M2 is made with a long channel length and a narrow channel
width. In practice, constraints on chip area limit gains to about 10.
At larger input voltage, M2 comes out of saturation and enters the triode
region. This occurs at,
Vi = Vi(satl
VDD +
= ----;====--
~~~~~: V TH
(2-91)
(WIL)!
1+
(W IL)2
(2-92)
2.3 Single-Transistor Gain Stages 79
r-------~------~----------~----_O+
+ r 02
Vi
(2-93)
which evaluates to
(2-94)
(2-95)
which, using Eq. (1-96), can be easily shown to be identical to Eq. (2-90).
The small-signal output resistance of this gain stage is
(2-96)
Av = - J 610 = - 7.75
gm2 = /-Ln C~x (:)2 (Voo - Vo - VTH ) = (20 /-L AN2 ) (1) (10 - 5 - 1) V = 80 /-LAN
80 Chapter 2 - Analog Integrated-Circuit Blocks
(2-97)
M 1 off, M 2 triode
V DD ~'-,~,,-
VDD-VSG3-VTP ---~-
M3 M2 I
I
I
fd2 I
VDD I
I ref .. Va
Vi 0----1 M1 VDS(sa1)
-=
VTN 2I ref
~nC~x(W/L)1
(a) (b)
Figure 2-30 (a) Common-source gain stage with active load. (b) Output voltage
versus input voltage.
2.3 Single-Transistor Gain Stages 81
Id2 Id3
(2-98)
I + Az V sdZ I + }..3 Vsd3
Now, Id3 = I fef , V sd2 = VDD - Vm and Vsd3 = V sg3 « I /}..3, which used in
Eq. (2-98) gives
(2-99)
Equating Idl and I d2 , and solving for the output voltage results in
V DD +-I [1 -
/-Ln-C~x
- - (W) (Vi-VTN) 2]
}..2 2Ifef L 1
Vo = -------=----:---;----'---'------"- (2-100)
I +_1 C' (W)
}.. ~ - (Vi - VTN/
}..2 2Ifef L 1
At
(2-101 )
(2-102)
(2-103)
(2-104)
82 Chapter 2 - Analog Integrated-Circuit Blocks
At
/-Ln c~x
- 2 - (W I L)I (Vi - VTN) 2 = I ref
(2-105)
The second term inside the square brackets of Eq. (2-105) is normally« 1
and can be neglected. This gives
(2-106)
The numerator on the right-hand side of Eq. (2-106) is equal to the transcon-
ductance gml of transistor MI. Using Eq. (1-98) to relate the output resistance of
transistors M I and M2 to the operating current I ref and their respective channel-
length modulation parameters >-.., Eq. (2-106) can be expressed as
(2-107)
(2-108)
(2-109)
2.3 Single-Transistor Gain Stages 83
Vee
Vee - veE(sat)
o - t - - F - - - - - - - -... Vi
VBE(On)
(a) (b)
Figure 2-31 (a) Common-collector (emitter follower) stage. (b) Voltage transfer
characteristic.
(2-110)
with
kT (Ie)
Vbe=q-In
kT (Is (1 + 1IIh)R
Is =q-In Vo ) (2-111)
E
Substituting Eqs. (2-110) and (2-111) into Eq. (2-109) yields the transfer
characteristic
It should be remarked that for small values of the input V be will be small,
resulting in a small collector current and a near zero output voltage. As an
approximation, we assume the transistor to essentially be turned off until Vi
reaches VBE(on). The voltage transfer characteristic is sketched in Fig. 2-31(b). For
small and moderate values of Vo. the logarithmic term in Eq. (2-112) is small
and the characteristic is nearly linear with a slope of approximately
(2-113)
84 Chapter 2 - Analog Integrated-Circuit Blocks
I
R·---.
I IR
I B
~----~----------~--OV,
I
+{-R
I 0
(a)
(b)
Figure 2-32 (a) Small-signal equivalent circuit of the common-collector (emitter
follower) configuration. (b) Circuit for calculating the small-signal output resis-
tance.
which approaches unity gain for small values of RB and/or large values of R E•
The upper limit on the output is reached when the transistor enters the satu-
ration region, giving Vo(max) = Vee - VeE(sat).
Figure 2-32(a) shows the small-signal equivalent circuit of the common-
collector stage from which the input resistance and voltage gain are calculated.
The transistor output resistance ro is in parallel with RE and as, normally, ro»
R E , it is neglected. From the circuit
Vi = ib(R B + r,,) + Vo (2-114)
where
Vo = ieRE = (h + gm v,)RE (2-115)
and
v,=ibr", (2-116)
2.3 Single-Transistor Gain Stages 85
(2-118)
The voltage gain is less than unity; however, if (~F + 1) RE » RB + r,", the gain
can be close to unity.
The circuit for calculating the small-signal output resistance is shown in Fig.
2-32(b). Here, it is more convenient to use a test voltage Vx and calculate the
resulting current response ix • Summing the currents at the emitter node gives
(2-122)
where
(2-123)
and
(2-124)
Combining Eqs. (2-123) and (2-124) into Eq. (2-122) gives the output resis-
tance
R
o
=~=REII(RB+r'lr)
ix ~F + 1
(2-125)
The two-port equivalent circuit shown in Fig. 2-33 can be used to represent
the small-signal behavior of the common-collector (emitter follower) stage,
where R;, Av, and Ro are given by Eqs. (2-118), (2-121), and (2-125), respect-
86 Chapter 2 - Analog Integrated-Circuit Blocks
ively. Because the voltage gain of the emitter follower is usually close to unity,
the dependent voltage-source form of the two-port equivalent circuit is more
appropriate than the equivalent Gm form, shown in Fig. 2-22.
kT ( 0.026V )
r1T=-I3F= (100)=5.25kO
q1c 0.495 rnA
1 kO + 5.25kO)
Ro=(2kO) II ( 101 =60.00
EXERCISE. For the previous example, determine the input bias voltage re-
quired to give a de operating point of Va = 1 V. Take for the transistor
Is = 2 X 10 - 16 A. (Ans. 1.75 V)
2.3 Single-Transistor Gain Stages 87
Vee
(2-126)
where
kT (lei)
Vbel =-In - kT (lei)
=-In - (2-127)
q lSI q lSI
Using lei = le2 and taking lez = I ref, the transfer characteristic becomes
kT (/ref)
Vo=Vj--ln - (2-128)
q lSI
The linear range extends over the region in which both QI and Qz are operating
in the forward-active region; this range is VCE(sat) < Vo < Vcc - VCE(sat).
(2-129)
88 Chapter 2 - Analog Integrated-Circuit Blocks
'lioo
VTH
(a) (b)
Figure 2-35 (a) Common-drain (source follower) stage. (b) Voltage transfer char-
acteristic.
where, for VTH < Vi:S Voo + VTH , the transistor is operating in saturation with a
drain current (neglecting A) given by
Id = -J-Ln2 z:
C~x- ( W) (Vi - Vo - VTH ) 2 (2-130)
Substituting Eq. (2-129) into Eq. (2-130) and solving the resulting quadratic
equation for the output voltage yields
J-LnCox(Z:)Rs
(2-131)
This characteristic is sketched in Fig. 2-35(b). For very large values of Rs, the
characteristic is nearly linear with a slope of unity.
A small-signal analysis of the source follower circuit [Fig. 2-35(a)] yields a
voltage gain of
_ Vo _
A •. - - - - - - - (2-132)
Vi 1
1+--
gmRs
an input resistance
Ri= 00 (2-133)
and an output resistance
(2-134)
2.3 Single-Transistor Gain Stages 89
VDD
A common-base (CB) stage, illustrated in Fig. 2-37, provides voltage gain and
exhibits a low input resistance and a high output resistance. In this configur-
ation, the input is applied to the emitter and the output is taken at the collector.
The resistance RE represents the output resistance of the driving source and the
resistance RB added in the base leg produces base degeneration (in the same
fashion as the emitter degeneration resistance in the common-emitter stage).
Unlike the CE stage, however, in which the driving source supplies an input
base current, the input current to the CB stage is a much higher emitter current.
For this reason, the common-base configuration is not as widely employed as
the common-emitter configuration; it does have a couple of features which
make it attractive in certain applications: (1) The base-collector capacitance
(Cf.L) in a CE configuration provides negative feedback from the output to the
90 Chapter 2 - Analog Integrated-Circuit Blocks
Vee
load element
Figure 2-37 Common-base gain stage with resistances added in the emitter and
base legs. Ri and Ro represent the small-signal input and output resistances, respect-
ively. TL is the small-signal equivalent resistance of the load element.
input; the feedback is enhanced by the gain of the stage (the Miller effect [5]),
resulting in a much degraded frequency response. In the CB configuration, this
capacitance appears at the output only, resulting in a much higher frequency
response. (2) The reverse-bias breakdown voltage between collector and base
is considerably higher than that between collector and emitter [6]; with the
same transistor, the CB configuration can provide higher output voltages,
which may be required in some high-voltage applications.
For the transistor operating in the forward-active region (which requires Vi
to be negative), we have for the collector current in terms of the input emitter
current
VA_)
I = _Ie_(_I_+_V_ee_/_ (2-137)
c 1 Vee
-+-
CiF VA
where
Ie = (2-138)
and
kT (CiFIe)
Vbe=-ln -- (2-139)
q Is
Substituting Eq. (2-138) into Eq. (2-137) yields
(Vi + Vbe ) 1 + Vee/VA
Ic = (2-140)
2.3 Single-Transistor Gain Stages 91
The unilateral two-port equivalent circuit shown in Fig. 2-38 may be used
to represent the small-signal behavior of the common-base stage; note the
direction of the collector current source relative to that in the CE two-port
equivalent circuit of Fig. 2-22. The small-signal input resistance Ri can be
obtained directly from Eq. (2-138):
dVi R8 dVbe
Ri= ---=RE+---+-- (2-141)
dIe I3F + 1 dIe
R8
R=RE+r +--- (2-142)
I e I3F + 1
(2-143)
which evaluates to
(2-144)
The output resistance rc seen looking into the collector of the CB transistor is
evaluated from the small-signal test circuit shown in Fig. 2-39; the common-
base equivalent circuit (Fig. 1-12) is used to model the transistor with the
collector current source being expressed in terms of the current i, in reo The
voltage Vx is equal to the voltage drop across ro plus the voltage drop across R E :
VX = (ix - (XFii) ro + [ix + (1 - (XF) i,] RE = ixCro + R E) + i, [(1 - (XF)R E - (XFr o]
(2-145)
92 Chapter 2 - Analog Integrated-Circuit Blocks
...:- rc
e +-__--"'\ C I
The current i) is
. Vb-Ve (uF-l)i)RB-[ix+(l+uF)idR E
1)=---= (2-146)
fe fe
fC =2=[1+
ix fe + (1
uFR E
- uF)(R B + R E )
Jf
0
(2-147)
(2-148)
Vee
Vee
------1'-------;--+--.... Vi
(a) (b)
Figurz 2-40 (a) Common-base gain stage with resistive load. (b) Voltage transfer
characteristic.
"tum-on" voltage of the base collector junction (about 0.5 V for a silicon
integrated-circuit BJT).
Taking the base-emitter voltage to be a constant VBE(on) for operation in the
active region and setting RB = 0, we have from Eq. (2-140)
_
1--
UF (Vi + VBE(On» ( 1 +Vee)
- (2-151)
C RE VA
where
(2-152)
Substituting Ie = (Vee - Vo)/Rc and Eq. (2-152) into Eq. (2-151) and solving for
the output voltage gives
(2-153)
Rc
Vo = Vee + UF(Vi + VBE(on»- (2-154)
RE
The small-signal voltage gain of the CB stage in Fig. 2-39(a) is
(2-155)
94 Chapter 2 - Analog Integrated-Circuit Blocks
G = 19.2mAN =6.58mAN
m 1 + (19.2 rnA N)(O. 1k0)
Using Eq. (2-155), the voltage gain is
A,. = (6.58mAN)(lOkO) = 65.8
2.3 Single-Transistor Gain Stages 95
Vee
II re f
Vi •
A common-base gain stage utilizing an active load is shown in Fig. 2-41. Like
the active-loaded common-emitter stage, this configuration also has a high
output resistance, resulting in high gain; the input resistance, however, is
low-a factor of 13 F + 1 lower than with an equivalent CE stage. The collector
current of Q I is
[ -
cl -
[
SI e
- qV;/kT
(1 + VV- V)
0
Al
I
(2-160)
The collector current le2 of the current source transistor is given by Eq. (2-79),
which, equated with lei and solved for the output voltage, yields
V =
Vee + VA2 [1 + (~-
VAl
1)~e
[ref
-QV;/kT]
o (2-161)
Except for the negative input voltage, this result is similar to that obtained for
the active-loaded CE stage [see Eq. (2-80)].
The small-signal voltage gain is
(2-162)
VDD
load element
I
Figure 2-42 Common-gate gain stage. R; and Ro represent the small-signal input
and output resistances, respectively.
Figure 2-42 shows a common-gate stage fashioned with NMOS, which func-
tions very similarly to the common-base stage. For the transistor operating in
the saturation region (V j < - VTH - IsRs and Va;::: - VTH ), the drain current is
given as
(2-165)
where
(2-166)
and
(2-167)
Substituting Eqs. (2-166) and (2-167) into Eq. (2-165) yields
The two-port equivalent circuit of Fig. 2-38 also applies for the common-
gate stage. The small-signal input resistance R j can be obtained directly from
Eq. (2-166):
dV j _ dVgs _ dVgs
Rj = - - - R s + - - - R s + - - (2-169)
dI, dIs dId
Noting that d1d/dVgs is the transistor transconductance gm gives
(2-170)
2.4 Two-Transistor Gain Stages 97
The first term on the right-hand side of Eq. (2-171) is gm and the last fraction
is Ri - I. This yields
(2-172)
Cascade Configuration
I c2
......."
_--:--0 Out
(a) (b)
Figure 2-43 (a) Cascode gain stage using BJTs. (b) Two-port small-signal equival-
ent circuit.
For the output resistance, we recognize that the output resistance of QI (rol) is
in series with the emitter of Q2; thus, Eq. (2-158) applies with "Re" = rol:
Ro= (I + 1 + gm2
gm2 r ol
rol/~F2
)r02 (2-176)
Vee
.,----0 Out
Figure 2-44 Emitter follower cascode. The bias current source for QI is optional.
For I bias = 0,
I - ~F2(~F1 + 1) I (2-182)
c2 - A cl
tJFl
which for identical transistors (~Fl = ~F2) gives r7l"1 = (~F + 1) r",2, and Eq. (2-181)
becomes
(2-183)
The effective transconductance of the emitter follower cascode is found from
1 dVj dV
be1 be2 be1 dV
be2 e2 dV dIc1 dV dI
- = -- =- - +-- =-- -- +-- -- (2-184)
Gm dIe3 dIe3 dIe3 dIe 1 dIe3 dIe2 dIe3
Neglecting base currents, we have dIe2 = dIe3 and dIc1 = dIb2 = dIe2 /~ F2 = dIe3 /~ F2.
Noting that dVbe/dIe = l/g m, Eq. (2-184) becomes
G = gmlgm2
(2-185)
m gml + gm2/~F2
For I bias = 0, gm2 = ~F2gml and
G = gm2 (2-186)
m 2
The small-signal output resistance Ro remains the same as given in Eq. (2-177).
The cascode gain stage fashioned with field-effect transistors is illustrated
in Fig. 2-45. In the JFET version [Fig. 2-45(b)], the input voltage is negative
and Vbias is set such that Vas2 is negative. Here, R j = 00. Because Idl = Id2 , the two-
port equivalent transconductance [Fig. 2-43(b)] is
(2-187)
100 Chapter 2 - Analog Integrated-Circuit Blocks
Out
I
M "'R o
I
+ 2
V bias_ y
In o--r-t~
I
R·---'
, I
(a) (b)
Figure 2-45 Cascode gain stage using FETs: (a) MOSFETS; (b) JFETs.
The output resistance is determined from Eq. (2-173) by setting "Rs" = rot and
rL = 00, giving
(2-188)
Cascade Configuration
Vee
Out
In 0-,--1
I bias CD
I
O2
(a) (b)
Figure 2-46 Common-collector-common-emitter cascade configuration. (a) Normal
connection with output taken at the collector of Q2' (b) Darlington connection with
the collectors of QI and Q2 tied together.
(2-190)
1 dVi
(2-191)
G = gmlgm2
(2-192)
m gml + gm2 / 13F2
The transcoductance for the Darlington configuration [Fig. 2-46(b)] is deter-
mined from
1 dVi dVi
-=--=----- (2-193 )
Vcc(10 V)
(20 kil)
.J---+-o Vo
I I
R·"'"
I I
~Ro
I
I bias
(100
Vee - Vo 10 V - S V = 2S0 A
fC2=--=~-::""
Rc 20 kfl J.1
Its transconductance is
and
Its transconductance is
0.101 rnA
gm! = 0.026 V = 3.88 rnA IV
2.4 Two-Transistor Gain Stages 103
and
100
r",1 = = 2S.8k!1
3.88mA/V
The input resistance, calculated from Eq. (2-181), is
Ri = 2S.8k!! + (l01)(10.4k!1) = 1.08M!1
The output resistance of Q2 is
VA2 SOV
ro2=-= =200k!1
Ic2 0.2S0mA
and the output resistance is
Ro = Rell ro2 = (20k!1) II (200k!!) = 18.2k!!
Using Eq. (2-18S), the transconductance of the amplifier is
G = (3.88mA/V)(9.62mA/V) =9.39mAN
m 3.88mA/V + (9.62 mA/V) 1100
The voltage gain is
Av= -GmRo= -(9.39mAN)(18.2k!!)= -171
The common-collector-common-collector (CC-CC) cascade configuration is
shown in Fig. 2-48. This configuration is used primarily as a buffer stage
Vee
I
R·~
cD
I I
----,.---t-<> Vo
I bias
I
--L
Figure 2-48 Common-collector-common-collector (CC-CC) cascade configuration.
'----+--r---....,.---o V0
(a)
+
vx
(b)
Figure 2-49 (a) Small-signal equivalent circuit of the CC-CC cascade. (b) Circuit
for calculating the small-signal output resistance.
the emitter of Q2. With reference to Fig. 2-49(a): the voltage at the emitter of
QI is V2 + Vo> so the base current of QI is
Vi - V2 - Vo
i bl =----- (2-194)
where
(2-195)
2.4 Two-Transistor Gain Stages 105
and
(2-196)
(2-197)
(2-198)
Av = ~ = _ _ _ _ _ _ _ _1_ _ _ _ _ _ __ (2-201)
Vi
1+ r"2 r"I
+ --------.::~---
(13F2 + l)RL (I3F' + 1)(13F2 + 1)RL
which for identical transistors and hia, = 0 becomes
(2-202)
Figure 2-49(b) shows the circuit for calculating the output resistance of the
CC-CC cascade. In normal application, the load RL represents the input resis-
tance of the next stage and so it is not included as part of the output resistance
of the CC-CC stage (the total resistance at the output is RoIIRL)' Summing the
currents at node (1),
(2-203)
where
(2-204)
(2-205)
106 Chapter 2 - Analog Integrated-Circuit Blocks
and
. V2
Ib2=- (2-206)
Tr 2 r
which combine to give
(~FI + I) r Tr 2
V2 =- v (2-207)
rTrI+(~FI+I)rTr2 x
. (~FI + 1)(~F2 + I)
Ix = Vx (2-209)
rTrI +(~FI + l)rTr2
The output resistance is
(2-211)
The input and output resistances of the CC-CC cascade can also be simply
obtained using the results of the single emitter follower, Fig. 2-31 (a). Consider
the node connecting the emitter of QI and the base of Q2. Looking into the base
of Q2 at this node, we see a resistance of r Tr2 + (~F2 + I)R L • This resistance at the
emitter of QI corresponds to the resistance" R£" in Fig. 2-31(a), giving an input
resistance
(2-212)
which is identical to Eq. (2-198). Looking back into the emitter of Qh we see
a resistance of rTrI /(~FI + 1). This resistance at the base of Q2 corresponds to the
resistance "R8" in Fig. 2-31(a), giving an output resistance
"R8" +r 2 Tr
Ro=---- (2-213)
~F2 + 1
Out
+V
In 0..-----1
Vgs -
+
® CD
I
I bias
Ibias
I
...L
( a) (b)
Figure 2-50 BiCMOS cascades: (a) Common-drain-common-collector configur-
ation; (b) Darlington configuration.
nite), two-transistor cascade configurations are rarely used in all FET circuits.
However, in circuits fabricated with both BJTs and MOSFETs (tenned Bi-
CMOS) or BJTs and JFETs (tenned BiFET) several mixed two-transistor
cascade configurations find useful application. Figure 2-S0 shows two Bi-
CMOS cascades: (a) a common-drain-common-collector (CD-CC) configur-
ation; (b) a Darlington configuration. The CD-CC configuration in Fig. 2-S0(a)
is used as a unity-gain buffer circuit with infinite input resistance. From the
circuit,
(2-214)
(2-21S)
which, combined with the load resistance, gives the small-signal voltage gain
(2-216)
(a) (b)
Figure 2-51 (a) PMOS-npn BJT cascade. (b) Composite equivalent.
ductance is calculated in a fashion similar to that for the all bipolar version
[Fig. 2-46 (b)], giving
(2-217)
The small-signal resistance seen looking into the drain of MI is (1 + g~ET r ... ) r~ET
[see Eq. (2-158) with I3F = 00] and the resistance seen looking into the collector
of Q I is r!fT. Thus, the small-signal resistance at the output of the BiCMOS
Darlington stage is
The PMOS-npn BJT cascade shown in Fig. 2-51(a) has interesting charac-
teristics [7, 8]. The base current in QI is set by the drain current in Mb which
is determined by the input applied across the gate and source. The output
current is
(2-219)
(2-220)
(2-221)
2.4 Two-Transistor Gain Stages 109
-t--~-----t------------,~ VCE
VBE(On) VBE(On)+IVOsatl
Substituting Egs. (2-220) and (2-221), with Vsd = Vee - Vbe = Vee, into Eg. (2-219),
and neglecting the cross-product tenn containing AIVA gives approximately
(2-222)
where
VA
VAeff = - - - (2-223)
1 + AVA
The output current thus appears to be that of the PMOS device multiplied by
a factor of I3F + 1. The composite equivalent shown in Fig. 2-51(b) may be
used to represent the PMOS-npn BJT cascade. This equivalent can be viewed
as a PMOS transistor with an effective W IL ratio that is (13 F + 1) times larger
than the actual PMOS device in the cascade. This equivalence must not be
taken too literally, however; Figure 2-52 shows the output characteristics of
the PMOS-npn BJT cascade, showing an offset of VBE(On) in the output voltage
characteristic.
The small-signal equivalent transconductance of the composite (for MI III
saturation and QI in the forward-active region) is
(2-224)
(2-225)
110 Chapter 2 - Analog Integrated-Circuit Blocks
Vss
(a) (b)
+1 d2
Vss
(c)
Figure 2-53 Differential-pair configuration: (a) using BJTs; (b) using MOSFETs;
(c) using JFETs.
Differential-pair gain stages are used widely in many monolithic analog cir-
cuits: operational amplifiers. comparators, and voltage regulators, to name a
few. The basic differential pair, illustrated in Fig. 2-53, consists of two emitter-
coupled (source-coupled) transistors with inputs applied to each base (gate) and
outputs taken at either or both collectors (drains). A current source is com-
monly used to bias the common-emitter (source) node, although a resistor can
also be used (with degraded amplifier characteristics). The symmetry between
the two branches of the differential pair provides for balanced operation of the
circuit in which inputs applied differentially are amplified and those applied
in common (to both inputs) are rejected [9]. In this section, we present the
characteristics of the differential-pair configuration using both bipolar and
field-effect transistors.
2.4 Two-Transistor Gain Stages 111
Consider the BJT differential pair shown in Fig. 2-53(a). The biasing current
source, lEE, is assumed initially to be ideal-the effects of a finite output
resistance of the actual current source will be considered later. Summing the
currents at the common-emitter node, and assuming identical transistors, we
have
(2-226)
Summing the voltages around the base-emitter loop of the two transistors gives
(2-228)
or
(2-229)
where V id denotes the difference of the two inputs, the differential input voltage.
The two collector currents thus scale as
(2-230)
(2-231)
(2-232)
(2-233)
112 Chapter 2 - Analog Integrated-Circuit Blocks
1.0 r--=::----,,---.,.----,.--:::::I::=--,
i
0.5 I - - - + - - - I - - - - l t - - - + - - - t - - - - \
0.0 '--_=:t::~.......J:...................J...o........o....I.-'-'~::t:::._....
-6 -4 -2 6
Figure 2-54 Collector currents as a function of differential input voltage for the
bipolar differential pair.
The slope of the Io-Vid characteristic represents the effective differential trans-
conductance:
(2-234)
dIn I (2-235)
dVid V,d=O
where ICQ represents the quiescent collector current of either transistor. The
maximum effective differential transconductance of the differential pair is thus
equal to the transistor transconductance.
For the MOSFET differential pair [Fig. 2-53(b)], summing the currents at the
common-source node gives
(2-236)
where, for operation in the saturation region, assuming identical transistors and
neglecting channel-length modulation,
Id2 2 - (W)
= -JJ.nC~x L (Vgs2 - VTH )
2
(2-237)
2.4 Two-Transistor Gain Stages 113
Combining Eqs. (2-236) and (2-239) and solving the resulting quadratic equa-
tion gives the drain currents as a function of the differential input voltage:
and
The maximum drain current that either transistor can have is Iss and occurs
when V id is large enough such that one transistor is off and the other is
conducting the full bias current. Using Eq. (2-239), the range in V id for which
Eqs. (2-240) and (2-241) remain valid is
- J/-Ln Cox2/ss
, J 2/ss
< Vid < -------:,-------:- (2-242)
(W IL) /-Ln Cox (W IL)
Unlike the bipolar differential pair in which the input voltage range depends
only on temperature, the input range for the MOSFET differential pair depends
on device geometry as well as bias current; typical input ranges are from 1 to
3 y. Taking the differential output current 10 = Id! - I d2 , we have
G d=
m
~
dV
= /-Ln C~x (W) J
id 2 L
4/ss
/-Ln C;x (W IL)
- V2d
I
[1-
4/ss 2
(2-244)
114 Chapter 2 - Analog Integrated-Circuit Blocks
1.0
/
/
V
0.5
t
10
/
0.0
Iss
-0.5
/
-1.0
-1.0
/ -0.5 0.0 0.5 1.0
V id
2ISS
-.
IlnCox (WIL)
(2-245)
Like the bipolar differential pair, the maximum effective differential transcon-
ductance of the MOSFET differential pair is equal to the quiescent transcon-
ductance of the transistor.
2Iss V~ 2
----Vid (2-246)
I Dss
and
2Iss V~
2
----Vid (2-247)
I Dss
2.4 Two-Transistor Gain Stages 115
The maximum drain current of either JFET in the pair is I DSS ; the resulting
differential input voltage range is
~
-SS- Vp<V
I DSS
id < - ~SS
- - Vp
I DSS
(2-248)
Resistor Load
1.0
~
~
i
Vod
0.5
\
0.0
1\
apIEERC
"
·0.5
·1.0
~
·6 ·4 ·2 o 2 4 6
and
(2-252)
Using Eq. (2-233), the differential output voltage is
which is plotted (in normalized form) in Fig. 2-57. Note that Vod is zero when
V id is zero; this allows differential gain stages to be directly cascaded together
without introducing dc offset voltages, and thereby not requiring dc level
shifting.
The range in input voltage over which the transfer characteristic in Fig. 2-57
is approximately linear is limited to about V id = ± kT/q. This linear range can
be extended by adding resistors in the emitter legs of the differential pair, as
illustrated in Fig. 2-58. This causes emitter degeneration and the "linear" range
is thereby increased by the voltage drop across the two resistors of lEE R E; the
voltage gain of the differential pair is, of course, reduced. Summing the
voltages around the base-emitter loop in Fig. 2-58 gives
(2-254)
For lEE RE ~ kT /q, the difference in the two base-emitter voltages will be small
compared to the leRE voltage drops allowing Vbel and Vbe2 to be taken as approxi-
mately equal in Eq. (2-254). Thus,
(2-255)
2.4 Two-Transistor Gain Stages 117
Using Eq. (2-255), combined with Eq. (2-226), gives for the collector currents
(2-256)
from which
(2-257)
which is valid for V id < lEE R E• The differential voltage gain in this case is deter-
mined by the ratio of the collector-load and emitter-degeneration resistances,
independent of the bias current of the pair.
The symmetry of the differential amplifier configuration allows the small-
signal response to be determined by splitting the amplifier into two equivalent
circuits, each of which is simpler than the original circuit. To do so, we decom-
pose the small-signal input voltages, Vii and ViZ, into two components: differential
and common; the total response is then given by the superposition of the
differential-mode and common-mode responses. With this in mind, we define
Tv~: ::;dT
vi 1 Vi2
1 1
VEE
+
Vic
-
Figure 2-59 Differential pair with small-signal differential-mode and common-
mode inputs.
Vid
VI
I
=-+
2 v IC
(2-260)
and
Vid
Vi2 == --+V
2 IC
(2-261)
This is illustrated for the differential amplifier shown in Fig. 2-59, where the
current biasing transistor is represented by a current source lEE and a resistance
REE, representing the output resistance of the current source transistor. Vid is the
desired signal applied differentially at the input. Vic represents a signal that is
applied in common to both inputs, usually arising from noise or other ex-
traneous signals that enter the amplifier circuit; a measure of the performance
of a differential amplifier is the degree by which common-mode input signals
are rejected compared to the degree by which differential-mode input signals
are amplified.
2.4 Two-Transistor Gain Stages 119
+---ovod1
+
vid
2
(a)
(b)
Figure 2-60 (a) Differential-mode half-circuit. (b) Small-signal equivalent circuit.
Consider first the circuit with only small-signal differential inputs applied:
input + VidJ2 applied to QI and input - Vid/2 applied to Q2. As Vid goes positive
the emitter current of QI will increase by a small amount above its quiescent
value (of approximately h E /2), whereas the emitter current of Q2 will decrease
below its quiescent value by the same amount. As a result, the potential Ve at
the common emitter node will remain constant and equal to its quiescent value,
denoted V EQ ; as far as the differential response is concerned, the common emitter
node potential can be set to VEQ (approximately - 0.7 V in value) without any
change in circuit response. The resulting circuit can be split into two halves,
each half (called the differential-mode half-circuit) representing the circuit that
describes the response to a differential input voltage. Figure 2-60(a) shows the
differential-mode half-circuit for QI. The corresponding small-signal equivalent
circuit is given in Fig. 2-60(b). From the circuit, the small-signal differential
output voltage at the collector of QI is
Vid
Vodl = - gmRcT (2-262)
120 Chapter 2 - Analog Integrated-Circuit Blocks
4-----a v oc
Vic
+
.......--x-
(a)
RC
(b)
Figure 2-61 (a) Common-mode half-circuit. (b) Small-signal equivalent circuit.
The right-hand side of the differential pair is identical except for the opposite
input polarity; the corresponding output at the collector of Q2 is
(2-263)
A vd -- Vodl - Vod2 -
-
-
gm
R
C (2-264)
Vid
Consider now the circuit with only a common-mode input. With Vic applied
to both inputs, each side conducts equally and the circuit can be split into two
halves without altering the response. The common-mode half-circuit is shown
in Fig. 2-6J(a), and the corresponding small-signal equivalent circuit is illus-
2.4 Two-Transistor Gain Stages 121
trated in Fig. 2-61(b). From the circuit, the small-signal common-mode output
voltage is
(2-265)
where
r" (2-266)
VI = Vie
r,,+2([3F+ l)REE
which substituted into Eq. (2-265) gives the common-mode voltage gain
CMRR = 1 + 2g m R EE ( 1 + ~J (2-269)
Figure 2-62 Equivalent circuit for the input resistance of the bipolar differential
pair.
The input resistance of the differential pair can be represented by the equiv-
alent circuit illustrated in Fig. 2-62.
+ 15 V
- 15 V
A = - (16.6mAIV)(10kO) = - 0.0576
ve 1 + (2)(16.6mAlV)(85.9kO)(1 + 11100)
and the common-mode rejection ratio is
Avd - 166
CMRR = Ave = _ 0.0576 = 2882 or 69.2dB
Vee
- 0.0_ _ _ , - - - - - 1 - - - - -
I bias $ $ I bias
G md = (2-275)
G d = gmi (2-276)
m 2
and
(2-277)
Active Load
A bipolar differential pair with an active load is illustrated in Fig. 2-65. Here,
the reference current for Q3 is set by the collector current of QI; under quiescent
conditions, lref = aFhEI2. This circuit with a large-value load resistance at the
output has a large voltage gain, requiring only a small input signal (usually
considerably less than kT /q in magnitude) to drive the output to its full
operating range. For V id "large" negative, Qi is off and Q2 conducts the full bias
current lEE, saturating with the output at approximately - VBC(on)' For V id "large"
positive, Q2 is off and Q, conducts the full-bias current; Q4 is saturated (at very
2.4 Two-Transistor Gain Stages 125
Vee
t---<>Vo
low current) and the output is at Vcc - VCE(sat). In between, all transistors are operat-
ing in the active region. Writing the collector currents for the active region,
[ c3 = [PNP
S eQV' b3 IkT(1 + VeC3)
PNP
VA
(2-278)
where we have assumed the NPN transistors to be identical, likewise for the
PNP transistors, and have taken both Early voltages V~PN and V~NP to be positive
quantities. From the circuit,
where we have taken Veb3 and Vbel to be equal because lei and Ic3 are approximate-
ly equal. For Q2,
126 Chapter 2 - Analog Integrated-Circuit Blocks
Using Eq. (2-278) to express the ratio of the collector currents of the differ-
ential-pair transistors, we have
1 + veelv;iPN
(2-279)
Ic3 1 + VBE(on)IV~NP
(2-280)
Ic4 1 + (Vee - Va) IV~NP
Now, (·2 = (4, and neglecting base currents, lei = le3' Thus, equating Eqs. (2-279)
and (2-280) we have
(2-281)
(2-284)
2.4 Two-Transistor Gain Stages 127
Vcc- VBE(on)
Figure 2-66 Voltage transfer characteristic for the active-loaded differential pair.
For Vid « 2kT (which is generally true for the operating range of the active-
loaded differential pair), tanh (q Vid /2kn = q Vid /2kT, giving a result identical to
Eq. (2-284).
The slope of the transfer characteristic gives the small-signal voltage gain.
Using Eq. (2-284), we obtain
dVo Q v1PN V~NP
(2-286)
dVid = kT v1PN + V~NP
(2-287)
~ = G md (NPN II
fo
PNP)
fo (2-288)
Vid
where Gmd is given by Eq. (2-235) and equals the transconductance gm of the pair
transistors, and the voltage gain is the same as that obtained in Eq. (2-287).
128 Chapter 2 - Analog Integrated-Circuit Blocks
+
PNP
ro Vo
Figure 2-67 Small-signal equivalent circuit for the active-loaded differential pair.
i oem = 0
---+
V - --2-
od - L RD V J J.Ln C~x4/ss(W IL) _V
J.Ln C~x (W)
id
2
id
(2-291)
2.4 Two-Transistor Gain Stages 129
Voo Voo
RO
V01 V0 2
+0---1 +0---1
Vid
_ 0 ~
Vs Vid
_ 0
Vss Vss
(a) (b)
Figure 2-69 NMOS differential pair: (a) fixed resistance load; (b) saturated
NMOS load.
Vodl = (2-292)
(2-293)
(2-294)
d
.-------1---0 v od1
RD
- S
(a)
RD
Figure 2-70 Small-signal equivalent circuits for the resistive-loaded NMOS dif-
ferential pair: (a) differential mode; (b) common mode. The resistance Rss repre-
sents the output resistance of the bias current source Iss.
Idl
I-Ln C~x (
= --2- L
W) I (Vgsl - VTH ) 2
Id3 = - C~x
I-Ln- - -- (W) (VDD - Vol - VTH ) 2
2 L 3
Id4
I-Ln-
=- - (W)
C~x - (VDD - Vo2 - VTH ) 2 (2-296)
2 L 4
2.4 Two-Transistor Gain Stages 131
(WIL) I
- - - (Vgs1 - VTH ) (2-297)
(WILh
v -
02 -
V
DD
- V
TH
_ I (WILh
V (W IL)4 (Vgs2 - V TH ) (2-298)
(W IL)] V (2-299)
(WILh ,d
where we have assumed that the channel width-to-Iength ratios (W IL) of the
differential-pair transistors (M] and M 2) are equal as are those of the load
transistors (M3 and M4)'
It can be easily shown that the small-signal differential-mode voltage gain
is given by
gml (WIL) I
(2-300)
gm3 (WILh
A = _ gm] (2-301)
em gm3 (l + 2gm! Rss)
(2-302)
M4
+---00 Vo
+0---1
- 0>--------1
Vss
Figure 2-71 CMOS differential pair with active load.
Vo
V+
+
--.
lin
+ V in
Vin Vo
~
-=- V-
(a) (b)
lin 10
Ro= 0
Rin= =
Vin Vo
(c) (d)
stage at the input to the output stage; in an actual output stage, its input
resistance should be high.
The nearly linear transfer characteristic and low output resistance of an emitter
follower make it ideal for use in an output stage. Figure 2-73(a) shows an
output stage using a single emitter follower. Q2 is a current-source transistor
which provides a bias current IQ for the emitter of Qj. This arrangement keeps
the bias current out of the load resistance which otherwise would result in
significant quiescent standby power being dissipated in the load. From the
circuit,
(2-305)
134 Chapter 2 - Analog Integrated-Circuit Blocks
Vee VDD
(a) (b)
Figure 2-73 (a) Emitter follower output stage. (b) Source follower output stage.
where
(2-307)
--------------------+-~~------------------~Vin
Q1 0ff
RL1-----~
RL2--------~. ________ _
VEE + V CE(sat)
Figure 2-74 Voltage transfer characteristic for the emitter follower output stage
of Fig. 2-73(a) depicting two different values of RdRL2 > R Ll ).
This circuit, like all Class A-type stages, suffers from low-power efficiency;
this is because the bias current IQ flows in both Ql and Q2 at zero output,
resulting in a standby quiescent power dissipation of (Vee - VEE)/Q' The maximum
power efficiency is limited to about 25%.
A source follower output stage using MOSFETs is shown in Fig. 2-73(b).
For this circuit,
where
(2-309)
resulting in
2(/Q+ VnIR L )
(2-310)
J.1n C~x (W IL)I = Vin - VTH
The low-power efficiency of the Class A-type stage can be improved by using
complementary devices in a push-pull configuration. Figure 2-75(a) illustrates
a complementary output stage using npn and pnp emitter followers operating
in Class AB. The two diode-connected transistors QI and Q2 provide a 2Vbe
voltage drop between the bases of Q3 and Q4; at zero output (VO = 0), both output
devices are biased slightly on with a quiescent current I Q• This arrangement
eliminates the "dead-band" (and the resulting crossover distortion) in the
transfer characteristic that would otherwise occur due to the positive Vbe re-
quired for Q3 to conduct and the negative Vbe required for Q4 to conduct.
Starting from Vo = 0, as V in is increased, the voltage at the base of Q4 is
increased, causing Q4 to conduct less; at the same time, the voltage at the base
of Q3 is increased due to the constant voltage drop across the two forward-
biased diodes QI and Q2, causing Q3 to conduct more heavily. With increasing
input voltage, Q4 turns off and Q3 sources the full output current to the load.
For a positive output, Q4 is essentially off and Q3 is on, giving
Vo = V in + Veb2 + V bel - Vbe3 = V in + VBE(on) (2-311)
The small-signal input resistance of the output stage for Vo positive is approxi-
mately
(2-312)
Vss
(a) (b)
-kT In (hi"
- ) +-
kT In (-hi'" ) =kT
- In (-I Q ) +-
kT In (-I Q ) (2-316)
q IS1 q IS2 q IS3 q IS4
from which
(2-317)
Vee
Vi n 0---+----/
Figure 2-76 Improved Class AB output stage with complementary emitter fol-
lower crossover distortion compensation.
138 Chapter 2 - Analog Integrated-Circuit Blocks
resulting in very little offset between input and output. This stage also has a
higher input resistance; for Vo positive,
(2-318)
and for Vo negative,
(2-319)
(2-320)
where, assuming equal threshold voltages and gate-oxide thicknesses for the
NMOS transistors and likewise for the PMOS transistors, gives
J 21Q
+ /-Lp C~xp (W IL)4
(2-323)
Solving for I Q,
Vee (+15V)
+
.1 0
Yin 10X
+
R1 RL
(30kn) Vo
(500n)
10X
VEE (-1 5 V)
(a) Summing the base-emitter and gate-source voltages around the loop
containing M], Qz, M z, and Qs gives
Neglecting base currents, we have Idl = IbiaJ[3F and IdZ = I Q I[3F, which used in the
expression for the source-gate voltages yields
-kT
I n (IQ
-- Isz) + J 21Q = J 2hias (3-325)
q hias Iss [3F/-LpC~x(WILh [3F/-LpC~x(WIL)1
From the circuit, Ibias = I ref (/s4 Ils3 ), where I ref = (Vce - VEE - VBE(On)IR I = 977 /-LA,
giving I bias = 195 /-LA. Substituting into Eq. (2-325) provides
0.026 In ( IQ 1) + J(100)(25)(20/2)
195 /-LA 10
21 Q =
(2)(195)
(100) (25) (100/2)
this point Vo- = VEE + VCE4 (sat) + Vsg2 ' The source-gate voltage of M2 is given by
V - - V + J 21d2
sg2 - TH
f.Lp c'ox (WIL) 2
where Id2 = le2/~F and le2 = - VoIRL' which at maximum negative output is ap-
proximately VEE. So le2 = - VEEIR L = 15V/0.5kO = 30mA, giving IdZ = 30 mAl
100 = 300 f.LA. The source-gate voltage of M2 is then
Plots of Yo> le5, and 1c6 versus Yin are presented in Fig. 2-78. From the plot, the
maximum Vo+ and Vo- are about 13.5 and - 12.5 V, respectively. The quiescent
2.5 Output Stages 141
I
I
OVt t
I
I
I
-15V + - - - - - - - - - + - - - - - - - - - + - - - - - - - - -+- - - - - - - - - -+- - - - - - - -- + - - - - - - - - - +
o V(7)
30mA +--------- + - - - - - - - - - +- -- - - - - - - -+- - - - - - - -- -+-- - - - - - - - + - -- - - - - - - +
I I
I
I
G ./
20mA~ .~:
. . . .
·
. .. 0'" +I
I
· • I
I
· . I
• . . , .
I
10mAt t
Figure 2-78 PSPICE plot of BiCMOS output stage characteristics. Upper curve:
Vo versus Vin- Lower curves: 1<5 and 1c6 versus V in -
currents from the simulation are fc4 (fbias ) = 193~, fc5 = 171J.1A, and fc6 = 173~,
all of which agree well with those calculated by hand.
142 Chapter 2 - Analog Integrated-Circuit Blocks
Problems
Figure 2-79 Base-current compensation of basic current mirror for Problem 2.1.
2.2 Show that the output resistance of the Wilson current source, Fig. 2-11, is
given by Eq. (2-22).
2.3 Show that the output resistance of the NMOS Wilson current mirror, Fig.
2-13(a), is given by Eq. (2-25).
2.4 In the current source of Fig. 2-80, neglecting base currents, show that
A3 A S
I =--1 f
o AI A 4 re
05
I ref.
(a)
Figure 2-81 Current source for Problem 2.5.
(b) Simulate this circuit using SPICE (or equivalent circuit simulator) to
show a plot of 12 versus V e2 (the collector voltage of Q2) for Vez ranging from
o to 10 V. From your results, determine the output resistance of the current
source and compare with that calculated using Eq. (2-22). Take for the
circuit, Vee = 10 V and R = 10 kil. Note: Because of the high output resis-
tance of this circuit, you will need to reduce the tolerance in the SPICE
program to get an accurate simulation. To do so, add the following
statement in your SPICE file: .OPTIONS RELTOL = .00001
2.7 Find the output current and output resistance for the Widlar current source
of Fig. 2-16. The transistors are identical. Circuit parameters: Vee = lOY,
Rref = 20 kil, and Rz = 1 kil.
2.8 Find the output current 12 and the output resistance of the current source
shown in Fig. 2-82. The pnp transistors are identical except for their
emitter areas, as indicated.
144 Chapter 2 - Analog Integrated-Circuit Blocks
+ 10 V
Figure 2-82 Current source for Problem 2.8. nx denotes relative emitter areas.
Vee
2.9 Find V2 relative to VI for the npn-pnp level-shift stage of Fig. 2-83. You
may neglect base currents and take Vbe = VBE(on)'
2.10 Neglecting base current, show that for the VBE multiplier circuit of Fig.
2-84,
Problems 145
2.11 (a) Derive an expression for the voltage transfer characteristic (Vo versus
V;) of the inverting amplifier circuit of Fig. 2-85. Base current may be
neglected.
(b) Sketch the transfer characteristic for Vi ranging from 0 to + Vee.
(c) This circuit can be used as a unity-gain inverting amplifier for proper
values of Rl and R 2• Determine this relation.
2.12 Derive an expression that gives the large-signal transfer characteristic (VO
as a function of Vi) for the common-emitter gain stage of Fig. 2-24 with
RB = O. Do not neglect the Early effect; use the Early voltage VA in your
analysis. What does the characteristic become for VA ~ 00 ?
2.13 Figure 2-86 shows a common-emitter amplifier with diode biasing. Tak-
ing Vbe = VBE(on), detennine an expression for the output voltage V", assuming
146 Chapter 2 - Analog Integrated-Circuit Blocks
Vec
Vi
Figure 2-86 Diode-biased common-emitter gain stage for Problem 2.13.
Vee
+
Vi
2.15 The emitter follower stage of Fig. 2-31 is biased at Vi = Vee/2. Determine
the output voltage Va' the small-signal input resistance, output resistance,
and voltage gain. Take for the circuit, Vee = IOV, R8 = 5oon, and
R£ = 1 kn. You may take Vbe = VSE(on) = 0.7 V.
2.16 Verify that the small-signal output resistance of the common-gate gain
stage of Fig. 2-42 is given by Eq. (2-173).
Problems 147
+ 15 V
2.17 For the cascade amplifier in Fig. 2-88 determine the quiescent (@ Vi = 0)
output voltage Va, the small-signal input resistance R;, output resistance Roo
and the voltage gain Va/Vi. Neglect the Early effect for Qj, but not for Q2.
2.18 Determine the quiescent (@ Vi = 0) collector current in Qj, drain current
in M j, output voltage Va, and the small-signal voltage gain Va /V i for the
BiCMOS Darlington stage shown in Fig. 2-89. Take Vbe = VBE(on) = 0.7 V
for Qj.
+ 15 V
3 kQ
r----r--o Vo
v~f
- R
1
+ S
Vbia~ 2.5 V
2.19 The /-LA 701 cascode amplifier circuit is shown in Fig. 2-90.
(a) Find the dc collector currents in the transistors and the output voltage
Va. Base currents may be neglected. Refer to Problem 2.13 for inspiration.
148 Chapter 2 - Analog Integrated-Circuit Blocks
Vee (+10 V)
t----r--o Va
I
Rs ~Ro
3 kQ
(b) Determine the small-signal input and output resistance, and the volt-
age gain Va Iv; for the amplifier.
2.20 For the emitter follower common-base cascode circuit of Fig. 2-91 de-
termine the small-signal input resistance R;, output resistance Rm and the
R~
I
Figure 2-91 Emitter follower common-base cascode circuit for Problem 2.20.
Problems 149
Vee Vee
2.21 Carry out the analysis for the drain currents in a JFET differential pair
leading to Eqs. (2-246) and (2-247).
assuming I3F ~ 1.
(b) Show that the corresponding common-mode rejection ratio becomes
2.23 Show that the two differential gain stages in Fig. 2-92 are equivalent.
Consider both the differential-mode and common-mode response. As-
sume that the output resistances of the current source transistors are much
larger than R E•
2.24 (a) Show for the single-ended amplifier of Fig. 2-93 that Va = ( - AVd +
Ave) v;l2. Neglect the output resistances of the differential-pair transistors.
150 Chapter 2 - Analog Integrated-Circuit Blocks
Vee
VEE
Figure 2-93 Single-ended differential-pair amplifier for Problem 2.24.
(b) Show that the maximum voltage gain (vo/v;) is equal to qVee/kT. Under
what conditions is this maximum gain reached?
2.27 (a) Determine the differential-mode and common-mode voltage gains, the
common-mode rejection ratio, and the differential-mode and common-
mode input resistances of Fig. 2-58 with Rc = 10 kn, RE = 250 n, and
hE = 500 J..LA. Neglect VA for QI and Q2, but not for Q3. Compare the value
of AVd with that evaluated using Eq. (2-257), explaining any discrepancy.
(b) Determine the range in common-mode input voltage over which
transistors QI-Q3 remain active with Vee = + 10 V and VEE = - 10 V. Take
VBE(on) = 0.7 V and VeE(Sat) = 0.2 V.
Problems 151
Vee (+10 V)
VEE (-10 V)
2.28 Consider the active-loaded differential pair of Fig. 2-65 with a load
resistance RL connected to the output. Show that, neglecting transistor
base currents and Early effect, the voltage transfer characteristic is given
by
V DD
+----0 Vo
Vss
(b)
Figure 2-96 BiCMOS differential gain stages for Problem 2.31.
2.32 Consider the emitter follower output stage of Fig. 2-73(a). The linearity
in the transfer characteristic can be calculated as Vo/(Vin - VBE(On)).
(a) Taking
Problems 153
Linearity = - - - - - - - - -
1 +kT- In (1 +--Vo)
qVo IQRL
Linearity = ----;=======---;=====,---
1 +_1 J__ [j
2I....:::...Q_
Vo f-lnC~x(W/L)l
1 + Vo -1]
IQRL
where
Calculate the linearity for the same circuit parameters as the emitter
follower stage. Take W IL = 300 for the MOSFETs.
2.34 For the output stage shown in Fig. 2-97 determine and carefully sketch
(including breakpoints, axis intercepts, slopes, etc.) the transfer charac-
teristic Vou , versus Vin for V in ranging from - 6 to + 6 V. You may neglect
base currents and take IVHE(on)1 =0.7V and IVCE(sat)1 =0.2V.
+5V
Vee
10 X
t---o V out
10 X
Figure 2-98 741 op amp output stage for Problem 2.35. Transistors Q4 and Qs are
identical to their npn and pnp counterparts, but have 10 times the emitter areas.
2.35 A simplified schematic of the 741 op amp output stage is shown in Fig.
2-98.
(a) Show that at Vo = 0, the quiescent bias current of the output transistors
is given approximately by
[
Q
=[
blas
Fl!Jjf
Q
1-'F2
54[55
[[
51 52
(b) What is the maximum value for [bias if the quiescent power dissipation
in the output stage is limited to 12 mW? Take Vee = 15 V and VEE = - 15 V.
(c) Assuming VEE < V in < Vee, sketch the transfer characteristic VOU! verses
V in for Vin ranging from - 15 V to + 15 V Assume VBE(on) = 0.7 V.
2.36 A simplified schematic of the 1530 op amp output stage is shown in Fig.
2-99.
(a) Describe qualitatively the operation of the circuit, including the maxi-
mum and minimum values for Vo.
(b) Determine the quiescent collector current [Q and the corresponding
input voltage ViQ at Va = 0
(c) Determine the small-signal voltage gain Va/Vi for Vi near ViQ. Neglect VA'
(d) Simulate the circuit using SPICE to verify your analysis. Show a plot
of Va versus V;.
Problems 155
VEE (-15 V)
Figure 2-99 1530 op amp output stage for Problem 2.36 nX denotes relative
emitter areas.
2.37 Repeat the example of Fig. 2-77 using the modified BiCMOS output
stage shown in Fig. 2-100. Explain any differences found with this circuit
compared to the example circuit.
Vee (+15V)
10X
R1
RL
(30kQ) (500Q)
10X
VEE (-15 V)
Figure 2-100 Class AB BiCMOS output stage for Problem 2-37. nx denotes rela-
tive emitter areas of the bipolar transistors; the fractions denote the channel-width
and channel-length dimensional WIL (fJ.m), respectively, the PMOS transistor.
156 Chapter 2 - Analog Integrated-Circuit Blocks
References
1. G.R. Wilson, "A Monolithic Junction FET-NPN Operational Amplifier," IEEE J. Solid State
Circuits, SC-3, 341-348 (1968).
2. R.I. Widlar, "Some Circuit Design Techniques for Linear Integrated Circuits," IEEE Trans.
Circuit Theory, CT-12, pp. 586-590 (1965).
3. A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, Wiley, New York, 1984,
Chap. 4.
4. P.R. Gray and RG. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., Wiley,
New York, 1993, p. 215.
5. A.S. Sedra and K.c. Smith, Microelectronic Circuits, 2nd ed., Holt, Rinehart and Winston,
New York, 1987, Chaps. 2 and 7.
6. A.S. Grove, Physics and Technology of Semiconductor Devices, Wiley, New York, 1967, pp.
230--233.
7. K. Tsugaru, Y. Sugimoto, M. Noda, and T. Ito, "A Single-Power-Supply lO-b Video BiCMOS
Sample-and-Hold IC," IEEE J. Solid State Circuits, 25, 653-659 (1990).
8. P.R Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., Wiley,
New York, 1993, p. 399.
9. L.I. Giacoletto, Differential Amplifiers, Wiley, New York, 1970, p. 5.
10. P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., Wiley,
New York, 1993, pp. 299-301.
11. Y.S. Choi, BiCMOS Operational Amplifier Design, Ph.D. Dissertation, Arizona State Univer-
sity, 1993, p. 37.
12. K. Fukahori, Y. Nishikawa, and A.R Hamade, "A High Precision Micropower Operational
Amplifier," IEEE J. Solid State Circuits, SC-/4 (1979).
Chapter 3
Operational Amplifiers
157
158 Chapter 3 - Operational Amplifiers
a(fO) = {' 00 )
1+J -00
0
(3-5)
The product of the open-loop gain and 3-dB bandwidth a o Wo represents the
unity-gain frequency WT' The gain-versus-frequency characteristics of the volt-
age-feedback amplifier are sketched in Fig. 3-2. Note the gain-bandwidth
trade-off: Avof - 3dB = fT.
3.1 Voltage-Feedback Amplifiers 159
+
Vi
(a)
gain (dB)
ao+----'lo..
( 1)
Avo+~-----~L-----~
-- ......,_--- ....., -
I
(2)' ,
Avo
Single-Stage Op-Amp
+
Yin
of the input gain stage and is assumed to dominate the frequency response of
the amplifier. The low-frequency open-loop gain is
(3-6)
where Gml is the effective transconductance of the input stage, Rol is the output
resistance of the input stage and Ri2 is the input resistance of the output stage.
The open-loop - 3-dB frequency is
1
w =----- (3-7)
o (R oI IIR i2 ) Cc
(3-8)
(3-9)
and
(3-10)
G R _ VA(eff)
ml 01 - -k-T-Iq- (3-11)
where
(3-12)
3.1 Voltage-Feedback Amplifiers 161
,----------------, Vee
,,
1___________ - - - - - - - - - ,
1
,
fa:,,
1
1°3
1
1
1
1
1
1
,
Vin
+0-:
1
1
°7 :,,
o
1
1 +--.;-.'-0 'lout
The voltage gain of the input stage is thus determined by the ratio of the
effective Early voltage of the input stage transistors to the thermal voltage.
Assuming a worst-case condition with a short circuit at the output, the input
resistance of the output stage is
(3-13)
Ri2 = ~~PN~[IQ
qlQ 12
+~NPNII (~+
12
~PNP)] (3-14)
Normally, the quiescent bias current (IQ) in the output transistors is of the same
order as the bias current 12 • Thus,
Ri2 = ~NPN-I-
3 kT ( 1~ ) (3-15)
q Q 1+ NPN
~PNP
and is typically much larger than the output resistance of the input stage (R al ).
The voltage gain of the output stage is approximately unity, giving for the
overall low-frequency open-loop gain of the amplifier:
VA (eff)
a =--- (3-16)
o kT/q
162 Chapter 3 - Operational Amplifiers
,-----------------------------,
vee
--------------,
I I
,,
I I I I
I I
I
,,
I
I I
,,,
I
I
I
,,
I
I
I
I
I I
+ 0-:--1----1_--, :-0 Vo
v.In I
I ,
I
,,,
I
I ,
,
I
I I
I
I '
: VEE I I
a-. ____________ __,
~------------------------------
Figure 3-S Simplified schematic of the HA-2S00 single-stage op-amp.
As an example, if the NPN and PNP Early voltages are 100 Veach, then at
room temperature, a o = 50 V/0.025 V = 2000 (or 66 dB).
A simplified schematic of the HA-2500 single-stage operational amplifier is
shown in Fig. 3-5. In the input stage, the cascode connections of QI-Q4 and
QrQ3 fonn a folded-cascode differential amplifier. This configuration gives a
higher bandwidth than a simple differential pair due to the reduced Miller
capacitance effect on the input stage.
Two-Stage Op-Amp
+
Yin
I I
~R01 ~Ro2
Input Stage Seoond Stage ~ Output Stage
(gain) (gain) (unity gain)
,,-------------.
t--------·,
,--------------------~
ce :
I
I
I
Vee
,
r;
II :I
I
,
I
I
.1 a:
I I
I I
I
I
I
I
I
I
+ ~O_TI--------·I-------~ Q7 :
Vin I
I
I
I Vo
I
I : RL
I I
I I
I I
I I-
I I-
I I
,
I I
I I
: VEE I I I
!-------------
I I I
--------------------~ --------~
Input Gain Stage Second Gain Stage Output Stage
op-amps, but they have larger phase shift, requiring additional compensation
to ensure stability. The low-frequency open-loop gain is
(3-17)
where Gml and Gm2 are the effective transconductance of the input and second gain
stages, respectively, Rol and Ro2 are the output resistance of the input and second
gain stages, respectively, and Ri2 and Ri2 are the input resistance of the second
gain and output stages, respectively.
A simple two-stage operational-amplifier circuit is shown in Fig. 3-7. For
the input stage, G ml and Rol are the same as given in Eqs. (3-9) and (3-10),
respectively. For the second gain stage
(3-20)
where rd is the small-signal diode resistance of diodes Dl and D 2 , and ron is the
output resistance of the bias current source 12 • In Eq. (3-18), we have assumed
164 Chapter 3 - Operational Amplifiers
equal current gains for transistors Q5 and Q6. For positive output, transistor Q7
is on, whereas for negative output, transistor Qs is on. Thus, the input resistance
of the output stage is given by
r,,7 + I3NPN R L , Va positive
R·3 = { (3-21)
I r"s + I3PNP R L , Va negative
Because the PNP beta is usually smaller than the NPN beta, the second
equation for Ri3 represents the worst-case loading on the second gain stage. In
addition, Ra2 will normally be much larger than R i3 •
High-Frequency Characteristics
(3-23)
+ o-------------------~
Vi
Slew Rate
The slew rate is a parameter used to characterize the rate at which the output
voltage of an operational amplifier can change; it is usually expressed in volts
per microsecond and is determined as the maximum rate of change in output
voltage for a large-signal step input. In practice, for op-amps whose frequency
response is dominated by the compensation capacitance, the slew rate is
limited by the maximum rate that the compensation capacitance can be
charged or discharged. Figure 3-9 shows a simplified model to calculate the
slew rate for a two-stage op-amp [1]. As depicted in the figure, for a large
positive step input, Q2 will tum off and QI will conduct the full input stage bias
current, II. This current, flowing into the reference transistor Q3, is mirrored in
Q4, giving a maximum output current 10 = II to charge C c: CcdVoldt = II.
The slew rate is thus determined by
II
S.R.=- (3-25)
Cc
Relating the transconductance of the input stage transistors to II, the slew rate
can be expressed in terms of the open-loop unity-gain frequency, Eq. (3-23):
II 2kT
S.R. = -{J)T= --{J)T (3-26)
gm q
Vo ~s R = dVo I
--Y-I
>--4----01
S.R. dt
--..t max
- vee
Figure 3-10 Simplified schematic of LM-6365 high-speed operational amplifier.
The slew rate (for the case of a simple bipolar input stage) is thus independent
of the input stage bias current; the increase in transconductance accompanying
an increase in bias current produces a higher amplifier gain, which requires a
larger compensation capacitance to set WT. For the example above with
I, = 20/-LA and Cc = 25 pF, the slew rate is 0.8 V//-Ls. Careful design with high-
frequency transistors can produce high-performance amplifiers with improved
slew rate. A simplified schematic of the LM-6365 high-speed operational
amplifier is shown in Fig. 3-10. It boasts an /T of 725 MHz and a slew rate of
300V//-Ls.
As expressed by Eq. (3-26), the slew rate for a given/T is determined by the
I,/gm ratio of the input stage, which for the simple bipolar circuit of the type
depicted in Fig. 3-9, is fixed at 2kT /q; altering the circuit to increase the I,/gm
ratio can improve the slew rate. One method is to use emitter degeneration to
reduce the transconductance of the input stage, illustrated in Fig. 3-11. Here,
the transconductance of the input stage is reduced by a factor of 1 + g,.RE, giving
an increased slew rate of
In the example above with I, = 20/-LA and RE = 20 kil, the slew rate would
increase from 0.8 V//-LS to about 7 V//-Ls. The physical reason for the increase
3.1 Voltage-Feedback Amplifiers 167
is that with emitter degeneration the gain of the input stage is reduced,
lowering the overall open-loop gain of the amplifier, thereby requiring a
smaller value of compensation capacitance C e. The input stage bias current is
the same; therefore, as indicated by Eq. (3-25), the slew rate increases. The
drawback to using emitter degeneration is that mismatches in the resistor
values produce a dc input offset voltage.
Another method to increase the II Igm ratio is to use field-effect transistors in
the input stage, such as illustrated in Fig. 3-12 with p-channel JFETs. At a
given bias current, the transconductance of a field-effect transistor is much less
than that of a bipolar transistor, increasing the slew rate by a factor of perhaps
10-30 for a typical FET device. A disadvantage is the increased input offset
voltage with field-effect transistors over bipolar transistors.
+ 0------------1-----------,
Vi
Vee
+ I bias
°9
+ + Vo
VIC VIC
-- ° 10
08
°5
VEE
Figure 3-13 Operational-amplifier circuit illustrating common-mode input range.
The common-mode input range is the maximum range in dc voltage that can
be applied simultaneously to both inputs without causing the op-amp to cease
operating normally. This range is an important parameter because it represents
the maximum dc levels of signals that may be applied to the amplifier inputs;
as such, a wide common-mode input range is desirable. The limits in input
range are reached when one or more of the transistors in the amplifier no
longer operate in the active region, usually in the input stage.
As an example, consider the operational-amplifier circuit shown in Fig.
3-13. The lower limit on VIC is reached when current source transistor Q5
saturates:
Thus, for this example, the common-mode input range is from about 1 V above
the VEE supply to about 0.1 V below the Vcc supply. This common-mode range is
usually adequate when power supply voltages are relatively large; for oper-
ational amplifiers operated from low supply voltages (say, 1-2 V), this range
may pose some limitations in certain applications. There are modifications to
the input stage which can extend this common-mode input range [2].
3.1 Voltage-Feedback Amplifiers 169
Voo
I 1
+ 0>-------1
optional
output stage
Vss
Figure 3-14 Simple two-stage CMOS op-amp.
with
ROI=r021Ir04=~( 1 )
II AN + Ap
(3-32)
and
where roI2 is the output resistance of the second stage bias current source 12 •
Owing to the smaller transconductances, the CMOS op-amp will have a lower
gain than its bipolar counterpart operating at the same bias current.
170 Chapter 3 - Operational Amplifiers
Vo= a
MS
Vss
Figure 3-15 Two-stage CMOS op-amp illustrating offset constraints. (From Ref. 3)
(3-35)
Because of the lower gm/I ratio for MOSFET devices, the CMOS amplifier
generally has a higher slew rate than a comparable bipolar amplifier.
As discussed in Ref. 3, the relatively low gain per stage of the CMOS
operational amplifier results in the input-referred dc offset voltage being heav-
ily dependent on both the differential input stage and the second gain stage,
unlike the bipolar amplifier in which the much higher gain per stage results
in the input offset voltage being determined primarily by the gain of the input
stage alone. Consequently, design constraints are placed on the relative chan-
nel-width-channel-length (W IL) dimensions of the transistors in the CMOS
amplifier. In the two-stage CMOS op-amp shown in Fig. 3-15, we desire Vo = 0
with the inputs grounded. In the input stage, ID4 = ID3 = 11 /2,
and assuming matched transistors, we have, therefore, V OS4 = VOS3 = V GS3 ; thus,
VGS5 = VGS4, which using Eq. (l-81) leads to
105
(3-36)
where
3.1 Voltage-Feedback Amplifiers 171
and
VDSS =- VSS
Now V GS1 = V GSS , which, noting that ID7 = 2ID4 and IDS = IDS, gives
(3-37)
where
and
V SDS = V DD
Combining Eqs. (3-36) and (3-37), the zero offset voltage constraint is
(-W)
L
[1 + AN (VTN + j-J.Ln-Cox,II(W
4
- - - )]
IL)4
(3-38)
In practice, the channel lengths (L) of the NMOS and PMOS transistors are
held fixed, and the channel widths (W) are scaled to fit the constraint require-
ments.
respectively, with
V
V SD6 = VSG6 =- V TP + _ _2_I_bia_,_ _ = 2
/-Lp C~x (W IL)6
(W ILh I bias
(WIL)6 2
Vsm = = + V TP - = 8.29V
C~x (:)2
V DD - V SG2 V DD
/-Lp
V SD8 = V DD = IOV
This gives I, = 56.0 /-LA and 12 = 115 /-LA. Now,
V =V +J I, = 1.43 V
DS4 TN /-Ln C~x ( WIL)4
unity-gain
voltage buffer
z(jO)) iINV
zo
z(jO)) = - - - -
1+ j( :0)
Figure 3-16 Idealized model for a current-feedback amplifier.
3.2 Current-Feedback Amplifiers 173
Zo
Z U00) = - - - - - (3-39)
1 + j(oo/ooo)
where 00 0 is the frequency at which the transimpedance is down by 3 dB from
its value (zo) at low frequency. In general, Zo will be high in value.
A noninverting amplifier configuration is shown in Fig. 3-17. Current is fed
back from the output through R z to the inverting input of the amplifier; due to
the unity-gain buffer between the two inputs, the voltage at the noninverting
input is equal to Vim and the feedback current is then (vo - vin)IR z, which, com-
bined at the input, gives
• _
lINV--
Vin _
Rl
Vo-Vin
Rz
-(1 +
- -
Rz) Vin
Rl R z + zUoo)
(3-40)
(3-43)
Note that the 3-dB bandwidth is a function only of the feedback resistance R 2 ;
it is, to first order, independent of the closed-loop gain. Unlike the voltage-
feedback amplifier, there is no gain-bandwidth trade-off. With the current-
174 Chapter 3 - Operational Amplifiers
gain (dB)
(1 )
Avo;-~----------------~
R 2 fixed
Avo
o dB-t--------""""II:----=.:r---~-_+ log(f
fa
Figure 3-17 (a) Noninverting current-feedback amplifier. (b) Gain·versus-fre-
quency characteristics.
Assuming identical NPN and PNP transistors and neglecting base currents, the
base-emitter voltages give
+ vee
iINV
V.+o---+ -+ V·"
I
.-R·"
I
- Vee
Figure 3-18 Unity-gain voltage butTer circuit.
Under quiescent conditions, iINV = 0, i3 = i4 = la, and the input offset voltage from
Eq. (3-44) is
(3-47)
R+ = /3NPN/3PNP
(3-48)
I 2gm
_ 1
R- = - (3-49)
I 2gm
where gm = qlolkT. The input resistance at the noninverting input is thus quite
high, and at the inverting input, it is low.
The LH-4012 wideband buffer uses a circuit identical to that in Fig. 3-18
except that resistors are used in place of active bias current sources. The input
to the buffer is taken at the noninverting terminal and the output is taken at
the inverting terminal. It can provide ± 10 V output into a 50n load and
boasts a 3-dB bandwidth of 500 MHz, a slew rate of 12,000 V/f.LS, a risetime
of 1.2 ns, and a phase linearity of 1°.
176 Chapter 3 - Operational Amplifiers
V+
I
- Vee
Figure 3-19 Circuit embodiment of a current-feedback amplifier.
Transimpedance
resistances of the output stage looking into the bases of Q9 and QIO. respectively.
From the equivalent circuit, the impedance at node Z is given by
Z Uw) = Zo
(3-50)
1 + jwzoC e
where
(3-51)
Under worst-case conditions with a short circuit at the output,
ri9,10 = r'IT9, 10 + 139,10 r'ITII, 12 (3-52)
Z Uw) represents the transimpedance of the current-feedback amplifier; its 3-dB
frequency is thus
1
w =-- (3-53)
o ZaCe
Slew Rate
To first order, the slew rate of the current-feedback amplifier is not limited by
internal bias currents in the circuit, as is the case for the voltage-feedback
amplifier [see, for exampte, Eq. (3-25)]. Figure 3-21 depicts a first-order model
to characterize the slew rate of the current-feedback amplifier. The slew rate
is limited by the charging current of C e,
i3
t i 3~
iINV
V.+ V·- -+ Vo
1
---+ 1
iINV i4 ~ ~ic
i4t Output Stage
ICc
--
I. ~ Vo(final)
oV~Jt*" slope = S.R.
~t i INV •
~t
Vi ~-.J\ o
(3-55)
But, ViA ..o is the final value of the output voltage. Thus, the slew rate is given by
V,,(final) Wal .
S.R. = = - -o Va (final) = Wa Va (fmal) (3-56)
R2 C c R2
As an example, take fa = 100 MHz and Va = 5 V: According to Eq. (3-56), the
slew rate would be 3100 VIlLS.
A simplified schematic of the OPA603 current-feedback amplifier is shown
in Fig. 3-23. Here, instead of current mirrors, current sampling resistors are
used in the collectors of the input buffer. Over a range in voltage gain of 1-10,
this circuit exhibits a bandwidth of 100 MHz and a slew rate of 1000 VIlLS.
V,+
I
08
- Vee
Figure 3-23 Simplified schematic of the OPA603 current-feedback amplifier.
.+ - .
I in
Vee
iin--'
O-----+--
(a) (b)
Figure 3-25 (a) Current differencing. (b) Basic gain stage.
current that is equal to the maximum output current divided by = [32; the input
current could be several microamperes for a peak output current of tens of
milliamperes, for example. To further reduce the input current requirements,
an additional buffer is added to the gain stage. Figure 3-26 shows a schematic
of the complete current-differencing amplifier; the pnp emitter follower (Q4)
provides additional buffering for the gain stage. The small-signal output volt-
age is given by
(3-57)
where
(3-58)
Vee
L - - -......---+---o v0
.in+---.
I 0-_-_--1
Ri4 is the small-signal resistance seen looking into the base of Q4 and is given by
Ri4 = r'IT4 + 134 (r'ITS + 135 R L) = 134 [kT + 135 ( kT + RL)] (3-59)
qII q(Iz - II)
ra3 is the output resistance of transistor Q3 and is determined from
134 VA3
ra3 =-1- - (3-60)
1
EXAMPLE. Determine the open-loop gain of the amplifier in Fig. 3-26. The
circuit parameters are II = 200/LA, 12 = 1.2 rnA, and RL = 5 kD. The transistor
parameters are v,iPN = 100 V, I3~PN = 100, and I3~NP = 40. Assume room tempera-
ture. From Eq. (3-60),
r 3 = (40)(100V) = 20MO
o 200/LA
Using the right-hand side of Eq. (3-59),
Inverting Amplifier
(3-61)
(3-63)
182 Chapter 3 - Operational Amplifiers
>--+--0 V 0
If we set the value of R3 to be equal to R I IIRz, then the terms inside the square
brackets in Eq. (3-63) cancel, giving
(3-64)
Vee
t----+---o v 0
1.3 rnA
+ O--t---+--1
vt 0----\
I bias t
Figure 3-29 Idealized model for a transconductance amplifier.
The external bias current ([bias) is the reference current for the current source (Qs and
Q6) biasing the differential pair, thus setting the value of the transconductance.
184 Chapter 3 - Operational Amplifiers
---.
i o=9m v in
+-----'-, --~-() Vo
,
.;.... Ro
Vin
+o-----------I·~----~
Ib~ 09
. Vee
With reference to Fig. 3-30, some observations are worthy of note: (1) The
output node is a high-impedance point with
(3-68)
Thus, for applications in which a large voltage gain is required, the external
load resistance, R L , must be large (some commercial transconductance ampli-
fiers have output buffers to maintain a high output impedance at this node).
(2) All the internal nodes are low-impedance points; they are connected to
base-emitter junctions. Thus, the frequency response of the amplifier is deter-
mined by the capacitance at the output node. Also, as a result, internal com-
pensation is usually not required.
A small-signal model representing the output of the transconductance am-
plifier is shown in Fig. 3-31. In the model, Co represents the output capacitance
of the amplifier itself and C L is any external load capacitance. From the circuit,
the small-signal voltage gain (Vo/Vin) is given by
. gm (RoIIRL)
Av Uw) = - - - = - - - - - - (3-69)
1 +jw(RoIIRL)(Co+CL)
where the - 3-dB frequency is given by
1
w =------- (3-70)
o (RoIIRL)(Ca + C L)
The low-frequency gain is determined by
3.4 Transconductance Amplifiers 185
Vo
and is set by the value of the external bias current. This feature finds appli-
cation in gain-controlled amplifiers. The unity-gain frequency is then given by
(3-72)
(3-73)
Because Avo is controlled by fbias. this makes the closed-loop bandwidth control-
lable by the external bias current; an application employing this feature is in
active filters in which the bandwidth is electrically controlled [8]. The gain-
bandwidth characteristics of the transconductance amplifier is illustrated in Fig.
3-32.
gain (dB)
Avo+-----_
o dB log (f)
- 00-----1------'
+
Ve
- Vee
Figure 3-33 A simple circuit to externally control the bias current for the trans-
conductance amplifier.
A simple method to set the bias current with an external control voltage is
shown in Fig. 3-33. With this scheme, the bias current is determined by
Vc + Vee - VBE
[bias = R8 (3-74)
Unfortunately, with this circuit, the bias current is dependent on the supply
voltage as well as Vbe (which varies with the collector currents of Q5 and Q6). It
will be left as a problem for the reader to design a bias control circuit to give
[bias as a function of Vc only.
To increase the output resistance of the transconductance amplifier (Ro) and
to reduce current source errors, Wilson or cascode current sources are some-
times used in practice. The LM-3080 operational transconductance amplifier,
illustrated in Fig. 3-34, utilizes Wilson current sources.
Linearization
Under open-loop operation, the input voltage (Vin ) may not be small in com-
parison to the thermal voltage, kT Iq. As a result, the transfer characteristic of
the amplifier will be nonlinear (due to the exponential relation between the
collector currents of the differential pair transistors and the input voltage). Two
techniques that can be used to improve linearity are (1) emitter degeneration
and (2) diode linearization.
Placing resistors (R E) in each of the emitter legs of the differential-pair
transistors (see Fig. 3- I I) increases the linear range of the input by approxi-
mately [bias RE voltS. Doing so, however, reduces the gain of the amplifier to the
extent
(3-75)
3.4 Transconductance Amplifiers 187
-,,
,
14- Wilson
\
,,
,
,,,
+0----1
~~~~~~~J-~ V,
o--------------I-------~
-.
I bias
- Vce
Figure 3-34 Simplified schematic of the LM-3080 operational transconductance
amplifier.
. 1bi • s
and 12 = l+e qVblkT (3-76)
In (1D2) (3-77)
1DI
Neglecting the base currents in QI and Q2, the diode currents are 1DI = (ID - i,) and
1D2 = (ID + i,).
Thus,
- --. -
kT In (ID
Vb=- is) (3-78)
q 1D + Is
188 Chapter 3 - Operational Amplifiers
Figure 3-35 Diode linearization scheme for the input stage of a transconductance
amplifier.
. . . hias .
1 =/2-/1 = - - 1 (3-80)
o s ID
which is seen to be linear with respect to the input source current, is.
This type of diode linearization is employed in many commercial trans-
conductance amplifiers; Figure 3-36 shows a simplified schematic of the
LM-13600 operational transconductance amplifier. With this amplifier, gm is
adjustable over six decades in bias current, ranging from 0.1 iJ.A to 1 rnA,
with good linearity. It has an open-loop bandwidth of 2 MHz and a unity-
gain compensated slew rate of 50 V/iJ.s. An optional Darlington buffer is also
included.
Applications
Out
- In ~-"----I
+ In o....------/------J
I bias
- Vee
+vecjb sample
hold
- V ee
+ Vee
I bias ~
+
- Vee
i o = __-
+
I bias t
signal and the end of the previous sample interval. (2) Figure 3-38 shows an
analog mUltiplier circuit; the y input is used to control the bias current which
sets the gain of the transconductance amplifier in response to the x input. For
a Wilson current source (as in Fig. 3-36), the bias current is given as
(3-82)
Normally, one would modify the bias current control circuit to give hias directly
proportional to Vy and thereby eliminate the Vx offset in Eq. (3-82). (3) A
voltage-controlled low-pass filter is illustrated in Fig. 3-39; the 3-dB band-
width of the filter is given by
(3-83)
3.4 Transconductance Amplifiers 191
Vc o----"'~.~------........,
+ vce
~---------~~------------------~-oVout
- vee
Figure 3-39 Voltage-controlled low-pass filter using a transconductance amplifier.
(3-86)
In practice, owing to the effects of channel-length modulation, the effective
transconductance of the amplifier will differ somewhat from that calculated by
192 Chapter 3 - Operational Amplifiers
V DD
Ms M3 M4 M6
.i S
•i1 i 2• i 6.
-~
--.
io
~
M1 Vo
V. is.
In RL
+ 0
tI bias
M7 MS
---.
I bias
M10
Mg
VSS
Figure 3-40 CMOS transconductance amplifier.
Eg. (3-86). Also of note: In the CMOS amplifier, the transconductance varies
as the square root of the bias current, compared to a linear variation in the
bipolar amplifier [see Eq. (3-67)]. The output resistance of the amplifier can
be increased by using cascode pairs for transistors M6 and Ms [9].
Linearization
(3-87)
and
(3-88)
3.4 Transconductance Amplifiers 193
f1 I 2•
v;+~
M1 M2
l
-- M3
a 3 b
1 '
M4 tl4
T
10
where the asterisk is used to denote the channel width /length ratio for the
linearization transistors M3 and M4 (which is different than that of the differen-
tial-pair transistors Ml and M2)' The node potentials are given by
Va = Vi - VGS1 = Vi - V TH -
J 211
C' (WIL) (3-89)
I-Ln ox
and
I 212
(3-90)
Vb = - VGS2 = - VTH - V I-Ln C~x (W IL)
Defining the output current as 11 - 12 = 2 (13 - 14), and noting that Vba = - Vah , we
find
Substituting for 11 and 12 in terms of 10, 13, and h and solving the resulting
quadratic equation, we obtain
which is linear in Vi. For a given bias current, 10, there is a relation between
194 Chapter 3 - Operational Amplifiers
the channel width !length ratios which optimizes the linear range; typically this
in a range (WIL) -:- (WIL)* of about 3-7.
Problems
3.1 Verify text Eqs (3-6) through (3-8) for the single-stage op-amp model
shown in Fig. 3-3.
3.2 For the folded-cascode differential amplifier stage shown in Fig. 3-42
determine:
(a) The low-frequency, small-signal voltage gain, VouJVin' for V in near zero.
(b) The maximum and minimum values for Vout . You may assume
IVCE(sat)i == 0.2 V.
+ 10 V
Vout
- 10 V
Figure 3-42 Folded-cascode differential amplifier for Problem 3.2.
Problems 195
3.3 (a) For the cascode differential amplifier stage shown in Fig. 3-43 deter-
mine the low-frequency small-signal voltage gain Avo. The diodes are fab-
ricated from NPN transistors.
(b) The frequency response of the circuit is dominated by the 10-pF load
capacitance. Determine the - 3-dB frequency for the amplifier stage.
(c) Use SPICE to simulate the circuit to check your results above. Spe-
cifically, (1) plot the dc transfer characteristic for Vin ranging from - 5 mY
to + 5 mY, and (2) plot the small-signal voltage gain versus frequency
(log-log plot) for frequency ranging from 1 Hz to 100 MHz.
3.4 For the two-stage voltage op-amp shown in Fig. 3-44, compensation can
be achieved either by placing C c as a feedback capacitor across the second
gain stage (a) or as a shunt capacitance at the input of the second stage
(b). In either case, Cc dominates the response. For this problem, the current
sources can be assumed to be ideal and the output resistances of the
transistors can be neglected.
(a) Find the low-frequency voltage gain, Avo and, for the feedback compen-
sation connection, the slew rate, S.R., the unity-gain bandwidth,fT, and the
- 3-dB frequency, fa.
(b) For the shunt compensation connection, find S.R., fr, and fa.
3.5 Derive an expression for the low-frequency voltage gain, Va/Vim for the
single-stage op-amp shown in Fig. 3-45. Express your result in terms of
196 Chapter 3 - Operational Amplifiers
+Vee
+
r-v-
12 200 IlA
20,F ~~smg,
--l '-,u.
....
-:
50 Kn
- Vee
Figure 3-44 Op-amp circuit for Problem 3.4.
Vee
+--__--0 Vo
+ 0------1
Vss
Figure 3-46 BieMOS op-amp for Problem 3.6.
3.7 The high-speed buffer circuit of Fig. 3-47 is relatively insensitive to the
load current in RL due to the current absorbing capability of Q9, controlled
by feedback through Q6.
(a) Describe the operation of the circuit, showing that Vo = Vin , and that this
result is maintained under a varying load current.
+ 10 V
Os
2X
_~----...--..---o Vo
1 rnA
- 10 V
Vee
t-----1---;:-O V out
I
(b) Simulate the circuit using SPICE for values of RL of 2kil, 5 kil, and
20 kil, to show Vo versus V in for V in ranging from - 10 V to + 10 V. Qs is
identical to the other NPN transistors except for its emitter area which is
twice the size.
(c) Show that the input offset voltage (for Vo = 0) is given by
kT In
Vos=- (ICllcs)
--2-
q 2IC2
Calculate Vas and compare with that determined from your simulation.
3.8 Figure 3-48 shows a closed-loop unity-gain buffer circuit in which the
feedback loop comprising Q2 and Q3 provides a low output resistance.
(a) Show that Vo = Vi, and Ro = 2 Ifh gm2'
(b) Show that the input offset voltage is given by
-+
kT In (II
Vas=- -12/~F)
--
q II - 12/~F
(c) Calculate Ro and Vas, given that II = 12 = 500 J.1A.
3.9 (a) Calculate the low-frequency value of the transimpedance, Zoo for the
current-feedback amplifier depicted in Fig. 3-19. Take 10 = 1 rnA, I bias = 2 rnA,
and assume a near short-circuit load at the output.
(b) The capacitance C c comprises primarily the base-collector junction
capacitance of transistors Q7 though QIO. If the capacitance of each transistor
is 0.05 pF, determine the open-loop, - 3-dB frequency, fo, for the ampli-
fier.
(c) Repeat (a) and (b) for a 5-kil load at the output instead of a short
circuit; assume that Vo is still near zero for this calculation.
Problems 199
10 kn
3.10 For the inverting amplifier shown in Fig. 3-27 with a transresistance
parameter r Uw) given by Eq. (3-65), show that for R3 = R ,IIR z, the closed-
loop voltage gain is given by
3.11 (a) For the Norton amplifier gain stage in Fig. 3-49 show that the
small-signal output current is given by in = -j3}iin, where QI and Q2 are
identical transistors.
(b) Simulate the circuit using SPICE, showing In versus lin> for lin ranging
from 2 to 5 J-LA. From the simulation, verify the result in (a). Take
Is=2X 1O-'5 A and j3F=50.
3.12 In Fig. 3-50, a transconductance amplifier is used as an inverting ampli-
fier. Show that the small-signal voltage gain is given by
Vo 1-g m R 2
Vi l+gm R I
+
Vi I
~Ro
I bias f I
3.16 Carry through the analysis using Eqs. (3-87), (3-88), and (3-91) to obtain
Eq. (3-92) for the linearized MOSFET transconductance amplifier.
References
I. l.E. Soloman, "The Monolithic Op Amp: A Tutorial Study," IEEE 1. Solid-State Circuits,
SC-9, 314--332 (Dec. 1974).
2. l.H. Huijsing and D. Linebarger, "Low-Voltage Operational Amplifier with Rail-to-Rail Input
and Output Ranges," IEEE 1. Solid-State Circuits, SC-20, 1144-1150 (Dec. 1985).
3. P.R. Gray and R.G. Meyer, "MOS Operational Amplifier Design-A Tutorial Overview," IEEE
1. Solid-State Circuits, SC-17, 969-982 (Dec. 1982).
4. P.E. Allen and M.B. Terry, "The Use of Current Amplifiers for High-Performance Voltage
Applications," IEEE 1. Solid-State Circuits, SC-I5, 155-162 (Apr. 1980).
5. T.M. Frederiksen, W.F. Davis, and D.W. Zobel, "A New Current-Differencing Single-Supply
Operational Amplifier," IEEE 1. Solid-State Circuits, SC-6, 340-347 (Dec. 1971).
6. O.H. Schade, lr. and EJ. Kramer, "A Low-Voltage BiMOS Op Amp," IEEE 1. Solid-State
Circuits, SC-I6, 661-668 (Dec. 1981).
202 Chapter 3 - Operational Amplifiers
7. R.L. Geiger and E. Sanchez-Sinencio, "Active Filter Design Using Operational Transconduc-
tance Amplifiers: A Tutorial," IEEE Circuits Devices Mag., I-i, 20-32 (Mar. 1985).
8. K. Fukahori, "A Bipolar Voltage-Controlled Tunable Filter," IEEE 1. Solid-State Circuits,
SC-i6, 729-737 (Dec. 1981).
9. E.A. Vittoz, "The Design of High-Performance Analog Circuits on Digital CMOS Chips,"
IEEE 1. Solid-State Circuits, SC-20, 657-665 (Jun. 1985).
10. F. Krummenacher and N. Joehl, "4-MHz CMOS Continuous-Time Filter with On-Chip Au-
tomatic Tuning," IEEE 1. Solid-State Circuits, SC-23, 750-758 (Jun. 1988).
Chapter 4
Figure 4-1 shows a block diagram of a general feedback amplifier system. The
basic amplifier is characterized by a forward gain a and the feedback network
is characterized by its reverse transmission! The input Xi and output Xo signals
may be voltages or currents. The signal is sampled at the output of the
amplifier and applied to the right-hand port of the feedback network. At the
left-hand port, the feedback signal fxo is mixed with the input signal, giving a
signal equal to Xi - fx o at the input to the amplifier. The output is then
(4-1)
203
204 Chapter 4 - Feedback and Compensation
Xi - f Xo
input output
basic amplifier
forward gain (a)
input output
Xi mixing sampling Xo
network network
feedback network
reverse transmission (f)
~=A= __
a_ (4-2)
Xi 1+ af
The product of a and f represents the net gain in the signal traversing forward
through the amplifier and back through the feedback network; it is referred to
as the loop gain T ( = af) and thereby Eq. (4-2) can be expressed as
~=A=_a_ (4-3)
Xi 1+ T
Equation (4-3) is a fundamental relation for negative feedback which expresses
the closed-loop gain (with feedback applied) A in terms of the open-loop gain
of the amplifier (without feedback) a and the loop gain T. The system gain is
thus reduced by a factor 1 + T. It is to be noted that if T ~ 1, then
a 1
A=-=- (4-4)
T f
and is independent of the gain of the basic amplifier. Because the feedback
network is often composed of stable, passive elements, the closed-loop gain is
well controlled.
Gain Stabilization
M= Lla
(1 + T)2
Expressed as a fractional change,
M Lla 1 Lla
-----,,- - --- (4-6)
A A(1+T)2 1+ T a
As expressed by Eq. (4-6), the fractional change in the overall closed-loop gain
A is a factor of 1 + T smaller than the fractional change in a. As an example,
if the gain a of an amplifier with T = 49 changes by 10%, then the closed-loop
gain A changes by 10%/(1 + 49) = 0.2%.
Reduction in Distortion
Nonlinearities in the basic amplifier give rise to distortion in the output signal,
especially if the signals in the amplifier are relatively large in magnitude. Such
conditions are often encountered, for example, in the output stage of an
amplifier where the output voltage has a large swing. Negative feedback
applied to such an amplifier causes the distortion components of the output
signal (also referred to as distortion products) to be fed back into the input of
the amplifier where they subtract from themselves, resulting in a decrease in
the overall distortion. The following discussion will demonstrate this process.
Consider the feedback amplifier system depicted in Fig. 4-1. Let the input
to the basic amplifier be denoted XE; with feedback, this is equal to the
difference in the input signal Xi and the feedback signal Jxo- In this context, X E
is referred to as the error signal. Without feedback, the output of the amplifier
Xo is equal to aXE. To see the reduction in distortion by feedback, it is simpler
to view the process in reverse [1]. Instead of viewing a pure input producing
a distorted output, we determine what predistortion is required at the input to
produce a pure undistorted output. In this case, we relate the input as a
function of the output, say in terms of a power series:
(4-7)
where U h Uz, U3,... are constants. For a linear amplifier (no distortion), all
constants but U] would be zero. Normalizing with respect to the linear term,
we obtain
(4-8)
206 Chapter 4 - Feedback and Compensation
amplifier
linear
feedback
network
The higher-order terms (x~, x~, ... ) are a measure of the distortion products in
the signal. With feedback applied, a signal - fx o is added to the input, giving
(4-9)
... ) (4-10)
(4- I I)
a I +f I + af I +T
Comparing Eqs. (4-8) and (4-10), we see that the distortion terms with feed-
back are reduced by a factor of I + T. In actuality, the nonlinear components
are reduced relative to the linear components.
To demonstrate the reduction in distortion with negative feedback, a non-
linear amplifier, depicted in Fig. 4-2, is simulated. The large-signal, voltage
transfer characteristic of the amplifier with and without feedback is shown in
Fig. 4-3; the improvement in linearity with feedback is evident. The price paid
is, of course, the lower closed-loop gain with feedback.
Increased Bandwidth
ao
a(jw)=---- (4- 12)
1 + j(wlw o )
4.1 Basic Feedback Concepts 207
2.0V-r---------------------------,
1.0V
ov
-l.OV
-2.0V-I---------r------.---------.--------l
-2.0V -l.OV ov l.OV 2.0V
[] V(3) • V(30)
VJN
Figure 4-3 Voltage transfer characteristic of a nonlinear amplifier with and with-
out negative feedback.
where Wo is the frequency at which the open-loop gain of the basic amplifier
in down by 3 dB from the gain at low frequency a o . Further, assume that the
feedback network is purely resistive such that the feedback factor ! is a
constant. From Eq. (4-2), the closed-loop gain is then
AUw)- aUw) aUw) (4-13)
1 + a Uw)! 1 + TUw)
which, using Eq. (4-12), results in
(4-15)
Eq. (4-14) can be expressed as
AUw) = Ao (4-16)
1 +j[WoOw+To)]
where To = aJ and is the low-frequency loop gain.
208 Chapter 4 - Feedback and Compensation
ao +-----...
open-loop
Ao +-----.....--....::1...
with feedback
The closed-loop gain A (jw) also has a single-pole response; its frequency is
larger than that of the basic amplifier by a factor of 1 + To. Feedback has thus
increased the - 3-dB bandwidth of the amplifier from Wo to (l + To) w o , as
illustrated in Fig. 4-4. This increase in bandwidth is accompanied by a decrease
in gain by the same factor (l + To).
The simple circuit of Fig. 4-5 will serve as an example to illustrate the analysis
of a feedback amplifier. In this circuit, a single transistor is connected as a
common-emitter transresistance amplifier; it develops an output voltage Vo pro-
portional to an input current signal 15 , Feedback is provided by resistor RF which
samples the voltage at the output node and feeds a current that is proportional
--..,.....--vcc
feedback network
I 5
- - - - - Vee
Is
---------
- ,,, R F ''
~-- -----~
-
'''
' RF
,,
, , '
feedback signal ~ Vo Vbe~ feedforward signal
,, '
~, ____________
-= : _____ 1''
(a) equivalent feedback network
--...,--- Vee
Is
,- - - - - - - - - - - --
,,,
,,
,,
,,
,,
:-------------------,
- -,
(b) approximate feedback network
Figure 4·6 (a) Equivalent circuit represention of the feedback network for the
amplifier of Fig. 4·5. (b) Neglecting the feedforward signal in the feedback network.
to the output voltage back to the input where it is mixed with the input signal.
To see that this is negative feedback, consider that the output voltage increases:
An increase in Vo results in an increase in the signal fed back to the base of the
transistor, resulting in an increased collector current; the increased collector
current results in a decrease in collector-to-emitter voltage, and hence a decrease
in Vo.
The feedback network may be replaced by the equivalent circuit shown in Fig.
4-6(a); this circuit produces the same feedforward and feedback signals as the
210 Chapter 4 - Feedback and Compensation
Vee
RF
Is
_ , loading of feedback
network at output
-= loading of feedback
feedback signal network at input
1
If b = • - Vo
RF
(a)
,...-----,r-----,---o+
....-Ro
RF Vo
(b)
(c)
-=
Figure 4-7 (a) Representing the feedback signal as a current. (b) Small-signal
equivalent circuit of the feedback amplifier. (c) Small-signal circuit for calculating
the output resistance.
original feedback network of Fig. 4-5. The signal fed forward through the
feedback network is normally much smaller than the signal fed forward through
the basic amplifier and can thus be neglected, resulting in the approximate
equivalent circuit of the feedback network shown in Fig. 4-6(b). In Fig. 4-7(a),
the feedback voltage source is replaced by its Norton equivalent, a current source
of value - VolRF in parallel with the resistance RF; this current source, I fb , is
directed opposite to the input signal, I" to emphasize the negative feedback. In
this equivalent circuit, the feedback resistance RF appears as a shunt at both the
input and output of the amplifier and represents the loading of the basic amplifier
by the feedback network.
4.2 Feedback Circuit Example 211
On the right-hand side of Eq. (4-18) we have substituted for the feedback current
itb = - VO IR F, and have introduced the parameter Rim which equals RsllRFllr". Substi-
tuting for VI from Eq. (4-18) into Eq. (4-17) yields
Va gmRioRoo
-
(4-19)
is 1 + gmRoRoolRF
This is the closed-loop gain of the amplifier with feedback.
If the feedback signal is removed (i.e., make itb = 0), the gain of the amplifier
can be easily shown to be
Va I = - gmRioRoo == a (4-20)
is i(b=O
In this context, a is the gain of the basic amplifier without feedback. Further, it
is profitable to define the feedback factor
f= (4-21)
(4-23)
is 1 + af
which is the fundamental feedback equation.
Input Resistance
With reference to Fig. 4-7(b), the input resistance of the amplifier with feedback
IS
VI
R=-
I •
(4-24)
Is
212 Chapter 4 - Feedback and Compensation
(4-25)
(4-26)
It is to be noted that if the feedback signal ilb is removed, the input resistance
would be
Output Resistance
The test circuit of Fig. 4-7(c) is used to calculate the output resistance of the
feedback amplifier. Formally,
R=-
o Vo
• 1 (4-28)
10 iJ=O
(4-29)
At the input,
(4-30)
Now,
so
4.3 Feedback Configurations 213
(4-31)
It is also noted that if the feedback is removed, the output resistance would be
Ro I. =RLIIRF=Roo (4-32)
Ifb=O
Cll
"
Cll
a.
C'
Il)
(')
Rs ii
---+ Il)
'"
basic ::J
+ 4- basic 4- a.
v;n vi transconductance io RL is current io RL ()
amplifier 0
amplifier 3
- vf b +
'0
It' If b Cll
::J
C/l
Il)
+ 4- 0'
feedback feedback -
::J
f i0 io Fio
network I_~~ network
( c) (d)
Figure 4-8 Feedback configurations. (a) Series voltage feedback (series-shunt); (b)
shunt voltage feedback (shunt-shunt); (c) series current feedback (series-series);
(d) shunt current feedback (shunt-series).
4.3 Feedback Configurations 215
Series Voltage
In the series voltage feedback configuration, repeated in Fig. 4-9(a), the output
voltage Va is sampled by the feedback network and a feedback voltage fo 0 is mixed
in series at the input. The effect of the feedback network on the amplifier can
be seen by the circuit transformation depicted in Fig. 4-9(b). As far as the
feedback network is concerned, it sees a current is at its input and a voltage Va at
its output; it is appropriate, therefore, to represent the input side of the feedback
network by its Thevenin equivalent and the output side by its Norton equivalent.
The Thevenin equivalent at the input consists of resistance rif in series with the
open-circuit voltage Voc; rif is the equivalent resistance at the input port of the
feedback network, evaluated with Va set to zero (output short circuited), and Voc is
the voltage at the input of the feedback network with is set to zero (input open
circuited). Voc is the feedback signal, equal to foa. The Norton equivalent at the
output consists of resistance roJ in parallel with the short-circuit current isc; rof is the
equivalent resistance at the output port of the feedback network, evaluated with
(, set to zero (input open circuited), and isc is the current at the output of the
feedback network with v0 set to zero (output short circuited). isc is the feedforward
signal. Because the feedback network is passive, this feedforward signal is
usually much smaller than the signal fed forward through the basic amplifier; isc
can thus be neglected, resulting in the approximate equivalent circuit for the
feedback network shown in the bottom panel of Fig. 4-9(b).
The basic voltage amplifier is represented by the equivalent circuit shown in
the upper portion of Fig. 4-1O(a); here ria represents the input resistance of the
216 Chapter 4 - Feedback and Compensation
basic +
+ voltage Vo
vs
amplifier
+
feedback
f Vo
network
(a)
feedback
network
Thevenin Norton
equivalent equivalent
;~+Yoc ;"
,, -
'Ol!,
L....::1r--4---i:-O
!---7 -------------- ----~
feedback signal ~ feedforward signal
1:9+ 8
, --------------------- I
I ri f '
1 Yo
0..:L ____________________ :-0 J
(b)
Figure 4-9 (a) Series voltage feedback amplifier. (b) Transformation of feedback
network.
4.3 Feedback Configurations 217
roa
+
Vi
·._-------------------.J
~-------------------~
: ri f :
• •
f Vo
•
~--------------------
•
approximate feedback network
(a)
(b)
Figure 4-10 (a) Series voltage feedback configuration using an equivalent circuit
for the basic amplifier. (b) Circuit for calculating the output resistance.
basic voltage amplifier and roa its output resistance. The feedback network is
replaced by its approximate equivalent circuit. From the circuit in Fig. 4-1O(a)
we have for the input current
(4-33)
where
218 Chapter 4 - Feedback and Compensation
(4-34)
and represents the input resistance of the amplifier without feedback (j= 0).
At the output,
(4-35)
where
(4-36)
(4-37)
avriaRoo
Va roaRio
(4-38)
Vs 1+ avriaRoo f
roa Rio
Vo I v
-a -ria
-= Roo
=a (4-39)
Vs f~O roaRio
In this context, a represents the gain of the amplifier without feedback. Equation
(4-38) can thus be expressed in terms of the fundamental feedback equation:
a a
(4-40)
Vs 1 + af 1+ T
Input Resistance
With reference to Fig. 4-1O(a), the input resistance of the amplifier with feed-
back is
V.,
R=-
I . (4-41)
Is
i = Vs - fvo =
s Rio
(1 _--.!!L).2
1 + af Rio
(4-42)
Thus,
Ri = (1 + af)Rio = (1 + T)Rio (4-43)
The input resistance of the amplifier with series feedback is increased by a
factor 1 + T. The reason for this is that the feedback voltage fv 0 subtracts from
the input voltage v" giving a smaller net input voltage to the amplifier and
thereby a smaller input current, is.
Output Resistance
To determine the output resistance of the amplifier with feedback, we set the
input signal source, v" to zero and apply a test source at the output; using a test
voltage vm the circuit is shown in Fig. 4-1O(b). The output current resulting from
the test voltage is
(4-44)
At the input,
(4-45)
(4-46)
Thus,
R=2=~=~ (4-47)
o io 1 + af 1+T
The output resistance of the amplifier with voltage feedback is reduced by a
factor 1 + T. The physical reason why voltage sampling by the feedback network
lowers the output resistance can be seen by examining Fig. 4-1O(b). Due to the
negative feedback signal, the dependent voltage source a v Vi in the equivalent
amplifier circuit will be a negative voltage, giving an increased current in rom
thereby increasing the output current io from what it would be without feedback;
220 Chapter 4 - Feedback and Compensation
Vee
I-
I .L--_-'" ...,----.-
I
I
I
I
I
I _ I
L _-__________I
feedback network
the output resistance is thereby reduced. It should be remarked that this will be
the case regardless of how the feedback signal is mixed at the input; the shunt
voltage feedback configuration will also have a reduced output resistance.
(4-48)
(4-49)
open X
Vo
+
Vfb short
--
(a) (b)
Figure 4-12 (a) Procedure for calculating feedback voltage and equivalent output
resistance of the feedback network. (b) Procedure for calculating the equivalent
input resistance of the feedback network.
(4-50)
(4-51)
so
222 Chapter 4 - Feedback and Compensation
~--~----~---OVo
-r----r----f R C2 4 - R 0
+
(a)
Rio"";"
I
+
Vs
-=-
(b)
Figure 4-13 (a) AC equivalent circuit of the series voltage feedback amplifier. (b)
Small-signal equivalent circuit without feedback.
where in the right-hand term ofEq. (4-52) we have used gml r.,,1 = f3FI. The output
voltage is
a a
(4-55)
Vs 1 + af 1+T
where
(4-56)
Shunt Voltage
In the shunt voltage feedback configuration, repeated in Fig. 4-14(a), the output
voltage v 0 is sampled by the feedback network and a feedback current fv 0 is mixed
in parallel at the input. The effect of the feedback network on the amplifier is
illustrated in the circuit transformation depicted in Fig. 4-l4(b). As far as the
feedback network is concerned, it sees a voltage Vi, the voltage at the input to
the basic amplifier, at its input and a voltage v 0 at its output; it is appropriate,
therefore, to represent the input and output sides of the feedback network by
their Norton equivalents. The Norton equivalent at the input consists of resis-
tance rif in parallel with the short-circuit current ise; rif is the equivalent resistance
at the input port of the feedback, evaluated with Vo set to zero (output short
circuited), and i,e is the current at the input of the feedback network with Vi set
to zero (input short circuited). i,e is the feedback signal, equal to fv The Norton
0"
equivalent at the output consists of resistance roJ in parallel with the short-circuit
feedforward current, which is neglected in comparison with the feedforward
signal through the basic amplifier. raj is the equivalent resistance at the output
port of the feedback network, evaluated with Vi set to zero (input short circuited).
The resulting approximate equivalent circuit for the feedback network is shown
in the bottom panel of Fig. 4-14(b).
The basic transresistance amplifier is represented by the equivalent circuit
shown in the upper portion of Fig. 4-l5(a); here, rio represents the input resistance
of the basic transresistance amplifier and roo its output resistance. The feedback
network is represented by its approximate equivalent circuit. From the circuit in
Fig. 4-15(a), the output voltage is
(4-61)
where
(4-62)
224 Chapter 4 - Feedback and Compensation
+ basic +
RS vi transresistance RL Vo
amplifier
i fb
t
-.
f v0
feedback
network
(a)
+
feedback
vi
network
Norton Norton
equivalent equivalent
,
,
: rif + f v0 S' r of
,
:
(b)
~~--------~---------;
feedback signal
Figure 4-14 (a) Shunt voltage feedback amplifier. (b) Transformation of feedback
network.
and represents the output resistance of the amplifier without feedback (j= 0).
At the input,
(4-63)
where
Ro == Rsllrifllr;a (4-64)
and represents the input resistance of the amplifier without feedback.
4.3 Feedback Configurations 225
___________________ J
(a) approximate feedback network
(b)
Figure 4-15 (a) Shunt voltage feedback configuration using an equivalent circuit
for the basic amplifier. (b) Circuit for calculating the output resistance.
The input current to the basic amplifier ii is equal to vslria, which, combined
with Eqs. (4-61) and (4-63), yields
(4-65)
ria roa
(4-66)
1 + rm Rio Roo f
ria roa
It is to be noted that for this amplifier the feedback factor f has units of
amps Ivolt. Further, it is noted that if the feedback signal is removed,
(4-67)
226 Chapter 4 - Feedback and Compensation
In this context, a (which has units of volts/amp) represents the gain of the
amplifier without feedback. Thus, Eq. (4-66) can be expressed in terms of the
fundamental feedback equation
a a
(4-68)
is 1+ af 1+ T
Input Resistance
Thus,
_ Rio _ RiO
R------ (4-71)
I 1 + af 1+T
Output Resistance
The test circuit shown in Fig. 4-15(b) is used to calculate the output resistance
of the shunt voltage feedback amplifier. The output current resulting from the
test voltage is
(4-72)
At the input,
(4-73)
(4-74)
4.3 Feedback Configurations 227
Vee
I s
feedback network
where in the last term we have used Eq. (4-67). The output resistance is then
_ Vo _ Roo _ Roo
R -------- (4-75)
o io 1 + at 1+T
(4-76)
(4-77)
228 Chapter 4 - Feedback and Compensation
-+ I
I
I fb RF I
r if-:'"
short
I
4?-
J r of
(a) (b)
Figure 4-17 (a) Procedure for calculating feedback current and equivalent output
resistance of the feedback network. (b) Procedure for calculating the equivalent
input resistance of the feedback network.
(4-78)
(4-79)
where in the second term we have used gm2 r,,2 = 13F2. Summing the currents at
the collector of QJ gives
V2+Vo V2
gmJvJ+ +-=0 (4-80)
Rc r,,2
4.3 Feedback Configurations 229
RF
-=\~
loading of feedback loading of feedback
network at input network at output
(a)
1...----4----',-0 V 0
,
(b)
Figure 4-18 (a) AC equivalent circuit of the shunt voltage feedback amplifier. (b)
Small-signal equivalent circuit without feedback.
(4-81)
(4-82)
which, solved for VI and substituted into Eq. (4-81), gives for the open-loop gain
a a
(4-84)
is 1 + af 1+T
230 Chapter 4 - Feedback and Compensation
where
a
T=af= - - (4-85)
RF
The input resistance without feedback [see Fig. 4-18(b)] is
(RsIIRF)r"l
Rio = --'----- (4-86)
RsIIRF+ r,,1
The input resistance with feedback is then
(4-87)
Series Current
is io
~ ~
basic
+ transconductance
Vs
amplifier
is+
+
feedback ~
f i0 10
network
(a)
feedback
is io
network
Thevenin Thevenin
equivalent equivalent
8+';0
~--------------------~
: ri f :
~
._--------------------
I I
Figure 4-19 (a) Series current feedback amplifier. (b) Transformation of feedback
network.
feedforward signal through the basic amplifier. roJ is the equivalent resistance
at the output port of the feedback network, evaluated with is set to zero (input
open circuited). The resulting approximate equivalent circuit for the feedback
network is shown in the bottom panel of Fig. 4-19(b).
The basic transconductance amplifier is represented by the equivalent circuit
shown in the upper portion of Fig. 4-20(a); here, ria represents the input
resistance of the basic transconductance amplifier and roa its output resistance.
232 Chapter 4 - Feedback and Compensation
V\.,.--........;;--.....
1.-i
I 0
I
+ + I
Vs ria vi roa:
I •
Ro
!---------------------J-:
~-------------------,
: ri f :
•• I
•
•• f io
•
•
•. --------------------•
approximate feedback network
(a)
(b)
Figure 4-20 (a) Series current feedback configuration using an equivalent circuit
for the basic amplifier. (b) Circuit for calculating the output resistance.
(4-90)
where
Roo = Toa+ TOf+RL (4-91)
and represents the output resistance of the amplifier without feedback (f= 0).
4.3 Feedback Configurations 233
At the input,
(4-92)
where
(4-93)
and represents the input resistance of the amplifier without feedback.
The input voltage to the basic amplifier Vi is equal to is ria, which, substituted
into Eq. (4-90) and combined with Eq. (4-92), yields the gain
grn ria roa
Rio Roo
(4-94)
It is noted that for this amplifier the feedback factor f has units of volts lamp.
If the feedback signal is removed,
Input Resistance
With reference to Fig. 4-20(a), the input resistance of the amplifier with
feedback is
VS
R·=-I •
(4-97)
Is
Output Resistance
In the series current feedback amplifier, the output signal is a current (io). The
output resistance is determined by breaking the series output circuit and ap-
plying a test current as shown in Fig. 4-20(b). The output voltage resulting
from the test current is
(4-100)
At the input,
ria fi == r;afio
Vi == -----1 (4-101)
Rs + ria + rif 0
Substituting for Vi into Eq. (4-100) gives
(4-102)
Thus,
(4-103)
Vee
feedback network
The procedure for calculating the equivalent circuit of the feedback network
is illustrated in Fig. 4-22. As shown in Fig. 4-22(a), we open-circuit the input
side of the feedback network to calculate the feedback voltage. The voltage
developed across RE2 is
(4-104)
Thus,
(4-105)
(a) (b)
Figure 4-22 (a) Procedure for calculating the feedback voltage and the equivalent
output resistance of the feedback network. (b) Procedure for calculating the equiv-
alent input resistance of the feedback network.
236 Chapter 4 - Feedback and Compensation
+~:'
V,1:" AS
RE2I1( R F+ R E1 )
oj:>.
~\ i:.v
loading of feedback "T1
R E111 ( R F+ R E2 ) CI>
~ loading of feedback network at output CI>
(a) network at input
a.
cr
~
;;-
()
o
::J
Req1~ Req3~ cO"
-
v 02 c
+ Pi0"
vs ::J
RL (J)
R E2 II ( R F+ R E1)
I\)
c.v
Figure 4-23 (a) AC equivalent circuit of the series current triple. (b) Small-signal equivalent circuit without feedback. -...J
238 Chapter 4 - Feedback and Compensation
a a
(4-114)
Vs 1 + af 1+ T
where
aR EI RE2
T= af= - - - - - - - (4-115)
aF3 (REI + RF + Rd
Typically, the open-loop gain for the series current triple is very large (a
numerical example follows). The loop gain T will, therefore, usually be much
larger than unity, giving
io 1 aF3 (REI + RF + Rd
-=- =------- (4-116)
Vs f REI RE2
The gain is thus set principally by the resistance values of the feedback
network.
EXAMPLE. Determine a, T, the closed-loop gain iolvso and R j for the series
current triple amplifier of Fig. 4-21. The circuit elements are Rs = 6000,
RCI = 5 kO, RC2 = 3 ill, REI = 200 0, RE2 = 1000, and RF = 1 k!1. The bias collector
currents are I CI = 500 ,....A, I C2 = 1 rnA, and I C3 = 2 rnA. In addition,
I3FI = 13F2 = 13F3 = 100. Take room temperature.
These bias currents give r1TI = 5.2 kO, r1T2 = 2.6 kO, and r1T3 = 1.3 kO. Using Eqs.
(4-110) and (4-108),
which indeed is much larger than unity. Hence, the closed-loop gain is
io 1
-=-=64.5mA/V
Vs f
For the input resistance
Rio = Rs + R eql = 0.6 kO + 5.37 kO = 5.97 kO
Thus,
Ri = (l + T)Rio = (451) (5.97 kO) = 2.69MO
which is large.
Shunt Current
In the shunt current feedback configuration, repeated in Fig. 4-24(a), the
output current io is sampled by the feedback network and a feedback current flo
is mixed in parallel at the input. The effect of the feedback network on the
amplifier can be seen by the circuit transformation depicted in Fig. 4-24(b).
As far as the feedback network is concerned, it sees a voltage Vi, the voltage
at the input to the basic amplifier, at its input and a current io at its output; it
is appropriate, therefore, to represent the input side of the feedback network
by its Norton equivalent and the output side of the feedback network by its
Thevenin equivalent. The Norton equivalent at the input consists of resistance
rif in parallel with the short-circuit current ise; rif is the equivalent resistance at
the input port of the feedback network, evaluated with io set to zero (output
open circuited), and isc is the current at the input of the feedback network with
Vi set to zero (input short circuited). isc is the feedback signal, equal to flo. The
Thevenin equivalent at the output consists of resistance r of in series with the
open-circuit feedforward voltage, which is neglected in comparison with the
feedforward signal through the basic amplifier. roJ is the equivalent resistance
at the output port of the feedback network, evaluated with Vi set to zero (input
short circuited). The resulting approximate equivalent circuit for the feedback
network is shown in the bottom panel of Fig. 4-24(b).
The basic current amplifier is represented by the equivalent circuit shown
in the upper portion of Fig. 4-25(a); here, ria represents the input resistance of
the basic current amplifier and roa its output resistance. The feedback network
is represented by its approximate equivalent circuit. From the circuit in Fig.
4-25(a), the output current is
(4-117)
where
(4-118)
and represents the output resistance of the amplifier without feedback if = 0).
240 Chapter 4 - Feedback and Compensation
----.
i i
basic
+
i s RS vi current
amplifier
+it b
----.
f io
feedback ~
io
network
(a)
feedback
io
network
Norton Thevenin
equivalent equivalent
G
~--------------------i
I I
l,u + lio
(b)
~--------~---------;
feedback signal
Figure 4-24 (a) Shunt current feedback amplifier. (b) Transformation of feedback
network.
I
Ro
~--------------------
r------------------~
I I
I I
I I
~------------- ______ I
(a) approximate feedback network
(b) r of
Figure 4-25 (a) Shunt current feedback configuration using an equivalent circuit
for the basic amplifier. (b) Circuit for calculating the output resistance.
The input current to the basic amplifier is equal to VJria, which, substituted
into Eq. (4-117) and combined with Eq. (4-119), gives the gain
airoaRio
ria Roo
(4-121)
It is noted that for this amplifier the feedback factor f has units of amps lamp.
If the feedback signal is removed,
io I =a = airoaRio (4-122)
is /=0 ria Roo
Here, a (which has units of amps lamp) represents the gain of the amplifier
242 Chapter 4 - Feedback and Compensation
without feedback. Thus, Eq. (4-121) can be expressed in terms of the funda-
mental feedback equation
a a
is 1+ af 1+ T
(4-123)
Input Resistance
With reference to Fig. 4-25(a), the input resistance of the amplifier with
feedback is
V·
R=~
I •
(4-124)
ls
Thus,
R.=~=~
I 1+ af 1+ T
(4-126)
Output Resistance
The output resistance is determined by breaking the series output circuit and
applying a test current as shown in Fig. 4-25(b). The output voltage resulting
from the test current is
(4-127)
At the input,
(4-129)
Thus,
(4-130)
Vee
I 5
1.. _ _ _ _ _ _ _ _ _ _ _ _ _
feedback network
-
Figure 4-26 Shunt current feedback example.
Figure 4-26 illustrates a shunt current feedback amplifier employing two com-
mon-emitter gain stages. In the circuit, the feedback network samples the
output current and a feedback current, proportional to 10> is applied in shunt
with the input. To show that this circuit constitutes negative feedback, visual-
ize the output current increasing: An increase in 10 increases the voltage across
RE which increases the current flowing through the feedback resistance RF to the
input node; this increases the base current of Qh causing it to conduct more
heavily, lowering the voltage at its collector. Q2 conducts less, lowering its
collector current 10 ,
The procedure for calculating the equivalent circuit of the feedback network
is illustrated in Fig. 4-27. As shown in Fig. 4-27(a), we short-circuit the input
side of the feedback network to calculate the feedback current
(4-131)
(4-132)
(4-133)
244 Chapter 4 - Feedback and Compensation
---+ I
I fb
r if-:'"
short
(a) (b)
Figure 4-27 (a) Procedure for calculating feedback current and equivalent output
resistance of the feedback network. (b) Procedure for calculating the equivalent
input resistance of the feedback network.
io I = a=
i, /=0 [r"l + Rsll(RF + Rd][Rc + r ,,2 + (13F2 + l)(RFIIR E)]
(4-l34)
Amplifiers may simultaneously employ both shunt and series feedback; such
amplifiers are termed dual-loop feedback amplifiers in that two separate feed-
back paths exist. Dual-loop feedback allows a more independent control of the
amplifier's closed-loop input and output impedances; this is useful, for
example, if the amplifier is to interface with specified source and load imped-
ances [5].
RL
is
RFIIRE -
feedback current ~
~"loading of feedback
network at output oc
(a) OJ
T
S-
o
"C
io II
(1)
~ (1)
a.
rr
gm2 v 2 RL ~
;'~-Rsf-:~Ri ,.1:, 7'
(b)
Figure 4-28 (a) AC equivalent circuit of the shunt current feedback amplifier. (b)
Small-signal equivalent circuit without feedback. I\)
~
(]'I
246 Chapter 4 - Feedback and Compensation
shunt voltage
feedback network
.--- l-
RS
I/\,
basic
amplifier +
+ .--- I-
vs RLS Vo
.~
""- I-
series current
feedback network
(a)
shunt current
feedback network
.--- l-
RS
../'v I-
basic
amplifier
+
Vs
.--- l- )
RL>
""-
series voltage
feedback network
(b)
Figure 4-29 (a) Series current-shunt voltage dual-loop feedback amplifier. (b)
Series voltage-shunt current dual-loop feedback amplifier.
Figure 4-29 illustrates the two possible global dual-loop configurations em-
ploying shunt and series feedback. In Fig. 4-29(a), a series current-shunt
voltage feedback amplifier is depicted, and in Fig. 4-29(b), a series volt-
age-shunt current feedback amplifier is shown. Each of these will be consider-
ed in the sections that follow.
4.4 Dual-Loop Feedback 247
shunt voltage feedback network
r olv
I I
~---------------------
+
,,
: ria Vi
: '
~----------------------~
~--------------------
,, rile
feio role
,
L ____________________ ~ ,
series current feedback network
Figure 4-30 shows a dual-loop series current and shunt voltage feedback
amplifier using a transconductance equivalent circuit model for the basic
amplifier. Any of the four equivalent circuit representations for the basic
amplifier could be used; the transconductance model is a convenient and
familiar form. Parameters representing the equivalent circuit of the series
current feedback network are denoted with the subscript c (for current) and
those representing the shunt voltage feedback network are denoted with the
subscript v (for voltage). We analyze this circuit for the closed-loop voltage
gain, volvs.
At the output, the voltage across the output resistance of the amplifier roo is
gm Vi roa [roJc + (rojVIIR L)]
vroa = - gm Vi roal I[roJc + (rojVIIR L)] = - -'-----'---'---- (4-135)
roo + roJc + (rojvlIRL)
The output voltage, using the voltage-divider relation, is
rojVllRL
Vo = Vroa (4-136)
(rojVllRL + roje)
248 Chapter 4 - Feedback and Compensation
(4-l38)
where
(4-l39)
and represents the output resistance of the amplifier without feedback and
excluding the external load, R L•
Summing the currents at the input gives
(4-140)
(4-141)
(4-142)
where
(4-143)
and represents the input resistance of the amplifier without feedback, excluding
the source resistance, Rs. Applying the voltage-divider relation at the input
gives
(4-144)
(4-145)
4.4 Dual-Loop Feedback 249
a= (4-148)
and
(4-149)
(4-150)
v, 1 + af
Here, f represents the net feedback factor combining both the series and shunt
feedback paths. If the loop gain, af, is much greater than unity, the closed-loop
gain is approximately
(4-151)
Input Resistance
(4-152)
(4-153)
250 Chapter 4 - Feedback and Compensation
--.
i in
.--i 0
roa
r ofc
+
fcio
(a)
roa
As r if v
r ofc
+
fcio
(b)
Figure 4-31 (a) Circuit for calculating the input resistance. (b) Circuit for calcu-
lating the output resistance.
a(1 +~)
RIO
v = -----'---'---- Vin (4-154)
o I _a (I +~)
Rio
(I +~) £RL
rajv
(4-155)
4.4 Dual-Loop Feedback 251
- (1 +
I-a ( 1 +RS) RL)-Ie-
R-=~= Rio rojv RL R- (4-156)
iin 1 + a(Rs + Rio) r/v _ (1 + ~)~]
t
1 10
rojv rifvRL
The numerator of Eq. (4-156) represents the increase in input resistance due
to the series feedback path and the denominator represents the decrease in
resistance due to the shunt feedback path.
If the series and shunt loop gains a( ) are much larger than unity, then the
input resistance is approximately
(4-157)
Output Resistance
To calculate the output resistance, excluding the load resistance, we place a
test source at the output of the feedback amplifier, as indicated in Fig. 4-31(b).
The output resistance is calculated from
R=~
o • (4-158)
Ix
(4-159)
Also,
(4-160)
which gives
(4-161)
(4-162)
Summing the currents at the input, denoting the voltage across the parallel
combination of resistors Rs and rifv as Vin' gives
which leads to
(4-164)
(4-165)
which, solved for Vin and substituted into Eq. (4-164), gives
(4-166)
Finally, combining Eq. (4-167) with Eq. (4-162), and noting Eq. (4-148), yields
ix[l-a(1 +RS)(I
riJl'
+~)£]=~{I
Roo RL Roo
+a(1 +Roo)[Rslv_
RL
(I +Rs)£]}
rifv rofo
(4-168)
Thus,
1+ (I + (I +~)£]
Ro = (4-169)
a Roo) [RsI,' _ 00
RL rifv rofo
The numerator of Eq. (4-169) represents the increase in output resistance due
to the series feedback path and the denominator represents the decrease in
resistance due to the shunt feedback path.
If the series and shunt loop gains a( ) are much larger than unity, then the
output resistance is approximately
(I + ~)fc
R = __'----_r2.:ift:. .'.-,- - - (4-170)
o ( R)I'
1 + _s _J_'c - Rslv
rifv r ofo
4.4 Dual-Loop Feedback 253
Figure 4-32 Dual-loop series current-shunt voltage feedback amplifier using local
feedback.
Figure 4-32 shows a dual-loop feedback employing local series current and
shunt voltage feedback; emitter-degeneration resistor RE provides the series
feedback for the single-transistor amplifier. and resistor RF provides shunt
feedback between collector and base. In this circuit, rife = rote = RE and rifv = rop = RF.
The series feedback voltage (neglecting base current) is
(4-l71)
so
(4-172)
The shunt feedback current (determined by shorting the input to the amplifier)
IS
(4-173)
so
(4-l74)
In this amplifier, rio = r m Rio = RFII(r + RE)' and Rno = R F, neglecting rna = roo
1T
Using Eq. (4-148), the open-loop gain, assuming that roo ~ raJe (i.e., ro ~ R E), is
I3FR~RL
a = - --------'---'---------- (4-175)
[(r 1T + R E) (Rs + RF) + RsRFl (RF + RL)
where we have substituted I3F = gm r 1T.
254 Chapter 4 - Feedback and Compensation
f= (4-176)
(4- I 77)
If the value of the loop gain is considerably larger than unity (for this ampli-
fier, this is achieved by making gmRE» 1), then the closed-loop gain of the
amplifier can be approximated as
Va I
-=-= (4- I 78)
V, f ~+(I+RS)(I+RL)RE
RF RF RF RL
Further, if the shunt feedback resistance RF is much larger than both the source
(Rs) and load (R L ) resistances, then the gain is
Va
-= ----- (4-179)
Rs RE
-+-
RF RL
The first term on the right-hand side of Eg. (4- I 79) represents the contribution
to the closed-loop gain resulting from the shunt feedback path, and the second
term represents the contribution to the gain from the series feedback path.
Also, for the loop gain much larger than unity, the input resistance (exclud-
ing Rs) from Eg. (4-157) is
(I +~) RE
RF RL
R i = ---,---'-=--,------.:..--- (4-180)
(I +~)~+-I-
RF RFRL RF
Likewise, from Eg. (4-170), the output resistance (excluding R L ) is
(4-181)
Note the symmetry in Egs. (4-180) and (4-181) as they relate to the source
and load resistances.
4.4 Dual-Loop Feedback 255
(4-186)
To design for a specific closed-loop gain under matched conditions, the feed-
back resistances are then given by
(4-187)
and
(4-188)
Figure 4-33(a) shows a series triple amplifier employing series current and
shunt voltage feedback; the feedback network comprising resistors REb RFh and
RE2 samples the output current and applies a feedback voltage in series at the
input, and resistor RF2 provides shunt voltage feedback from the output to the
input of the amplifier.
256 Chapter 4 - Feedback and Compensation
shunt voltage
feedback network
+
-,
I
I
I
I
I
I
series current
(a) feedback network
+
I
R·--.
I I
(b)
Figure 4-33 (a) Dual-loop series current-shunt voltage feedback amplifier. (b) AC
circuit for calculating feedback parameters.
so
fv= (4-190)
4.4 Dual-Loop Feedback 257
(4-191)
where in the rightmost term we have taken aF3 to be unity. The series feedback
voltage is then
(4-192)
so
(4-193)
(4-195)
v, I RsRL(REI + RFI + Rd + REI RE2RF2
In arriving at Eq. (4-195), we have assumed that RF2 » Rs and RL. Likewise, the
input resistance (excluding Rs) is, from Eq. (4-157),
R= Ie (4-196)
I £-Rdv
rifv
(4-197)
As with the previous example, a simultaneous match at both the input and
output requires that Rs = RL, giving
(4-198)
where R = Rs = RL.
258 Chapter 4 - Feedback and Compensation
(4-199)
The dual-loop series voltage and shunt current feedback amplifier, also using
a transconductance equivalent circuit model for the basic amplifier, is shown
in Fig. 4-34. Analysis of this circuit proceeds in a fashion similar to that
RS
I 1
I + 1
I
I r oa :
I 1
Ri-++
liin ~----------------------!
1--------------------,
: r ilv :
.--_--'--+_..J
1
1
fvvo r olv :
1
1
L ____________________ 1,
carried out for the series current-shunt voltage configuration. Again, the
closed-loop voltage gain can be expressed as
Vo a
(4-202)
Vs 1 + af
with
a= (4-203)
and
(4-204)
Here,
(4-205)
and
(4-206)
If the loop gain, of, is much greater than unity, the closed-loop gain is given
approximately by
(4-207)
Input Resistance
The circuit in Fig. 4-35(a) is used to calculate the closed-loop input resistance;
Ri is equal to Vin li in , and results in
1+ a (1 + Rs )fv
RIO R. (4-208)
l-a(R s +R io)[(1 +~)£_£] 10
roIv RL rije
The numerator of Eq. (4-208) represents the increase in input resistance due
to the series feedback path and the denominator represents the decrease in
resistance due to the shunt feedback path.
For large loop gain,
(4-209)
260 Chapter 4 - Feedback and Compensation
i in io
-+- 4-
r olc +
+ r olv RL Vo
vin r ilc + Icio
roa
+
Iv v0
(a)
io
4-
r olc
+
r olv Vo
RS r ilc + Icio
roa
+
Iv Vo
(b)
Figure 4-35 (a) Circuit for calculating the input resistance. (b) Circuit for calcu-
lating the output resistance.
Output Resistance
The test circuit in Fig. 4-35(b) is used to calculate the closed-loop output
resistance; Ro is equal to voli m and results in
I - a (I + Roo) Rs fe
RL Roo R
Ro = (4-210)
I +a(l + Roo)[(l +~)fe-!!!...fe] 00
RL rife roJv
The numerator of Eq. (4-210) represents the increase in output resistance due
to the series feedback path and the denominator represents the decrease in
resistance due to the shunt feedback path.
If the loop gain is much larger than unity, the output resistance is approxi-
mately
(4-211)
4.4 Dual-Loop Feedback 261
Vcc
+ .- - - - - - - - - - - -- -.
"- - - - - - - - I
r~~:~-----::1--~t
1 1 ,
,
, shunt current
R E2: feedback network
1 1 ,
1 1 ,
1 _ 1 , _
1____________ -' ,_____ _
series voltage
(a) feedback network
Rc .- io . ; - Ro
Vo
°2
°1
+ RF2
Vs
,,
,~
I fb
-L- RF1
+
(b) - --
Figure 4-36 (a) Dual-loop series voltage-shunt current feedback amplifier. (b) AC
circuit for calculating feedback parameters.
Figure 4-36(a) shows a two-stage amplifier employing series voltage and shunt
current feedback; the voltage divider comprising resistors REI and RFI provide the
feedback voltage and the current divider comprising resistors RE2 and RF2 provide
the feedback current.
262 Chapter 4 - Feedback and Compensation
(4-212)
so
fc= (4-213)
Also,
(4-214)
(4-215)
so
(4-216)
Also,
(4-217)
Typically, the feedback resistances RFI and Rn will be considerably larger than
the source, R s, and load, R L , resistances. If this is the case, then Eq. (4-218)
simplifies to
(4-219)
(4-220)
4.4 Dual-Loop Feedback 263
From Eqs. (4-209) and (4-211), the approximate input and output resistances
are
(4-221)
and
EXERCISE. Assuming that the current gain (I3F) of the transistors are much
larger than unity, show that the open-loop gain of the dual-loop feedback
amplifier in Fig. 4-36(a) is given by
Vee (+6 V)
200 n
~------+---~ Vo
12 n
200 n
Figure 4-37 NE5205 wideband amplifier employing series voltage and shunt cur-
rent feedback.
264 Chapter 4 - Feedback and Compensation
(fT) of about 2 GHz [6]. In the circuit, the Darlington pair comprising transistors
Q2 and Q6 are used in place of the single second gain transistor Q2 in Fig.
4-36(a); this provides additional buffering at the output. Transistor Q3 buffers
the feedback loading of RFI at the output, and the diodes formed by Q4 and Qs
provide dc level shifting.
It is clear that for IT(jw) I = I and <I> = - 180°, the gain [from Eq. (4-223)]
would become infinite. The conditions for stability can be stated: If the
magnitude of the loop gain is equal to or greater than unity at some frequency
where the phase of the loop gain is - 180°, then the amplifier is unstable.
Stated mathematically,
ITUw)l::=: I atw where L TUw) =- 1800 (4-224)
Both the gain and phase are affected by feedback. Consider the feedback
system depicted in Fig. 4-38 in which the feedback network is independent of
frequency-such as would be for a feedback network fashioned from passive
resistive elements. As there is no phase shift associated with the feedback
network, the closed-loop phase derives solely from the amplifier. Denoting the
4.5 Stability of Feedback Amplifiers 265
phase shift of the amplifier by 8, the closed-loop gain can be expressed in the
form
The denominator in Eq. (2-226) is larger than unity, giving <I> < 8. Thus, the
phase is reduced with negative feedback.
To illustrate the gain and phase relationship with feedback, consider first an
amplifier with a single pole at frequency PI' The open-loop gain of the ampli-
fier is then
(4-227)
(4-228)
and phase
.
LaUw)= -tan -I( -w )
Ipil
(4-229)
266 Chapter 4 - Feedback and Compensation
With feedback
(4-230)
1 + jw/lpd
where To = ao! and Ao = aol(l + To).
In terms of gain magnitude and phase,
IAUw)1 = Ao 2
(4-231 )
~ 1+ [wl(l + To)PI]
I
and
20 log(a o ) I---,t.-----~
To
-45
gain (dS)
closed· loop gain at this value is stable
-------:-------f
I I I
20 10g(Ao)
= ~t I
I
for To» 1
phase (deg)
-90
-180
-270
-360
Consider now an amplifier with multiple poles (more than two) such that
an
aUw) = . . . (4-233)
(1 +~)(1
Iptl
+~)(1
Ip21
+~)
Ip31
...
and
-La U)
w=tan -I(W)
--+tan -I(W)
--+tan _I(W)
- - + ... (4-234)
Ipll Ip21 Ip3 1
The gain and phase characteristics of this amplifier are illustrated in Fig. 4-40.
The phase shift for an amplifier with three or more poles can exceed 180°, so
the potential for instability exists with feedback applied. If the magnitude of
the loop gain TUw) is greater than or equal to unity at the frequency at which
268 Chapter 4 - Feedback and Compensation
its phase is - 180°, then the amplifier will be unstable; the frequency at the
180° phase point is denoted WISO and marks the boundary between stable and
unstable operation: As illustrated in Fig. 4-40, a feedback amplifier with a
closed-loop gain equal to or smaller than that given for IT(jw)1 = 1 at W = WISO
is unstable-closed-Ioop gains larger than this value are stable and have a
phase less than - 180°. The difference between this phase and the 180° line
is the phase margin, denoted <Pm. At W = WISO, the amplifier's open-loop phase is
- La U ) =tan -I(WISO)
WISO - - +tan -I(WISO) - - + ... = 1800
- - +tan -I(WISO)
Ipil Ip21 Ip31
(4-235)
The poles in most amplifiers are usually widely separated in frequency. Thus,
poles beyond the third contribute little to the total phase shift of the amplifier.
In addition, one pole is usually dominant, meaning it is at a frequency that is
perhaps 5 or 10 times lower than the frequency of the next pole. If this is the
case, then the first dominant pole, say p" will contribute nearly 900 to the phase
shift of the amplifier. Thus,
(4-236)
so
(4-237)
where a trigonometric identity has been used for the middle terms in Eq.
(4-237). Thus, the WISO frequency is approximated by
(4-239)
4.5 Stability of Feedback Amplifiers 269
(4-241)
If the low-frequency loop gain To = aof is much greater than unity, then 1 If = Am
and the gain at Wo relative to the gain at low frequency becomes
The relative gain at Wo for various values of phase margin is listed in Table
4-1. A phase margin of 90° is achievable only for amplifiers containing a
single pole. At a 60° phase margin, the response is flat at woo Smaller values
of phase margin give rise to gain peaking. In practice, amplifiers are designed
for phase margins in excess of 30° to minimize peaking of the response.
Figure 4-41 shows the simulated gain and phase response of a feedback
amplifier containing three poles, at - 10 kHz, - 100 kHz, and - 1 MHz.
Without feedback, the open-loop gain is 60dB. Various amounts of feedback
are applied to give closed-loop gains of 40, 30, and 20dB. Both gain peaking
and the steepness of the phase shift increase with increased feedback, f At
40 dB gain, the phase margin is 58° with a gain peaking of 0.3 dB. At 30 dB,
the phase margin is 26° with a gain peaking of 6.8 dB, and at 20 dB, the phase
margin is 14° with a gain peaking of 12dB.
270 Chapter 4 - Feedback and Compensation
gain (dB)
60 " - -_ _ __
openlo~G~_
u~
=-----~-r--------=
40 dB
30 +---- . . ----:~--- . . - - - - -
30 dB
~~~---~------~
20 dB
o+-------~~-------+------~~~
1 kHz 10 kHz 100 kHz 1 MHz
phase (deg)
•
frequency
o !J_iS~~!!!::::::{'~*::==:=:=:::: ,~
-100
'~.~
U.... ;
-----------------------~ - - - -180
-200
'~,
Figure 4-41 Gain and phase response of a three-pole feedback amplifier.
(4-244)
The gain and phase characteristics of this amplifier are sketched in Fig. 4-42.
The maximum phase shift is 27ff, which can lead to instability if the amplifier
is operated with sufficient feedback such that phase shift is 180 at a frequency
0
where the magnitude of the loop gain is unity. For unconditional stability, that
4.6 Compensation of Feedback Amplifiers 271
gain (dB)
20 log(ao) I--------,.~
I
I stable
-90
-180
- 270
Figure 4-42 Gain and phase characteristics of an amplifier containing three poles.
Compensation Methods
20 log(ao)
o
';j"
~
"0
CD
.....
-
.j:>.
"'T1
CD
CD
o I ",,, \: • (0 (log scale) a.
CT
Ip A I Ip 11 (OTC Ip ;1 Ip 3 I (OTU
phase (deg) ~
~
'"
ot • (0 (log scale) ::J
a.
o
o
-90 3
compensated phase "0
CD
::J
-1 80 en
~
<:5"
::J
-270
-360
. vee
Figure 4-44 Two-stage op-amp using added-pole compensation.
which indeed is at a frequency much lower than the original dominant pole
(1 MHz) of the amplifier. The resistance in parallel with Cc sets the added-pole
frequency:
1
IPAI = 21T !fpA I = 31.4 radsls = ------,-
(R ol IIR i2 ) C c
where Ro' is the output resistance of the differential input stage (neglected in
this example) and R;2 is the input resistance of the second gain stage (Q5 and
Q6) and is equal to approximately 600 k!1. The value of the compensation
capacitance is then
1
Cc = =53nF
(31.4 rads/s)(600k!1)
which is rather large.
gain (dB)
20 log(a 0)
o::::;
Il)
"0
m
"'"'
~
"TI
en
en
a.
CT
Il)
o I '-toe:: \. ~ ro (Jog scale) o
Ip'1 I III Ip 1 I ro TG Ip 2I Ip 3 I ro TU Il)
"
phase (deg) :::J
a.
ot ~ ro (log scale) oo
3
"0
-90 en
:::J
compensated phase C/l
!!?
- 180 o·
--------------------------------f-------~. :::J
-270
Figure 4-45 Compensation by moving the dominant pole of the amplifier to a lower frequency.
4.6 Compensation of Feedback Amplifiers 275
(a)
Cc
i s
(b)
Figure 4-46 (a) Pole-splitting compensation capacitance added to amplifier gain
stage. (b) Equivalent circuit of gain stage with compensation capacitance.
This approach yields a much larger bandwidth than with the added dominant
pole method because (J)rc is now near pz. which may be 5-10 times the frequency
of PI. Also, the required value of the compensation capacitance is much lower,
making it integratable on-chip.
Moving the dominant pole is achieved by Miller multiplication, in which
the compensation capacitor is connected as a feedback element across the
second-gain stage. This is illustrated in Fig. 4-46(a). In Fig. 4-46(b), the gain
stage is modeled in terms of the total resistance R; and capacitance C; at its
input, the total resistance Ro and capacitance Co at its output, and the effective
transconductance Gm of the stage. Compensation capacitance Cc is connected
between the input and output of the stage.
Consider first the response of the stage without the compensation capacitor.
It is easy to show that
GmRiRo ao
(4-245)
(l + SRi C;) (1 + sRo Co) (1 - s /PI)(l - s /P2)
Consider now the circuit with the compensation capacitor. Summing the cur-
rents at the input node in Fig. 4-46 gives
(4-247)
(4-248)
Combining Eqs. (4-247) and (4-248) gives, for the response of the stage,
Vo - RiRo(Gm - sCc)
i, 1 + S [Ri(Ci + Cc) + Ro(C + Cc) + GmRiRol +/ RiRo [CC + CdC + Co)]
(4-249)
The response has two poles and a zero; the zero is at a frequency Gm/C e . The
compensation capacitance C e is generally small. Thus, if the transconductance
G m of the stage is reasonably large, then the zero will be at a much higher
frequency than those of the poles. The zero will have a negligible effect on
the response and can be neglected. In addition, the term GmR;Ro is generally
much larger than the first two terms mUltiplying s in the denominator of Eq.
(4-249). Thus, Eq. (2-249) becomes approximately
Vo ao
-= (4-250)
is 1 + sGmR;Ro + i R;Ro [CC o + CdC; + Co)]
which can be written as
Vn an ao
(4-251)
i, (l-s/p[)(I-s/pD l-s(lIp[+lIpD+i(lIp[pD
where p[ and p~ are the new pole frequencies of the gain stage. Normally, one
of the poles will be dominant, say p [. Hence,
Vo an
-=-----:-....."..---:---:- (4-252)
is l-s/p[+i(lIp[pD
Equating the coefficients of s in the denominator of Eqs. (4-250) and (4-252)
gives
p[= (4-253)
(4-254)
4.6 Compensation of Feedback Amplifiers 277
'--
P2 (4-255)
+Vee
+
Vin
_ 0'----1------1
-,-
--.- ,, Co
,: Ci
- Vee '--v--'
Gm
Figure 4-47 Two-stage op-amp using pole-splitting compensation.
278 Chapter 4 - Feedback and Compensation
This frequency is six times larger than the 5 Hz obtained in the previous
example. The required value for the compensation capacitance is from Eq.
(4-253):
1
--------------------~----------=25pF
(7.5mAIV)(600ko')(50X 10 3 0,)(174 rads/s)
which is considerably smaller than the 58 nF required in the previous example.
The second pole (originally at - 6 MHz) has been moved out [using Eq.
(4-255)] to
I Gm 7.5xlO- 3
-9.43 X 109 rads Is ( - 1.5 GHz)
P2=- C;+Co =- (0.265+0.53)XlO 12
which is now truly nondominant. The third pole of this amplifier at - 40 MHz
now becomes the second most dominant pole.
If MOSFETs are used in the second gain stage, the value of Gm will be
considerably lower (perhaps a factor of 10) than for a bipolar stage. The
transfer function of the stage is still given by Eq. (4-249); however, due to the
lower value of G m , the frequency of the zero may not (in fact, probably not)
be much higher than that of the poles. Consequently, the effect of the zero
cannot be ignored; the zero tends to flatten the gain at high frequencies due
to its + 20 dB Idecade contribution to the amplitude response. In addition, this
positive real zero contributes - 90° to the phase shift, giving a negative phase
margin at the unity-gain frequency. As a result, the compensation will not be
effective in stabilizing the amplifier.
Two techniques, illustrated in Fig. 4-48, have been developed to eliminate
the effect of this low-frequency zero. At high frequencies, the feedforward
signal through the feedback network (Cd is not negligible with respect to the
feedforward gain of the amplifier stage; in Fig. 4-48(a), a unity-gain buffer
inserted in the feedback path eliminates the feedforward signal through Cc [7].
Although this technique works well, it does require additional devices and adds
to the circuit complexity. A simpler method is to insert a nulling resistor, R z,
in series with the compensation capacitance, as illustrated in Fig. 4-48(b) [8].
With this resistor, the frequency of the zero is given by
1
z=------ (4-256)
(1 IG m - Rz) Cc
4.6 Compensation of Feedback Amplifiers 279
unity-gain
buffer
(a)
Cc RZ
(b)
Figure 4·48 Compensation schemes for MOSFET gain stages: (a) using a buffer to
eliminate the feedforward signal through the compensation capacitor; (b) using a
resistor to alter the location of the zero.
(4-258)
280 Chapter 4 - Feedback and Compensation
For the special case in which the frequency of the zero is set equal to that of
the dominant pole PI, the loop gain becomes
(I__S)[I+_I (1 __S)(I-_S)]
A (s) = --c-----,--;:------------:;-
PI + 1 To P2 P3
( I_~)[I
PI
+_1 __
s (_I +_1)+
I+Tn I+Tn P2 P3
i
(l+To )P2P3
]
(4-262)
In the denominator of Eq. (4-262), the term 11(1 + To) can be neglected with
respect to 1. In addition, if P3 is much larger than P2, then the term Ilp3 may
be neglected with respect to the I1p2 term in the denominator. Consequently,
Eq. (4-262) becomes approximately
An
A (s) = (4-263)
s]
2
(1 -S)[
- 1- S +-----
PI (l + Tn) P2 (l + To) P2P3
which, for Ip31 » Ip21, can be expressed in the form
A (s) = Ao (4-264)
(1 -PIS)(
- 1-
[1
S)(
+ To ]P2
1+-S)
P3
4.6 Compensation of Feedback Amplifiers 281
gain (dB)
20 log(ao) 1 - - - - - - ,......
20 10g(Ao) +-------j.. . .
-9 0
closed-loop
-180 ---------------------- ~- ---- -f~
open-loop /" ~
-270
ZFI =
I\)
vo (Xl
I I\)
RC2
,
L._______ -- FBN CD
CD
"a.
rr
~
RS 200 0.1 pF 0.1 Dl
'"
::J
\, II L---------,r:::-i'-O v 0 a.
+ ~~----~----~~--~~II RC2 n
Vs o
5 k 3
-g
::J
fJ)
~
o·
::J
Figure 4-50 (a) AC schematic of feedback zero amplifier. (b) Small-signal equivalent circuit.
4.6 Compensation of Feedback Amplifiers 283
and a pole at
Because RF ~ R E , the feedback zero is dominant and PFI can be neglected, giving
!(S)=!o(l--S)
ZFI
where
At a bias current of 1 rnA, gml = 40mA/V for QI, and gm2 = 80mA/V for Q2
biased at 2 rnA; for 13 F = 100, r'IT I = 2.5 kG for Q h and r 'lT2 = 1.3 kG for Q2. For the
transistors, CjE and CjC are taken as 0.3 pF and 0.1 pF, respectively, and 'TF is given
as 30 ps. This gives C'lT1 = 1.S pF and C'lT2 = 3 pF. The small-signal equivalent
circuit for the feedback amplifier is shown in Fig. 4-S0(b).
Figure 4-S1 shows the simulated gain and phase response for the feedback
amplifier of Fig. 4-S0(b). Two sets of characteristics are shown: one without
the feedback zero (C F = 0), and one with O.IS pF of feedback capacitance.
Without the feedback zero, the amplifier is unstable; with the zero, the ampli-
fier has a phase margin of about 7So.
gain (dB)
30
20
10
O+-----------r-----------r---------~~--~----~~
1 MHz 10 MHz 100 MHz 1 GHz 10 GHz
phase (deg) frequency
o o-----.-----o~ee~~=_--------------------~--~-- ••
-.~
-------.-------~----~--
-100
-180
-200 . . . ~
-300
\ . . . 0,
Figure 4-51 Gain and phase response of a feedback zero amplifier.
284 Chapter 4 - Feedback and Compensation
Problems
For all problems assume room temperature, kT/q = 26mV.
Note: Where required, use the following device parameters unless otherwise
specified:
NPN: 13F = 100 I s =2XlO- 16 A
PNP: 13F = 50 Is = 5 X 10 -17 A VA = 75 V
NMOS: W /L = 10 f-lnC~x = 30 I-J.A /V 2 VTH = 1 V
PMOS: W /L = 30 f-lpC~x = 10 f-lA/V 2 VTH = - 1 V A = 0.02 V-I
4.1 An amplifier has a measured gain of 2000. After adding negative feed-
back, the gain is reduced to 50.
(a) Find the loop gain, T, and the feedback factor, f
(b) The gain of the basic amplifier has a sensitivity to temperature of 10%.
What is the sensitivity of the closed-loop gain (with feedback) to tempera-
ture?
4.2 A feedback amplifier is to have a closed-loop gain of 30dB and a sensitivity
of 2% with respect to gain variations in the basic amplifier. What open-loop
gain, a, of the basic amplifier is required? Determine the loop gain, T.
4.3 A feedback amplifier has a low-frequency open-loop gain, am of 104 and
an open-loop unity-gain frequency,fr, of 100 MHz. The basic amplifier can
be characterized by a single-pole response. With feedback, the amplifier
is to have a - 3-dB bandwidth of 2 MHz. Determine the required feedback
factor, 1, and the resulting low-frequency, closed-loop gain, Am of the
amplifier.
4.4 In the feedback amplifier of Fig. 4-52, the transistor bias currents are
lei = 500 f-lA and IC2 = 1.2 rnA. Determine the closed-loop gain, Vo/Vi, and the
~----~-----T--OVO
+
bias currents
I C1 = 500 IlA
I C2= 1.2 rnA
'-----+-00 Vo
~Ro
of---1~:-o v0
I
where
and
+6 V
-6 V
Figure 4-56 Feedback amplifier for Problem 4.8.
Problems 287
I
' -IR o
transistors, take IVBE (on) I = 0.8 V and VA = 00. Assume the quiescent output
voltage is zero.
4.9 Show that the open-loop gain of the amplifier in Fig. 4-26 is given by
Eq. (4-134).
4.10 In the analysis of the feedback amplifier of Fig. 4-57, To of the transistor
may be neglected.
(a) Show that the open-loop gain is given by
_
a- -
Vo _
- -
gm(RFIIT,,)(RFIIR L)
..::....c....:.......'--....:.......-'---_ _
Vs Rs+(RFIIT,,)
(b) Excluding the source and load resistances, show that the closed-loop
input and output resistances are given by
and
where
Rs
and f= RF
5V
Ri~
"t
':-'f'""----1
(b) Determine the open-loop gain a = in/is, the closed-loop gain vn/i s, and
the closed-loop input resistance, R i•
(c) Check your results in (b) using SPICE (or similar) circuit simulation.
4.12 For the CMOS feedback amplifier shown in Fig. 4-59, determine the
open-loop gain, a = vn/v" the closed-loop voltage gain, and the closed-
loop output resistance. Use the transistor parameters given at the begin-
ning of the problem section except for M 7, which has a channel width/
length ratio W /L = 60.
+5 V
W/L = 60
M7
I -__.J\I\~--+---o V 0
- M6 Me
-5 V
- 0-' I
II I II II .I ________ •
4.13 Figure 4-60 shows a voltage regulator circuit; its purpose is to deliver a
constant (regulated) voltage from a power supply which may vary in
value. Additionally, the output voltage, Vo> should remain constant with
changes in the load, RL • The circuit functions as a feedback amplifier
which forces the voltage at the base of Qz (the inverting input of the
differential amplifier) to be equal to the reference voltage connected at
the noninverting input of the amplifier. The voltage divider provided by
the feedback sampling resistors then gives Vo = (l + RFIR E) Vref •
(a) The loading of the feedback network may be neglected in comparison
with R L • Show that the open-loop gain, depicting the gain between the
base of Qz and the output, is given approximately by
a= !l!.!....(~
VAZ VA4 II13F513 F6 Yo)
2kT 11 VAZ + VA4 10
(b) To maintain good regulation with respect to changes in the load, the
regulator should have a very low output resistance. Again neglecting the
loading effect of the feedback network, and assuming that the loop gain
T is much larger than unity, show that the closed-loop output resistance
of the regulator, including R L , is given by
2 kQ
- I c(bias) = 10 rnA
(c) The change in output voltage resulting from a change in load current
is determined by LlVa = LlloRo- The load regulation is defined as
Ll Vo Ra
Load regulation = - - = -Ma
Va Va
Determine the load regulation for the circuit of Fig. 4-60 for a change
in output current of lOOmA in which Va = IOV and 10 = lOrnA.
4.14 Determine the closed-loop voltage gain, input resistance, and output
resistance of the cascode feedback amplifier shown in Fig. 4-6\. The
transistors are each biased at 10 rnA and their output resistances, ra> may
be neglected.
4.15 Figure 4-62 shows the NE5205 used as a high-frequency amplifier. The
dc blocking capacitors, Cs and CL , may be assumed large such that they
have zero impedance at the frequencies used by the amplifier.
(a) Calculate the quiescent bias collector currents of all transistors in the
amplifier as well as the quiescent voltage at the collectors of Q2 and Q6.
You may neglect the Early voltage for the transistors and take
VBE(onl = 0.75 V.
(b) Determine the closed-loop voltage gain, va/v" as well as the input (R;)
and output (Ra) resistances, as indicated in the figure.
(c) Check your results in (a) and (b) using SPICE circuit simulation.
4.16 Verify Eq. (4-226) for the closed-loop phase of a feedback amplifier.
4.17 An amplifier has a low-frequency gain of 60 dB (1000) and a frequency
response with three negative real poles at - 100 kHz, - 1 MHz, and
- 10MHz.
(a) This amplifier is to be connected in a feedback loop withf= constant
and a low-frequency closed-loop gain of 40 dB (100). Determine the
bandwidth fa> the phase margin <Pm, and the amount of gain peaking atfo-
(b) Repeat (a) for a closed-loop gain of 20 dB (l0).
Problems 291
Vee (+6 V)
650 n R e
+r':
I
R·~
50 n Cs
Vs
200 n
+Vee
- Vce
Figure 4-63 Operational amplifier circuit for Problem 4.19.
+5 V
_0--1 . . . ---...~2
Vi
M_1 R Z 2 pF
+o~-----I
MS
W/L = 5
-5 V
4.20 In the CMOS operational amplifier shown in Fig. 4-64, resistor Rz is used
in conjunction with the 2-pF compensation capacitor to move the zero to
infinity. The amplifier itself can be characterized as having a capacitance
of 0.5 pF at the output of the input stage (from the drain of M2 to ground)
and a capacitance of 0.5 pF at the output (from the drain of M7 to ground).
(a) Determine the value of the resistance Rz needed to move the zero to
infinity. Use the transistor parameters given at the beginning of the
problem section except for Ms which has a channel width !length ratio
WIL=5.
Problems 293
+5 V
(b) Calculate the open-loop voltage gain a, the - 3-dB bandwidthfm and
the unity-gain frequency he.
(c) Compare your results in (b) with a SPICE circuit simulation. Also,
simulate the circuit with Rz set to zero to show the effect of the zero on
the phase margin of the amplifier.
4.21 In the CMOS amplifier of Fig. 4-64, a load capacitance CL is connected
at the output.
(a) Determine the largest value for CL for which the amplifier maintains a
phase margin of 45°. Assume that the conditions stated in Problem 4.20
apply.
(b) Using the value for C L determined in (a), simulate the circuit using
SPICE to verify the phase margin.
4.22 In Fig. 4-65 (which shows a portion of the CMOS amplifier of Fig. 4-64),
transistor M9 is used in place of the zero compensation resistor R z . Deter-
mine the required channel widthllength ratio (WILh of M9 such that its
resistance is equal to that required to move the zero to infinity.
4.23 The ac schematic of a fixed-gain feedback amplifier is given in Fig. 4-66.
+
Vo
is
References
Translinear Circuits
Translinear circuits form a class of circuits which exploit the linear relation-
ship between the transconductance of a transistor and its voltage or current.
These circuits were originally developed with integrated bipolar transistors [1],
but more recently, have included integrated MOSFET devices as well [2].
Applications of translinear circuits include (1) wideband current amplifiers, (2)
analog multiplier/divider circuits, (3) root-mean-square (rms) conversion cir-
cuits, (4) sine/cosine generation circuits, and (5) other signal processing cir-
cuits, to name a few.
In this chapter, we present the translinear circuit principle as it applies to
bipolar and MOS circuits. Several types of translinear circuits are also dis-
cussed.
There are two classes of trans linear circuits which relate the transconductance
of a transistor to either its current or voltage:
(5-1)
295
296 Chapter 5 - Translinear Circuits
I 1
its collector current and that this relationship is maintained over a wide range
(many orders of magnitude) in current. This property, as we shall see, when
applied to circuits containing loops of base-emitter junctions and which have
inputs and outputs consisting of currents allows precise linear and nonlinear
signal processing functions to be implemented.
An example of a simple translinear circuit is shown in Fig. 5-1; the reader
will recognize this circuit as a basic current mirror. Here, however, we will
view the circuit in a slightly different context. The base-emitter voltages of
the two transistors are
(5-3)
and
where JS I,2 and A 1.2 are the saturation current densities and emitter areas of tran-
sistors QI and Q2, respectively. In the right-hand term of Eq. (5-3), we have
neglected base currents and approximated lei by the current source h Assuming
identical transistors (except for emitter areas), J SI = JS2 , and noting that Vbel = Vbe2 ,
Eqs. (5-3) and (5-4) give
(5-5)
six decades in current and several hundred degrees Celsius. In the circuit of
Fig. 5-1, current source II may be viewed as an input signal and 12 as an output;
this circuit functions then as a current amplifier, with a gain equal to A 2 IA I •
Figure 5-2 shows another translinear circuit; here Ix and Iv are input currents
and the output is taken as the collector current of Q4, 10 • We will neglect base
currents and assume that the four transistors are identical. Summing the base-
emitter voltages around the closed-loop containing Qh Q2, Q3, and Q4 gives
(5-6)
kT (Ix)
2-ln kT (Iv)
- = -In --'- kT (10)
+ -In - (5-7)
q Is q Is q Is
from which
l
I=~ (5-8)
o Iv
which again, over a wide range, is independent of temperature, the value of Is,
or the magnitudes of signals Ix and Iv.
,
",
--- _......
Figure 5-3 Translinear loop containing bipolar transistors.
current sources are shown connected as inputs and outputs are taken as col-
lector currents. Summing the base-emitter voltages around the loop gives
N
L Vbej = 0
j=1
or L Vbej = L Vbej
CW CCW
(5-9)
where
kT (le
Vbej=-ln --j )
(5-10)
q Ajls
Substituting Eq. (5-10) into Eq. (5-9) and assuming identical transistors, except
for emitter areas, yields
"" kT
L -In(/ej -
) _-"L - n (Ie
" kTI - j) (5-11)
cw q Aj ccw q Aj
which can be written as
n(/c,) n (/c
cw AJ
=
ccw
1)
AJ
(5-12)
Noting that lejlA j equals the collector-current density, Eq. (5-12) expresses the
trans linear circuit principle for bipolar transistors: The product of the current
densities in a clockwise direction equals the product of current densities in a
counterclockwise direction [1].
5.1 Translinear Circuit Classes 299
The translinear circuit of Fig. 5-2 is repeated in Fig. 5-4 to illustrate analysis
using the translinear circuit principle. Transistors Q3 and Q4 have clockwise
base-emitter polarities and transistors QI and Q2 have counterclockwise polar-
ities. With identical emitter areas, we have
12
Iylo = Ix Ix ~ 10 = ~ (5-13)
Iy
Figure 5-5 shows another example of a translinear circuit having two inputs;
the bidirectional arrow on the Ix input current indicates that it may flow in
either direction. Input Iv may flow only in the direction indicated. The IX and
2X notations indicate relative emitter areas for the transistors. Applying the
translinear principle to loop 1 containing transistors Q I, Qz, Q4, and Q5 yields
Icl Iez Iv Iv
----- (5-14)
2 2
and for loop 2 comprising Q I and Q3,
(5-15)
Taking I, to be a positive quantity when flowing into the circuit, summing the
currents at the x input (neglecting base currents) gives
(5-16)
At the output,
(5-17)
Substituting Eq. (5-15) into Eq. (5-17) and combining with Eq. (5-16) yields
10 + Ix 10 - Ix
lei =--- and I cz =--2- (5-18)
2
which, using Eq. (5-14), gives
(5-19)
This circuit forms a vector magnitude.
Gilbert [1] classifies translinear loops according to the arrangement of base-
emitter junctions. In Fig. 5-6(a), the translinear loop contains junctions ar-
ranged with alternating polarities, and in Fig. 5-6(b), the arrangement is bal-
anced. Both circuits have the same translinear response, namely
12 14 II 13
(5-20)
A2 A4 Al A3
There is a difference, however, with respect to I3F sensitivity as it relates to
base current. Consider currents II and 12 to be inputs and the collector currents
of Q3 and Q4 to be outputs. Then for equal emitter areas,
(5-21)
13 12
In the balanced arrangement, the base currents of Q3 and Q4 are dependent on
the emitter currents of QI and Q2, and hence on the input currents II and 12• The
relationship in Eq. (5-21) is thereby sensitive to I3F. In the alternate arrange-
5.1 Translinear Circuit Classes 301
ON roN ON
(a)
(b)
Figure 5-6 (a) Translinear loop with alternating polarities. (b) Loop in which the
polarities are balanced.
ment, the base currents of Q3 and Q4 are not dependent on II and 12 and thus the
relationship is, to first order, independent of I3F.
Consider a translinear circuit with a voltage source Vs inserted into the loop.
Taking Vs to be positive for a clockwise sense, summation of the voltages
around the loop gives
I
CW
V~i+ Vs= I
CCW
Vbej (5-22)
In n(~) +
cw AJs
qVs = In
kT
n(~)
ccw AJs
(5-23)
302 Chapter 5 - Translinear Circuits
from which
n (Icj)
cw Aj = e -qV,lkT
(5-24)
n (Icj)
ccw Aj
The differential pair shown in Fig. 5-7 may be analyzed as a translinear loop
containing a voltage source. From Eq. (5-24), we have directly
II qV,lkT
-=e (5-25)
12
1 2
1=-aV+b (5-27)
2
where b is another constant.
Equation (5-27) describes the ID - Vas characteristic for a MOSFET operating
in saturation. Like the bipolar counterpart, circuits containing loops of gate-
source junctions of MOSFETs operate in a translinear fashion. The range in
current over which the transconductance remains linear with voltage is con-
siderably less than with bipolar transistors. None the less, useful MOSFET
translinear circuits have been produced.
5.1 Translinear Circuit Classes 303
Icw V gsj = I
ccw
Vgsj (5-28)
with
(5-29)
where
K = fLC;x
.I 2
Thus,
(5-30)
For matched devices, the threshold voltage terms cancel, and thereby the K j
terms. The translinear principle for MOSFETs then becomes
~"~dj- - - - - -_ ~
" ~dj
----- (5-31)
cw (W IL)j ccw (W IL)j
304 Chapter 5 - Translinear Circuits
which states: The sum of the square-root currents per unit aspect ratio in a
clockwise direction equals the sum of the square-root currents per unit aspect
ratio in a counterclockwise direction [2].
A MOSFET translinear circuit is shown in Fig. 5-9; the (4X) notation on
transistors M 1 and M2 indicate that their channel !length ratios (W IL) are four
times that of the other transistors. Application of Eq. (5-3\) to the loop
containing transistors M J, Mb M 3, and M4 yields
Here, Idl = Id2 = II'. Also, Id4 = Id3 + Ix = IdS, and 10 = Id3 + IdS. Combining these
Pi"-
relations into Eq. (5-32) results in
2 - - /10
-- + It+ J-
10 - -
Ix (5-33)
4 V 2 2
which solved for 10 yields
(5-34)
5.2 Analog Functions with Translinear Circuits 305
Vector Magnitude
(5-37)
Combining Eqs. (5-35) and (5-36) into Eq. (5-37) then gives
10 = JI; + I; (5-38)
306 Chapter 5 - Translinear Circuits
Vee
The vector magnitude circuit of Fig. 5-10 operates in a current mode; input
signals, as well as the output, are currents. For the circuit to operate with
voltage signals, voltage-to-current converter circuits can be placed at the inputs
and a current-to-voltage converter circuit can be placed at the output.
Figure 5-11 illustrates a circuit that functions well as a voltage-to-current
converter. In the circuit, QI and Q2 form a current mirror which, due to their
equal base-emitter voltages, have the same collector currents. These current
are reflected in the collector currents of Q3 and Q4, causing them to have the
same base-emitter voltages; the voltage at the emitter of Q4 is thereby equal to
the input voltage Vx at the emitter of Q3. The emitter current of Q4 is thus equal
to VJR" which is then (neglecting base currents) equal to the collector current
of Q2. This current is mirrored by Q5 giving an output current that is propor-
tional to the input voltage. This circuit derives from a general form of this
configuration called a current conveyor [4].
The circuit of Fig. 5-10, combined with voltage/current converter circuits,
results in the voltage-mode vector magnitude circuit shown in Fig. 5-12. In the
circuit, the current mirror provided by QI and Q2 converts the output current to
an output voltage Vo = R 2 I o. Thus,
(5-39)
Two-Quadrant Squarer
Circuits that provide an output proportional to the square of the input find
application in power measurement and high-frequency, radio-frequency (RF)
5.2 Analog Functions with Translinear Circuits 307
+ +
(5-40)
2 2
Neglecting base currents and taking Ix positive entering the input node,
(5-41)
which combine to give
I bias + Ix
II
c
= ---.::.:=---.:.:..
2 and (5-42)
Vee
~
o
VDD
(5-43)
Absolute Value
----'1----------+--- vee
Ix
QI. which is part of a Wilson current source comprising transistors Qt, Q3, and
Qs. The output current is then given from Eq. (2-24) as
I = I [1 -
o x
2
~}+2~F+2
]= I
x
(I - ~)
~}
(5-45)
For Ix negative, the Wilson current source is off and the output current flows
through transistors Q2 and Q4. It is easily shown that
I =I
a x
[1 - ~}+2~F+2
1 ]= I (1 __~;,1_)
x
(5-46)
Analog Multipliers
10
10
6
rnA
0
-10 rnA o 10 rnA
Ix
Figure 5-16 Simulation of the absolute-value circuit.
such as mixers, balanced modulators, and phase detectors. The Gilbert multi-
plier cell, illustrated in Fig. 5-17, fonns the basis of many multiplier circuits
[5].
The Gilbert cell consists of two cross-coupled differential pairs (QJ, Q2 and
Q3, Q4), fed serially by a third differential pair (Q5, Q6); the x-input signal is
+
Vx
+ 0----/
Vy
applied to the upper differential pairs and the y-input signal is applied to the
lower differential pair. The output is taken differentially at the collectors of
the cross-coupled pairs, expressed as
(5-48)
As expressed by the right-hand term in Eq. (5-48), the output is equal to the
difference in the differential collector currents of the two upper differential
pairs. The differential output current of a single pair is given by Eq. (2-233)
(5-49)
where base currents have been neglected; V!2 is the differential input voltage.
Applying Eq. (5-49) to Eq. (5-48) gives
(5-50)
Substituting for the differential current of the lower differential pair, Eq. (5-50)
becomes
_f
fo - bias
(qV y) (qVx)
tanh 2kT tanh 2kT (5-51)
The product is nonlinear in Vx and Vy • If, however, the amplitudes of the signais
are much smaller than the thermal voltage, kT /q, then the tanh functions are
approximately linear, giving
(5-52)
To remove this restriction on the signal amplitudes, the input signals can be
preprocessed to compensate for the tanh nonlinearity. In this regard, consider
the circuit shown in Fig. 5-18. Here, the modulation parameter x in the current
sources represents an input signal; its value can vary between - I and + I.
The voltage difference between the emitters of the two transistors is given by
(I+X)
tanh ~I x =I - I n - - (5-54)
2 I-x
shows that the circuit in Fig. 5-18 can be used to compensate for the tanh
nonlinearity of the differential pairs in the multiplier circuit. This compensa-
tion needs to be applied only to the x input; because (Fig. 5-17) Ie5 - Ic6 varies
as tanh (V,), the lower differential pair (Qs, Q6) can be eliminated if the y inputs
are supplied as currents. Such a linearized multiplier circuit is shown in Fig.
5-19. In the circuit, the x and y signals are proportional to the input voltage
signals: x = K, V, and y = K, V" The output current (lei + Ie3 ) - (lc2 + I(4 ) is given by
10 = [(1 + y) I, - qLlV)
(1 - y) Iv] tanh ( 2kT (5-55)
+
v
Diode Linearization
lei = (1 + _1_·
hias
)h
and
(5-59)
lei = (1 +_V_)h= (l + x) IE
2hias R
and
+
v R R
- o~----------I----------~
2 IE
(a)
(b)
Figure 5-21 Two forms of linearization by emitter degeneration_
where x = V f2hias R. The two collector currents are now linearly proportional to
the input voltage V.
Emitter Degeneration
Placing resistors in the emitter circuit of a differential pair can linearize the
response; the resistors provide emitter degeneration and two alternate forms
are shown in Fig. 5-21. For the circuit in Fig. 5-21(a), summing the voltages
around the base-emitter loop yields
(5-62)
where base currents have been neglected. If IER» kT fq, then the two base-
emitter voltages in Eq. (5-62) can be assumed to be approximately equal; they
thereby cancel, giving leI - Ie2 = V fR. Also, leI + Ie2 = 2/e. Combining these
relations with Eq. (5-62) gives
leI = (I + _V_) Ie = I +x
2IeR
5.2 Analog Functions with Translinear Circuits 315
+ vee
+-_--()+ V Z - 0----+
\i
Y
- vee
Figure 5-22 Four-quadrant analog multiplier (MC-1495 type).
and
Ic2= (I-~)IE=
2IeR
I-x
,.
(5-63)
where x = V 12IeR.
The version shown in Fig. 5-2I(b) gives the same result [Eq. (5-63)];
however, it has a voltage range that is about 2Vbe less than that using the version
in Fig. 5-2l(a).
A simplified schematic of a commercial four-quadrant analog multiplier
circuit is shown in Fig. 5-22; it utilizes the second version of emitter degen-
eration [Fig. 5-21(b)] for linearization. The output voltage Vz = loRz = 2lyR z xy,
which, using Eqs. (5-52) and (5-63), results in
(5-64)
10T-------------------------------------------~
v z (volts)
o ~----~------------~~~------------------~
10~--------~----------------------~--------~
-10 -5 o 5 10
Vx (volts)
The MOS version of the Gilbert multiplier cell is shown in Fig. 5-24 [6]. As
with the bipolar transistor version, the output is taken differentially as
(5-65)
W) 2Iss _ V2
Idl - Id2 = K (L VIZ K(WIL) 12
(5-66)
where K = I-LnC~x 12 and VIZ is the differential input voltage, with a range given by
-~<V<~
VKcWii5 VK(Wii) 12
(5-67)
5.2 Analog Functions with Translinear Circuits 317
Vx
hi as +V 2/bias _ V2 _ V2
K(W IL) y K(W IL) y x
hias
-- --V 2 2]
21bias -V-V (5-69)
K(WIL) Y K(WIL) Y x
I -_K(W)
-V [( hias V; + Vy)2
-- - - V2
o L x K(WIL) 2 [2 x
Here, the output current is nonlinear in Vx and Vy , in which both inputs interact.
Thus, the inputs cannot be predistorted to compensate for the nonlinearity as
was done with the bipolar multiplier circuit. However, if the magnitudes of
J
the inputs are kept small with respect to I bias K (W IL), Eq. (5-70) simplifies to
which is linear in Vx and V,,; typically, the inputs are limited to about ± 0.5 V
before significant nonlinearity appears.
Linearization
Consider the differential pair shown in Fig. 5-25 wherein a component pro-
portional to the square of the differential input voltage is added to the com-
mon-source bias current. Here,
Thus,
(5-73)
+ 0----1
V
- O~----I
Vx
- 0-----1--------'
K (W' L) v2 K (W' L) v2
+ 0>------1 2 x 2 x
Vy
- 0---------- ---------~
(5-74)
hias [bias
---<Vx,y< (5-75)
K(WIL) K(WIL)
which implies that a small channel width--channel length ratio (W IL) is desired
for a large input range; VDsat is equal to this range, however. Thus, Vx needs to
have a large common-mode component relative to the differential-mode com-
ponent to keep transistors M 1-M2 and MrM4 operating in the saturation region.
320 Chapter 5 - Translinear Circuits
I hi" ~
+O~I~
Vx
- O~----~--------------I
+ O~------I~
Vy
- 0--1 Ms M6
Using a folded CMOS Gilbert cell structure, shown in Fig. 5-27, allows a
smaller common-mode voltage to be used. For this circuit,
and
hias Kp (W IL)p
Id6=-+ V (5-77)
2 2 v
(5-78)
5.2 Analog Functions with Translinear Circuits 321
Linearization Implementation
The two circuits shown in Fig. 5-28 can be used to implement the MOS
linearization scheme. Consider first the circuit of Fig. 5-28(a), in which input
Vx contains a common-mode component Vex. The output current is
Voo
+ 0---1
o----------------~
(a)
Voo
0 - - - -__-1
+
\lex
c:L
(b)
Figure 5-28 Linearization circuits for the MOS multiplier.
322 Chapter 5 - Translinear Circuits
The first tenn on the right-hand side of Eq. (5-80) represents the bias current
due to the common-mode voltage, Ven and the second tenn represents the
linearization component. The common-mode component can be implemented
by the circuit of Fig. 5-28(b) in which
(5-81)
(5-82)
(5-84)
(5-86)
::E
;:::+
::J
-i
i»
:J
~
M 21 S·
CD
III
M 20 -.
o
~.
c:
-Voo
~
Figure 5-29 Linearized CMOS multiplier circuit.
w
I\:)
w
324 Chapter 5 - Translinear Circuits
I c 1 + I c5 + +IC2+I C6
TL sine
0.5
c
-0
-
( ,)
C
0.0
:::II
-0.5
-1 .0 1-.I.--'--'--'--1......&--'--'--'--I........L--'--'-..L....JL.......I.--'--'-............
-1 .0 -0.5 0.0 0.5 1.0
X (radians)
Figure 5-31 Plots of Eq. (5-86) and sin (x).
which corresponds to an angle - 1T < e < 1T radians, and is plotted in Fig. 5-31
along with the trigonometric sine function. The maximum error in the two
curves is about 3%.
A more accurate synthesis of the sine function can be obtained with the
circuit shown in Fig. 5-32 [7]. In this circuit, the inner transistor bases (Q2 and
Q3) are biased at a potential l88R more positive than the outer transistor bases
(QI and Q4); here, the voltage drop lEER controls the angle scaling factor. The
5.3 Trigonometric Functions with Translinear Circuits 325
input signal Vx controls the equivalent angle of the sine function, and for one
cycle of the function ( - 1 < x < 1)
(5-87)
When Vx = 0, the circuit is balanced with lei = Ic4 and Ie2 = I e3 . Taking the output
differentially as
(5-88)
(5-89)
326 Chapter 5 - Translinear Circuits
(5-90)
(5-91)
Combining Eqs. (5-91) and (5-92) and substituting into Eq. (5-88) yields
1- + eqlssRlkT (e2q'M3kT _ e qV,13kT)
eqV.lkT
It is profitable to let a = qIBB R IkT; then from Eq. (5-87), q Vx 13kT = a1T Ix. This
allows Eq. (5-93) to be cast in the following form:
~ = 1- e(3cdlT)x + eO. (e(2o.h')X _ e(o.h,)x)
hE 1 + e(3o.h,)x + eO. (e(2o.h')X + e(o.h,)x) (5-94)
600uA ~------------------------------------------------~
10 0A
-~0uA ~------~------~--------T-------~------~r-----~
-300mV -200mV -100mV 0.mV 100mV 200mV 300mV
Vx
Figure 5-33 Simulation of the circuit in Fig. 5-32 at various temperatures.
~I c2+ [c4
( 1-X)Ix
where, neglecting base currents, lei = (1 - x)/x and Ie4 = (1 + X)/e4' Additionally,
Iez + Ie3 = 2Iy (neglecting base currents), which, combined with Eq. (5-95), gives
Iez = (1 + x) Iy and Ie3 = (1 - x) Iy (5-96)
Taking the output differentially at the collectors of QI, Q3 and Qz, Q4, we obtain
10 = (lez + I e4 ) - (lcl - I e3 ) = 2x(Ix + I,,) (5-97)
Likewise, taking the input differentially at the emitters of QI and Q4,
lin = (1 + X) If - (1 - X) Ix = 2xlx (5-98)
The gain of this amplifier is then expressed as
(5-99)
where the ratio of the bias currents Ix and Iv sets the gain. The minimum gain
is unity and the maximum gain is limited to about 10 or so due to errors due
to finite base currents; the base currents of transistors Qz and Q3 add to the
output via transistors QI and Q4, which are out of phase. It is left as an exercise
for the reader to show that if base currents are taken into account, the gain is
given approximately by
. II Iz In
Gam = 1 +-+-+ ... +- (5-101)
Ii Ii Ii
The gain of each stage is limited to a maximum of about 10 and can be
independently controlled by its bias current, In. Used as a current-mode ampli-
fier, this circuit achieves a large bandwidth.
Problems
PNP: i3F= 50 Is = 5 X 10 - 17 A
Problems 329
(1-X)Ij (1+X)Ij
..--- INPUT---I~
5.1 Using the translinear circuit principle, determine the currents 11-/4 in the
diode ring in Fig. 5-36.
5.2 Using four bipolar transistors and a bias current source, design a trans-
linear circuit that gives
where A 1.2, 3, 4 are the emitter areas of the transistors, Base currents may be
neglected,
5.3 Using three MOS transistors and a bias current source, design a translinear
circuit that gives
I = (WILh I
o (W IL) 1 + (W ILh bias
10 = Idl -1d2 = K( W
L ) Vs 2/bias - V2
K(WIL) s
Problems 331
+ Vee
- Vee
Figure 5-38 Class AB output stage for Problem 5.5.
5.5 The Class AB output stage shown in Fig. 5-38 may be viewed as a
translinear circuit. Neglecting base currents, show that for VOU! = 0, the
quiescent bias current of the output transistors is given by
sources for transistors Q2 and Q5 to Vee and connect a second 5-V source to
the collector of Q5 to measure the output current 10 , In the simulation, vary
Ix from - 1 rnA to + 1 rnA, and plot the square root of 10 versus Ix to show
the squarer relationship. Simulate the circuit first with I3F set to 10,000 and
then with I3F set to 100 to show the effects of base current on the circuit
performance. Comment on it.
5.7 Verify that the output current of the two-quadrant CMOS squarer circuit
in Fig. 5-14 is given by Eq. (5-44).
5.8 In the translinear circuit shown in Fig. 5-39, all transistors are identical.
Determine the output current 100 neglecting base currents.
5.9 In the translinear circuit shown in Fig. 5-40, all transistors are identical,
(2X)
I cHIc2 +
Figure 5-42 Gilbert cell used as a four-quadrant multiplier for Problem 5.11.
334 Chapter 5 - Translinear Circuits
Voo
~
o
Iy
I x
21x l v
10 = . 2
KN(W IL)N(Vbias - 2VTN )
5.13 Figure 5-44 shows an analog function circuit in which input signal x
varies from - 1 to + 1. Determine the output function, taken as
10 = (lc2 + leg) - (lei + le7), expressing it as a function of x; base currents may
be neglected. Plot your result, normalized to I bia" for x varying from - 1
to + 1.
5.14 Show that the gain of the Gilbert gain cell shown in Fig. 5.34 is given
by Eq. (5-100).
Problems 335
I c1 + I c7 +
References
1. B. Gilbert, "Translinear Circuits: A Proposed Classification," Electron. Lett., 11, 14-16 (1975).
2. E. Seevinck and R.J. Wiegerink, "Generalized Translinear Circuit Principle," IEEE 1. Solid-
State Circuits, 26, 1098-1102 (Aug. 1991).
3. B. Gilbert, "Current-Mode Circuits from a Translinear Viewpoint: A Tutorial," Analogue IC
Design: The Current-Mode Approach, C. Toumazou, F.l. Lidgey, and D.G. Haigh, Eds., Peter
Peregrinus, London, 1990, Chap. 2.
4. A.S. Sedra and G.W. Roberts, "Current Conveyor Theory and Practice," Analogue IC Design:
The Current-Mode Approach, C. Toumazou, F.l. Lidgey, and D.G. Haigh, Eds., Peter Peregri-
nus, London, 1990, Chap. 3.
5. B. Gilbert, "A Precise Four-Quadrant Multiplier with Subnanosecond Response," IEEE 1.
Solid-State Circuits, SC-3, 365-373 (Dec. 1968).
6. l.N. Babanezhad and G.C. Ternes, "A 20-V Four-Quadrant CMOS Analog Multiplier," IEEE
1. Solid-State Circuits, vol. SC-20, 1158-1168 (Dec. 1985).
7. B. Gilbert, "A Monolithic Microsystem for Analog Synthesis of Trigonometric Functions and
Their Inverses," IEEE 1. Solid-State Circuits, SC-17, 1179-1191, (Dec. 1982).
Index
A Small-Signal Models, 14
saturation current, 3, 5
absolute value, 308
Transistor Cutoff Frequency, 18
additional pole, 271
transconductance, 16, 22
analog multiplier, 190
transit time, 10
B
C
BiCMOS,107
Bode plot, 266 Cascode,97
base-emitter voltage, 16, 50 input resistance, 98
base-emitter voltages, 296 output resistance, 98, 100
bias current, 111, 124, 133, 137, 166, 185 transconductance, 97, 99
bipolar junction transistor, 1 Cascade, 100
Base-Width Modulation, 10 input resistance, 100, 106
base resistance, 16, 22 output resistance, 101, 106
Cutoff,7 transconductance, 101, 107
Charge storage, 10 CMOS op-amp, 170
collector current, 4, 12 Common-Base, 89
collector-current density, 298 Active Load, 95
common-base current gain, 8 Gain Stages, 89
common-emitter current gain, 8 input resistance, 91, 94
diffusion capacitance, 10, 16 Miller effect, 90
Early effect, 11 output resistance, 91
Early voltage, 11 Resistive Load, 92
Ebers-Moll, 9 transconductance, 91
Ebers-Moll model, 2, 7 voltage gain, 93
emitter current, 4 Common-Emitter, 70
Forward-active, 5 Active Load, 74
junction currents, 3 Early voltages, 75 - 76
junction capacitances, 9 Gain Stages, 70
output conductance, 11 input resistance, 71
output resistance, 16, 22 output resistance, 72, 75
Parasitic Elements, 17 output voltage, 73, 76
Reverse-active, 6 Resistive Load, 72
337
338 Index