EXPERIMENT NO.

16

Aim: Verify the Full adder and counter (up, down, up/down) in FPGA kit.
Tools used: Xilinx ISE 14.7
Theory:
a) Full adder
Full adder is a digital circuit used to perform addition. It adds three one-bit binary
numbers, two operands and a carry bit.
Truth table:
Table no. 16.1 Design table for Full adder
a b c SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Block diagram:

Fig 16.1 Block diagram for Full Adder

Synthesis equation
i) SUM =X Y Z
ii) CARRY = XY+YZ+ZX

b) Up counter
An Up counter counts number of clock pulses from initial state to last state in a sequence.
Here a 4-bit Up counter is designed using asynchronous counter (where only first flip flop is clocked by
an external clock). For an n-bit Up counter there are total 2^n states.
Truth table:
Table 16.2 Truth table for Up counter
Clock Q0 Q1 Q2 Q3 Q0(+) Q1(+) Q2(+) Q3(+)
Cycle
1 0 0 0 0 0 0 0 1
2 0 0 0 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 0 1 1 0 1 0 0
5 0 1 0 0 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 1 0 0 1 1 1
8 0 1 1 1 1 0 0 0
9 1 0 0 0 1 0 0 1
10 1 0 0 1 1 0 1 0
11 1 0 1 0 1 0 1 1
12 1 0 1 1 1 1 0 0
13 1 1 0 0 1 1 0 1
14 1 1 0 1 1 1 1 0
15 1 1 1 0 1 1 1 1
16 1 1 1 1 0 0 0 0

Synthesis equation
̅ +QT
Qn+1 = TQ ̅

BLOCK DIAGRAM
Pre

1 1 1
1 Q Q
Q T T Q T
T
Clk Clk Clk
Neg edge f2 f3
clock Clk f1
f0

Qbar Qbar Qbar

Qbar

Clr

Fig 16.2 Block diagram for Up counter

c) Down counter
A DOWN counter counts number of clock pulses in inverse sequence. A 4-bit DOWN counter is designed
using an asynchronous counter. For an n-bit DOWN counter there are total 2^n number of states.
Truth table
Table 16.3 Design table for DOWN counter
Clock Q0 Q1 Q2 Q3 Q0(+) Q1(+) Q2(+) Q3(+)
Cycle
1 0 0 0 0 1 1 1 1
2 1 1 1 1 1 1 1 0
3 1 1 1 0 1 1 0 1
4 1 1 0 1 1 1 0 0
5 1 1 0 0 1 0 1 1
6 1 0 1 1 1 0 1 0
7 1 0 1 0 1 0 0 1
8 1 0 0 1 1 0 0 0
9 1 0 0 0 0 1 1 1
10 0 1 1 1 0 1 1 0
11 0 1 1 0 0 1 0 1
12 0 1 0 1 0 1 0 0
13 0 1 0 0 0 0 1 1
14 0 0 1 1 0 0 1 0
15 0 0 1 0 0 0 0 1
16 0 0 0 1 0 0 0 0

Synthesis equation
̅ +QT
Qn+1 = TQ ̅

Block diagram
Pre

1 1 1
1 Q Q
Q T T Q T
T
Clk Clk Clk
f2 f3
Pos edge Clk f1
clock f0

Qbar Qbar Qbar

Qbar

Fig 16.3 Block diagram for DOWN counter

d) UP/DOWN counter:
UP/DOWN counter counts both in a sequential order and in reverse order. Here an UP/DOWN counter is
designed using asynchronous counter and in order to select mode i.e., UP or DOWN counting mode a 2:1
Multiplexer has been used.
Synthesis equation:
Qn+1 = TQ̅ +QT
̅
Block diagram
Pre

I0 1 1 I0 1
1 Q I0 Q
Q T T Q T
T
Y Y
Y m2 Clk m3 Clk
Clk f3
m1 f2
Pos edge Clk f1
clock f0
S S
S Qbar Qbar Qbar
Qbar
I1 I1 I1

Clr

Fig 16.4 Block diagram for UP/DOWN counter

VERILOG CODE:
a) Full adder
module fa_fpga(
input a,
input b,
input c,
output S,
output Ca
);
assign {Ca,S}=a+b+c;
endmodule

b) Counter
i) Up counter
module counterup(input clk,reset,output reg [3:0]q);
reg [25:0] cnt = 0;
initial q<=4'b0000;
always @(posedge clk) cnt<=cnt+1; //cnt[25] is used as clock
always @(posedge cnt[25])
begin
if (reset) q<=4'b0000;
else q<=q+1;
end
endmodule
ii) Down counter
module downFPGA(input clk , input clr, output reg [3:0]q);
reg [24:0] cnt;
initial begin cnt<=0 ;
q<=4'b1111; end
always@(posedge clk)
cnt<=cnt+1;
always@(posedge cnt[24])
begin
if(clr)
q<=4'b1111;
else
q<=q-1;
end
endmodule

iii) Up/Down counter

module up_down_counter_FPGA( input CLK, RESET, MOD, output reg[3:0]Q );
reg [24:0] cnt;
initial begin Q <= 4'b1111; cnt <= 0; end
always @ (posedge CLK) cnt <= cnt+1;
always @ (posedge cnt[24]) //cnt[24] is used as Clock
begin
/////// if RESET ///////
if (RESET) Q <= 4'b1111;
else begin
/////// if MOD = 1 => UP COUNTER ///////
if (MOD) Q <= Q+1;
////// if MOD = 0 => DOWN COUNTER //////
else if (~MOD) Q <= Q-1;
end
end //end of "always"
endmodule
IMPLEMENTATION CONSTRAINTS FILE:
FULL ADDER:
NET “a” LOC = ”N17” ;
NET “b” LOC = ”H18” ;
NET “c” LOC = ”L14” ;
NET “S” LOC = ”F9” ;
NET “Ca” LOC = ”E9” ;
UP COUNTER / DOWN COUNTER / UP/DOWN COUNTER:
NET "clk" LOC= "C9";
NET "clr" LOC="N17";
NET "q[0]" LOC="F9";
NET "q[1]" LOC="E9";
NET "q[2]" LOC="D11";
NET "q[3]" LOC="C11";
Output:
a) Full adder

Fig 16.5 Output verification on FPGA kit for Full adder

b) Counter
i) Up counter

Fig 16.6 Output verification on FPGA kit for Up counter

ii) Down counter

Fig 16.7 Output verification on FPGA kit for Down counter

iii) Up/Down counter

Fig 16.8 Output verification on FPGA kit for Up/Down counter

RESULT: Verified Full adder and up,down,up/down counters in FPGA kit.