Independent University, Bangladesh (IUB)

School of Engineering, Technologies and Science (SETS)

Department of Computer Science & Engineering (CSE)
Marks Lab Report No 03

Allocated Obtained Course Code CSC204L/CCR204L

Course Title Digital Circuit Lab Report
Course Instructor Sheikh Saif Simran
Section 01
Student Name Md. Sahadat Hossain
Student ID 2221634
Due Date Submission Date

Experiment 3:
Designing and testing of 4-bit even parity generator and checker circuits using EX- OR
gates

OBJECTIVE:
● To verify of even parity generator and even
parity checker EX-OR gates.

APPARATUS:
● IC Type 7486 Quadruple 2-input XOR gates
● Digital Electronic Trainer Kit ● Power Supply
Unit

THEORY:

Example:
1) Signal without p.b.: 101101110010100
Signal with p.b.: 0101101110010100

2) Signal without p.b.: 101101110010100

Signal with p.b.: 1101101110010100

CIRCUIT DIAGRAM:

Truth Table:
Parity Generator:

Input Output
D3 D2 D0
D1 P
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
 1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Parity Checker:
I/P 0/P

P D D2 D1 D0 E
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 1 1
1 0 1 1 0 1
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 0
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 1 0 0
1 1 1 1 1 1
AND Operation:
Symbol Truth table

A B Q=A.B
0 0 0
0 1 0
1 0 0
1 1 1

OR Operation:
Symbol Truth table

A B Q=A+B
0 0 0
0 1 1
1 0 1
1 1 1

NOT Operation:
Symbol Truth table
A Q=Ā
0 1
1 0
** Presence of a small circle at the output side of any gate always denotes inversion

NOR Operation:
Symbol Truth table

A B
Q=̅𝐀̅̅̅̅̅̅+̅̅𝐁̅̅̅
0 0 1
0 1 0
1 0 0
1 1 0

NAND Operation:
Symbol Truth table

A B Q=̅𝐀̅̅̅̅̅𝐁̅̅̅
0 0 1
0 1 1
1 0 1
1 1 0
Pin diagram:

1. IC 7408 AND gate

 PIN diagram PIN description

PIN no. Function PIN no. Function

7 Ground 14 +Vcc
1,2 Input 3 Output
4,5 Input 6 Output
9,10 Input 8 Output
12,13 Input 11 Output

2. IC 7432 OR gate
PIN diagram PIN description

PIN no. Function PIN no. Function

7 Ground 14 +Vcc
1,2 Input 3 Output
4,5 Input 6 Output
9,10 Input 8 Output
12,13 Input 11 Output

3. IC 7404 NOT gate

PIN diagram PIN description

PIN no. Function PIN no. Function

7 Ground 14 +Vcc
1 Input 2 Output
3 Input 4 Output
5 Input 6 Output
9 Input 8 Output
11 Input 10 Output
13 Input 12 Output

4. IC 7400 NAND gate

PIN diagram PIN description

PIN no. Function PIN no. Function

7 Ground 14 +Vcc
1,2 Input 3 Output
4,5 Input 6 Output
9,10 Input 8 Output
12,13 Input 11 Output
5. IC 7402 NOR gate
PIN diagram PIN description

PIN no. Function PIN no. Function

 7 Ground 14 +Vcc
2,3 Input 1 Output
5,6 Input 4 Output
9,10 Input 8 Output
12,13 Input 11 Output

Overview:
In this lab, the goal is to plan and test a 4-bit even equality generator and
checker circuits utilizing EX-OR entryways. Equality is a method used to
recognize blunders in computerized information transmission. Indeed, even
equality guarantees that the quantity of 1s in each arrangement of pieces is
even. The lab involves implementing both the generator and checker circuits
using EX-OR gates to achieve even parity on a 4-bit binary input.

Methodology:

1. Planning the 4-bit Even Equality Generator:

Characterize reality table for a 4-cycle even equality generator. Utilize EXOR
doors to carry out the rationale for producing even equality. Connect the 4
input bits and the output bit.

2. Planning the 4-Bit Even Equality Checker:

Characterize reality table for a 4-digit even equality checker.Use EX-OR
gates to implement the logic for checking even parity Connect the 4 input
bits and the output bit.

3. Circuit Execution:
Utilize electronic reenactment programming or physical breadboarding to
carry out the planned circuits. Associate power supplies and ground fittingly.
4. Testing:
Apply various 4-bit binary inputs to the even parity generator. Verify that the
generated parity is even for all inputs. Apply inputs to the even parity
checker and confirm correct output based on the parity of the input.

Results:

Verify that the generator produces the correct even parity bit for various 4-bit
inputs. Confirm that the output bit is 1 if the number of 1s in the input is odd
and 0 if even. Confirm that the checker correctly identifies whether the input
has even parity. The output of the checker should be 1 if the input has an
odd number of 1s and 0 if even.

Conclusion:

The lab effectively showed the plan and usefulness of 4-digit even equality
generator and checker circuits utilizing EX-OR doors. The EX-OR doors
really played out the vital rationale tasks to produce and really look at even
equality in a 4-digit double succession. The consequences of the testing
stage affirmed the right activity of the two circuits, giving a solid method for
mistake location in computerized information transmission. This exercise
contributes to a deeper understanding of digital logic design and practical
applications in error detection techniques.