GM950
GM950
GM950E/GM950i
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8.
Mobile Radio
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Service Manual io
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6804111J39-B
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CAUTION
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ELECTROSTATIC SENSITIVE DEVICES
ISSUE 2.
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Cautions and Warnings
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Cautions and Warnings
SAFETY WARNINGS
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THE ELECTRICAL POWER USED IN THIS EQUIPMENT IS AT A VOLTAGE
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HIGH ENOUGH TO ENDANGER LIFE.
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CONCERNED MUST ENSURE THAT THIS EQUIPMENT IS ISOLATED
FROM THE ELECTRICAL SUPPLY AND TESTS ARE MADE TO ENSURE
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THAT ISOLATION IS COMPLETE.
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Cautions and Warnings
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Contents
Service Manual
Contents
Chapter
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1.0 Introduction
Gives a brief introduction into the manual and the service policy.
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2.0 Model Chart and Accessories
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Provides list of models and accessories available for the mobile radio.
3.0 Maintenance
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Describes how to disassemble/assemble the radio for maintenance purposes
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and gives details on safety precautions. There is also information on testing/
servicing the radio using the front panel and diagnostics test modes.
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Gives a detailed description about the operation of the radio. The information is
supplied to circuit reference detail.
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Appendix
A.0 PL (CTCSS) Codes
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Chapter 1
Introduction
Table of Contents
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Paragraph Page
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1.0 Introduction ................................................................................................ 1
8.
2.0 Scope of Manual ........................................................................................ 1
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3.0 How to Use This Manual ............................................................................ 1
4.0
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Warranty and Service Support ................................................................. 1
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4.1 Waranty Period ............................................................................................ 1
4.2 After Warranty Period .................................................................................. 1
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5.2 Transmitter.................................................................................................. 3
5.3 Receiver...................................................................................................... 3
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Introduction 1-i
Table of Contents
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1-ii Introduction
Introduction
1.0 Introduction
1
This chapter outlines the scope and use of the service manual and provides an overview of the
warranty and service support. The radio speciÞcations are also supplied in this chapter.
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3.0 How to Use This Manual
8.
This manual contains introductory material such as overview, model charts, speciÞcations and
accessories and the remaining chapters deal with speciÞc service aspects of the radio.
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Refer to the Table of Contents for a general overview of the manual.
Reseller contract. These conditions may change from time to time and the following notes are for
guidance purposes only.
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In instances where the product is covered under a "return for replacement" or "return for repair"
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warranty, a check of the product should be performed prior to shipping the unit back to Motorola. To
ensure the product has been correctly programmed or has not been subjected to damage outside
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Prior to shipping any radios back to the appropriate Motorola warranty depot, please contact
Customer Services. All returns must be accompanied by a Warranty Claim Form, available from
your Customer Services representative. Products should be shipped back in the original packaging,
or correctly packaged to ensure no damage occurs in transit.
1. Motorola's Accessories and Aftermarket Division (AAD) offers a repair service to both end
users and dealers at competitive prices.
2. AAD supplies individual parts and modules that can be purchased by dealers who are techni-
cally capable of performing fault analysis and repair.
Introduction 1-1
GM950E/GM950i Technical SpeciÞcation
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Singapore 569059
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Tel: 65-4815560
Fax: 65-4846123
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4.4 Technical Support
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Motorola Product Services is available to assist the dealer/distributors in resolving any malfunctions
which may be encountered. Initial contact should be by telephone whenever possible. When
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contacting Motorola Technical Support, be prepared with the product model number and the unitÕs
serial number.
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5.0 GM950E/GM950i Technical SpeciÞcation
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5.1 General
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Weight 1030g
Environmental
- Mechanical Vibration IEC 68/2/27 and Shock IEC 28/2/6
European Dust & Water protection IP54
1-2 Introduction
GM950E/GM950i Technical SpeciÞcation
5.2 Transmitter
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Conducted/Radiated Emission <0.25uW (0.1...1000MHz); <1uW (1...4GHz)
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Adjacent Channel Power <-60dB (12.5kHz); <-70dB (25kHz)
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Audio Distortion <5% @ 1kHz, 60% deviation
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Transmit turn on time <25msec
5.3 Receiver io
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SPECIFICATION ITEM TYPICAL VALUE
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Introduction 1-3
GM950E/GM950i Technical SpeciÞcation
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1-4 Introduction
Table of Contents
Chapter 2
Model Chart and Accessories
Table of Contents
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Paragraph Page
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1.0 Overview..................................................................................................... 1
8.
2.0 Model Chart ................................................................................................ 1
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3.0 Accessories................................................................................................ 2
3.1
3.2 io
Mechanical Hardware Kits: ..........................................................................
Microphones: ...............................................................................................
2
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3.3 Speakers:..................................................................................................... 2
3.4 Cables:......................................................................................................... 2
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3.5 Other:........................................................................................................... 2
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1.0 Overview
2
This chapter lists the models and accessories available for the GM950E/GM950i mobile radio.
GM950E/GM950i
136-174 MHz VHF
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403-470 MHz UHF
Description
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X = Indicates one of each required
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AZM08RHE4AA2AA
AZM08RHE6AA2AA
AZM08RDE4AA2AA
AZM08RHF4AA3AA
AZM08RHF6AA3AA
AZM08RFF4AA3AA
AZM08JHE4AA2AA
AZM08JHE6AA2AA
AZM08JDE4AA2AA
AZM08JHF4AA3AA
AZM08JHF6AA3AA
AZM08JFF4AA3AA
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Model
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Item Description
X X X X X X X X X X X X PMBN4039_ Packaging Kit
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3.0 Accessories
3.2 Microphones:
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GMN6146 Enhanced Compact Microphone (Standard)
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GMN6148 DTMF Microphone
HMN3141 Handset, low cost with Hang-up cup
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HMN3000 Desk Microphone
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3.3 Speakers:
All speaker connecting cables have 16-pin accessory connector plug.
GSN6059 13W External Speaker, square
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3.4 Cables:
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3.5 Other:
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Chapter 3
Maintenance
Table of Contents
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1.0 Overview..................................................................................................... 1
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2.0 Disassemble the Radio ............................................................................. 1
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2.1 Remove the Control Head ........................................................................... 1
2.2 Remove the Top Cover................................................................................ 1
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Remove the Transceiver Board ................................................................... 2
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2.4 Disassemble the Control Head .................................................................... 2
Maintenance 3-i
Table of Contents
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3-ii Maintenance
Overview
1.0 Overview
3
This chapter explains, step by step, how to disassemble and assemble the radio, to transceiver
board level. The chapter also contains a list of test equipment required to service the radio. The
procedure for radio alignment and the test setup is also available in this chapter.
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Recess
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1. Insert a small ßat blade screw driver, or similar, in the recess between the control head and the
transceiver (to minimise cosmetic damage to the radio cover start from the bottom side).
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2. Press until the side of the control head releases and then repeat the operation on the opposite
side of the radio.
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Maintenance 3-1
Disassemble the Radio
1. Insert a small ßat blade screw driver in the side recess of the radio chassis.
2. Lift the top cover over the chassis.
Protruding Tabs
Flex
Clip
Flex
Recess
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Clip
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Recess
ChassisRecess Printed Circuit Board
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Top Cover
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Chassis Transceiver Board Top Cover
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1. Remove the power and antenna connector retaining clips by inserting a small ßat blade screw
driver between the clip and the top of the chassis wall and gently prying the clip upwards.
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Slowly lift the board on the front edge, the side with the connector that mates with the control
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CAUTION: The thermal grease can act as an adhesive and cause the leads of the
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heat dissipating devises to be over stressed if the board is lifted too quickly.
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3-2 Maintenance
Assemble Radio
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Protuding Tabs
Recess
Keypad
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Recess
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Speaker
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Printed Circuit Board
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Figure 3-4 Control Head Assembly.
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1. Place the keypad onto the board assembly, making sure the keypad is ßush with the board.
2. Make sure the speaker including the gasket is well positioned.
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recesses.
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1. Inspect and if necessary, reapply thermal grease to the heatsinking pads in the chassis.
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2. Before installing the connector retaining clips, ensure that the board is sitting ßush on the
chassis mounting surface.
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3. Install the 13 screws with 0.4 -07 NM (4-6 in lbs) of torque using a T8 TORX driver.
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Maintenance 3-3
Exploded View Diagrams and Parts
Recess
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Figure 3-5 Control Head Replacement.
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4.0 Exploded View Diagrams and Parts
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Cover Chassis 1502609Y01
incl. Gasket Chassis
3202619Y01
Shield
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2602640Y01
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Screw M3x10
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03S10911A12
Controlhead with
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Clip 4205938V01
Pad
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7502618Y01
Gasket Connector 1580922V01
Controlhead
3202620Y01 Gasket Accessory Conn.
Antenna Conn. 3202606Y01
0905901V06
incl. Gasket
3205929V01 Chassis
2702608Y01
Gasket Cover
3202607Y01
3-4 Maintenance
Exploded View Diagrams and Parts
Housing
1502611Y02
Keypad
7502614Y02
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Gasket 3505932V01
Speaker 5005156Z02 Printed Circuit Board
8480573Z01
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Figure 3-7 Control Head Model A2.
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Housing incl.
LCD Gasket
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1502612Y03
Connector Elastromeric
2802638Y04 top
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2802638Y03 bottom
LCD 8480479Z01
7202662Y01
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5005156Z02 0702643Y01
and
Gasket
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Keypad
3205932V01 7502615Y02
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GEPD5493
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Maintenance 3-5
Service Aids
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GPN6133 Power Supply Used to supply power to the radio.
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GKN6266 DC Power Cable for radio Interconnects radio to power supply.
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switching for radio testing.
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RLN4008 Radio Interface Box Enables communications between the radio and the com-
puterÕs serial communications adapter.
EPN4040 Power Supply Used to supply power to the RIB (240 VAC).
3-6 Maintenance
Test Equipment
MODEL
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DESCRIPTION CHARACTERISTICS APPLICATION
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No.
R2000 System Analyser This monitor will substi- Frequency/deviation meter and sig-
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Series tute for items with an nal generator for wide-range trouble-
asterisk (*) shooting and alignment.
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*R1150C Code Synthesizer Injection of audio and digital signal-
ling codes
*S1053D
*HM-203-7
220 VAC Voltmeter
*S1350C Watt Meter 50 ohm, ±5% accuracy Transmitter power o/p measurements
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S1347D or DC Power Supply 0-20Vdc, 0-5 Amps Bench supply for 13.2Vdc current
S1348D (pro- limited
grammable)
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* Any of the R2000 Series system analysers will substitute for items with an asterisk (*)
Maintenance 3-7
Radio Tuning Procedure
7.1 General
The recommended hardware platform is a 386 or 486 DX 33 PC (personal computer) with 8 MBytes
RAM, MS DOS 5.0, Windows 3.1, and RSS (Radio Service Software). These are required to align
the radio. Refer to your RSS Installation Manual for installation and setup procedures for the
required software; the user manual is accessed (and can be printed if required) via the RSS.
To perform the alignment procedures, the radio must be connected to the PC, RIB (Radio Interface
Box), and Universal Test Set as shown in Þgure 3-9.
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Before going into the Service menu, the radio must Þrst be read using the File / Read Radio menu (if
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the radio has just been programmed with data loaded from disk or from a newly created codeplug,
then it must still be read so that the RSS will have the radioÕs actual tuning values).
All Service windows read and program the radio codeplug directly; you do NOT have to use the RSS
Read Radio / Write Radio functions to program new tuning values.
CAUTION: DO NOT switch radios in the middle of any Service procedure. Always use the
Program or Cancel key to close the tuning window before disconnecting the radio.
Improper exits from the Service window may leave the radio in an improperly
conÞgured state and result in seriously degraded radio or system performance.
3-8 Maintenance
Radio Tuning Procedure
The Service windows introduce the concept of the ÒSoftpotÓ, an analog SOFTware controlled
POTentiometer used for adjusting all transceiver alignment controls. A softpot can be selected by
clicking with the mouse at the value or the slider or by hitting the TAB key until the value or the slider
is highlighted.
Each Service window provides the capability to increase or decrease the ÔsoftpotÕ value with the
mouse, the arrow keys or by entering a value with the keyboard. The window displays the minimum,
maximum, and step value of the softpot. In addition transmitter tuning windows indicate the
transmitter frequency and whether the radio is keyed.
Adjusting the softpot value sends information to the radio to increase (or decrease) a DC voltage in
the corresponding circuit. For example, increasing the value in the Reference Oscillator tune window
instructs the radio microprocessor to increases the voltage across a varactor in the reference
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oscillator to increase the frequency. Pressing the Program button stores all the softpot values of the
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current window permanently in the radio.
8.
In ALL cases, the softpot value is just a relative number corresponding to a D/A (Digital-to-Analog)
generated voltage in the radio. All standard measurement procedures and test equipment are
similar to previous radios.
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Refer to the RSS on-line help for information on the tuning software.
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Perform the following procedures in the sequence indicated.
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Note: All tuning procedures must be performed at a supply voltage of 13.2V unless otherwise
stated. The Modulation Analyser to measure the deviation should be set to frequency
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modulation with de-emphasis switched off and all high pass Þlters switched off.
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Adjustment of the PA Bias is critical for proper radio operation. Improper adjustment will result in
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poor operation and may damage the PA FET device. For this reason, the PA bias must be set before
the transmitter is keyed the Þrst time.
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2. Select Bias Voltage to open the bias voltage tuning window. If the control voltage is out of
range, an error message will be displayed. In this case the radio hardware has a problem and
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RF-Band Target
UHF 440mA±10%
VHF 150mA±15%
Maintenance 3-9
Radio Tuning Procedure
The radio uses 2 battery threshold levels Tx High and Tx Low to determine the battery condition.
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7.4 Transmitter Power
8.
IMPORTANT: To set the transmitter power for customer applications use the Per Radio
window under the Edit menu and set the ÒLevel 1Ó and ÒLevel 2Ó powers to
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the desired values. Only if the transmitter components have been
changed should the following procedure be performed.
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The advanced power setting technology employed in the GM950E/GM950i makes use of two
reference power level settings along with parameters describing the circuit behaviour. To set the
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reference points requires tuning on two power level settings, a high power level setting, and a low
power level setting.
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4. Press Toggle PTT to key the radio. The status bar will indicate that the radio is transmitting.
5. Measure the transmitter power on your power meter.
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11. Repeat steps 3 - 10 for all test frequencies shown in the window.
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3-10 Maintenance
Radio Tuning Procedure
Adjustment of the reference oscillator is critical for proper radio operation. Improper adjustment will
not only result in poor operation, but also a misaligned radio that will interfere with other users
operating on adjacent channels. For this reason, the reference oscillator should be checked every
time the radio is serviced. The frequency counter used for this procedure must have a stability of 0.1
ppm (or better).
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5. Adjust the reference oscillator softpot on the RSS screen to achieve a frequency as measured
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on the frequency counter to be within the limits shown in table 3-4 of the target frequency
displayed on the RSS window.
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6. Press Toggle PTT again to dekey the radio and then press Program to store the softpot value.
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Table 3-4 Reference Oscillator Alignment.
RF-Band Target
UHF
VHF io±150 Hz
±150 Hz
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Alignment of the front-end pre-selector is normally not required on these radios. Only if the radio has
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poor receiver sensitivity or the pre-selector parts have been replaced the following procedure should
be performed. The softpot value sets the control voltage of the pre-selector. Its value needs to be set
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1. Set the test box (GTF180B) meter selection switch to the ÒAudio PAÓ position and connect a
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3. Select Front End Filter to open the pre-selector tuning window. The window will indicate the
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in Table 3-5.
5. Set the RF test generator to the receive test frequency, and set the RF level to 10µV modulated
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with a 1kHz tone at the normal test deviation shown in table 3-6.
6. Measure the RSSI voltage at accessory connector pin 15 with a dc voltmeter capable of 1 mV
resolution. The RSSI output is available on A2, 4 channel, radios but it is unbuffered. Therefore
a high impedance (1 MW) voltmeter must be used.
7. Decrease/increase the softpot value and note the RSSI voltage. The target softpot value is
achieved when the voltage change between 2 softpot steps is lower than 0.75% of the RSSI
voltage for the Þrst time. Set test box (GTF180B) audio switch to the ÒSPKRÓ position. The 1kHz
tone must be audible at the target value to make sure the radio is receiving.
8. Repeat steps 4 - 7 for all test frequencies shown in the window.
9. Press Program to store the softpot values.
Maintenance 3-11
Radio Tuning Procedure
UHF Maximum
VHF Minimum
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20 kHz 2.4 kHz
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25 kHz 3 kHz
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7.7 Rated Volume
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The rated volume softpot sets the volume at normal test modulation.
1. Set test box (GTF180B) meter selection switch to the ÒAUDIO PAÓ position and the speaker
4. Set the RF test generator to the receive test frequency, and set the RF level to 1mVolt
modulated with a 1kHz tone at the normal test deviation shown in table 3-6. Set test box
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(GTF180B) audio switch to the ÒSPKRÓ position. The 1kHz tone must be audible to make sure
the radio is receiving.
5. Adjust the value of the softpot to obtain rated audio volume (as close to 3.74 Vrms)
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Note: The voltage at the meter port of the testbox GTF180B is only half the voltage at the
speaker.
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7.8 Squelch
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The squelch softpots set the signal to noise ratio at which the squelch opens. The squelch value
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needs to be set at 7 frequencies across the frequency range. For 20/25kHz radios, the radio stores
separate tuning data for 20kHz and 25kHz channel spacing. Therefore, both sets of tuning data
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1. Set the test box (GTF180B) meter selection switch to the ÒAudio PAÓ position and connect a
SINAD meter to the ÒMETERÓ port.
2. From the Service menu, select Rx Alignment.
3. Select ÔSquelchÕ to open the squelch tuning window. This window is used to set the values for
12.5kHz radios and the 25kHz data for 20/25kHz radios. The window will indicate the receive
test frequencies to be used.
4. Select the Þrst test frequency shown, and set the corresponding value to 0.
5. Set the RF test generator to the test frequency and modulate the signal generator at the normal
test deviation shown in table 3-6, with 1kHz tone. Adjust the generator for a 8-10 dB SINAD
level (weighted with psophometric Þlter).
3-12 Maintenance
Radio Tuning Procedure
The transmit deviation limit softpot sets the maximum deviation of the carrier. Unlike other radios,
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the deviation limit for GM950E/GM950i is set using low frequency (PL) rather than the usual 1kHz
tone. The deviation value needs to be set at 7 frequencies across the frequency range. No audio
signals need to be injected, as the radio generates a 82.5Hz tone while the deviation limit alignment
8.
window is open. This tone is used to set the maximum deviation. For 20/25kHz radios, the radio
stores separate tuning data for 20kHz and 25kHz channel spacing. Therefore, both sets of tuning
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data should be set independently.
values for 12.5kHz radios and the 25kHz data for 20/25kHz radios. The window will indicate the
transmit test frequencies to be used.
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Maintenance 3-13
Radio Tuning Procedure
Compensation alignment balances the modulation sensitivity of the VCO and reference modulation
(synthesizer low frequency port) lines. Compensation algorithm is critical to the operation of
signalling schemes that have very low frequency components (e.g. PL) and could result in distorted
waveforms if improperly adjusted. The compensation value needs to be set at 7 frequencies across
the frequency range. For 20/25kHz radios, the radio stores separate tuning data for 20kHz and
25kHz channel spacing. Therefore, both sets of tuning data should be set independently.
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3. Set the Test Box (GTF180B) meter selector switch to the ÒGENÓ position, and inject a 2kHz (two
kilohertz) tone at 800 mVrms (eight-hundred millivolts) into the ÒAudio InÓ port.
4. Connect an AC meter to the meter port to insure the proper input signal level.
8.
5. Select the Þrst test frequency shown in the window.
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6. Press Toggle PTT to key the radio. The status bar will indicate that the radio is transmitting.
7. Measure the transmitter deviation.
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Adjust the transmitter deviation using the appropriate softpot to the value shown in Table 3-8.
Press Toggle PTT to dekey the radio.
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10. Repeat steps 5- 9 for the remaining test frequencies.
11. Press Program to store the softpot values.
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12. If the radio is a 20/25kHz channel spacing model, repeat steps 1 - 11 for 20kHz channel
spacing using the ÔModulation Balance (20kHz)Õ window.
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The transmit control voltage limit softpot sets the maximum power control voltage. All 7 voltage limit
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softpots are tuned and programmed automatically when the Program button is pressed.
1. From the Service menu, select Tx Alignment.
2. Select Control Voltage Limit to open the control voltage limit tuning window.
3. Set the Power Factor to 1.3.
4. Press Program to store the softpot values.
3-14 Maintenance
Table of Contents
Chapter 4
Theory of Operation
Table of Contents
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1.0 Overview..................................................................................................... 1
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2.0 Controller.................................................................................................... 2
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2.1 General ........................................................................................................ 2
2.2 Voltage Regulators ...................................................................................... 2
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Electronic On/Off ......................................................................................... 3
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2.4 Mechanical On/Off ....................................................................................... 3
2.5 Ignition ......................................................................................................... 3
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7.0 Receive Signalling Circuits..................................................................... 15
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7.1 Sub-audible Data Decoder (PL/DPL) ........................................................ 15
8.
7.2 High Speed Data Decoder......................................................................... 15
7.3 Alert Tone Circuits ..................................................................................... 16
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8.0 Receiver Front-End.................................................................................. 17
8.1
8.2
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Front-End Band-Pass Filter & Pre-Amplifier .............................................. 17
Mixer and Intermediate Frequency (IF) Section ........................................ 17
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8.3 IF IC (U5201) ............................................................................................. 18
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13.1 Reference Oscillator ................................................................................. 28
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13.2 Fractional-N Synthesizer (U3701)............................................................. 28
8.
13.3 Voltage Controlled Oscillator (VCO) ......................................................... 29
13.4 Synthesizer Operation .............................................................................. 29
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1.0 Overview
4
This section provides a detailed theory of operation for the radio and its components.
The main radio is designed to accept one additional option board. This may provide functions such
as secure voice/or a signalling decoder.
The control head is mounted directly on the front of the radio. The control head contains a speaker,
LED indicators, a microphone connector, buttons and dependant of radio type, a display. These
provide the user with interface control over the various features of the radio.
In addition to the power cable and antenna cable, an accessory cable can be attached to a
connector on the rear of the radio. The accessory cable provides the necessary connections for
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items such as external speaker, foot operated PTT, ignition sensing, etc.
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2.0 Controller
2.1 General
■ Digital Control
■ Audio Processing
■ Power Control
■ Voltage Regulation
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The digital control section of the radio board is based upon a closed architecture controller
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conÞguration.
The digital section consists of a microprocessor, support memory, support logic, signal MUX ICs, the
8.
On/Off circuit, and general purpose Input/Output circuitry.
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The closed architecture controller uses the Motorola 68HC11E9 (U0101) for a GM950E radio and
the 68HC11E20 for a GM950i radio. In this conÞguration RAM and ROM are contained within the
microprocessor itself. The only external memory device in the closed architecture controller is an
EEPROM (2KByte for GM950i).
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Note: From this point on the 68HC11E9 or E20 microprocessor will be referred to as E9/20mP or
mP. References to a Control Head will be to radio model A3 (Display radio).
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Voltage regulation for the controller is provided by 3 separate devices; U0631 (LP2951CM) +5V,
U0601 (LM2941T) +9.3V, and UNSW 5V (a combination of R0621 and VR0621). An additional
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Voltage regulation providing 5V for the digital circuitry is done by U0631. Input and output capacitors
(C0631/0632 and C0633-0635) are used to reduce high frequency noise and provide proper
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operation during battery transients. This regulator provides a reset output (pin 5) that goes to 0 volts
if the regulator output goes out of regulation. This is used to reset the controller to prevent improper
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operation. Diode D0631 prevents discharge of C0632 by negative spikes on the 9V3 voltage
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Regulator U0601 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors (C0601-0603 and C0604/0605) are used to
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reduce high frequency noise. R0602/R0603 sets the output voltage of the regulator. If the voltage at
pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 volts
the regulator output increases. This regulator output is electronically disabled by a 0 volt signal on
pin 2. Q0601 and associated circuitry (R0601/0604/0605 and C0606) are used to disable the
regulator when the radio is turned off.
UNSW 5V is only used in a few areas which draw low current and requires 5 V while the radio is off.
UNSW 5V CL is used to buffer the internal RAM. C0622 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Diode D0621 prevents radio
circuitry from discharging this capacitor.
The voltage 9V3 SUPP is only used in the VHF radio to supply the drain current for the RF MOS
FET in the PA.
The voltage SW B+ is monitored by the mP through the voltage divider R0641/R0642. Diode VR0641
limits the divided voltage to 5.1V to protect the mP.
Diode D5601 (UHF) / D3601 (VHF) located on the PA section acts as protection against transients
and wrong polarity of the supply voltage.
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off
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without direct user action. For example, automatic turn on when ignition is sensed and off when
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ignition is off.
8.
Q0611 is used to provide SW B+ to the various radio circuits. Q0611 acts as an electronic on/off
switch controlled by Q0612. The switch is on when the collector of Q0612 is low. When the radio is
off Q0612 is cutoff and the voltage at Q0611-base is at A+. This effectively prevents current ßow
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through Q0611 from emitter to collector. When the radio is turned on the voltage at the base of
Q0612 is high (about 0.6V) and Q0612 switches on (saturation) and pulls down the voltage at
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Q0611-base. With Transistor Q0611 now enabled current ßows through the device. This path has a
very low impedance (less than 1 ohm) from emitter to collector. This effectively provides the same
voltage level at SWB+ as at A+.
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The electronic on/off circuitry can be enabled by the microprocessor (through AFIC port GCB1, line
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B+ CONTROL), the mechanical On/Off button on the control head (line ON OFF CONTROL), or the
ignition sense circuitry (line IGNITION CONTROL). If any of the 3 paths cause a low at the collector
of Q0612, the electronic ON is engaged.
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This refers to the on/off button, located on the control head, and which turns the radio on and off. If
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the radio is turned off and the on/off button is pressed, line ON OFF CONTROL goes high and
switches the radio on as long as the button is pressed. The microprocessor is alerted through line
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ANALOG 3 which is pulled to low by Q0925 (Control Head Model A3) while the on/off button is
pressed. If the software detects a low state it asserts B+ CONTROL via AFIC pin 39 low which
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keeps Q0612 and Q0611, and in turn the radio switched on.
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If the on/off button is pressed and held while the radio is on, the software detects the line ANALOG
3 changing to low and switches the radio off by setting B+ CONTROL to low.
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2.5 Ignition
Ignition sense is used to prevent the radio from draining the vehicleÕs battery because the engine is
not running.
When the IGNITION input (J0400- 10) goes above 6 volts Q0421 and Q0612 turn on. This turns on
SW B+ by turning on Q0611 via line IGNITION CONTROL and Q0612 and the microprocessor
starts execution. The software reads the line IGNITION SENSE, determines from the level that the
IGNITION input is active and sets the B+ CONTROL output of the AFIC pin 39 to high to latch on
SW B+.
When the IGNITION input goes below 6 volts, Q0421 switches off and R0426, R0427 pull line
IGNITION SENSE high. The software is alerted by line IGNITION SENSE to switch off the radio by
setting B+ CONTROL to low. The next time the IGNITION input goes above 6 volts the above
process will be repeated.
2.6 Hook
The HOOK input is used to inform the mP when the Microphone«s hang-up switch is engaged.
The signal is routed from J0101-3 and transistor Q0137 to the E9/20mP U0101-56. The voltage
range of HOOK in normal operating mode is 0-5V. If a rear GP input line is set as HOOK then the
front HOOK signal is overriden.
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2.7 Microprocessor Clock Synthesizer
The controller uses the oscillator in the microprocessor E9/20µP along with some external
8.
components (C0115-C0117, L0114, R0115, Y0114) to generate the clock. Q0114 is used to alter
the clock frequency slightly under software control if there is a possibility of harmonics of this clock
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source interfering with the desired radio receive frequency.
(E9/20µP:U0101-53) and chip select lines going to the various ICÕs, connected on the SPI PORT
(BUS). This BUS is a synchronous bus, in that the timing clock signal CLK is sent while SPI data
(SPI TRANSMIT DATA or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on
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either SPI TRANSMIT DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The
SPI TRANSMIT DATA is used to send serial from a µP to a device, and SPI RECEIVE DATA is used
to send data from a device to a µP. The only device from which data can be received via SPI
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On the controller there are three ICs on the SPI BUS, AFIC (U103-33), EEPROM (U0108-1) and
D/A (U0731-6). In the RF sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The
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SPI TRANSMIT DATA and CLK lines going to the RF section are Þltered by L0194/L0195 to
minimize noise. The chip select lines for the IC«s are decoded by the address decoder U102.
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The SPI BUS is also used for the control head. U0104-1,2 buffer the SPI TRANSMIT DATA and CLK
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lines to the control head. U0104-3 switches off the CLK signal for the LCD display if it is not selected
via LCD CE.
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When the µP needs to program any of these ICÕs it brings the chip select line for that IC to a logic 0
and then sends the proper data and clock signals. The amount of data sent to the various ICÕs are
different, for example the FRAC-N can receive up to 13 bytes (97 bits) while the DAC can receive up
to 3 bytes (24 bits). After the data has been sent the chip select line is returned to a logic 1.
The Option board interfaces are different in that the µP can also read data back from devices
connected.
The timing and operation of this interface is speciÞc to the option connected, but generally follows
the pattern:
The SBEP serial interface allows the radio to communicate with the Radio Service Software (RSS).
This interface connects to the Microphone connector (J0903/J0803) via Control Head connector
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(J0101) and comprises BUS+ (J0101-15). The line is bi-directional, meaning that either the radio or
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the RSS can drive the line.
8.
When the RSS needs to communicate with the radio, an interrupt is generated by the BUS+ signal
through R0104. The µP then starts serial data communication on BUS+ by sending data from pin 50
through D0101 and receiving data at pin 47 through R0104. While the radio is sending serial data at
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pin 50 it receives an ÓechoÓ of the same data at pin 47.
GP3,5,6 are bidirectional. The software and the hardware conÞguration of the radio model deÞne the
function of each port. Some ports are not connected on GM950E radio, refer to appendix B.
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GP1 can be used as external PTT input or others, set by the RSS.
GP2 can be used as normal output (Q0441 placed) or external alarm output (Q0442 placed). The
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GP4 can be used as normal input (D0471, R0477 not placed) or emergency input (D0471, R0477
placed).
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GP3,5,6 are bidirectional and use the same circuit conÞguration. Each port uses an output transistor
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controlled by µP port PB5,4,7 and an input transistor read by µP port PC2,5,3. To use one of the
GP«s as input the µP must turn off the corresponding output transistor.
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In addition the signals from GP3-6 are fed to the option board connectors J0102, J0103.
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The 470pF and 10nF capacitors serve to Þlter out any AC noise which may ride on the GP lines.
The E9/20µP (U0101) contains internal 12 (E9) or 20 (E20) Kilobytes ROM, 512 (E9) or 768 (E20)
bytes SRAM and 512 bytes EEPROM.
The E9/20µP RAM is always powered to maintain parameters such as the last operating mode. This
is achieved by maintaining 5V at U0101-25. Under normal conditions, when the radio is off UNSW
+5V is formed by FLT A+ running to D0621.
C0622 allows the battery voltage to be disconnected for a couple of seconds without losing RAM
parameters. Diode D0621 prevents radio circuitry from discharging this capacitor.
U0101-22 is the high reference voltage for the A/D ports on the E9/20µP. Resistor R0105 and
capacitor C0105 Þlter the +5V reference. If this voltage is lower than +5V the A/D readings will be
incorrect. Likewise U0101-21 is the low reference for the A/D ports. This line is normally tied to
ground. If this line is not connected to ground, the A/D readings will be incorrect.
The MODB (U0101-25) input of the E9/20µP must be at a logic 1 for it to start executing correctly.
The XIRQ (U0101-45) and the IRQ (U0101-46) pins should also be at a logic 1.
Optional external EEPROM (U0108) is available on some radio models. The external EEPROM is
accessed through a serial connection. The E9/20µP generates SPI CLK (U0101-53), SPI
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TRANSMIT DATA (MOSI) (U0101-52) and SPI RECEIVE DATA (MISO) (U0101-51) to read or write
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EEPROM. On a read of EEPROM the E9/20µP continues generating the clock and the EEPROM
places the requested data on the SPI RECEIVE DATA (MISO) line. On a write the message is
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followed by the data to be written to the EEPROM.
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2.12 Control Head Model A2 or A3
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Two Control Head versions (A2 or A3) are available for user interface. Both Control Heads contain
the internal speaker, the microphone connector, several buttons to operate the radio and several
indicator LEDs to inform the user about the radio status. Additionally the Control Head model A3
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uses a 3 digit, 7 segment, LCD display for the channel number.
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The On/Off button when pressed switches the voltage regulators on by pulling ON OFF CONTROL
to high and connects the base of Q0925(A3), Q0825(A2) to FLT A+. This transistor pulls the line
ANALOG 3 to low to inform the µP that the On/Off button is pressed. If the radio is switched off, the
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µP will switch it on and vice versa. All other buttons work the same way. If a button is pressed, it will
connect one of the 3 lines ANALOG 1,2,3 to a resistive voltage divider connected to +5V. The
voltages of the lines are A/D converted inside the µP and specify the pressed button.
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All the back light and indicator LEDs are driven by current sources and controlled by the µP via
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SERIAL PERIPHERAL INTERFACE (SPI) interface. The LED status is stored in shiftregister
U0941(A3), U0841(A2). Line LED CE enables the serial write process via Q0941(A3), Q0841(A2)
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while line LED CLCK BUF shifts the data of line SPI DATA BUF into the shiftregister.
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In addition Control Head Model A3 contains the LCD display H0931. The display data of line SPI
DATA BUF is shifted into the display driver by clock signal LCD CLCK BUF.
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3.0 General
The AFIC (U0103) used in the controller performs RX/TX audio shaping, i.e. Þltering, ampliÞcation,
attenuation.
The AFIC is programmable through the SPI BUS (U0103-30/31/33), normally receiving 6 bytes. This
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programming sets up various paths within the AFIC to route audio signals through the appropriate
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Þltering, gain and attenuator blocks. The AFIC also has 4 General Control Bits GCB1,3-5 which are
CMOS level outputs. GCB1 is used to switch the radio on and off under µP control via line B+
CONTROL. GCB3 is used to switch the audio PA on and off (AUDIO PA ENABLE). GCB4 selects
8.
between the UNATTEN RX OUT audio signal and the unÞltered DET AUDIO signal. GCB5 HIGH
LOW BAND can be used to switch between band splits.
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3.2 Audio Ground
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VAG is the dc bias used as an audio ground for the op-amps that are external to the Audio Filter IC
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(AFIC). U0105-1 forms this bias by dividing 9.3V with resistors R0171, R0172 and buffering the
4.65V result with a voltage follower. VAG emerges at pin 1 of U0105-1. C0172 is a bypass capacitor
for VAG. The AFIC generates its own 2.5 V bias for its internal circuitry. C0153 is the bypass for the
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AFICÕs audio ground dc bias. Note that while there are AFIC VAG, and BOARD VAG (U0105-1) each
of these are separate. They do not connect together.
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The radio supports 2 distinct microphone paths known as internal and external mic and an auxiliary
path (FLAT TX AUDIO). The microphones used for the radio require a DC biasing voltage provided
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by a resistive network.
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These two microphone audio inputs are connected together. Following the internal mic path; the
microphone is plugged into the radio control head and is connected to the controller board via
J0101-16. From here the signal is routed to C0142. R0141 and R0142 provide the 9.3VDC bias.
R0142 and C0141 provide a 1kW AC path to ground that sets the input impedance for the
microphone and determines the gain based on the emitter resistor in the microphoneÕs ampliÞer
circuit.
The MIC signal is routed to the AFIC«s TX IN input (U0103-10) through R0146 and R0145 (4
channel radio) or through op-amp buffer U0106-2 and option board connector J0103-3,1 (128
channel radio). The audio signal at the output of U0106-2 should be approximately 80mV deviation
with 25kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector U0400-5 is buffered by op-amp U0106-1 and
fed to the AFIC U0103-13 through gate U0107-1. Gate U0107-1 is controlled by the µP port PC7
(U0101-42) and selects between FLAT TX AUDIO or signalling signal created by the µP.
J0101
J0103-3 J0103-1
IN OUT
OPTION
BOARD
9
MIC
CONTROL HEAD 10
CONNECTOR
FILTERS AND
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PREEMPHASIS
J0400
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ASFIC LIMITER
U0201
2
EXT MIC
8.
5 13 TX IN SPLATTER
FLAT TX
FILTER
AUDIO
16
ACCESSORY
CONNECTOR
21 TX OUT
14
4-BIT
DEVIATION
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19
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ATTENUATOR TO
MOD IN RF
SECTION
(SYNTHESIZER)
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5-BIT 20
15
DEVIATION
ATTENUATOR
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GEPD 5427
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The external microphone signal enters the radio on accessory connector J0400 pin 2 and connects
to the standard microphone input through R0421.
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Mic PTT is sensed by the µP U0101 pin 22. An external PTT can be generated by grounding pin 3
on the accessory connector if this input is programmed for PTT.
The MIC signal is routed to the AFIC (U0103) through R0146 and R0145 (4 channel radio) or
through op-amp buffer U0106-2 and option board connector J0103-3,1 (128 channel radio). R0145,
C0145, the ampliÞer inside the AFIC (pins 9,10) and gain setting resistor R0147 pre-emphasise the
MIC audio signal. After further limiting and Þltering the modulation signal emerges from the AFIC at
U0103-19/20. Both signals are weighted by resistors R0181, R0182 and add up to signal MOD IN.
The audio coming from the microphone (J0101-16) or the external microphone (J0400-2) is routed
through op-amp buffer U0106-2 (128ch only) to the option board connector J0103-3. After option
board processing the signal emerges at J0103-1. The source resistor of the option board output and
C0145, the ampliÞer inside the AFIC (U0103-9,10) and gain setting resistor R0147 pre-emphasise
the signal. Inside the AFIC the signal follows a path identical to conventional transmit audio. The
modulation signal emerges from the AFIC at J0103-19/20. Both signals are weighted by resistors
R0181, R0182 and add up to signal MOD IN.
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8.
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1. Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signal-
ling,
2. DTMF data for telephone communication in trunked and conventional systems, and
3. Audible signalling including Select 5, MPT-1327, MDC, Single Tones.
All three types are supported by the hardware while the radio software determines which signalling
type is available. Currently only PL/DPL and Single tones are supported in the software.
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62
8.
54 13 AUX TX SPLATTER
IN FILTER
58
16
MICRO
39 GCB1
CONTROLLER
57
PL
GEPD_5432
32 CLOCK
STROBE
PL
ENCODER io LS
SUMMER
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TO RF
19, 20
ATTENUATOR SECTION
MOD IN (SYNTHESIZER)
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GEPD 5432
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Sub-audible data implies signalling whose frequency is below 300Hz. Although it is referred to as
Ósub-audible data,Ó the actual frequency spectrum of these waveforms may be as high as 250 Hz,
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which is audible to the human ear. However, the radio receiver Þlters out any audio below 300Hz, so
these tones are never heard in the actual system.
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Only one type of sub-audible data can be generated by U0103 (AFIC) at any one time. The process
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is as follows, using the SPI BUS, the µP programs the AFIC to set up the proper low-speed data
deviation and select the PL or DPL Þlters. The µP then generates a square wave which strobes the
AFIC PL / DPL encode input PL CLOCK STROBE U0103-32 at twelve times the desired data rate.
For example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0103 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass Þltered and summed with voice
or data. The resulting summed waveform then appears on U0103-19,20 (MOD IN), where it is sent
to the RF board as previously described for transmit audio.
The High Speed Data and DTMF waveforms are created by the µP U0101 using summer U0105-3.
Op-amp U0105-3 and resistors R0121-R0124 add up the three signals coming from the µP pins 58,
59 and 62. The output signal of U0105-3 is routed to the AFIC (U0103-13) through gate U0107-1.
Inside the AFIC the signal enters the conventional transmitter audio path at the splatter Þlter input.
Gate U0107-1 controlled by µP port PC7 (U0101-42) selects between data signal and FLAT TX
AUDIO signal. Microphone audio is muted during High Speed Data signalling.
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8.
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ACCESSORY
CONNECTOR
11
FLAT RX AUDIO
J0400
1
AUDIO 4 SPKR + 16
PA EXTERNAL
SPKR - 1
U0401 SPEAKER
9 6
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INT
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SPKR-
INT
SPKR+ CONTROL
HEAD
CONNECTOR
ATTEN.
8.
2
INTERNAL
1 SPEAKER
J0101
14 HANDSET
16
AUDIO
23
RX AUD OUT
UNAT
IN 2 J0103-4
22 RX OUT
OPTION VOLUME
BOARD
IN 1
OUT
J0103-2 7 RX IN
FILTER AND
PL IN DEEMPHASIS
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ATTEN.
AFIC
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8 U0103
J0103-5
6 AUX
RX IN
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IF IC TX
SQUELCH ATTENUATOR
U5201 DET AUDIO 21 OUT
(DISCRIMINATOR
AUDIO)
DET AUDIO 28
SQ IN SQ OUT
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23 16 18
SQ LIM OUT
20
SQ RECT IN
MICRO CONTROLLER
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15 U0101
CSQ DET
15
CSQ DET
18
FAST SQ
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GEPD 5429
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The IF IC controls the squelch characteristics of the radio. With a few external parts (R5222, C5229,
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C5230, R5223) the squelch tail, hysteresis, attack and delay are optimized for the radio. To set the
squelch threshold the signal from IF IC pin 23 (line SQ ATT IN) is routed to the squelch attenuator
input of the AFIC (U0103-16). The attenuated signal (line SQ ATT OUT) from the AFIC (U0103-18)
enters the IF IC at pin 20 and is used to create a squelch indicator signal available at pin 15 (line
CSQ DET).
The microprocessor controlled ADAPT signal at pin 22 activates the fast squelch indicator signal at
IF IC pin 18 (FAST SQ). Both squelch indicator signals CSQ DET (pin 15) and FAST SQ (pin 18) are
combined, weighted by resistors R0111 / R012 and fed to one of the microprocessor«s ADCs
(U0101-15) for interpretation. From the voltage weighted by the resistors the µP determines whether
CSQ DET, FAST SQ or both are active.
The receiver audio signal enters the controller section from the IF IC (U5201-28) on DET AUDIO.
The signal is AC coupled by C0181 and enters the AFIC via the RX IN pin U0103-7.
Inside the AFIC the signal entering RX IN (U0103-7) goes through the audio path while the signal
entering PL DPL IN (U0103-8) via C0182 goes through the PL/DPL path.
The audio path has a programmable ampliÞer, whose setting is based on the channel bandwidth
being received, then a LPF Þlter to remove any frequency components above 3000Hz and then an
HPF to remove any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis Þlter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
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is set depending on the value of the volume control. Finally, the Þltered audio signal passes through
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an output buffer within the AFIC. The audio signal exits the AFIC at RX AUDIO U0103-23.
8.
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/
maximum settings of the attenuator are set by codeplug parameters.
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Since sub-audible signalling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signalling enters the AFIC from the IF
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IC at PL DPL IN U0103-8. Once inside it goes through the PL/DPL path. The signal Þrst passes
through one of 2 low pass Þlters, either PL low pass Þlter or DPL/LST low pass Þlter. Either signal is
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then Þltered and goes through a limiter and exits the AFIC at PL DPL DECODER OUT U0103-27. At
this point the signal will appear as a square wave version of the sub-audible signal which the radio
received. The microprocessor (U0101-64) will decode the signal directly to determine if it is the tone/
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The output of the AFIC«s digital volume pot, U0103-23 is routed through a voltage divider formed by
R0401 and R0402 to set the correct input level to the audio PA (U0401). This is necessary because
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the gain of the audio PA is 46 dB, and the AFIC output is capable of overdriving the PA unless the
maximum volume is limited.
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The audio then passes through C0401 which provides AC coupling and low frequency roll-off.
C0402 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the audio
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The audio power ampliÞer has one inverted and one non-inverted output that produces the
differential audio output SPK+ / SPK- (U0401-4/6). The inputs for each of these ampliÞers are pins 1
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and 9 respectively; these inputs are both tied to the received audio. The audio PAÕs DC biases are
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via AUDIO PA ENABLE signal from the AFIC (U0103-40). When the base
of Q0401 is low, the transistor is off and U0401-8 is high, using pull up resistor R0406, and the Audio
PA is ON. The voltage at U0401-8 must be above 8.5VDC to properly enable the device. If the
voltage is between 3.3 and 6.4V, the device will be active but has its input (U0401-1/9) off. R0404
ensures that the base of Q0401 is high on power up. Otherwise there may be an audio pop due to
R0406 pulling U0401-8 high before the software can switch on Q0401.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT
A+ (U0401-7). FLT A+ of 11V yields DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V. If
either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and
SPK- are routed to the accessory connector (J400-16 and 1) and to the control head (connector
J0101-1 and 2).
Certain hand held accessories have a speaker within them which require a different voltage level
than that provided by U0401. For those devices HANDSET AUDIO is available at J0101-14.
The received audio from the output of the AFIC«s digital volume attenuator is also routed to U0105-
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4 pin 9 where it is ampliÞed 15 dB; this is set by the 10k/68k combination of R0154 and R0155. This
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signal is routed from the output of the op amp U0105-4 pin 8 to J0101-14. The control head sends
this signal directly out to the microphone jack. The maximum value of this output is 6.6Vp-p.
8.
6.5 Filtered Audio
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The AFIC has an audio whose output at U0103-22 has been Þltered and de-emphasized, but has
not gone through the digital volume attenuator. From AFIC U0103-22 the signal is routed through
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gate U0107-2 and AC coupled to U0106-4. The gate controlled by AFIC port GCB4 (U0103-2)
selects between the Þltered audio signal from the AFIC or the unÞltered discriminator signal from the
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IF IC U5201.The output at U0106-4 is then routed to J0400-11. Note that any volume adjustment of
the signal on this path must be done by the accessory.
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Note that discriminator audio DET AUDIO from the IF IC U5201, in addition to being routed to the
AFIC, is also routed to the option connector J0103-5 (See Secure Rx description blocks for further
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information).
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Discriminator or Þltered audio, enters the option board at connector J0103-5 and J0103-4. On the
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option board, the signal may be processed and then fed back through (J0103-2) to AUX RX IN of the
AFIC (U0103-6). From then on it follows a path identical to conventional receive audio, where it is
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CENTER SLICER
U0105-2
22
1
UNATTEN
RX OUT
PL CLOCK 32 57
STROBE
t
AFIC MICRO
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U0103 CONTROLLER
U0101
PL
8 64
DPL
GEPD_5430 PL DPL 27
8.
DET AUDIO FILTER LIMITER
IN DECODER
DISCRIMINATOR AUDIO
OUT
FROM RF SECTION
(IF IC)
16
DPL TPL
25 24
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Figure 4-4 Receive Signalling Path.
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The receiver audio signal entering the AFIC U0103 at pin 8 Þrst passes through the Tone PL Þlter or
the Digital PL Þlter, depending on the PL option selected for the current operating mode. Filtered PL
is then coupled to the PL detector circuit, with detected PL output at U0103-27. At this point the
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signal will appear as a square wave version of the sub-audible signal which the radio received. The
microprocessor U0101-64 will decode the signal directly to determine if it is the tone / code which is
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The unattenuated receiver audio signal from U0103-22 is AC coupled to the input of centre slicer
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circuit U0105-2. The non-inverting input of op-amp U0105-2 is fed through resistor R0162. Capacitor
C0164 sets a low-pass corner frequency of 3.3kHz. The inverting input of op-amp U0105-2 is fed
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through resistor R0163. Capacitor C0163 sets a low-pass corner frequency of 16Hz.
During operation, R0163 / C0163 establish an average DC offset level at U0105-2 pin 6 dependent
on the average DC level of the undetected signal to set the ÒtriggerÓ threshold of U0105-2. R0162 /
C0164 provide high audio frequency roll-off to improve falsing immunity, but passes 600 or 1200
baud signals. The detected output from the centre slicer circuit is buffered and inverted by Q0161
and then coupled to the µP U0101-1 where algorithms perform the Þnal decoding.
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status , it sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0103 which sets up the audio path to the speaker for alert
tones. The alert tone itself is generated by the AFIC.
The allowable internal alert tones are 410, 820, and 1640Hz. In this case a code contained within
the SPI BUS load to the AFIC sets up the path and determines the tone frequency, and at what
volume level to generate the tone. (It does not have to be related to the voice volume setting).
Inside the AFIC, this signal is routed to the alert tone generator; the output of the generator is
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summed into the audio chain just after the RX audio de-emphasis block. Inside U0103 the tone is
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ampliÞed and Þltered, then passed through the 8-bit digital volume attenuator, which is typically
loaded with a special value for alert tone audio. The tone exits at U0103-23 and is routed to the
8.
audio PA like receive audio.
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Two crystal Þlters in the Þrst IF section and two ceramic Þlters in the second IF section provide the
required selectivity. The second IF at 455 kHz is mixed, ampliÞed and demodulated in the IF IC. The
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processing of the demodulated audio signal is performed by an audio processing IC located in the
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controller section.
8.
8.1 Front-End Band-Pass Filter & Pre-AmpliÞer
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A two pole pre-selector Þlter tuned by the varactor diodes D5301 and D5302 pre-selects the
incoming signal (PA RX) from the antenna switch to reduce spurious effects to following stages. The
tuning voltage (FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analog
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(D/A) converter (U0731-11) in the controller section. A dual hot carrier diode (D5303) limits any
inband signal to 0 dBm to prevent damage to the pre-ampliÞer.
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The RF pre-ampliÞer is an SMD device (Q5301) with collector base feedback to stabilize gain,
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impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the
voltage 9V3.
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A second two pole varactor tuned bandpass Þlter provides additional Þltering to the ampliÞed signal.
The varactor diodes D5304 and D5305 are controlled by the same signal which controls the pre-
selector Þlter. A following 3 dB pad (R5310, R5314, R5316) stabilizes the output impedance and
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intermodulation performance.
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If the UHF radio is conÞgured for a base station application, R5319 is not placed and TP5301 and
TP5302 are shorted.
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The signal coming from the front-end is converted to the Þrst IF (45.1 MHz) using a double balanced
schottky diode mixer (D5401). Its ports are matched for incoming UHF signal conversion to the
45.1MHz IF using low side injection. The injection signal (VCO MIXER) coming from the mixer buffer
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(Q5771) is Þltered by the lowpass consisting of (L5403, L5404, C5401 - C5403) and has a level of
approximately 10 dBm.
The mixer IF output signal (RX IF) from transformer T5401 pin 2 is fed to the Þrst two pole crystal
Þlter Y5201. The Þlter output in turn is matched to the following IF ampliÞer.
The IF ampliÞer Q5201 is actively biased by a collector base feedback (R5201, R5202) to a current
drain of approximately 5 mA drawn from the voltage 5V STAB. Its output impedance is matched to
the second two pole crystal Þlter Y5202. A dual hot carrier diode (D5201) limits the Þlter output
voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
8.3 IF IC (U5201)
The Þrst IF signal from the crystal Þlters feeds the IF IC (U5201) at pin 6. Within the IF IC the
45.1MHz Þrst IF signal mixes with the second local oscillator (LO) at 44.645MHz to the second IF at
455 kHz. The second LO uses the external crystal Y5211. The second IF signal is ampliÞed and
Þltered by two external ceramic Þlters (FL5201, FL5202). Back in the IF IC the signal is demodulated
in a phase-lock detector and fed from IF IC pin 28 to the audio processing circuit AFIC U0103
located in the controller section (line DET AUDIO).
The IF IC also controls the squelch characteristics of the radio. With a few external parts (R5222,
C5229, C5230, R5223) the squelch tail, hysteresis, attack and delay were optimized for the radio. To
set the squelch threshold the signal from IF IC pin 23 (line SQ ATT IN) is attenuated by a
microprocessor controlled audio processing IC AFIC (U0103) located in the controller section. The
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attenuated signal from the AFIC (line SQ ATT OUT) enters the IF IC at pin 20 and is used to create
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a squelch indicator signal available at pin 15 (CSQ DET).
8.
The microprocessor controlled ADAPT signal at pin 22 activates the fast squelch indicator signal at
IF IC pin 18 (FAST SQ). Both squelch indicator signals CSQ DET (pin 15) and FAST SQ (pin 18) are
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combined, weighted by R0111 / R0112 and fed to the microprocessor U0101 pin 15 for
interpretation. From the voltage weighted by the resistors the µP determines whether CSQ DET,
FAST SQ or both are active.
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At IF IC pin 11 an RSSI signal is available with a dynamic range of 70 dB. The RSSI signal is
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buffered by op-amp U0106-3 and available at accessory connector J0400-15.
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The radioÕs 5-25 W PA is a four stage ampliÞer used to amplify the output from the exciter to the
radio transmit level. It consists of four stages in the line-up. The Þrst (Q5510) is a bipolar stage that is
controlled via the PA control line. It is followed by another bipolar stage (Q5520), a MOS FET stage
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Devices Q5510 and Q5520 are surface mounted. MOS FET Q5530 and bipolar Transistor Q5536
are directly attached to the heat sink.
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The Þrst stage (Q5510) ampliÞes the RF signal from the VCO (line EXCITER PA) and controls the
output power of the PA. The output power of the transistor Q5510 is proportional to its collector
current which is adjusted by a voltage controlled current source consisting of Q5612 and Q5621.
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The whole stage operates off the K9V1 source which is 9.1V in transmit mode and nearly 0V in
receive mode.
The collector current of Q5510 causes a voltage drop across the resistors R5623 and R5624.
Transistor Q5612 adjusts the voltage drop across R5621 through PA control line (PWR CNTL). The
current source Q5621 adjusts the collector current of Q5510 by modifying its base voltage until the
voltage drop across R5623 and R5624 plus VBE (0.6V) equals the voltage drop across R5621 plus
VBE (0.6V) of Q5611. If the voltage of PWR CNTL is raised, the base voltage of Q5612 will also rise
causing more current to ßow to the collector of Q5612 and a higher voltage drop across R5621. This
in turn results in more current driven into the base of Q5510 by Q5621 so that the current of Q5510
is increased. The collector current settles when the voltage over the series conÞguration of R5623
and R5624 plus VBE of Q5621 equals the voltage over R5621 plus VBE (0.6V) of Q5611.
By controlling the output power of Q5510 and in turn the input power of the following stages the ALC
loop is able to regulate the output power of the transmitter.
9.2 PA Stages
The bipolar transistor Q5520 is driven by Q5510. To reduce the collector - emitter voltage and in turn
the power dissipation of Q5510 its collector current is drawn from the antenna switch circuit.
In transmit mode the base of Q5520 is slightly positive biased by a divided K9V1 signal to allow a
collector current to be drawn from the antenna switch circuit and in turn switches the antenna switch
to transmit while in receive mode the low K9V1 signal cuts off the collector current and in turn
switches the antenna switch to receive.
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The following stage uses an enhancement mode N-Channel MOS FET device (Q5530) and requires
a positive gate bias and a quiescent current ßow for proper operation. The voltage of the line BIAS
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VLTG is set in transmit mode by a Digital to Analog (D/A) converter (U0731-4) and fed to the gate of
Q5530 via a resistive divider. The bias voltage is tuned in the factory. If the transistor is replaced, the
bias voltage must be tuned with the Radio Service Software (RSS). Care must be taken, not to
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damage the device by exceeding the maximum allowed bias voltage. The collector current is drawn
from the supply voltage A+.
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The Þnal stage uses the bipolar device Q5536 and operates off the A+ supply voltage. For class C
operation the base is DC grounded by two series inductors (L5533, L5534). A matching network
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consisting of C5542-C5544 and two striplines transform the impedance to 50 Ohms and feed the
directional coupler.
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The directional coupler is a microstrip printed circuit which couples a small amount of the forward
power off the RF power from Q5536. The coupled signal is rectiÞed to an output power proportional
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negative DC voltage by the diode D5553 and sent to the power control circuit in the controller
section via the line PWR DETECT for output power control. The power control circuit holds this
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voltage constant, thus ensuring the forward power out of the radio to be held to a constant value.
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The antenna switch is switched synchronously with the K9V1 voltage and feeds either the antenna
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signal coming through the harmonic Þlter to the receiver or the transmitter signal coming from the PA
to the antenna via the harmonic Þlter.
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In transmit mode, this K9V1 voltage is high and biases Q5520 to allow a collector current to be
drawn. The collector current of Q5520 drawn from A+ ßows via L5542,L5541, directional coupler,
D5551, L5551, D5631, L5631, R5616, R5617 and L5611 and switches the PIN diodes D5551 and
D5631 to the low impedance state. D5551 leads the RF signal from the directional coupler to the
harmonic Þlter. The low impedance of D5631 is transformed to a high impedance at the input of the
harmonic Þlter by the resonant circuit formed by L5551,C5633 and the input capacitance of the
harmonic Þlter.
In receive mode the low K9V1 turns off the current through the PIN diodes and switches them to the
high impedance state. The antenna signal, coming through the harmonic Þlter, is channelled to the
receiver via L5551, C5634 and line PA RX.
A high impedance resonant circuit formed by D5551 in off state and L5554, C5559 prevents an
inßuence of the receive signal by the PA stages. The high impedance of D5631 in off state doesn«t
inßuence the receiver signal.
The transmitter signal from the antenna switch is channelled through the harmonic Þlter to the
antenna connector J5501.The harmonic Þlter is formed by inductors L5552, L5553, and capacitors
C5557,C5552 through C5555. This network forms a low-pass Þlter to attenuate harmonic energy of
the transmitter to speciÞcations level. R5550 is used for electro - static protection.
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9.6 Power Control
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The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
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MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
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using a Digital to Analog (D/A) converter (U0731). The microprocessor writes the data into the D/A
converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
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time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
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The microprocessor controls K9V1 ENABLE (U0101-6) to switch on the Þrst and the second PA
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stage via K9V1. The antenna switch is turned on by the collector current of the second PA stage. PA
DISABLE, also microprocessor controlled (U0101-54), sets BIAS VLTG (U0731-4) and VLTG LIMIT
SET (U0731-13) in receive mode to low to switch off the bias of the MOS FET device Q5530 and to
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Through an Analog to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA control
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The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward
power voltage PWR DETECT at a constant level.
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Opamp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT
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voltage from the PWR SET D/A output U0731 pin 2. The result is connected to opamp inverting
input U0701-4 pin 9. This voltage which is compared with a 4.6 volt reference VAG present at
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noninverting input U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line
PWR CNTL. The 4.6 volt reference VAG is set by a resistive divider circuit (R0171, R0172) which is
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During normal transmitter operation the voltages at the opamp inputs U0701-4 pins 9 and 10 should
be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7 volts. If
power falls below the desired setting, PWR DETECT increases, causing the output at U0701-2 pin 7
to decrease and the opamp output U0701-4 pin 8 to increase.
A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is
at the desired level. The power set D/A output voltage PWR SET (U0731-2) at U0701-2 pin 5 adjusts
power in steps by adjusting the required value of PWR DETECT. As PWR SET (U0731-2)
decreases, transmitter power must increase to make PWR DETECT larger and keep the inverting
input U0701-4 pin 9 at 4.6 volts.
Loop frequency response is controlled by opamp feedback components R0712 and C0711. Opamp
U0701-3 compares the power control voltage PWR CNTL divided by resistors R0717 to R0719 with
the voltage limit setting VLTG LIMIT SET from the D/A converter (U0731-13) and keeps the control
voltage constant via Q0711 if the control voltage, reduced by the resistive divider (R0717 to R0719),
approaches the voltage of VLTG LIMIT SET (U0731-13).
Rise and fall time of the output power during transmitter keying and dekeying is controlled by the
comparator formed by opamp U0701-3.
During normal transmitter operation the voltage at U701-3 pin 13 is higher than the voltage at pin 12
causing the output at pin 14 being low and switching off transistor Q0711. Diode D0732 reduces the
bias voltage BIAS VLTG for low control voltage levels.
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The temperature of the PA area is monitored by opamp U0701-1 using thermistor R5641 (located in
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the PA section). If the temperature increases, the resistance of R5641 decreases, decreasing the
voltage PA TEMP. The inverting ampliÞer formed by U0701-1 ampliÞes the PA TEMP voltage and if
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the voltage at opamp pin 1 approaches 4.6 V plus the voltage (ON) across D0721, U701-1 simulates
an increased power which in turn decreases the power control voltage until the voltage at U0701-4
pin 9 is 4.6V again. During normal transmitter operation the output voltage of opamp U701-1 pin 1 is
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below 4.6V. Diode D5601 located in the PA section acts as protection against transients and wrong
polarity of the supply voltage.
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10.0 Frequency Synthesis
The complete synthesizer subsystem consists of the Reference Oscillator (U7502), the Fractional-N
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synthesizer (U7501), the Voltage Controlled Oscillator (Q5741, Q5751), the RX and TX buffer stages
(Q5771, Q5781) and the feedback ampliÞer (Q5791).
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The Reference Oscillator (Y5702) contains a temperature compensated crystal oscillator with a
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frequency of 16.8 MHz. An analog to digital (A/D) converter internal to U5701 (FRAC-N) and
controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of
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U5701 pin 16 to set the frequency of the oscillator. The output of the oscillator (pin 2 of Y5702) is
applied to pin 14 (XTAL1) of U5701 via a RC series combination.
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In applications were less frequency stability is required the oscillator inside U5701 is used along with
an external crystal Y5701, the varactor diode D5702, C5708, C5710 and R5704.
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The FRAC-N synthesizer IC (U7501) consists of a pre-scaler, a programmable loop divider, control
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
modulation, a balance attenuator to balance the high frequency analog modulation and low
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
Þnally a super Þlter for the regulated 9.3 volts.
A voltage of 9.3V applied to the super Þlter input (U7501 pin 22) supplies an output voltage of 8.6
VDC at pin 18. It supplies the VCO (Q5741), VCO modulation bias circuit (via R5714) and the
synthesizer charge pump resistor network (R5723, R5724, R5726). The synthesizer supply voltage
is provided by the 5V regulator U5801.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U5701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
(D5701-1-3, C5716, C5717). This voltage multiplier is basically a diode capacitor network driven by
two (1.05MHz) 180 degrees out of phase signals (U5701-9 and -10).
Output LOCK (U5701-2) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U5701 divides the 16.8 MHz reference frequency down
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U5701-5),
clock line SPI CLK (U5701-6), and chip enable line FRACN CE (U5701-7).
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10.3 Voltage Controlled Oscillator (VCO)
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The Voltage Controlled Oscillator (VCO) is formed by the colpitts oscillator FET Q5741. Q5741
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draws a drain current of 12 mA from the FRAC-N IC super Þlter output. The oscillator frequency is
half of the desired frequency and mainly determined by L5743, C5742, C5743, C5745 - C5748 and
varactor diodes D5741 / D5742. Diode D5743 controls the amplitude of the oscillator.
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A balanced frequency doubler T5751, D5751 converts the oscillator fundamental to the desired UHF
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frequency. With a steering voltage from 2.5V to 10.5V at the varactor diodes the full RX and TX
frequency range from 357.9 MHz to 470 MHz is covered.
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After the doubler a 3-pole bandpass Þlter rejects unwanted harmonics at the Þrst and third oscillator
fundamental frequency and matches the output to the Common VCO Buffer Q5751. Q5751 draws a
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collector current of 13 mA from the stabilized 5V (U5801) and drives the Pre-scaler Buffer Q5791,
the PA Buffer Q5781 (Pout = 13dBm) and Mixer Buffer Q5771 (Pout = 10dBm). Q5791 draws a
collector current of 8 mA from the stabilized 5V and Q5771, Q5781 both draw 17mA form the 9V3
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source. The buffer stages Q5771, Q5781 and the feedback ampliÞer Q5791 provide the necessary
gain and isolation for the synthesizer loop.
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Q5731 is controlled by output AUX3 of U7501 (pin 1) and enables the RX or TX buffer. In RX mode
AUX3 is nearly at ground level, in TX mode about 5V DC. In TX mode with R5732 pulled to ground
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level by Q5731 the modulation signal coming from the FRAC-N synthesizer IC (U7501 pin28)
modulates the VCO via varactor diode D5731 while in RX mode the modulation circuit is disabled by
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The complete synthesizer subsystem works as follows. The output signal of the VCO (Q5741) is
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frequency doubled by doubler D5751 and, buffered by Common VCO Buffer Q5751. To close the
synthesizer loop, the collector of Q5791 is connected to the PREIN port of synthesizer U5701 (pin
20). The buffer output (Q5751) also provides signals for the Mixer Buffer Q5771 and the PA Buffer
(Q5781).
The pre-scaler in the synthesizer (U5701) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
of the loop divider is connected to the phase detector, which compares the loop divider«s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y5702).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 29 (I OUT of U5701). The loop Þlter (which consists of
R5715-R5717, C5723-C5725, C5727) transforms this current into a voltage that is applied to the
varactor diodes D5741, D5742 and alters the output frequency of the VCO. The current can be set to
a value Þxed in the FRAC-N IC or to a value determined by the currents ßowing into CPBIAS 1
(U5701-27) or CPBIAS 2 (U5701-26). The currents are set by the value of R5724 or R5726
respectively. The selection of the three different bias sources is done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT line (U5701-31) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the FRACN CE line. When the synthesizer is within the lock range the current is
determined only by the resistors connected to CPBIAS 1, CPBIAS 2, or the internal current source.
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A settled synthesizer loop is indicated by a high level of signal LOCK DET (U5701-2). This signal is
routed to uP U0101-17 for further processing.
8.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on
U5701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance
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attenuator (high freq path). The A/D converter converts the low frequency analog modulating signal
into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The
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balance attenuator is used to adjust the VCOÕs deviation sensitivity to high frequency modulating
signals. The output of the balance attenuator is present at the MODOUT port (U5701-28) and
connected to the VCO modulation diode D5731.
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Two crystal Þlters in the Þrst IF section and two ceramic Þlters in the second IF section provide the
required selectivity. The second IF at 455 kHz is mixed, ampliÞed and demodulated in the IF IC. The
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processing of the demodulated audio signal is performed by an audio processing IC located in the
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controller section.
8.
11.1 Front-End Band-Pass Filter and Pre-AmpliÞer
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A two pole pre-selector Þlter tuned by the dual varactor diode D3301 pre-selects the incoming signal
(PA RX) from the antenna switch to reduce spurious effects to following stages. The tuning voltage
(FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analog (D/A) converter
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(U0731-11) in the controller section. A dual hot carrier diode (D3303) limits any inband signal to
0dBm to prevent damage to the pre-ampliÞer.
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The RF pre-ampliÞer is an SMD device (Q3301) with collector base feedback to stabilize gain,
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impedance, and intermodulation. The collector current of approximately 11-16 mA, drawn from the
voltage 9V3, is controlled by a current source composed of Q3302, R3302, R3300, and R3311 -
R3313. In transmit mode the high K9V1 signal fed through diode D3300 switches off the current
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source and in turn the pre-ampliÞer. In receive mode K9V1 must be low to switch on the current
source. A 3 dB pad (R3306 - R3308 and R3316 - R3318) stabilizes the output impedance and
intermodulation performance.
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A second two pole varactor tuned bandpass Þlter provides additional Þltering to the ampliÞed signal.
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The dual varactor diode D3304 is controlled by the same signal which controls the pre-selector Þlter.
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If the VHF radio is conÞgured for a base station application, R3318 is not placed and TP3301 and
TP3302 are shorted.
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The signal coming from the front-end is converted to the Þrst IF (45.1 MHz) using a double balanced
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schottky diode mixer (D3331). Its ports are matched for incoming VHF signal conversion to the
45.1MHz IF using high side injection. The injection signal (VCO MIXER) coming from the mixer
buffer (Q3770) is Þltered by the lowpass consisting of (L3333, L3334, C3331 - C3333) and has a
level of approximately 10 dBm.
The mixer IF output signal (RX IF) from transformer T3301 pin 2 is fed to the Þrst two pole crystal
Þlter Y5201. The Þlter output in turn is matched to the following IF ampliÞer.
The IF ampliÞer Q5201 is actively biased by a collector base feedback (R5201, R5202) to a current
drain of approximately 5 mA drawn from the voltage 5V STAB. The output impedance is matched to
the second two pole crystal Þlter Y5202. A dual hot carrier diode (D5201) limits the Þlter output
voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
11.3 IF IC (U5201)
The Þrst IF signal from the crystal Þlters feeds the IF IC (U5201) at pin 6. Within the IF IC the
45.1MHz Þrst IF signal mixes with the second local oscillator (LO) at 44.645MHz to the second IF at
455 kHz. The second LO uses the external crystal Y5211. The second IF signal is ampliÞed and
Þltered by two external ceramic Þlters (FL5201, FL5202). Back in the IF IC the signal is demodulated
in a phase-lock detector and fed from IF IC pin 28 to the audio processing circuit AFIC U0103
located in the controller section (line DET AUDIO).
The IF IC also controls the squelch characteristics of the radio. With a few external parts (R5222,
C5229, C5230, R5223) the squelch tail, hysteresis, attack and delay were optimized for the radio. To
set the squelch threshold the signal from IF IC pin 23 (line SQ ATT IN) is attenuated by a
microprocessor controlled audio processing IC AFIC (U0103) located in the controller section. The
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attenuated signal from the AFIC (line SQ ATT OUT) enters the IF IC at pin 20 and is used to create
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a squelch indicator signal available at pin 15 (CSQ DET).
8.
The microprocessor controlled ADAPT signal at pin 22 activates the fast squelch indicator signal at
IF IC pin 18 (FAST SQ). Both squelch indicator signals CSQ DET (pin 15) and FAST SQ (pin 18) are
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combined, weighted by R0111 / R0112 and fed to the microprocessor U0101 pin 15 for
interpretation. From the voltage weighted by the resistors the µP determines whether CSQ DET,
FAST SQ or both are active.
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At IF IC pin 11 an RSSI signal is available with a dynamic range of 70 dB. The RSSI signal is
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buffered by op-amp U0106-3 and available at accessory connector J0400-15.
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The radioÕs 5-25 W PA is a three stage ampliÞer used to amplify the output from the exciter to the
radio transmit level. It consists of three stages in the line-up. The Þrst (Q3511) is a bipolar stage that
is controlled via the PA control line. It is followed a MOS FET stage (Q3521) and a Þnal bipolar stage
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(Q3531).
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Devices Q3511 and Q3521 are surface mounted. Bipolar Transistor Q3531 is directly attached to the
heat sink.
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The Þrst stage (Q3511) ampliÞes the RF signal from the VCO (line EXCITER PA) and controls the
output power of the PA. The output power of the transistor Q3511 is proportional to its collector
current which is adjusted by a voltage controlled current source consisting of Q3641 and Q3642.
ht
The current of the whole stage is drawn from the RX-TX Switch through coil L3652.
The collector current of Q3511 causes a voltage drop across the resistors R3645 and R3646.
Transistor Q3641 adjusts the voltage drop across R3644 through PA control line (PWR CNTL). The
current source Q3642 adjusts the collector current of Q3511 by modifying its base voltage until the
voltage drop across R3645 and R3646 plus VBE (0.6V) equals the voltage drop across R3644. If the
voltage of PWR CNTL is raised, the base voltage of Q3641 will also rise causing more current to
ßow to the collector of Q3641 and a higher voltage drop across R3644. This in turn results in more
current driven into the base of Q3511 by Q3642 so that the current of Q3511 is increased. The
collector current settles when the voltage over the series conÞguration of R3645 and R3646 plus
VBE of Q3642 equals the voltage over R3644. By controlling the output power of Q3511 and in turn
the input power of the following stages the ALC loop is able to regulate the output power of the
transmitter.
In receive mode the PA control line (PWR CNTL) is at ground level and switches off the collector
current of Q3641 which in turn switches off the current source transistor Q3642 and the RF
transistor Q3511.
12.2 PA Stages
The following stage uses an enhancement mode N-Channel MOS FET device (Q3521) and requires
a positive gate bias and a quiescent current ßow for proper operation. The voltage of the line BIAS
VLTG is set in transmit mode by a Digital to Analog (D/A) converter (U0731-4) and fed to the gate of
Q53521 via the resistive network R3613 - R3615. The bias voltage is tuned in the factory. If the
transistor is replaced, the bias voltage must be tuned with the Radio Service Software (RSS). Care
must be taken, not to damage the device by exceeding the maximum allowed bias voltage. The
t
collector current is drawn from the supply voltage 9V3 SUPP.
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The Þnal stage uses the bipolar device Q3531 and operates off the A+ supply voltage. For class C
8.
operation the base is DC grounded by two series inductors (L3521, L3522). A matching network
consisting of C3530-C3534, L3532, L3533 and two striplines transform the impedance to 50 Ohms
and feed the directional coupler.
16
12.3 Directional Coupler
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The directional coupler is a microstrip printed circuit which couples a small amount of the forward
ad
power off the RF power from Q3531. The coupled signal is rectiÞed to an output power proportional
negative DC voltage by the diode D3657 and sent to the power control circuit in the controller
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section via the line PWR DETECT for output power control. The power control circuit holds this
voltage constant, thus ensuring the forward power out of the radio to be held to a constant value.
.m
The antenna switch is switched synchronously with the PWR CNTL signal and feeds either the
antenna signal coming through the harmonic Þlter to the receiver or the transmitter signal coming
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In transmit mode, this PWR CNTL signal is above 1 V and biases Q3511 through Q3641 and Q3642
to allow a collector current to be drawn. The collector current of Q3511 drawn from A+ ßows via
://
L3631, L3531, L3532, L3533, directional coupler, D3551, L3651, D3651, L3652, Resistors R3645,
R3646, R3648 and switches the PIN diodes D3551 and D3651 to the low impedance state. D3551
tp
leads the RF signal from the directional coupler to the harmonic Þlter. The low impedance of D3651
is transformed to a high impedance at the input of the harmonic Þlter by the resonant circuit formed
ht
In receive mode the PWR CNTL signal at ground level turns off the current through the PIN diodes
and switches them to the high impedance state. The antenna signal, coming through the harmonic
Þlter, is channelled to the receiver via L3651, C3651 and line PA RX. The high impedance of D3651
in off state does not inßuence the receiver signal.
The transmitter signal from the antenna switch is channelled through the harmonic Þlter to the
antenna connector J3501.The harmonic Þlter is formed by inductors L3551, L3552, and capacitors
C3551 - C3554 This network forms a low-pass Þlter to attenuate harmonic energy of the transmitter
to speciÞcations level. R3551 is used for electro - static protection.
The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
t
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
ne
using a Digital to Analog (D/A) converter (U0731). The microprocessor writes the data into the D/A
converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
8.
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
16
voltage.
The microprocessor controls K9V1 ENABLE (U0101-6) to switch on the Þrst and the second PA
io
stage via K9V1. The antenna switch is turned on by the collector current of the Þrst PA stage. PA
DISABLE, also microprocessor controlled (U0101-54), sets BIAS VLTG (U0731-4) and VLTG LIMIT
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SET (U0731-13) in receive mode to low to switch off the bias of the MOS FET device Q3521 and to
switch off the power control voltage (PWR CNTL).
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Through an Analog to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA control
voltage (PWR CNTL) during the tuning process.
.m
The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward
power voltage PWR DETECT at a constant level.
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Opamp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT
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voltage from the PWR SET D/A output U0731 pin 2. The result is connected to opamp inverting
input U0701-4 pin 9. This voltage which is compared with a 4.6 volt reference VAG present at
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noninverting input U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line
PWR CNTL. The 4.6 volt reference VAG is set by a resistive divider circuit (R0171, R0172) which is
connected to ground and 9.3 volts and buffered by opamp U0105-1.
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During normal transmitter operation the voltages at the opamp inputs U0701-4 pins 9 and 10 should
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be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7 volts. If
power falls below the desired setting, PWR DETECT increases, causing the output at U0701-2 pin 7
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A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is
at the desired level. The power set D/A output voltage PWR SET (U0731-2) at U0701-2 pin 5 adjusts
power in steps by adjusting the required value of PWR DETECT. As PWR SET (U0731-2)
decreases, transmitter power must increase to make PWR DETECT larger and keep the inverting
input U0701-4 pin 9 at 4.6 volts.
Loop frequency response is controlled by opamp feedback components R0712 and C0711. Opamp
U0701-3 compares the power control voltage PWR CNTL divided by resistors R0717 to R0719 with
the voltage limit setting VLTG LIMIT SET from the D/A converter (U0731-13) and keeps the control
voltage constant via Q0711 if the control voltage, reduced by the resistive divider (R0717 to R0719),
approaches the voltage of VLTG LIMIT SET (U0731-13).
Rise and fall time of the output power during transmitter keying and dekeying is controlled by the
comparator formed by opamp U0701-3.
During normal transmitter operation the voltage at U701-3 pin 13 is higher than the voltage at pin 12
causing the output at pin 14 being low and switching off transistor Q0711. Diode D0732 reduces the
bias voltage BIAS VLTG for low control voltage levels.
The temperature of the PA area is monitored by opamp U0701-1 using thermistor R3611 (located in
the PA section). If the temperature increases, the resistance of R3611 decreases, decreasing the
voltage PA TEMP. The inverting ampliÞer formed by U0701-1 ampliÞes the PA TEMP voltage and if
the voltage at opamp pin 1 approaches 4.6 V plus the voltage (ON) across D0721, U701-1 simulates
an increased power which in turn decreases the power control voltage until the voltage at U0701-4
pin 9 is 4.6V again. During normal transmitter operation the output voltage of opamp U701-1 pin 1 is
t
below 4.6V. Diode D3601 located in the PA section acts as protection against transients and wrong
ne
polarity of the supply voltage.
8.
13.0 Frequency Synthesis
16
The complete synthesizer subsystem consists of the Reference Oscillator (Y3702 or Y3701), the
Fractional-N synthesizer (U3701), the Voltage Controlled Oscillator (Q3741, Q3751), the RX and TX
io
buffer stages (Q3760, Q3770, Q3780) and the feedback ampliÞer (Q3790).
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13.1 Reference Oscillator
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The Reference Oscillator (Y3702) contains a temperature compensated crystal oscillator with a
frequency of 16.8 MHz. An analog to digital (A/D) converter internal to U3701 and controlled by the
.m
microprocessor via serial interface (SRL) sets the voltage at the warp output of U3701 pin 16 to set
the frequency of the oscillator. The output of the oscillator (pin 2 of Y3702) is applied to pin 14
(XTAL1) of U3701 via a RC series combination.
w
In applications were less frequency stability is required the oscillator inside U3701 is used along with
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an external crystal Y3701, the varactor diode D3702, C3708, C3710 and R3704.
w
The FRAC-N synthesizer IC (U3701) consists of a pre-scaler, a programmable loop divider, control
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
tp
modulation, a balance attenuator to balance the high frequency analog modulation and low
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
ht
A voltage of 9.3V applied to the super Þlter input (U3701 pin 22) supplies an output voltage of 8.6
VDC at pin 18. It supplies the VCO (Q3741 / Q3751), VCO modulation bias circuit (R3714) and the
synthesizer charge pump resistor network (R3723, R3724). The synthesizer supply voltage is
provided by the 5V regulator U3801.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U3701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
(D3701-1-3, C3716, C3717). This voltage multiplier is basically a diode capacitor network driven by
two (1.05 MHz) 180 degrees out of phase signals (U3701-9 and -10).
Output LOCK (U3701-2) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U3701 divides the 16.8 MHz reference frequency down
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U3701-5),
clock line SPI CLK (U3701-6), and chip enable line FRACN CE (U3701-7).
The Voltage Controlled Oscillator (VCO) uses 2 colpitts oscillators, FET Q3741 for transmit and FET
Q3751 for receive. The appropriate oscillator is switched on or off by FRAC-N IC output AUX3
(U3701-1) using transistors Q3742 and Q3752. In RX mode AUX3 is nearly at ground level and
t
Q3742 enables a current ßow from the source of FET Q3751 while Q3752 is switched off. In TX
ne
mode AUX3 is about 5V DC and Q3742 is switched off. Q3752 is switched on and enables a current
ßow from the source of FET Q3741 while Q3751 is switched off. When switched on the FETs draw a
8.
drain current of 8 mA from the FRAC-N IC super Þlter output. The frequency of the receive oscillator
is mainly determined by L3752, C3752, C3754 - C3756 and varactor diodes D3751 / D3752. Diode
D3754 controls the amplitude of the oscillator. The frequency of the transmit oscillator is mainly
16
determined by L3734, C3736 - C3740 and varactor diodes D3732 / D3733. Diode D3739 controls
the amplitude of the oscillator. With a steering voltage from 3V to 10V at the varactor diodes the RX
io
frequency range from 181.1 MHz to 219.1 MHz and the TX frequency range from 136 MHz to 174
MHz are covered. In TX mode the modulation signal coming from the FRAC-N synthesizer IC
(U3701 pin 28) modulates the TX VCO via varactor diode D3731.
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Both oscillator outputs are combined and buffered by the VCO Buffer Q3760. Q3760 draws a
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collector current of 13 mA from the stabilized 5V (U3801) and drives the Mixer Buffer Q3770. Q3770
draws a collector current of 17 mA from the 9V3 voltage and drives the PA Buffer Q3780 (Pout =
13dBm) and the Pre-scaler Buffer Q3790. Q3790 draws a collector current of 8 mA from the
.m
stabilized 5V (U3801) and drives the pre-scaler internal to the FRAC-N IC. In transmit mode Q3780
is switched on by the K9V1 signal and draws a collector current of 19 mA from the K9V1 voltage.
The injection signal VCO MIXER with a level of 10dBm feeds the mixer through R3774. The buffer
w
stages Q3760, Q3770, Q3780 and the feedback ampliÞer Q3790 provide the necessary gain and
isolation for the synthesizer loop.
w
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The complete synthesizer subsystem works as follows. The combined output signal of the RX VCO
(Q3751) and TX VCO (Q3741) is buffered by VCO Buffer Q3760, Mixer Buffer Q3770 and Pre-scaler
tp
Buffer Q3790. To close the synthesizer loop, the collector of Q3790 is connected to the PREIN port
of synthesizer U3701 (pin 20). The output of (Q3770) also provides signals for the mixer (via VCO
ht
The pre-scaler in the synthesizer (U3701) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
of the loop divider is connected to the phase detector, which compares the loop divider«s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y3702).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 29 (I OUT of U3701). The loop Þlter (which consists of
R3715 - R3717, C3723 - C3725, C3727) transforms this current into a voltage that is applied to the
varactor diodes D3732, D3733 (TX), D3751, D3752 (RX) and alters the output frequency of the TX
VCO (Q3741) and RX VCO (Q3751). The current can be set to a value Þxed in the FRAC-N IC or to
a value determined by the current ßowing into CPBIAS 1 (U3701-27). The current is set by the value
of R3723 and R3724. The selection of the two different bias sources is done by software
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT line (U3701-31) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the FRACN CE line. When the synthesizer is within the lock range the current is
t
determined only by the resistors connected to CPBIAS 1 or the internal current source.
ne
A settled synthesizer loop is indicated by a high level of signal LOCK DET (U3701-2). This signal is
8.
routed to µP U0101-17 for further processing.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on
16
U3701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance
attenuator (high freq path). The A/D converter converts the low frequency analog modulating signal
io
into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The
balance attenuator is used to adjust the VCOÕs deviation sensitivity to high frequency modulating
signals. The output of the balance attenuator is present at the MODOUT port (U3701-28) and
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connected to the VCO modulation diode D3731.
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.m
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tp
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Chapter 5
Diagrams and Parts Lists
Table of Contents
t
Description Page
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UHF Diagrams and Parts Lists
8.
Main Board - UHF PCB Layout Component Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
16
Main Board - UHF PCB Layout Solder Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Main Board - UHF GM950i, Controller Schematic Diagram 1 of 2 . . . . . . . . . . . . . . . . . 5
io
Main Board - UHF GM950i, Controller Schematic Diagram 2 of 2 . . . . . . . . . . . . . . . . . 7
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ad
Main Board - UHF GM950E, Controller Schematic Diagram 1 of 2. . . . . . . . . . . . . . . . 13
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Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Main Board - UHF Power AmpliÞer 5-25W Schematic Diagram . . . . . . . . . . . . . . . . . . 29
w
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
://
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Main Board - UHF RX-FE Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Main Board - UHF RX-IF Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Description Page
VHF Diagrams and Parts Lists
Main Board - VHF PCB Layout Component Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Main Board - VHF PCB Layout Solder Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Main Board - VHF GM950i, Controller Schematic Diagram 1 of 2 . . . . . . . . . . . . . . . . 53
Main Board - VHF GM950i, Controller Schematic Diagram 2 of 2 . . . . . . . . . . . . . . . . 55
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Main Board - VHF GM950E, Controller Schematic Diagram 1 of 2 . . . . . . . . . . . . . . . 61
t
Main Board - VHF GM950E, Controller Schematic Diagram 2 of 2 . . . . . . . . . . . . . . . 63
ne
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Main Board - VHF Supply Voltage Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . 69
8.
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16
Main Board - VHF Power Control Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 73
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
io
Main Board - VHF Power AmpliÞer 5-25W Schematic Diagram . . . . . . . . . . . . . . . . . . 77
ad
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Main Board - VHF Synthesizer Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Main Board - VHF Voltage Controlled Oscillator Schematic Diagram . . . . . . . . . . . . . 85
.m
Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Main Board - VHF RX-FE Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
://
C0104
R0105
R0138
R0137
R0115 J0101
L0114
C0103
Y0114 C0105 E5702
R5703
C0116 C0117
C5726 R5724 C5801
Q0137
Shield 2605915V01
C0115 C0125 R0127 C0127 R5723 R5726 C5707
Q0114 C0137 C0110
C0126 R0104 C5226 4
R0102 R0125 C5728
C0114 5
R0103 R5705 R5221
R0114 Y5702
FL5202
Q0138 R0126 C5702 R5702 C5802
R0119 C0194
C0118 R0116 D0101 C5724 U5801 C5235
U0104
C0102 C5701
R0113 U0101 D5702
C5727
R0110 R5701 C5713 C5709
C5703
R0106
R0134 C0134 C5706
R0107 U0102 C5803
R0109 C5727 R5801
R5708 6
R0108 R0131 C0101 C5214 2
C0181
h
R0167 R0130 R0101
C0163 C0162 E5732 C5704 R5212 C5213
R0163 Shield 2605782V03 FL5201
C5731 C5212
R0192
R0128
C5733
R0120
t
C5741
R0123 C0121
R0122 C0122
R0121 R0124
D5742
L5742
Q0161 R0187
R0162 L5741 R5732 C5403
t
C0161 U0107 C0622 C0634
R0164 L5731 Y5201 Y5202 L5211 R5211
p
R0166 R0161 C0171 L5743
C0164 R0185 D5731 L5201
C0184 R0184 C5743 C5744 L5404
R0165 R0183 C0131 C0635 D5741 T5402
R0172 R0191 C5742 C5734 R5733 C5732 Y5211
:
R0171 R0186 R0616 C0633
C0182 C5745
C0132
U0108 R0605
U0631 R5742 C5746 Q5731 C5752 C5211
R0188 C0641 C5747 C5402
// w
C5317
C5316
C5315
C5321
C5324
C5749
R5743
U0105 C0632 L5403
R0604 D5743
Q5741 R5753 C5756 C5401
C0191
C5306
C5305
C5304
C5300
C5319 E5301
C0621 C5307
Q0601
Q0731 R5744 D5751 D5401
R0719 D0621 C5750 C5748 T5751 L5401 C5323
D0731
R0601 C5310 R5301
R5751
R5752
L5744
C5320 R5302
Shield 2605915V01
C0155 C0141 C5759
VR0621 R5789 R5401 C5311
w
R0155 C0172 R5309
L5302
C0142 R0621 C5760 R5308 D5302 C5326 D5301
C5753 R5756
R0143 C5784 D5305 C5329 R5306
L5781
R0154
C5328
Q0741 R5304 C5327
D5304
R0135 R5755 L5402
C0154 R0146 R0142 C5787 R5787 C5754 Q5301
R0741 C5751 R5307 C5309
R0145 R0141 R0136 R0742 R5788 C5783 C5404 C5303
C0742
R0721
w
Q5751
R5754
R0144 5 3 1 Q5781 T5401 C5314 C5302
U0731 C5781C5763
C5761
C5313
C5312
R5303
C5308
R0156 C5786 R5316 R5305
R5313 C5301
C0156 C0133 C0701 R5790
R5781
Q0742 C0721 R5784 R5782 L5754 C5762
R5786
C5782
R5785
U0106 R5310 C5325
.m
R0153 D5303
R5783
R0732 R0731 C0732 U0601
C0731 D0732 C5318 R5314
C0151
R0189 R0152 R0715 R0733 C0713
C0185 R0151
y
R0404 R0405
Q0401
C5502
L0401 L0402 C0403
r
R5501 C5503
R0407 C5611 C5633 C5634
C0404 R0401
R5502
a
R0406 R5623
R0402
L5554
L5501
Q5621
R5624 L5503
C0419 C0420 C0407 C0401 C5544 D5631
D5551
L5551
C0402 C5613 L5542
C5501 L5541 C5632
C5623
C5548 L5631
i
C5622 C5559
C5616 C5547
o
Q5510
4
C5617
L5611 C5530
1 R5513
C5553
R5614
C5511
C5551
C5513
6
R5512
U0401
L5553
C5512 C5520
Q5520 L5552
3
C5534
8
R5511 C5521
1
C5541
C5536 C5557
R5641 R5525
L5600 C5600 R5550
.
VR0422 R0432
t
VR0411
C0455
VR0420
C0464 VR0431
C0405
R0454
J0400
R5225
C5238 R0117 R0157
C0109
C5232
C5220
R5224
C5234
C5231 R5222 R5216
E5703 VR5701 C5718 E5701
C5729 TP5703 C0111 C0150 C0152
C5233 L0195
C5700 R0112 R0182 R0181
C5237 R0173
R0111 C0176 J0103
C5227
L0194 C0153
C0112
Y5701 U5701 C0175
U5201
R0175
C5224 C5720 C0199 R0139
C5239 C0173
tp_060sq TP_060SQ
R0148
TP5702
C0198
R5711
C5721
C5236 C5717 C0147
C5715 C5708 C0157 C0196 U0103 R0149
C5225
C5711
R5710
R0147
R5704
C5710
D5701 C0145
C5716
TP_060SQ
C0148 C0146
h
R5700
R5203 TP5701
TP_060SQ
TP5705
C0149 R0150
C5221
C5714 C5719
C5223 TP_060SQ
TP_060SQ C0174
tt p
C5228 L0170
R5202
C5222 R5713 R5712
C5712
C5204 Q5201 R5718
C5207 C5723 R0614 C0170
R5204 R5205 R5717
C5722
C5740
C0611
:/
C5208 R5716
R5714 R0615 D0611
L5203
R5715
C5205
C5203
R5201 C5725 C0612
D5201 C5200 TP5704 R5741
/
C5206
R0617
R0612
R0613
Q0612
w
C5201
R5207 L5202 C5202 E5731 C5793 R5794 R5795 C0631
Q5791 R0611
Q0611
TP_060SQ
R5315 C5785 C5774 R0632 C0613
D0631
w
C5792 R0631
R5774
R0642 R0641
R5792
TP5301
TP5302
R5776 R5793 R0603 R0602 R0722
C0703 R0725
R5777
C5791
R5791
w
Q5771R5773
TP5777
R0606 R0703
L5771
R0724
Q5302 C5771 C0602 C0601 C0702
R0723
R5771 C0605 VR0641 R0702
C5773
R5317 C0722
R5778
C0723
C5775
R5772
.m
R5311 R5779 D0721
R5318
R0734
R0704
C5322 C5331 R5775 C5772 R0711
C0741 U0701
C0604 C0712
R5312 C0603 R0701
R5319 Q0711
C0711
y
R0714
TP5788
R0717
R0735 C0714 R0713 C0439
r
R0712 R0716 R0718
C0733 C0716 R0435 R0439 C0435
a
J0102
R0100 R0438 Q0432
d
C0438
R5612 C5612 C5621 C0461
D0471
i
TP5204 R0461 Q0433
D5553 R0471 R0436
R5611 C5614 R5622
o
R0437
C0471 Q0461
Q5612
TP5201 R0476
R5553
C5558
TP5202 R0472 R0462
C5631
R5552
R5551
1 6
R5541
TP5203
C5618
R5616
C5615 R5613 R5621
Q5611
R0473 Q0471
R0463
Q0462 R0465
R0413
C0413
C5619 R0474 Q0412
C5556 R0477 C0462
C5531
R0475 R0412 R0414 R0415
R0464
8
R5615 R0442 C0414
R5617 C0463
Q0411
Q0441
R0411
.
L5532
C0411
n
Q0442 C0441
C5532 C5603
e
R5521
L5534
R0450
R0455 VR0435
VR0421 VR0441 VR0444 VR0471
R5531
R0456
D5601 R0451 C0454
C0472 VR0419
C0421 C0442 R0444 C0444 C0451 C0436
U0107-3
J0102 MIC_PTT MC14053B
+5V 9V3 9V3 +5V
R0116 R0117 R0118 INHIBIT
6 XX 12
1 +5V 0
XX U0104-4 11
2 SPI_MISO 270 270 4.7K 14 4 4 16 XX 1 XX 13 74AC08
3 J0102_3 (GP6)
C0118 C0119 VCC VCC VCC VDD
4 SPI_MOSI VR0118
R0119 470pF 470pF U0104-5 C0134 U0105-5 C0132 U0106-5 C0133 U0107-4 C0131
5 OPTION_BD_CE 1K ADAPT_5 5.1V
PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF
6 SPI_CLCK_SRC ADAPT
GND GND GND VEE VSS
7 J0102_7 (GP4)
7 11 11 7 8
8 +5V
C0102
470pF
(GP4-IN) PA2 +5V +5V 9V3 9V3
(GP2-OUT) PC0
(GP1-IN) PC1 L0114 C0116 Y0114 +5V +5V
(GP3-IN) PC2 R0113 33uH 3.6pF INSTPAR +2V5 +5V
C0164
(GP6-IN) PC3 10K R0164
Q0114 R0167 .0047uF 1MEG
(GP5-IN) PC5 R0114 X
R0115 47K NU L0194
(GP5_OUT) PB4 4.7K L0170 270nH SPI_CLK_5
1.8MEG R0161
(GP3_OUT) PB5 SPI_CLCK_SRC SPI_CLK
100K 33000nH
(GP6_OUT) PB7 R0110 R0162 L0195 SPI_DATA_5
TP0106 TP0107 C0161 C0162
10K 10K SPI_MOSI SPI_DATA
C0114 5 270nH
h
+5V Q0161 R0165 UNATTEN_RX_OUT FRACN_CE_5
33pF 7 U0105-2
Y R0163 0.1uF FRACN_CE FRACN_CE
MC3403 0.1uF
47K HIGH_LOW_BAND_5
6 C0170
R0102 +5V 100K HIGH_LOW_BAND
R0106 C0115 C0117 R0166 R0173 SQ_ATT_IN_5
USW_+5V_CL 33pF
tt p
2.2K 22pF 10K C0173 C0163 SQ_ATT_IN
4.7K C0104 0.1uF 1uF
RESET .01uF 0 NU SQ_ATT_OUT_5
K9V1_ENABLE_5 C0103 SQ_ATT_OUT
R0105 1uF C0176 C0174
K9V1_ENABLE 3.3uF MOD_IN_5
10K
SPI_MOSI MOD_IN
:/
TP0109
C0101 R0101 SPI_CLCK_SRC 3.3uF 0.1uF
+5V
0.1uF 10K RESET C0194 C0199
470pF 470pF
/
43
12
42
41
40
39
38
37
36
34
25
27
30
29
16 C0105
+5V
VDDH2 38
RESET 34
31
30
29
12
14
15
21
17
MODB
MODA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB0
w
55 0.1uF TP0108
R_W*
RESET
WDT_DISABLE 4
1
VDD
CLK_E
VDD
11
TIMING_CAP
1
VDDH1
4_BIT_ATTEN_IN
5_BIT_ATTEN_IN
EXT_ALERT_TONE_IN
VRH 22 C0175 R0175
SERIAL_CLOCK_IN
VDDL
SERIAL_DATA_IN
TX_OUT
A0 PB1 C0196 C0197 C0198
15 2 10 .001uF 150K
Y0 A1 PB2 VRL 21 470pF 470pF 470pF
14 3 9 37
EEPROM_CE Y1 U0102 A2 PB3 R0108 NC
13 8 R0109
GCB5 3
MC74HC138A
w
AFIC_CE Y2 PB4 R0107
12 7 33 47K 47K R0188
DAC_CE Y3 +5V PB5 XTL 100 0 C0185
11 6 31 16 NU 100pF
FRACN_CE Y4 PB6 EXTAL SQ_ATTEN_IN
10 6 5 18
OPTION_BD_CE Y5 CS1 PB7 IRQ 46 SQ_ATTEN_OUT
9 Y6 CS2 4 R0120 XIRQ 45
LED_CE R0181
w
7 5 10K 23 28 33 19 30K U0107-2 R0189
LCD_CE Y7 CS3 VSS STRA AFIC_CE CHIP_SELECT 4_BIT_ATTEN_OUT MC14053B
49
VSS
U0101 B+_CONTROL INHIBIT C0184
GND TP0105 24
VSS
27
PL_DPL_DECODER_OUT 5_BIT_ATTEN_OUT
20 10K R0182 2 6 1uF 82K
8 MC68HC711E20 1 0 15 9
R0100 PA0
0 64 32 PL_CLOCK_STROBE R0183 1 1 8
47 10K 10 U0106-4
.m
NU PD0 PA1
50 63 10 MC3403
PD1 PA2 R0121
51 62 UNATTEN_RX_OUT 22 FLT_RX_AUDIO
FLT_A+ TP0104 PD2 PA3 +2V5 R0130 R0185 NU R0187
52 59 0 NU 7 C0181
+5V
D0101 53
PD3 PA4
58 160K 13 AUX_TX_IN U0103 RX_IN
8 0.1uF
J0101 PD4 PA5 PL_DPL_IN 30K 0
R0104 54 57 R0122 AFIC 40 NU
3 PD5 PA6 U0107-1 GCB3 R0186
33K 56 12 39 36 R0184
FLT_A+ 17 PA7 MC14053B XTAL_OUT
NC10
220K GCB1
y
30K
* note 1
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC1
14 12 6 2
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
C0121 U0105-3
NC
20
18
16
14
19
17
15
13
11 0.1uF
4
3
2
9 PRE_EMPHASIS_OUT
100K R0124 RX_OUT
r
R0103 C0125 NU .039uF
PBIAS_RESISTOR
AUX_RX_IN
10K 2 1 0.1uF
SPI_MISO R0125 6.8K R0131 VAG_BYPASS 28 AUDIO_PA_ENABLE
VAG_VOLUME
a
SPI_MOSI C0126 C0122
0.1uF 200K 0 26
DPL_CAP
BUS+ 15 BUS+ SPI_CLCK_SRC GND RX_AUDIO
35 XTAL_IN
25 PL_CAP
ANALOG_1 10 NU
R0126
d
.01uF
TX_IN
ANALOG_2 11 C0153 DET_AUDIO_5
+5V
R0139 0.1uF TP0111
ANALOG_3 13 DET_AUDIO
1 200K 240K
LED_CE 12 LED_CE +5V
10
11
24
3 U0104-1
5
SPI_DATA_BUF 6
74AC08 2 C0157
LED_CLCK_BUF 5 R0157
o
C0127 R0127 R0136 +2V5 470pF
LCD_CLCK_BUF 8 0.1uF 200K
6 U0104-2
4 33K R0148
470K
R0150
51K
C0152
1uF C0150 * note 1
R0137 .47uF
7
GND
19
20
74AC08 5
8 U0104-3
9
R0134
10K
R0138
4.7K
Q0137
47K
1 6
FLAT_TX_AUDIO
R0135
47K
2
U0106-1
3 MC3403
1
R0147
180K
C0148
MIC C0147 C0146 RX_AUDIO-SEND J0103-5 5
74AC08 10 470pF
56pF GP3 J0103-7 7 J0103_7
47K C0137 GP3
HOOK 3 .01uF NU GP5 J0103-8 8 J0103_8
.001uF GP5
8
+2V5 6
MIC_PTT 4 MIC_PTT NU GROUND J0103-6
47K
MIC 16 Q0138
HANDSET_AUDIO 14 R0149
0
.
+5V +5V
+5V +5V
PC5
Q0461
(GP5) PC2 (GP3) Q0431 47K
Q0412
47K VR0431
C0461 47K C0413 47K C0431 14V
.01uF .01uF 470pF
47K C0464 47K
R0463 VR0464
470pF
270 14V R0414 C0412 VR0411
270 470pF
14V
Q0462 Q0411
R0464 R0411 +5V FLT_A+
PB4 PB5
h
10K 10K
R0465
0
C0463
.01uF R0415
C0411
.01uF D0471
(GP2) R0442
4.7K
R0443
4.7K
NU 0 NU NU
NU
tt p
XX
EMERGENCY_CONTROL
XX Q0441
XX R0441 NU
J0103_8 J0103_7 10K C0442
PC0 470pF
C0462
:/
C0414 Q0442 VR0441
470pF 470pF +5V XX 33V
C0441
FLT_A+ .01uF
XX
/
(GP4)
w
+5V R0474 R0475 XX
47K 4.7K R0477
R0472
0 10K
NU
w
PA2
R0437 R0444
R0436
4.7K Q0471 BUS+
47K
47K 270
(GP6) R0471 R0473
w
0 68K C0444
47K VR0444
PC3 NU NU 470pF
Q0432 5.1V
R0476 VR0471
270 33V
C0435 47K C0472
.m
.01uF 470pF
47K J0102_7
R0435
270 C0471
C0436 VR0435
470pF 470pF J0400
14V
y
Q0433 (IN)
R0438 3 GP1
PB7 4 GP2 (OUT)
10K 6 BUS+
r
8 GP3 (IN/OUT)
R0439 12 GP5 (IN/OUT)
a
0 C0438 14 GP6 (IN/OUT)
0
NU .01uF 15 RSSI
16 EXT_SPKR+
d
1 EXT_SPKR-
J0102_3 MIC 2 EXTERNAL_MIC_AUDIO
10 IGNITION
i
C0445
C0439
9 GP4 (IN)
C0421 VR0421
o
FLAT_TX_AUDIO 5 FLAT_TX_AUDIO
470pF 470pF 14V
FLT_A+ 11 FLT_RX_AUDIO
.47uF 13 ANALOG_GND/SW_B+
1 VR0445 R0446 C0446
14V 7 GROUND
100K 470pF
6
C0454
470pF
C0407
C0401
8
.1uF R0450
R0401 .100uF C0450 560
+5V SW_B+
RX_AUDIO FLT_RX_AUDIO
.
.001uF
1K SW_B+ U0401 47K 100K 470pF
7 TDA1519C R0427 VR0450
+5V R0406 0 14V
e
INT_SPKR+
GEPD5462 -1
FLT_A+ FLT_A+
+5V +5V
C0102 2113741F17 470pF 50V C0150 2311049A05 TANT CP 470nF 10% 25V
t
C0103 2311049A42 TANT CP 3.3uF 10% 6V C0151 2113741F17 470pF 50V
ne
C0104 2113741F49 10nF 50V C0152 2311049A07 TANT CP 1uF 10% 16V
8.
C0109 2113741F17 470pF 50V C0154 2113743K15 100nF 16V
16
C0110 2113741F17 470pF 50V C0155 2113740F39 33pF 5% 50V
C0117 2113740A41 33pF 5% 50V C0170 2311049A07 TANT CP 1uF 10% 16V
C0119 2113741F17 470pF 50V C0172 2311049A07 TANT CP 1uF 10% 16V
w
C0121 2113743K05 39nF 16V C0173 2311049A07 TANT CP 1uF 10% 16V
C0132 2113743K15 100nF 16V C0184 2311049A07 TANT CP 1uF 10% 16V
C0141 2311049J26 TANT CP 10uF 20% 16V C0196 2113741F17 470pF 50V
t
C0411 2113741F49 10nF 50V
ne
L0114 2460578C43 INDUCTOR CHIP 33.0UH
C0412 2113741F17 470pF 50V
L0170 2462587K26 CHIP IND 33000 NH
8.
C0413 2113741F49 10nF 50V
L0194 2462587Q40 COIL CHIP 270nH
C0414 2113741F17 470pF 50V
16
L0195 2462587Q40 COIL CHIP 270nH
C0419 2113741F25 1nF 50V
L0401 2484657R01 Ferrite Bead
C0420
C0421
2113741F25
2113741F17
1nF 50V
470pF 50V
L0402
io
2484657R01 Ferrite Bead
ad
Q0114 4880214G02 TSTR NPN 40V .2A
C0422 2113741F17 470pF 50V
Q0137 4880048M01 TSTR NPN DIG 47k/47k
C0431 2113741F17 470pF 50V
yr
t
R0112 0662057A93 68k 1/16W 5% R0152 0662057A73 10k 1/16W 5%
ne
R0113 0662057A73 10k 1/16W 5% R0154 0662057A73 10k 1/16W 5%
8.
R0114 0662057A65 4k7 1/16W 5% R0155 0662057A93 68k 1/16W 5%
16
R0116 0662057C61 270 1/16W 5% R0157 0662057A77 15k 1/16W 5% (12.5kHz)
0662057A84 30k 1/16W 5% (20/25kHz)
R0117
R0118
0662057C61
0662057A65
270 1/16W 5%
4k7 1/16W 5% io
R0161 0662057A97 100k 1/16W
ad
R0162 0662057A73 10k 1/16W 5%
R0119 0662057A49 1k 1/16W 5%
R0163 0662057A97 100k 1/16W
R0120 0662057A73 10k 1/16W 5%
yr
t
R0425 0662057A73 10k 1/16W 5%
ne
2-CHNL
R0426 0662057A89 47k 1/16W 5% U0108 5105462G78 IC EEPROM !&K SPEI
CMOS
8.
R0427 0662057B47 0 1/16W
U0401 5109699X01 AUDIO PA TDA1915C
R0431 0662057A89 47k 1/16W 5%
16
VR0118 4880140L06 DIODE 5.1V 5% 225mW
R0432 0662057A65 4k7 1/16W 5%
VR0411 4813830A27 DIODE 14V 5% 225mW
R0435
R0436
0662057C61
0662057A89
270 1/16W 5%
47k 1/16W 5%
VR0421
io
4813830A27 DIODE 14V 5% 225mW
ad
VR0422 4880140L06 DIODE 5.1V 5% 225mW
R0437 0662057A65 4k7 1/16W 5%
VR0431 4813830A27 DIODE 14V 5% 225mW
R0438 0662057A73 10k 1/16W 5%
yr
U0107-3
J0102 MIC_PTT MC14053B
+5V 9V3 9V3 +5V
R0116 R0117 R0118 INHIBIT
6 XX 12
1 +5V NU 0
XX U0104-4 11
2 SPI_MISO 270 270 4.7K 14 4 4 NU 16 NU XX 1 XX 13 74AC08
3 J0102_3 (GP6)
C0118 C0119 VCC VCC VCC VDD
4 SPI_MOSI VR0118
R0119 470pF 470pF U0104-5 C0134 U0105-5 C0132 U0106-5 C0133 U0107-4 C0131
5 OPTION_BD_CE 1K ADAPT_5 5.1V
PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF
6 SPI_CLCK_SRC ADAPT
GND GND GND VEE VSS
7 J0102_7 (GP4)
7 11 11 7 8
8 +5V
C0102
470pF
(GP4-IN) PA2 +5V +5V 9V3 9V3
(GP2-OUT) PC0
(GP1-IN) PC1 L0114 C0116 Y0114 +5V +5V
(GP3-IN) PC2 R0113 33uH 3.6pF INSTPAR +2V5 +5V
C0164 R0164
(GP6-IN) PC3 10K .0047uF
Q0114 R0167 1MEG
(GP5-IN) PC5 R0114 X
R0115 47K NU L0194
(GP5_OUT) PB4 4.7K L0170 270nH SPI_CLK_5
1.8MEG R0161
(GP3_OUT) PB5 SPI_CLCK_SRC SPI_CLK
100K 33000nH
(GP6_OUT) PB7 R0110 R0162 L0195 SPI_DATA_5
TP0106 TP0107 C0161 C0162
10K 10K SPI_MOSI SPI_DATA
C0114 5 270nH
+5V Q0161 R0165 UNATTEN_RX_OUT FRACN_CE_5
h
33pF 7 U0105-2
Y R0163 0.1uF FRACN_CE FRACN_CE
MC3403 0.1uF
47K HIGH_LOW_BAND_5
6 C0170
R0102 +5V 100K R0173 HIGH_LOW_BAND
R0106 C0115 C0117 R0166 SQ_ATT_IN_5
USW_+5V_CL NU
2.2K 22pF 33pF 10K C0173 C0163
tt p
4.7K C0104 SQ_ATT_IN
0.1uF 1uF
RESET .01uF 0 SQ_ATT_OUT_5
K9V1_ENABLE_5 C0103 C0176 SQ_ATT_OUT
R0105 1uF NU C0174
K9V1_ENABLE 3.3uF MOD_IN_5
10K
SPI_MOSI MOD_IN
TP0109
:/
C0101 R0101 SPI_CLCK_SRC 3.3uF 0.1uF
+5V
0.1uF 10K RESET C0194 C0199
470pF 470pF
/
43
12
42
41
40
39
38
37
36
34
25
27
30
29
16 C0105
+5V
38
RESET 34
31
30
29
12
14
15
21
17
MODB
MODA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB0
55 0.1uF TP0108
R_W*
RESET
w
WDT_DISABLE 4
1
VDD
CLK_E
VDD
11
TIMING_CAP
1
VDDH1
VDDH2
4_BIT_ATTEN_IN
5_BIT_ATTEN_IN
EXT_ALERT_TONE_IN
VRH 22 R0175
SERIAL_CLOCK_IN
VDDL
SERIAL_DATA_IN
TX_OUT
A0 PB1 C0175 C0196 C0197 C0198
15 2 10 150K
Y0 A1 PB2 VRL 21 .001uF 470pF 470pF 470pF
14 3 9 37
EEPROM_CE Y1 U0102 A2 PB3 R0108 NC
13 8 R0109
GCB5 3
MC74HC138A
Y2 PB4
w
AFIC_CE 47K 47K R0107 R0188
12 7 33
DAC_CE Y3 +5V PB5 XTL 100 0 C0185
11 6 31 16 NU 100pF
FRACN_CE Y4 PB6 EXTAL SQ_ATTEN_IN
10 6 5 18 NU
OPTION_BD_CE Y5 CS1 PB7 IRQ 46 SQ_ATTEN_OUT
9 Y6 CS2 4 R0120 XIRQ 45
LED_CE R0181
w
7 5 10K 23 28 33 19 30K U0107-2 R0189
LCD_CE Y7 CS3 VSS STRA AFIC_CE CHIP_SELECT 4_BIT_ATTEN_OUT MC14053B
49
VSS
U0101 B+_CONTROL INHIBIT
GND TP0105 24
VSS
27
PL_DPL_DECODER_OUT 5_BIT_ATTEN_OUT
20 10K R0182 2 6 C0184 82K NU
8 MC68HC711E20 1 0 15 NU 9
R0100 PA0
0 64 32 PL_CLOCK_STROBE R0183 NU 1 1 8
47 10K 10 U0106-4
.m
NU PD0 PA1
50 63 1uF 10 MC3403
PD1 PA2 R0121
51 62 UNATTEN_RX_OUT 22 NU FLT_RX_AUDIO
FLT_A+ TP0104 PD2 PA3 +2V5 R0130 R0185 NU R0187
52 59 0 NU 7 C0181
+5V
D0101 53
PD3 PA4
58 160K 13 AUX_TX_IN U0103 RX_IN
8 0.1uF
J0101 PD4 PA5 PL_DPL_IN 30K 0
R0104 54 57 R0122 AFIC 40 NU
3 PD5 PA6 U0107-1 NU GCB3
33K 56 12 39 36 R0184 R0186
MC14053B
y
FLT_A+ 17 PA7 XTAL_OUT
NC10
14 6 2
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
C0121 U0105-3
NC
20
18
16
14
19
17
15
13
13 11 0.1uF
4
3
2
9 PRE_EMPHASIS_OUT
100K
r
R0103 C0125 .039uF R0124 RX_OUT
NU
PBIAS_RESISTOR
AUX_RX_IN
10K 2 1 0.1uF
6.8K VAG_BYPASS 28
a
SPI_MISO R0125 R0131 AUDIO_PA_ENABLE
VAG_VOLUME
SPI_MOSI C0126 C0122
0.1uF 200K 0 26
DPL_CAP
BUS+ 15 BUS+ SPI_CLCK_SRC GND RX_AUDIO
35 XTAL_IN
25 PL_CAP
NU
d
ANALOG_1 10 R0126 .01uF
TX_IN
ANALOG_2 11 C0153 DET_AUDIO_5
+5V R0139
ANALOG_3 13 0.1uF TP0111 DET_AUDIO
1 200K 240K
i
LED_CE 12 LED_CE +5V
10
11
24
3 U0104-1
5
SPI_DATA_BUF 6
C0157
o
LED_CLCK_BUF 5 74AC08 2 C0127 R0127 R0157
R0136 +2V5 470pF
LCD_CLCK_BUF 8 0.1uF 200K
6 U0104-2
4 1 33K R0148
470K
R0150
51K
C0152
1uF C0150 * note 1
R0137 .47uF
GND 7 R0134 R0138 NU
74AC08 5 10K 4.7K
47K
R0135
R0147
19 NU 2 180K
20 FLAT_TX_AUDIO
9 U0106-1 1
6
Q0137
8 U0104-3 47K 3 MC3403 C0148
MIC NU C0147 C0146 RX_AUDIO-SEND J0103-5 5
74AC08 10 470pF
56pF GP3 J0103-7 7 J0103_7
47K C0137 GP3
8
HOOK 3 .01uF NU GP5 J0103-8 8 J0103_8
+2V5 GP5
.001uF GROUND 6
MIC_PTT 4 MIC_PTT 47K NU J0103-6
MIC 16 Q0138
R0149
.
HANDSET_AUDIO 14 0
INT_SPKR+ 1 INT_SPKR+
n
47K +5V
INT_SPKR- 2 INT_SPKR- R0145 C0145
9V3 R0146
ON_OFF_CONTROL 18 ON_OFF_CONTROL 0 30K .001uF
47K U0108 9V3
LCD_CE
e
NU
DAC_CE_5 NU EEPROM_X25160 VAG_7
R0141 R0144 NU 8
DAC_CE DAC_CE 2_1MHZ_5 TP0110 C0191 VAG
100 R0191 VCC
t
+5V +5V
+5V +5V
PC5
Q0461
(GP5) PC2 (GP3) Q0431 47K
Q0412
NU NU
47K
C0461 47K C0413 47K C0431 VR0431
.01uF .01uF 470pF 14V
NU 47K C0464 47K
R0463 VR0464 NU
470pF R0414
270 14V C0412 VR0411
NU NU 270 470pF 14V
NU
NU NU NU
Q0462
NU Q0411
R0464 R0411 NU +5V FLT_A+
PB4 PB5
h
10K 10K
NU
R0465
C0463
.01uF R0415
NU
C0411
.01uF D0471
(GP2) R0442
4.7K
R0443
4.7K
0 NU 0 NU NU NU NU
XX
tt p
EMERGENCY_CONTROL R0441
XX Q0441
XX 10K VR0441
NU
J0103_8 J0103_7 NU C0442
470pF 33V
PC0
Q0442 NU
C0462 NU
:/
C0414
470pF +5V C0441 NU
470pF XX
NU FLT_A+ .01uF
NU
NU
XX
/
(GP4)
w
+5V R0474 XX
R0475
47K 4.7K R0477
R0472
NU 10K
0
w
NU
PA2
R0444
R0436 R0437
4.7K Q0471 BUS+
47K
NU 47K 270
(GP6) R0471 R0473 NU
w
0 68K 47K C0444 VR0444
PC3 Q0432 NU 470pF 5.1V
NU R0476 VR0471
270
33V
.m
C0435 47K NU C0472
.01uF 470pF NU
NU 47K J0102_7 NU
R0435 C0436 VR0435
270 470pF 14V C0471
NU NU
NU 470pF J0400
y
Q0433 NU
R0438 NU 3 GP1 (IN)
PB7 4 GP2 (OUT)
10K 6 BUS+
r
NU 8 GP3 (IN/OUT)
12 GP5
a
R0439 (IN/OUT)
0 C0438 14 GP6 (IN/OUT)
NU .01uF 15 RSSI
d
NU 16 EXT_SPKR+
1 EXT_SPKR-
J0102_3 MIC 2 EXTERNAL_MIC_AUDIO
i
10 IGNITION
C0445
9 GP4 (IN)
o
C0439 C0421 VR0421 .47uF NU
FLAT_TX_AUDIO 5 FLAT_TX_AUDIO
470pF 470pF 14V
FLT_A+ 11 FLT_RX_AUDIO
NU
13 ANALOG_GND/SW_B+
1 6 VR0445
14V
NU
R0446
100K
C0446
470pF
7 GROUND
C0454
470pF
8
C0407
C0401 .1uF
R0401 .100uF C0450 R0450 NU
+5V NU SW_B+
RX_AUDIO FLT_RX_AUDIO
.
C0419 47uF
R0402 .0033uF R0426 R0451 C0451 0
.001uF
1K SW_B+ U0401 47K 100K 470pF
7 TDA1519C R0427 VR0450
e
+5V 0 14V
VCC PE3
R0406 9 NU
22K INV L0401 R0456
t
GEPD5448 -1
FLT_A+ FLT_A+
C0101 2113743K15 100nF 16V C0150 2311049A05 TANT CP 470nF 10% 25V
t
C0103 2311049A42 TANT CP 3.3uF 10% 6V C0152 2311049A07 TANT CP 1uF 10% 16V
ne
C0104 2113741F49 10nF 50V C0153 2113743K15 100nF 16V
8.
C0109 2113741F17 470pF 50V C0155 2113740F39 33pF 5% 50V
16
C0110 2113741F17 470pF 50V C0157 2113741F17 470pF 50V
C0116 2113740G16 CERAMIC CHIP 3.6 P C0170 2311049A07 TANT CP 1uF 10% 16V
.m
C0118 2113741F17 470pF 50V C0172 2311049A07 TANT CP 1uF 10% 16V
w
C0119 2113741F17 470pF 50V C0173 2311049A07 TANT CP 1uF 10% 16V
w
C0131 2113743K15 100nF 16V (not used) C0194 2113741F17 470pF 50V
ht
C0133 2113743K15 100nF 16V (not used) C0197 2113741F17 470pF 50V
C0141 2311049J26 TANT CP 10uF 20% 16V C0401 2113743A19 100nF 16V
C0148 2113741F17 470pF 50V C0404 2311049A99 TANT CP 47uF 20% 10V
C0407 2109720D14 CER LOW DIST 100nF R0107 0662057A25 100 1/16W 5%
t
C0431 2113741F17 470pF 50V R0112 0662057A93 68k 1/16W 5%
ne
C0444 2113741F17 470pF 50V R0113 0662057A73 10k 1/16W 5%
8.
C0454 2113741F17 470pF 50V R0114 0662057A65 4k7 1/16W 5%
16
D0101 4813833C02 DUAL SOT MMBD6100 R0116 0662057C61 270 1/16W 5%
J0101
J0102
0902636Y01
0904424J06
Connector Flex Side Entry
R0118 io
0662057C61
0662057A65
270 1/16W 5%
4k7 1/16W 5%
ad
J0103 0904424J06 Connector double row 8pin R0119 0662057A49 1k 1/16W 5%
L0194 2462587Q40 COIL CHIP 270nH R0123 0662057A97 100k 1/16W (not used)
w
t
R0156 0662057B47 0 1/16W R0444 0662057C61 270 1/16W 5%
ne
R0157 0662057A77 15k 1/16W 5% (12.5kHz) R0454 0662057A49 1k 1/16W 5%
0662057A84 30k 1/16W 5% (20/25kHz)
8.
R0461 0662057A89 47k 1/16W 5%
R0161 0662057A97 100k 1/16W
R0465 0662057B47 0 1/16W
16
R0162 0662057A73 10k 1/16W 5%
R0471 0662057B47 0 1/16W
R0163 0662057A97 100k 1/16W
R0474
0662057B47
0662057A89
0 1/16W
47k 1/16W 5%
ad
R0166 0662057A73 10k 1/16W 5%
U0101 5102898X67 PROC350 PLAT S/W
R0167 0662057A89 47k 1/16W 5% R010000 A2
yr
__3403_
R0183 0662057A73 10k 1/16W 5% (not used) U0401 5109699X01 AUDIO PA TDA1915C
w
t
ne
8.
16
io
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yr
.m
w
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w
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tp
ht
FLT_A+
USW_+5V
D0621
2
3
FLT_A+_8 R0621 USW_+5V_CL
1
FLT_A+
2.2K
h
tt p
9V3_SUPP
R0606 9V3
U0601
:/
0 0
4 LM2941T 5
LM2941T
/
2 1 R0602 R0631 D0631 U0631
R0601 ON_OFF* ADJ 7.5K
w
C0604 10 LP2951CM
10K C0605 1
33uF
GND .1uF 3 8 1
C0601 C0602 C0603 INPUT OUTPUT +5V
470pF .1uF 10uF 3 2 7 5
FEEDBACK ERROR
w
3 2
R0632 SHUTDOWN SENSE
5V_TP 6 C0633 C0634 C0635
10 C0631 C0632
.1uF .022uF 47uF .1uF
33uF
w
R0603 GND
1.2K
4
Q0601
.m
R0604 R0605
y
1K 6.8K
RESET
ra
d
SW_B+
i
Q0611
R0611
1.2K
1 R0612
o
C0613
470pF
R0641
30K
SW_B+
6
3.3K 3.3K
470pF
R0613
8
3.3K
3.3K
BATTERY_VOLTAGE
R0617
3.3K
.
3.3K
C0641 VR0641
n
R0642
10K 0.1uF 5.1V
EMERGENCY_CONTROL
e
ON_OFF_CONTROL
t
1 R0614 R0615
B+_CONTROL 10K1K 10K
10K
3 Q0612
2
IGNITION_CONTROL
R0616 C0612
C0611
D0611 10K 0.1uF
47uF
GEPD5449-1
t
C0603 2380090M24 LYT 10uF 50V 20% R0614 0662057A73 10k 1/16W 5%
ne
C0604 2311049A97 33uF 20% 16V R0615 0662057A73 10k 1/16W 5%
8.
C0611 2311049A99 TANT CP 47uF 20% 10V R0617 0662057C87 3300 5 1/8
16
C0612 2113743K15 100nF 16V R0621 0662057A57 2k2 1/16W 5%
C0632 2311049A97 33uF 20% 16V U0601 5105625U25 9.3V REG 2941
.m
t
ne
8.
16
io
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(CNTL) VAG
VAG_7
C0711 R0712
R0702
39000pF 330
47K
PWR_DETECT_7 R0701
6
(PA) PWR_DETECT R0704
U0701-2 7 9
68K PWR_CNTL_7
5 MC3403 8
68K R0711 U0701-4 PWR_CNTL
10
C0701 C0702 (PA)
22K C0713
100pF 100pF MC3403 100pF 9V3
C0712
h
R0716 R0717
R0703 43pF 560K 33K
10K
tt p
Q0711 R0714 12
14 U0701-3
22K
13 C0716 R0718
MC3403 3300pF 68K
:/
R0713
VAG 3.3K
VLTG_LIMIT_7
VLTG_LIMIT
/
9V3_7
w
9V3 C0714 (CNTL)
(SV) 9V3
R0719
R0725 68K
10K .100uF
w
R0715
3 22K
D0721
w
C0723
R0721 C0722 100pF
10K 100pF
2 1
.m
R0724
3 1
PA_TEMP_7 R0722 U0701-1 3
(PA) PA_TEMP 100K 9V3
2 D0732
22K MC3403
C0731
y
R0731
C0721 R0723 22K
2 1
100pF 0.1uF
r
47K U0731
MC144111
a
16
PA_PWR_SET VDD 2
SPI_CLCK_SRC_7 Q1 R0733 BIAS_VLTG_7
d
10 4
(CNTL) SPI_CLCK_SRC CLK Q2 BIAS_VLTG
11
DAC_CE_7 Q3 47K (PA)
6 13
i
(CNTL) DAC_CE EN Q4
C0732
o
SPI_DATA_SRC_7 D0731
1 3 100pF
(CNTL) SPI_DATA_SRC D_IN R1
5 1
R2
1 6
8
9
NC
R3
R4
12
14 2
3 R0732
4.7K
C0733
.220uF
NC1
D_OUT 15
GND
8
7 FE_CNTL_VLTG_7
R0735
FE_CNTL_VLTG
.
PA_ENABLE_7 47K 0
n
Q0731 (FE)
(CNTL) PA_ENABLE
R0734
47K 47.5K
e
9V3
t
SW_B+_7 C0703
(SV) SW_B+ Q0742 K9V1_7
K9V1 (PA)
4 0.1uF
VCC
U0701-5 R0742 C0741
PWR_GND 1K 100pF
GND
R0741 0102725B24 UHF PWR CNTL
11
1K
K9V1_ENABLE_7 47K
(CNTL) K9V1_ENABLE Q0741
47K
GEPD 5403-1
t
C0703 2113743K15 100nF 16V R0714 0662057A81 22k 1/16W 5%
ne
C0711 2113741A59 CL2 R0715 0662057A81 22k 1/16W 5%
8.
C0713 2113740F51 100pF 5% 50V R0717 0662057A85 33k 1/16W 5%
16
C0714 2113743A19 100nF 16V R0718 0662057A93 68k 1/16W 5%
Q0741 4880048M01 TSTR NPN DIG 47k/47k U0731 5113811G02 IC D/A CONV & BIT 4
CHAN
Q0742 4805128M27 TSTR PNP SOT89
BSR33
A+
L5600
FLT_A+_1
1 FLT_A+
J5601
L5601
2
D5601
C5600 C5601 C5604 A+ C5602 C5603
330pF 10uF 10uF 100pF .001uF
C5531 C5548
h
L5532 L5542
TP5201
C5622 C5532 C5530 C5547
K9V1_1 R5623 R5624
K9V1
tt p
4.7 4.7 .01uF 100pF .1uF 100pF
C5621
.001uF Q5611
:/
R5621
680
/
C5611
.01uF C5623 R5522
w
R5622 R5521
10K 100pF 1K 1K
NU Q5621
R5513 R5523
w
C5613 C5523
2.2K 47K L5541
TP5202 .01uF .01uF C5541
NU 18nH
Q5612 NU 36pF
PWR_CNTL_1 R5611
DIRECTIONAL COUPLER
w
C5614 C5533 1.5mmx2mm 1.5mmx25mm
C5536
10K .001uF 36pF 27pF
PWR_CNTL C5502
NU Q5530 C5542
C5612 5mmx3mm C5535 1mmx3mm
MRF5015 36pF C5543 C5544
.m
.01uF R5525
R5612 C5619 .01uF PART OF 27pF 13pF
2K 100pF HARDWARE KIT 30pF D5553
4.7 Q5540
R5502 L5533 C5537 C5558 R5553
R5511 C5534
R5613
68 C5521 1.5mmx2mm 30pF
13.85nH 27pF MRF650 5.1pF 120
1K Q5510 Q5520 R5526 PART OF
10 HARDWARE KIT
MRF MRF557 1
y
EXCITER_PA_1
R5552
C5503 R5501 L5501 6 2 27pF 4.7 51 TP5204
C5512 1.5mmx2mm R5512
7.66nH 7 3 3 C5522
4.7 R5527 PWR_DETECT_1
r
EXCITER_PA 27pF 2 43pF
10 R5531 PWR_DETECT
18pF L5534
4.7 10
a
L5503 C5501 1 5 4
C5511
22nH 10pF 4 8 C5556 R5551
4.7pF C5513 R5614 .001uF 10K
d
NU 20pF 51
i
L5611 C5616 C5617
330pF 330pF
PA_TEMP
PA_TEMP_1
TP5203
1 o
6
C5642 R5641 L5554 C5559
.001uF 100K C5618 120nH .001uF HARMONIC FILTER
.1uF
8
D5551 C5551 L5552 L5553
J5501
18nH 18nH
.
100pF 2 3
n
C5554 R5550
L5551 C5557 C5552 C5553 10K
8.2pF 6.8pF
R5616 R5617 18nH 9.1pF 12pF
e
10 NU
10
t
C5555
160pF
0102725B23 PA ASSEMBLY
t
C5503 2113740F37 27pF 5% 50V C5602 2113740F51 100pF 5% 50V
ne
C5512 2113740F33 18pF 5% 50V C5603 2113741F25 1nF 50V
C5513 2113740F34 20pF 5% 50V C5604 2311049A45 TANT CP 10uF 10% 35V
8.
C5521 2113740A39 27pF 5% 50V C5611 2113741F49 10nF 50V
16
C5522 2113740A44 43pF 5% 50V C5612 2113741F49 10nF 50V
C5532 2113740F51 100pF 5% 50V C5618 2311049A01 TANT CP 100nF 10% 35V
yr
t
L5600 2484657R01 Ferrite Bead R5617 0680194M01 10 1W 5%
ne
L5601 2484657R01 Ferrite Bead R5621 0662057A45 680 OHMS 5%
8.
L5611 2484657R01 Ferrite Bead R5623 0662057C19 4R7 1/10W 5%
16
Q5510 4813827A26 RF NPN MRF R5641 0680149M02 Thermistor Chip
100K @25C
Q5520 4813827D13 TSTR 870MHz PWR
MACRO-X
io
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Q5611 4813824A17 TSTR PNP 40V 0.2A
R5531 0680194M01 10 1W 5%
R5541 0680194M01 10 1W 5%
h
tt p
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w
w
.m
Not Used
y r
d a
i o
1 68 .
e n
t
t
C5702 2113741F13 330pF 50V R5705 0662057A89 47k 1/16W 5%
ne
C5703 2113743K15 100nF 16V R5708 0662057A01 10 1/16W 5%
8.
C5706 2113741F49 10nF 50V R5711 0662057A15 39 1/16W 5%
16
C5707 2113741F49 10nF 50V R5712 0662057A59 2k7 1/16W 5%
C5721 2113741F49 10nF 50V Y5702 4809863M01 REF OSC 16.8 MHZ
TEMPUS
tp
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16
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1 68 .
e n
t
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C5733 2113741F49 10nF 50V C5785 2113741F49 10nF 50V
ne
C5734 2113740F11 2.2pF 5% 50V C5786 2113740F18 4.3pF 5%
8.
C5742 2113740F41 39pF 5% 50V C5791 2113740F51 100pF 5% 50V
16
C5743 2113740F39 33pF 5% 50V C5792 2113741F25 1nF 50V
SOT23
C5749 2113741F25 1nF 50V
D5741 4805649Q13 DIODE VCTR 1SV228
.m
SOT23
C5752 2113740F17 3.9pF 5% 50V
D5743 4813825A05 DIODE CHIP SCHOTTKY
w
TKY SOT23
C5756 2113740F25 8.2pF 5% 50V
E5731 2605915V01 SHLD PCB MOUNT 1
://
t
R5801 0662057A09 22 1/16W 5%
ne
R5733 0662057A89 47k 1/16W 5%
T5751 2505515V03 XFMR JEDI MIXER SMD
R5741 0662057A25 100 1/16W 5% 4:1
8.
R5742 0662057A97 100k 1/16W U5801 5105469E65 IC VLTG REGLTR
LP2951C
16
R5743 0662057A13 33 1/16W 5%
9V3_2 R5302
9V3
330 TP5301 L5401 RX_IF_2
RX_IF
C5331 C5310 C5311 470nH
330pF C5307 330pF .0033uF TP5302
9V3_2_3 .0033uF
R5311 R5401
9V3
4.7K
NU 51
R5317
Q5302 L5302 150
NU 470nH L5402 C5404
150nH 82pF
h
R5312 R5318
C5302 C5303 150 R5308 C5313 C5314
L5406 L5408 4.7K R5306 L5407 L5409
C5309 270
NU R5313 270
C5322 10K
1.8pF 33pF 1.8pF 12pF
tt p
.01uF
PA_RX_2 NU NU 100pF
3 3 R5310 D5401
PA_RX D5301 D5302 R5307 C5312 D5304 D5305 10 T5402
R5305 3 T5401
3
3
5
:/
C5301 3 D5303 10K 68 1
4
.001uF
2.2pF C5308 R5316 2
C5326 C5327 C5318
2
.001uF R5303 R5319 C5325 C5328 C5329 470
1.8pF 1.8pF 10pF
/
2.7K 3.9pF 1.8pF 1.8pF NU
4 3
5
R5314
1
w
33
1 2 Q5301 270
R5304
w
3.9K L5403 L5404
C5323 C5300 R5301 C5304 C5305 C5306 C5324 C5321 R5309 C5315 C5316 C5317
36pF 43pF 100K 43pF 43pF 36pF 36pF 36pF 100K 36pF 36pF 36pF 27nH 15nH
w
FE_CNTL_VLTG C5401 C5402 C5403
6.2pF 16pF 16pF
FE_CNTL_VLTG_2
.m
C5319 C5320
.001uF .001uF R5315
10
y
VCO_MIXER_2
VCO_MIXER
ra
5V_STAB_2_IN 5V_STAB_2_OUT
d
5V_STAB 5V_STA
IF_4
i o
1 68 . n
NU NU
t
t
C5302 2113740F09 1.8pF 5% 50V C5402 2113740F32 16pF 5% 50V
ne
C5303 2113740F39 33pF 5% 50V C5403 2113740F32 16pF 5% 50V
8.
C5305 2113740F42 43pF 5% 50V D5301 4862824C01 VARACTOR CHIP
16
C5306 2113740F40 36pF 5% 50V D5302 4862824C01 VARACTOR CHIP
C5314 2113740F29 12pF 5% 50V L5403 2462587N46 IND CHIP LO-PRO 27.0 N
w
C5315 2113740F40 36pF 5% 50V L5404 2462587N43 IND CHIP LO-PRO 15.0 N
Circuit Motorola
Description
Ref Part No.
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8.
16
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1 68 .
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t
t
C5202 2113740F31 15pF 5% 50V C5239 2113740F44 51pF 5% 50V
ne
C5203 2113743A19 100nF 16V X7R D5201 4880154K03 Dual Schottky SOT23
C5204 2113743A19 100nF 16V X7R FL5201 9180098D04 Filter CER 4-EL 455kHz
8.
(12.5kHz)
C5205 2113740F33 18pF 5% 50V 9180098D06 Filter CER 3WR
16
(20/25kHz)
C5208 2113743A19 100nF 16V
FL5202 9180097D04 Filter CER 6-EL 455kHz
C5211 2113740F31 15pF 5% 50V
C5231 2311049A07 TANT CP 1uF 10% 16V R5221 0662057B02 150k 1/16W (12.5kHz)
0662057B05 200k 1/16W 5%
C5232 2113740F51 100pF 5% 50V (20/25kHz)
Circuit Motorola
Description
Ref Part No.
U5201 5180207R01 IF IC
t
12.5KHz 60dB
ne
9102652Y02 XTAL FLTR 45.1MHZ
20/25KHz 80dB
8.
Y5211 4802653Y01 XTAL OSC 44.645MHZ
16
io
ad
yr
.m
w
w
w
://
tp
ht
R0105
R0138
R0137
C0104 J0101
R0115
C0103
L0114 Y0114 E3701
C0105 R3703
1 C3726 R3724
C0116 C0117 6 12 18
Q0137
C3801
C3707
C0115 C0137
C0125
C0126
R0127
C0127
Q0114 40 21 C0110 R3723 4
R0125
R0102 C3727 C5226
C0114 41 8 7 R0104 5
20 8 5
R0114
C0118 R0116 R0126 R0103 C3702 R3702
R3705 Y3702 C3802 R5221
Q0138 C0194
D0101 U3801 FL5202
U0104
R0119
R0113 D3702 C5235
C0102 R3701 C3713 1 4
C3709
U0101 9
R0134
C0134
R0110 16
C3724 C3701 1
R0106
C3706
R0107 14 1 U0102 C3803
R0109
R0167 R0108 R3709 R3801
R0131
C0101
R0130 1 8 C5214
60 1 C0181
h
R5212 C5213 FL5201
C0163
61 R0101 E3731 C3704
C0162
80
R0163
Q0161 16 9
C5212
R0192
R0128
R0120
R0123 C0121
R0122 C0122
R0121 R0124
C3735
t
1
D3733
R0187
R0162
L3733
U0107 4
t
C0634 D3731 C3731 C3333 5
R0164 C0161 Y5201 Y5202
C0622
R0166 L3732 C3733 R5211
p
C0171
C0164 R0161 8 L5201
R0185 1 2
R0165
C3766
R3769
L5211
R0172
R0191
R0183 C0131 L3731 T3302
C3734
4 1 C0635 L3734 D3732 R3731
R0184
R0186
R0171
L3334
4 1 Y5211
C0184
:
R0616 1 2 3 1 2 3
C3736 C3738
C3737 C3739
C0182
7 1 1 3 1
C0132 C0633 U0631 R3767 2
R3766 C3765
U0108 C0632 Q3742 C5211
R0188 R0605 R3739 R3765 C3332 8 5
C3317
C3316
C3315
// w
U0105 C0641 5 8 C3320
R0604
R3743
R3752
C0191
5 8 L3741 Q3752
L3333
R3763 C3307 C3319
C3306
C3305
C3304
C0621
Q0601
8 14 C3763 D3331 R3301
D0621 R0601 R3741 C3740 L3331 R3309
D3739 U3741 R3302 C3310
Q0731
D0731
R0719
C3745 C3744
L3761
C0155 C0141
L3750
R3315 R3314
R3308
4
VR0621
R3306
w
R0155 5 4 3 2 1 R3742 C33311 R3331 C3311
L3302 R3305
R0154 C0172 R0143 C0142 9 8 L3754
L3751
R3761
Q0741 2 1 D3304 D3301
Q3301
R0135 R0621 C3764 3
C3752
L3332
C3757
R3753
R3307
C0154 R0145 R0146 R0142 D3752 D3751 C3754 E3301
C3761
R0741
R0136
C3309
R0144 R0141 C3314 C3302
C0742
R0721
w Q3751 D3754
R0742 Q3760 T3301 C3334
7 1 R3303
U0731 C3762
C3312
3 2 1
C3318
R0156 R3313 C3308 C3301
C0133 C0701 L3752 R3754 R3762 4 5 C3313
R3321 C3321
C3755
U0106 Q0742 C0721 C3756 C3758
R0153
.m
C0156 R3304 D3303
16 1 R3751
8 14 U0601
C0732
C0713
C0731
R0732
R0715
R0733
D0732
C0151 R0731
R0189 R0152
C0185 R0151
y
R0404
R0405
Q0401
L0401
L0402
C3641
R3642
R3641
C0403
r
C0404 R0407 R0401 C3652
a
L3501
C3651
R0406
d
R3503
R3649
C0402 Q3641 R3502 C3632
C3643
R3647
C3502
C3501
1 5 C3623 D3651 C3653
9 R3643 C3622
i
R3644
C3527 C3654
C3642 8 5
o
C3534
R3525
R3645 Q3511
U0401 R3646
1 6
1 4
L3511
C3512
C3513
R3615
L3533
C3551 C3552
C3553
Q3642 C3511
R3648 L3641 L3552
C3644 C3520 R3526 C3533 C3555 L3551
8
C3645 R3511
C3554
C3646
R3513 C3514 L3532
.
C3602
n
SH3501
C3521
R0426
VR0445 C0445
R0427
R0431
Q0431
2
C0455 VR0420 J3501
VR0411 C3523 C3530
VR0431
C0464
C0405
R0454
C3525
C3524
VR0464 C0422 R0446
R0422 C0412C0446 C0431 C0406 J3601
15 13 11 9 7 5 3 1
16 14 12 10 8 6 4 2
J0400
R0157
C0119
C0197
R5225
C5238
VR0118
R0118
R5223 C5230 C5229 R0117
C5232
C5220
R5224
C5234
R5216 C0109
C3718
R5222 E3702 C0111
VR3701
C5237 C5233 32 25 R0112
C0152
C5231
R0182
R0181
C0150
L0195
30 23 1 24 R0111 J0103
C0176 R0173
C5227
L0194
C3705
C0112 C0153
U3701 25 16 C0175
C3720
R0175
C5224
R0139
C0199 26 15
C5239 Y3701
8 17
C3721
C0198
C0173
C3717
C5236
R3711
9 16 C0157 C0196 C0147 R0148
36 17 U0103
U5201
C5225
1 C3715 C3708 R0149
R3710
C3711
R0147
C0146
C3716 C3710
E3703 D3701 C0145
h
C3703 R3704
C0148
6
C3712
5 12 R3708 35
C5221
C3719 C0149 36 40
1 5 R0150
C5222
C5223
tt p
C0170
C0174 L0170
R5203
R5202
C5228
R3712
C5207 R5204 C5204 Q5201 C3723 L3742
R3713
:/
R5205 R3718 R3717 R0614
C5208 R3716 R0615
R3740 D0611
L5203
C3722 C3743 C0611
C5206
C5205
R3714 R3715 C3725
C5203
C0612
/
D5201 R5201
C5200
R0617
R0612
R0613
w
C5201 Q0612
C3773
R3772
C3772
R5207 C0631
L5202 C5202
C3792
C3790
Q3790
R3793
C3791 R0632
R0611
Q0611
D0631
R3768
w
Q3770 L3768 C0613
R3771 R3791R3792 R0631
R3794C3793 R0602
L3783 C3784 R0603 R0722
L3773
C0703
R0642 R0641 R0725
C3767
L3781
R0606
w
E3732
C3781R3795
R0703
R0724
C0722
R0723
R3774
C3771
C0601 C0605
C3786C3785
R3778
Q3302 C3751R3781 R0702 C0702
C3774 VR0641
C3783 C0602
R3316
R3785
1
.m
C3775 C3780 7 D0721
R3311
R3317 R3782
C3300 Q3780 R3786 R0734 C0723
R0704
C3322 C3782 U0701 R0711
C3303 C0741 C0712
R3775
R3776
R3777
C3777
R3779
R3312 R3318 C0603 C0604
R0701
Q0711
8 14R0714
y
R3300
R0735
C0711
D3300
C0733
R0717
R0716
C0716
C0714 R0713 C0439
r
R0712 R0718
R0439 C0435
a
J0102 R0435
R0438
R0436 Q0432
d
R0100 C0438
R0471 C0461
Q0433
i
R3651
R0461
D0471
C0471
R0437
o
Q0461
R0476
C3655 C3658 R3631 C3631
C3634 R0462
R3657
1 R0472
R0465 R0413
Q0471
R3658 R0473
Q0462 R0463 C0413
Q0412
D3657 C3633 C0462
6
R0474
R0477
C0463
R0464
R0475 R0415
R3614 C3614
R0442 R0412R0414 C0414
8
R0411
C3657 3 2 1 Q0411
Q0441
C0441
.
C0411
C3611
Q0442
n
C3601
R3611
C3605 C3603 R0443 R0441
C3604
e
L3522
Q3531
t
L3601
L3521
Q3521 VR0450
R3551
C0450
VR0435
R0450
VR0421 VR0471 R0455
VR0441 VR0444 R0456
D3601 R0451 C0454VR0419
R3616
C0421 C0442 C0444
C0451 C0436
R0444 C0472
1 15
2 16
U0107-3
J0102 MIC_PTT MC14053B
+5V 9V3 9V3 +5V
R0116 R0117 R0118 INHIBIT
6 XX 12
1 +5V 0
XX U0104-4 11
2 SPI_MISO 270 270 4.7K 14 4 4 16 XX 1 XX 13 74AC08
3 J0102_3 (GP6)
C0118 C0119 VCC VCC VCC VDD
4 SPI_MOSI VR0118
R0119 470pF 470pF U0104-5 C0134 U0105-5 C0132 U0106-5 C0133 U0107-4 C0131
5 OPTION_BD_CE 1K ADAPT_5 5.1V
PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF
6 SPI_CLCK_SRC ADAPT
GND GND GND VEE VSS
7 J0102_7 (GP4)
7 11 11 7 8
8 +5V
C0102
470pF
(GP4-IN) PA2 +5V +5V 9V3 9V3
(GP2-OUT) PC0
(GP1-IN) PC1 L0114 C0116 Y0114 +5V +5V
(GP3-IN) PC2 R0113 33uH 3.6pF INSTPAR +2V5 +5V
C0164
(GP6-IN) PC3 10K R0164
Q0114 R0167 .0047uF 1MEG
(GP5-IN) PC5 R0114 X
R0115 47K NU L0194
(GP5_OUT) PB4 4.7K L0170 270nH SPI_CLK_5
1.8MEG R0161
(GP3_OUT) PB5 SPI_CLCK_SRC SPI_CLK
100K 33000nH
(GP6_OUT) PB7 R0110 R0162 L0195 SPI_DATA_5
TP0106 TP0107 C0161 C0162
10K 10K SPI_MOSI SPI_DATA
C0114 5 270nH
+5V Q0161 R0165 UNATTEN_RX_OUT FRACN_CE_5
h
33pF 7 U0105-2
Y R0163 0.1uF FRACN_CE FRACN_CE
MC3403 0.1uF
47K HIGH_LOW_BAND_5
6 C0170
R0102 +5V 100K HIGH_LOW_BAND
R0106 C0115 C0117 R0166 R0173 SQ_ATT_IN_5
USW_+5V_CL 33pF
2.2K 22pF 10K C0173 C0163 SQ_ATT_IN
tt p
4.7K C0104 0.1uF 1uF
RESET .01uF 0 NU SQ_ATT_OUT_5
K9V1_ENABLE_5 C0103 SQ_ATT_OUT
R0105 1uF C0176 C0174
K9V1_ENABLE 3.3uF MOD_IN_5
10K
SPI_MOSI MOD_IN
TP0109
:/
C0101 R0101 SPI_CLCK_SRC 3.3uF 0.1uF
+5V
0.1uF 10K RESET C0194 C0199
470pF 470pF
43
12
42
41
40
39
38
37
36
34
25
27
30
29
/
16 C0105
+5V
VDDH2 38
RESET 34
31
30
29
12
14
15
21
17
MODB
MODA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB0
55 0.1uF TP0108
R_W*
RESET
WDT_DISABLE 4
1
VDD
CLK_E
w
VDD
11
TIMING_CAP
1
VDDH1
4_BIT_ATTEN_IN
5_BIT_ATTEN_IN
EXT_ALERT_TONE_IN
VRH 22 C0175 R0175
SERIAL_CLOCK_IN
VDDL
SERIAL_DATA_IN
TX_OUT
A0 PB1 C0196 C0197 C0198
15 2 10 .001uF 150K
Y0 A1 PB2 VRL 21 470pF 470pF 470pF
14 3 9 37
EEPROM_CE Y1 U0102 A2 PB3 R0108 NC
13 8 R0109
GCB5 3
MC74HC138A
w
12 7 33
DAC_CE Y3 +5V PB5 XTL 100 0 C0185
11 6 31 16 NU 100pF
FRACN_CE Y4 PB6 EXTAL SQ_ATTEN_IN
10 6 5 18
OPTION_BD_CE Y5 CS1 PB7 IRQ 46 SQ_ATTEN_OUT
9 Y6 CS2 4 R0120 XIRQ 45
LED_CE R0181 U0107-2
7 23 28 33 19 30K R0189
CS3 5 10K
w
LCD_CE Y7 VSS STRA AFIC_CE CHIP_SELECT 4_BIT_ATTEN_OUT MC14053B
49
VSS
U0101 B+_CONTROL INHIBIT C0184
GND TP0105 24
VSS
27
PL_DPL_DECODER_OUT 5_BIT_ATTEN_OUT
20 10K R0182 2 6 1uF 82K
8 MC68HC711E20 1 0 15 9
R0100 PA0
0 64 32 PL_CLOCK_STROBE R0183 1 1 8
47 PD0 PA1 10K 10 U0106-4
NU
.m
50 63 10 MC3403
PD1 PA2 R0121
51 62 UNATTEN_RX_OUT 22 FLT_RX_AUDIO
FLT_A+ TP0104 PD2 PA3 +2V5 R0130 R0185 NU R0187
52 59 0 NU 7 C0181
+5V
D0101 53
PD3 PA4
58 160K 13 AUX_TX_IN U0103 RX_IN
8 0.1uF
J0101 PD4 PA5 PL_DPL_IN 30K 0
R0104 54 57 R0122 AFIC 40 NU
3 PD5 PA6 U0107-1 GCB3 R0186
33K 56 12 39 36 R0184
FLT_A+ 17 PA7 MC14053B XTAL_OUT
NC10
14 12 6 2
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
U0105-3
y
C0121
NC
20
18
16
14
19
17
15
13
11 0.1uF
4
3
2
9 PRE_EMPHASIS_OUT
100K R0124 RX_OUT
R0103 C0125 NU .039uF
PBIAS_RESISTOR
r
AUX_RX_IN
10K 2 1 0.1uF
SPI_MISO R0125 6.8K R0131 VAG_BYPASS 28 AUDIO_PA_ENABLE
VAG_VOLUME
C0126 C0122
a
SPI_MOSI
0.1uF 200K 0 26
DPL_CAP
BUS+ 15 BUS+ SPI_CLCK_SRC GND RX_AUDIO
35 XTAL_IN
25 PL_CAP
ANALOG_1 10 NU
R0126 .01uF
TX_IN
DET_AUDIO_5
d
ANALOG_2 11 +5V C0153
R0139 0.1uF TP0111
ANALOG_3 13 DET_AUDIO
1 200K 240K
LED_CE 12 LED_CE +5V
10
11
24
3 U0104-1
5
SPI_DATA_BUF 6
74AC08 2 C0157
LED_CLCK_BUF 5 C0127 R0127 R0136 +2V5 470pF
R0157
o
LCD_CLCK_BUF 8 0.1uF 200K
6 U0104-2
4 33K R0148
470K
R0150
51K
C0152
1uF C0150 * note 1
R0137 .47uF
GND 7 R0134 R0138 R0147
74AC08 5 47K
19
20
8 U0104-3
9
10K 4.7K
Q0137
1 6
FLAT_TX_AUDIO
R0135
47K
2
U0106-1
3 MC3403
1
180K
C0147 C0148 5
MIC C0146 470pF RX_AUDIO-SEND J0103-5
74AC08 10 56pF GP3 7
47K C0137 J0103-7 J0103_7 GP3
HOOK 3 .01uF NU GP5 J0103-8 8 J0103_8
+2V5 .001uF GP5
6
8
MIC_PTT 4 MIC_PTT NU GROUND J0103-6
47K
MIC 16 Q0138
HANDSET_AUDIO 14 R0149
0
.
6 1 U0105-1 1
SPI_CLCK_SRC_5 J0103-1 TX_AUDIO_RET
MC3403 VAG
U0106-2 7 3 C0149 3 WP 5 3
SPI_CLCK_SRC SPI_CLCK_SRC 1K 47K J0103-3 TX_AUDIO_SEND 33pF SI SPI_MOSI
.100uF 5 MC3403 2
PA_ENABLE_5 R0128 AUX_RX_IN J0103-2 RX_AUDIO_RET
C0141 4 1 2
PA_DISABLE +5V UNATTEN_RX_OUT J0103-4 UNATTEN_RX_OUT CS SO
10uF R0192 R0172 C0171 C0172
VLTG_LIMIT_5 10K VAG 1uF
VSS 0 47.5K 10uF
VLTG_LIMIT NU
C0156 C0155 EEPROM_CE 4
47uF
BATTERY_VOLTAGE NU 33pF SPI_MISO
+5V +5V
+5V +5V
PC5
Q0461
(GP5) PC2 (GP3) Q0431 47K
Q0412
47K VR0431
C0461 47K C0413 47K C0431 14V
.01uF .01uF 470pF
47K C0464 47K
R0463 VR0464
470pF
270 14V R0414 C0412 VR0411
270 470pF
14V
Q0462 Q0411
R0464 R0411 +5V FLT_A+
PB4 PB5
10K
h
10K
R0465
0
C0463
.01uF R0415
C0411
.01uF D0471
(GP2) R0442
4.7K
R0443
4.7K
NU 0 NU NU
NU XX
tt p
EMERGENCY_CONTROL
XX Q0441
XX R0441 NU
J0103_8 J0103_7 10K C0442
PC0 470pF
C0462 VR0441
:/
C0414 Q0442
470pF 470pF +5V XX 33V
C0441
FLT_A+ .01uF
XX
(GP4)
/ w
+5V R0474 R0475 XX
47K 4.7K R0477
R0472
0 10K
NU
w
PA2
R0437 R0444
R0436
4.7K Q0471 BUS+
47K
47K 270
(GP6) R0471 R0473
C0444
w
0 68K 47K VR0444
PC3 NU NU 470pF
Q0432 5.1V
R0476 VR0471
270 33V
C0435 47K C0472
.m
.01uF 470pF
47K J0102_7
R0435
270 C0471
C0436 VR0435
470pF 470pF J0400
Q0433 14V
(IN)
y
R0438 3 GP1
PB7 4 GP2 (OUT)
10K 6 BUS+
r
8 GP3 (IN/OUT)
R0439 12 GP5 (IN/OUT)
a
0 C0438 14 GP6 (IN/OUT)
0
NU .01uF 15 RSSI
16 EXT_SPKR+
d
1 EXT_SPKR-
J0102_3 MIC 2 EXTERNAL_MIC_AUDIO
10 IGNITION
i
C0445
C0439
9 GP4 (IN)
C0421 VR0421 FLAT_TX_AUDIO 5 FLAT_TX_AUDIO
o
470pF 470pF 14V
FLT_A+ 11 FLT_RX_AUDIO
.47uF 13 ANALOG_GND/SW_B+
VR0445 R0446 C0446
14V 7 GROUND
1 6
100K 470pF
C0454
470pF
C0407
C0401 R0450
8
.1uF C0450
R0401 .100uF 560
+5V SW_B+
RX_AUDIO FLT_RX_AUDIO
4.7K C0402
.
22K PE3
9
INV L0401 R0454 R0456
1 4 C0405 VR0419
3
NINV OUT1
.001uF 14V
(IGNITION_SENSE) 1K 0
t
INT_SPKR+
GEPD5462 -1
FLT_A+ FLT_A+
+5V +5V
C0102 2113741F17 470pF 50V C0150 2311049A05 TANT CP 470nF 10% 25V
t
C0103 2311049A42 TANT CP 3.3uF 10% 6V C0151 2113741F17 470pF 50V
ne
C0104 2113741F49 10nF 50V C0152 2311049A07 TANT CP 1uF 10% 16V
8.
C0109 2113741F17 470pF 50V C0154 2113743K15 100nF 16V
16
C0110 2113741F17 470pF 50V C0155 2113740F39 33pF 5% 50V
C0117 2113740A41 33pF 5% 50V C0170 2311049A07 TANT CP 1uF 10% 16V
C0119 2113741F17 470pF 50V C0172 2311049A07 TANT CP 1uF 10% 16V
w
C0121 2113743K05 39nF 16V C0173 2311049A07 TANT CP 1uF 10% 16V
C0132 2113743K15 100nF 16V C0184 2311049A07 TANT CP 1uF 10% 16V
C0141 2311049J26 TANT CP 10uF 20% 16V C0196 2113741F17 470pF 50V
t
C0411 2113741F49 10nF 50V
ne
L0114 2460578C43 INDUCTOR CHIP 33.0UH
C0412 2113741F17 470pF 50V
L0170 2462587K26 CHIP IND 33000 NH
8.
C0413 2113741F49 10nF 50V
L0194 2462587Q40 COIL CHIP 270nH
C0414 2113741F17 470pF 50V
16
L0195 2462587Q40 COIL CHIP 270nH
C0419 2113741F25 1nF 50V
L0401 2484657R01 Ferrite Bead
C0420
C0421
2113741F25
2113741F17
1nF 50V
470pF 50V
L0402
io
2484657R01 Ferrite Bead
ad
Q0114 4880214G02 TSTR NPN 40V .2A
C0422 2113741F17 470pF 50V
Q0137 4880048M01 TSTR NPN DIG 47k/47k
C0431 2113741F17 470pF 50V
yr
t
R0112 0662057A93 68k 1/16W 5% R0152 0662057A73 10k 1/16W 5%
ne
R0113 0662057A73 10k 1/16W 5% R0154 0662057A73 10k 1/16W 5%
8.
R0114 0662057A65 4k7 1/16W 5% R0155 0662057A93 68k 1/16W 5%
16
R0116 0662057C61 270 1/16W 5% R0157 0662057A77 15k 1/16W 5% (12.5kHz)
0662057A84 30k 1/16W 5% (20/25kHz)
R0117
R0118
0662057C61
0662057A65
270 1/16W 5%
4k7 1/16W 5% io
R0161 0662057A97 100k 1/16W
ad
R0162 0662057A73 10k 1/16W 5%
R0119 0662057A49 1k 1/16W 5%
R0163 0662057A97 100k 1/16W
R0120 0662057A73 10k 1/16W 5%
yr
t
R0425 0662057A73 10k 1/16W 5%
ne
2-CHNL
R0426 0662057A89 47k 1/16W 5% U0108 5105462G78 IC EEPROM !&K SPEI
CMOS
8.
R0427 0662057B47 0 1/16W
U0401 5109699X01 AUDIO PA TDA1915C
R0431 0662057A89 47k 1/16W 5%
16
VR0118 4880140L06 DIODE 5.1V 5% 225mW
R0432 0662057A65 4k7 1/16W 5%
VR0411 4813830A27 DIODE 14V 5% 225mW
R0435
R0436
0662057C61
0662057A89
270 1/16W 5%
47k 1/16W 5%
VR0421
io
4813830A27 DIODE 14V 5% 225mW
ad
VR0422 4880140L06 DIODE 5.1V 5% 225mW
R0437 0662057A65 4k7 1/16W 5%
VR0431 4813830A27 DIODE 14V 5% 225mW
R0438 0662057A73 10k 1/16W 5%
yr
U0107-3
J0102 MIC_PTT MC14053B
+5V 9V3 9V3 +5V
R0116 R0117 R0118 INHIBIT
6 XX 12
1 +5V NU 0
XX U0104-4 11
2 SPI_MISO 270 270 4.7K 14 4 4 NU 16 NU XX 1 XX 13 74AC08
3 J0102_3 (GP6)
C0118 C0119 VCC VCC VCC VDD
4 SPI_MOSI VR0118
R0119 470pF 470pF U0104-5 C0134 U0105-5 C0132 U0106-5 C0133 U0107-4 C0131
5 OPTION_BD_CE 1K ADAPT_5 5.1V
PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF PWR_GND 0.1uF
6 SPI_CLCK_SRC ADAPT
GND GND GND VEE VSS
7 J0102_7 (GP4)
7 11 11 7 8
8 +5V
C0102
470pF
(GP4-IN) PA2 +5V +5V 9V3 9V3
(GP2-OUT) PC0
(GP1-IN) PC1 L0114 C0116 Y0114 +5V +5V
(GP3-IN) PC2 R0113 33uH 3.6pF INSTPAR +2V5 +5V
C0164 R0164
(GP6-IN) PC3 10K .0047uF
Q0114 R0167 1MEG
(GP5-IN) PC5 R0114 X
R0115 47K NU L0194
(GP5_OUT) PB4 4.7K L0170 270nH SPI_CLK_5
1.8MEG R0161
(GP3_OUT) PB5 SPI_CLCK_SRC SPI_CLK
100K 33000nH
(GP6_OUT) PB7 R0110 R0162 L0195 SPI_DATA_5
TP0106 TP0107 C0161 C0162
10K 10K SPI_MOSI SPI_DATA
C0114 5 270nH
+5V Q0161 R0165 UNATTEN_RX_OUT FRACN_CE_5
h
33pF 7 U0105-2
Y R0163 0.1uF FRACN_CE FRACN_CE
MC3403 0.1uF
47K HIGH_LOW_BAND_5
6 C0170
R0102 +5V 100K R0173 HIGH_LOW_BAND
R0106 C0115 C0117 R0166 SQ_ATT_IN_5
USW_+5V_CL NU
2.2K 22pF 33pF 10K C0173 C0163 SQ_ATT_IN
tt p
4.7K C0104 0.1uF 1uF
RESET .01uF 0 SQ_ATT_OUT_5
K9V1_ENABLE_5 C0103 C0176 SQ_ATT_OUT
R0105 1uF NU C0174
K9V1_ENABLE 3.3uF MOD_IN_5
10K
SPI_MOSI MOD_IN
TP0109
:/
C0101 R0101 SPI_CLCK_SRC 3.3uF 0.1uF
+5V
0.1uF 10K RESET C0194 C0199
470pF 470pF
43
/
12
42
41
40
39
38
37
36
34
25
27
30
29
16 C0105
+5V
38
RESET 34
31
30
29
12
14
15
21
17
MODB
MODA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB0 55 0.1uF TP0108
R_W*
RESET
WDT_DISABLE 4
1
VDD
w
CLK_E
VDD
11
TIMING_CAP
1
VDDH1
VDDH2
4_BIT_ATTEN_IN
5_BIT_ATTEN_IN
EXT_ALERT_TONE_IN
VRH 22 R0175
SERIAL_CLOCK_IN
VDDL
SERIAL_DATA_IN
TX_OUT
A0 PB1 C0175 C0196 C0197 C0198
15 2 10 150K
Y0 A1 PB2 VRL 21 .001uF 470pF 470pF 470pF
14 3 9 37
EEPROM_CE Y1 U0102 A2 PB3 R0108 NC
13 8 R0109
GCB5 3
MC74HC138A
w
12 7 33 47K 47K R0188
DAC_CE Y3 +5V PB5 XTL 100 0 C0185
11 6 31 16 NU 100pF
FRACN_CE Y4 PB6 EXTAL SQ_ATTEN_IN
10 6 5 18 NU
OPTION_BD_CE Y5 CS1 PB7 IRQ 46 SQ_ATTEN_OUT
9 Y6 CS2 4 R0120 XIRQ 45
LED_CE R0181 U0107-2
w
7 23 28 33 19 30K R0189
LCD_CE Y7 CS3 5 10K VSS STRA AFIC_CE CHIP_SELECT 4_BIT_ATTEN_OUT MC14053B
49
VSS
U0101 B+_CONTROL INHIBIT
GND TP0105 24
VSS
27
PL_DPL_DECODER_OUT 5_BIT_ATTEN_OUT
20 10K R0182 2 6 C0184 82K NU
8 MC68HC711E20 1 0 15 NU 9
R0100 PA0
0 64 32 PL_CLOCK_STROBE R0183 NU 1 1 8
47 10K 10 U0106-4
.m
NU PD0 PA1
50 63 1uF 10 MC3403
PD1 PA2 R0121
51 62 UNATTEN_RX_OUT 22 NU FLT_RX_AUDIO
FLT_A+ TP0104 PD2 PA3 +2V5 R0130 R0185 NU R0187
52 59 0 NU 7 C0181
+5V
D0101 53
PD3 PA4
58 160K 13 AUX_TX_IN U0103 RX_IN
8 0.1uF
J0101 PD4 PA5 PL_DPL_IN 30K 0
R0104 54 57 R0122 AFIC 40 NU
3 PD5 PA6 U0107-1 NU GCB3
33K 56 12 39 36 R0184 R0186
FLT_A+ 17 PA7 MC14053B XTAL_OUT
NC10
GCB1
y
220K 12 30K 27k
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC1
14 6 2
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
C0121 U0105-3
NC
20
18
16
14
19
17
15
13
13 11 0.1uF
4
3
2
9 PRE_EMPHASIS_OUT
100K R0124 RX_OUT
r
R0103 C0125 NU .039uF
PBIAS_RESISTOR
AUX_RX_IN
10K 2 1 0.1uF
SPI_MISO R0125 6.8K R0131 VAG_BYPASS 28 AUDIO_PA_ENABLE
VAG_VOLUME
SPI_MOSI C0126 C0122
0.1uF 200K 0 26
DPL_CAP
BUS+ 15 BUS+ SPI_CLCK_SRC GND RX_AUDIO
35 XTAL_IN
25 PL_CAP
NU
d
ANALOG_1 10 R0126 .01uF
TX_IN
ANALOG_2 11 C0153 DET_AUDIO_5
+5V R0139
ANALOG_3 13 0.1uF TP0111 DET_AUDIO
1 200K 240K
i
LED_CE 12 LED_CE +5V
10
11
24
3 U0104-1
5
SPI_DATA_BUF 6
74AC08 2 C0157
o
LED_CLCK_BUF 5 C0127 R0127 R0136 +2V5 470pF R0157
LCD_CLCK_BUF 8 0.1uF 200K
6 U0104-2
4 33K R0148
470K
R0150
51K
C0152
1uF C0150 * note 1
R0137 .47uF
GND 7
19
20
74AC08 5
9
R0134
10K
R0138
4.7K
Q0137
47K
1 6
FLAT_TX_AUDIO
R0135
NU 2
NU
U0106-1 1
R0147
180K
HANDSET_AUDIO 14 0
INT_SPKR+ 1 INT_SPKR+
n
47K +5V
INT_SPKR- 2 INT_SPKR- R0145 C0145
9V3 R0146
ON_OFF_CONTROL 18 ON_OFF_CONTROL 0 30K .001uF
47K U0108 9V3
LCD_CE
e
NU
DAC_CE_5 NU EEPROM_X25160 VAG_7
R0141 R0144 NU 8
DAC_CE DAC_CE 2_1MHZ_5 TP0110 C0191 VAG
100 R0191
0.1uF VCC R0171
t
+5V +5V
+5V +5V
PC5
Q0461
(GP5) PC2 (GP3) Q0431 47K
Q0412
NU NU
47K
C0461 47K C0413 47K C0431 VR0431
.01uF .01uF 470pF 14V
NU 47K C0464 47K
R0463 VR0464 NU
470pF R0414
270 14V C0412 VR0411
NU NU 270 470pF 14V
NU
NU NU NU
Q0462
NU Q0411
R0464 R0411 NU +5V FLT_A+
PB4 PB5
h
10K 10K
NU
R0465
C0463
.01uF R0415
NU
C0411
.01uF D0471
(GP2) R0442
4.7K
R0443
4.7K
0 NU 0 NU NU NU NU
XX
tt p
EMERGENCY_CONTROL R0441
XX Q0441
XX 10K VR0441
NU
J0103_8 J0103_7 NU C0442
470pF 33V
PC0
Q0442 NU
C0462 NU
:/
C0414
470pF +5V C0441 NU
470pF XX
NU FLT_A+ .01uF
NU
NU
XX
/
(GP4)
w
+5V R0474 XX
R0475
47K 4.7K R0477
R0472
NU 10K
0
w
NU
PA2
R0444
R0436 R0437
4.7K Q0471 BUS+
47K
NU 47K 270
(GP6) R0471 R0473 NU
w
0 68K 47K C0444 VR0444
PC3 Q0432 NU 470pF 5.1V
NU R0476 VR0471
270
33V
.m
C0435 47K NU C0472
.01uF 470pF NU
NU 47K J0102_7 NU
R0435 C0436 VR0435
270 470pF 14V C0471
NU NU
NU 470pF J0400
y
Q0433 NU
R0438 NU 3 GP1 (IN)
PB7 4 GP2 (OUT)
10K 6 BUS+
r
NU 8 GP3 (IN/OUT)
12 GP5
a
R0439 (IN/OUT)
0 C0438 14 GP6 (IN/OUT)
NU .01uF 15 RSSI
d
NU 16 EXT_SPKR+
1 EXT_SPKR-
J0102_3 MIC 2 EXTERNAL_MIC_AUDIO
i
10 IGNITION
C0445
9 GP4 (IN)
o
C0439 C0421 VR0421 .47uF NU
FLAT_TX_AUDIO 5 FLAT_TX_AUDIO
470pF 470pF 14V
FLT_A+ 11 FLT_RX_AUDIO
NU
13 ANALOG_GND/SW_B+
1 6 VR0445
14V
NU
R0446
100K
C0446
470pF
7 GROUND
C0454
470pF
8
C0407
C0401 .1uF
R0401 .100uF C0450 R0450 NU
+5V NU SW_B+
RX_AUDIO FLT_RX_AUDIO
.
C0419 47uF
R0402 .0033uF R0426 R0451 C0451 0
.001uF
1K SW_B+ U0401 47K 100K 470pF
7 TDA1519C R0427 VR0450
e
+5V 0 14V
VCC PE3
R0406 9 NU
22K INV L0401 R0456
t
GEPD5448 -1
FLT_A+ FLT_A+
C0101 2113743K15 100nF 16V C0150 2311049A05 TANT CP 470nF 10% 25V
t
C0103 2311049A42 TANT CP 3.3uF 10% 6V C0152 2311049A07 TANT CP 1uF 10% 16V
ne
C0104 2113741F49 10nF 50V C0153 2113743K15 100nF 16V
8.
C0109 2113741F17 470pF 50V C0155 2113740F39 33pF 5% 50V
16
C0110 2113741F17 470pF 50V C0157 2113741F17 470pF 50V
C0116 2113740G16 CERAMIC CHIP 3.6 P C0170 2311049A07 TANT CP 1uF 10% 16V
.m
C0118 2113741F17 470pF 50V C0172 2311049A07 TANT CP 1uF 10% 16V
w
C0119 2113741F17 470pF 50V C0173 2311049A07 TANT CP 1uF 10% 16V
w
C0131 2113743K15 100nF 16V (not used) C0194 2113741F17 470pF 50V
ht
C0133 2113743K15 100nF 16V (not used) C0197 2113741F17 470pF 50V
C0141 2311049J26 TANT CP 10uF 20% 16V C0401 2113743A19 100nF 16V
C0148 2113741F17 470pF 50V C0404 2311049A99 TANT CP 47uF 20% 10V
C0407 2109720D14 CER LOW DIST 100nF R0107 0662057A25 100 1/16W 5%
t
C0431 2113741F17 470pF 50V R0112 0662057A93 68k 1/16W 5%
ne
C0444 2113741F17 470pF 50V R0113 0662057A73 10k 1/16W 5%
8.
C0454 2113741F17 470pF 50V R0114 0662057A65 4k7 1/16W 5%
16
D0101 4813833C02 DUAL SOT MMBD6100 R0116 0662057C61 270 1/16W 5%
J0101
J0102
0902636Y01
0904424J06
Connector Flex Side Entry
R0118 io
0662057C61
0662057A65
270 1/16W 5%
4k7 1/16W 5%
ad
J0103 0904424J06 Connector double row 8pin R0119 0662057A49 1k 1/16W 5%
L0194 2462587Q40 COIL CHIP 270nH R0123 0662057A97 100k 1/16W (not used)
w
t
R0156 0662057B47 0 1/16W R0444 0662057C61 270 1/16W 5%
ne
R0157 0662057A77 15k 1/16W 5% (12.5kHz) R0454 0662057A49 1k 1/16W 5%
0662057A84 30k 1/16W 5% (20/25kHz)
8.
R0461 0662057A89 47k 1/16W 5%
R0161 0662057A97 100k 1/16W
R0465 0662057B47 0 1/16W
16
R0162 0662057A73 10k 1/16W 5%
R0471 0662057B47 0 1/16W
R0163 0662057A97 100k 1/16W
R0474
0662057B47
0662057A89
0 1/16W
47k 1/16W 5%
ad
R0166 0662057A73 10k 1/16W 5%
U0101 5102898X67 PROC350 PLAT S/W
R0167 0662057A89 47k 1/16W 5% R010000 A2
yr
__3403_
R0183 0662057A73 10k 1/16W 5% (not used) U0401 5109699X01 AUDIO PA TDA1915C
w
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FLT_A+
USW_+5V
D0621
2
3
FLT_A+_8 R0621 USW_+5V_CL
1
FLT_A+
2.2K
h
tt p
9V3_SUPP
R0606 9V3
U0601
:/
0 0
4 LM2941T 5
LM2941T
/
2 1 R0602 R0631 D0631 U0631
7.5K
w
R0601 ON_OFF* ADJ C0604 10
1 LP2951CM
10K 33uF C0605
GND .1uF 3 8 1
C0601 C0602 C0603 INPUT OUTPUT +5V
470pF .1uF 10uF 3 2 7 5
w
FEEDBACK ERROR
3 2
R0632 SHUTDOWN SENSE
5V_TP 6 C0633 C0634 C0635
10 C0631 C0632
.1uF .022uF 47uF .1uF
33uF
w
R0603 GND
1.2K
4
.m
Q0601
R0604 R0605
y
1K 6.8K
RESET
ra
d
SW_B+
i
Q0611
R0611
1.2K
1 R0612
o
C0613 R0641
SW_B+
6
3.3K 3.3K
470pF
470pF
30K
R0613
8
3.3K
3.3K
BATTERY_VOLTAGE
R0617
.
3.3K 3.3K
n
ON_OFF_CONTROL
t
1 R0614 R0615
B+_CONTROL 10K1K 10K10K
3 Q0612
2
IGNITION_CONTROL
R0616 C0612
C0611
D0611 10K 0.1uF
47uF
GEPD5449-1
t
C0603 2380090M24 LYT 10uF 50V 20% R0614 0662057A73 10k 1/16W 5%
ne
C0604 2311049A97 33uF 20% 16V R0615 0662057A73 10k 1/16W 5%
8.
C0611 2311049A99 TANT CP 47uF 20% 10V R0617 0662057C87 3300 5 1/8
16
C0612 2113743K15 100nF 16V R0621 0662057A57 2k2 1/16W 5%
C0632 2311049A97 33uF 20% 16V U0601 5105625U25 9.3V REG 2941
.m
t
ne
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16
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1 68 .
e n
t
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C0703 2113743K15 100nF 16V Y5V R0716 0662057B16 560k 1/16W 5%
ne
C0711 2113741A59 CL2 X7R REEL R0717 0662057A85 33k 1/16W 5%
8.
C0713 2113740F51 100pF 5% 50V R0719 0662057A93 68k 1/16W 5%
16
C0714 2113743A19 100nF 16V R0721 0662057A69 6k8 1/16W 5%
h
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1 68 .
e n
t
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C3511 2113740F29 12pF 5% 50V C3621 2113741A57 33nF 50V
ne
C3512 2113740F37 27pF 5% 50V C3622 2113741A57 33nF 50V
8.
C3514 2113741F25 1nF 50V C3631 2113741A57 33nF 50V
16
C3520 2111078B32 39pF 5% C3632 2111078B59 470pF 5%
C3601 2380090M24 10uF 50V 20% D3651 4802482J02 DIODE PIN MA/COM
t
R3616 0680194M01 10 1W 5%
ne
L3532 2460591L29 Coil Air Wound Inductor
16.03 R3617 0680194M01 10 1W 5% (not used)
8.
L3533 2460591M77 Coil Air Wound Inductor R3631 0680194M01 10 1W 5%
38.13
R3641 0662057A49 1k 1/16W 5%
16
L3551 2460591W04 Coil Square
R3642 0662057A56 2k 1/16W 5%
L3552 2460591W04 Coil Square
R3644 io
0662057A49
0662057A37
1k 1/16W 5% (not used)
330 1/16W 5%
ad
L3621 2484657R01 Ferrite Bead (not used)
R3645 0662057C19 4R7 1/10W 5%
L3622 2484657R01 Inductor Bead Chip
R3646 0662057C19 4R7 1/10W 5%
yr
R3525 0680194M07 18 1W 5%
h
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1 68 .
e n
t
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C3703 2113743E20 0.1uF 10V R3702 0662057C61 270 1/16W 5%
ne
C3704 2113741F49 10nF 50V R3703 0662057A49 1k 1/16W 5%
8.
C3706 2113743E20 0.1uF 10V R3708 0662057B47 0 1/16W
16
C3707 2113741F49 10nF 50V (12.5kHz) R3709 0662057A01 10 1/16W 5%
2113743E07 22nF (20/25kHz)
R3711 0662057A25 100 1/16W 5%
C3708 2113740F59 220pF 5% 50V (12.5kHz)
(not used) io
R3712 0662057A59 2k7 1/16W 5%
ad
C3709 2113743E20 0.1uF 10% R3713 0662057A47 820 1/16W 5% (12.5kHz)
0662057A56 2k 1/16W 5% (25kHz)
C3710 2113740F43 47pF 5% 50V (20/25kHz)
yr
C3711 2311049A63 TANT CP 10uF 10% 10V R3715 0662057A41 470 1/16W
.m
C3719 2311049A19 TANT CP 10uF 10% 25V VR3701 4813830A23 10V 5% 20mA 350mW
tp
C3720 2113741F49 10nF 50V Y3701 4802081B71 Crystal Quartz 16.8 MHZ
TEMPUS (20/25kHz)
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L3742
F
1uH
9V3_1_4 9V3_4
C3733 R3731 C3734 9V3 9V3
C R3740
8.2pF 68 1.5pF
22
L3731 Ud
C3731
.001uF C3743 R3742 C3744
68nH K9V1_4
0.1uF 39 .001uF K9V1
D3731 5V_STAB
C3736 C3780
9V3
h
D3732 0.1uF C3781
56pF 33pF C3763 R3771
R3739 S 150
L3733 L3734 C3739 D3739 27K .01uF
1uH T45 10pF R3741 C3745 .01uF
R3778
tt p
68 470pF L3761 L3781 TP3732
L3732 68nH 2.7K 22nH
D L3783 C3785 R3785 EXCITER_PA_4
1uH C3764 C3767 R3768 L3768
.01uF 2.7K 120nH 120nH 10 EXCITER_PA
C3777 10pF
:/
D3733 L3773 C3775 R3776
C3735 C3740 5.6pF Q3780
470pF 12pF L3741 C3786
56nH 39 C3783 C3784 R3786
1uH C3765 C3766 470pF 470pF 10pF
R3766 39pF 10pF 150
/
C3761 R3779 NU
Q3770 NU
6.8pF C3773 R3775 R3777 1.5K
w
22 C3774
12pF 100pF 12pF 10pF 270 150 R3782
Ud R3761 100
R3769 C3782
1.5K R3765 R3767
1K 100pF
270 270
w
Q3760 C3772
R3743 Q3742 R3772
100pF 100
4.7K 2DTC143ZK
Q3752 R3762
R3752
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2.2K C3762
5.6pF
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L3750 43pF 27pF
1uH R3751 S
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L3752 C3755 D3754 27K .01uF
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T44 10pF R3753 C3757 R3791
D3751 100 470pF 270
L3751 1
1uH
D3752
6
C3751 C3756 C3791 R3792
.01uF 10pF L3754 2.7K
1uH Q3790
C3793 VCO_MIXER_4
8
.01uF R3795
C3790 VCO_MIXER
3.9pF 270 470
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R3793
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U3801
LP2951CM
R3801 5V_STAB_4
9V3 8 INPUT OUTPUT 1 5V_STAB (SOURCE)
7 FEEDBACK ERROR 5
22
SHUTDOWN SENSE 2
3 5V_TAP 6
C3801 C3802 C3803
.220uF GND .022uF 10uF
4
E3731 E3732
GEPD5440-1
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C3734 2113740F07 1.5pF 5% 50V C3777 2113741F17 470pF 50V
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C3735 2113741F17 470pF 50V C3780 2113741F25 1nF 50V
8.
C3737 2113740F45 56pF 5% 50V C3782 2113740F51 100pF 50V
16
C3738 2113740F39 33pF 5% 50V C3783 2113740F41 39pF 5%
C3754 2113740F37 27pF 5% 50V C3803 2311049A63 TANT CP 10uF 10% 10V
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C3767 2113741F49 10nF 50V X7R L3732 2462587T30 COIL CHIP 1uH
C3772 2113740F51 100pF 50V L3734 0105950T45 Helical Molded FIN .175
L3752 0105950T44 Helical Molded FIN .175 R3771 0662057A29 150 1/16W 5%
t
L3768 2462587T16 COIL CHIP 120nH R3775 0662057C61 270 1/16W 5%
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L3773 2462587T12 COIL CHIP 56nH R3776 0662057A15 39 1/16W 5%
8.
L3781 2462587T38 COIL CHIP 22nH R3777 0662057A29 150 1/16W 5%
16
Q3742 4805921T09 XSTR DUAL ROHM R3779 0662057A53 1k5 1/16W 5%
FMG8
R3782 io
0662057A25
0662057A25
100 1/16W 5%
100 1/16W 5%
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Q3752 4880214G02 NPN 40V .2A R3785 0662057A01 10 1/16W 5%
Q3770 4813827A07 NPN SML SIG MMBR9 R3791 0662057C61 270 1/16W 5%
.m
Q3780 4813827A07 NPN SML SIG MMBR9 R3792 0662057A59 2k7 1/16W 5%
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C3302 2113740F24 7.5pF 5% 50V L3302 2462587T23 COIL CHIP 470nH
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C3303 2113741F37 3.3nF 50V L3331 2462587T23 COIL CHIP 470nH
8.
C3305 2113740F51 100pF 5% 50V L3333 2462587T38 COIL CHIP 22nH 5%
16
C3306 2113740F39 33pF 5% 50V L3334 2462587T38 COIL CHIP 22nH 5%
C3307 2113741F37 3.3nF 50V Q3301 4813827A07 NPN SML SIG MMBR9
Circuit Motorola
Description
Ref Part No.
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C5202 2113740F31 15pF 5% 50V C5239 2113740F44 51pF 5% 50V
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C5203 2113743A19 100nF 16V X7R D5201 4880154K03 Dual Schottky SOT23
C5204 2113743A19 100nF 16V X7R FL5201 9180098D04 Filter CER 4-EL 455kHz
8.
(12.5kHz)
C5205 2113740F33 18pF 5% 50V 9180098D06 Filter CER 3WR
16
(20/25kHz)
C5208 2113743A19 100nF 16V
FL5202 9180097D04 Filter CER 6-EL 455kHz
C5211 2113740F31 15pF 5% 50V
C5231 2311049A07 TANT CP 1uF 10% 16V R5221 0662057B02 150k 1/16W (12.5kHz)
0662057B05 200k 1/16W 5%
C5232 2113740F51 100pF 5% 50V (20/25kHz)
Circuit Motorola
Description
Ref Part No.
U5201 5180207R01 IF IC
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12.5KHz 60dB
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9102652Y02 XTAL FLTR 45.1MHZ
20/25KHz 80dB
8.
Y5211 4802653Y01 XTAL OSC 44.645MHZ
16
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D0843
D0868
D0866
D0867
D0842 D0841
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D0848 D0847 D0846 D0845
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D0864 D0863 D0862 D0861 D0865
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Control Head ÔKÕ
Component Side
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R0813 Q0843
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D0825 C0826 R0845 R0812 R0811
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R0814 Q0841
1 R0841 R0846
VR0809 R0843 VR0801
Q0862 Q0842
U0841
6
J0801 R0862
C0825
R0801
R0864
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C0806 C0803 Q0861 R0844 VR0803 VR0804
C0841
C0815 R0842 R0861 C0801
R0847 Q0844
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R0863
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VR0806 C0811
R0853 Q0847
Q0848
R0849Q0845 R0851 C0842 R0848
Q0846 R0855
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Control Head K
PCB No. 8480573Z01
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2 1 2 1
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4 3 4 3
2 3 1 2 3 1
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4 3 4 3
6 5 6 5
Main Board -
Control Head K
C0801 2113741F17 470pF 50V X7R R0845 0662057A89 RES CHP 47k 1/16W 5%
C0802 2113741F17 470pF 50V X7R R0846 0662057A41 RES CHP 470 1/16W 5%
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C0841 2113743K15 100nF 16V Y5V R0847 0662057A89 RES CHP 47k 1/16W 5%
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C0842 2311049J23 TANT 10uF 10% 6V R0848 0660076A35 RES CHIP 270 5 1/8
D0825 4813833C02 DUAL SOT MMBD6100 R0849 0662057A89 RES CHP 47k 1/16W 5%
8.
D0841 4805729G73 LED SMT YEL HP R0850 0660076A35 RES CHIP 270 5 1/8
16
D0842 4805729G73 LED SMT YEL HP R0851 0662057A89 RES CHP 47k 1/16W 5%
D0843 4805729G74 LED SMT RED HP R0852 0660076A35 RES CHIP 270 5 1/8
D0844-
D0848
4805729G75 LED SMT GREEN HP
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R0853 0662057A89 RES CHP 47k 1/16W 5%
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R0854 0660076A35 RES CHIP 270 5 1/8
D0861- 4805729G75 LED SMT GREEN HP
D0868 R0855 0662057A89 RES CHP 47k 1/16W 5%
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J0801 0902636Y01 CONN Flex Side Entry R0856 0660076A35 RES CHIP 270 5 1/8
.m
J0802 2809926G01 CONN 1.25MM CTR SUR R0861 0662057A65 RES CHP 4k7 1/16W 5%
J0803 2805924V01 CONNECTOR MIC R0862 0662057A65 RES CHP 4k7 1/16W 5%
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Q0825 4880048M01 NPN DIG 47k/47k R0863 0662057A35 RES CHP 270 1/16W 5%
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Q0841 4880048M01 NPN DIG 47k/47k R0864 0662057A35 RES CHP 270 1/16W 5%
Q0842- 4813824A10 NPN 40V .2A B=50-150 U0841 5113806A35 MC14094, REG, 8-Stage,
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Q0848 SHIFT/STOREU
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Q0861 4813824A10 NPN 40V .2A B=50-150 VR0801 4813830A14 5.1V 5% 225mW
Q0862 4813824A10 NPN 40V .2A B=50-150 VR0802 4813830A14 5.1V 5% 225mW
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R0801 0660076A35 RES CHIP 270 5 1/8 VR0803- 4813830A27 14V 5% 225MW
VR0805
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H0931
D0943
D0968 D0964 D0953 D0957 D0961 D0965 D0969 D0956
D0942 D0941
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R0902
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Control Head ÔPÕ
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R0945 R0912
R0946
1 Q0943
C0906
C0926
R0911
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R0922
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Q0941 R0921 Q0942
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VR0904 C0901VR0901
VR0909 C0903 C0941 R0901
R0943
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C0934 R0933
C0935
C0915 R0920
U0932
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C0911
R0947
VR0906 R0914 R0941 R0919
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Q0944
C0904 J0901 C0942
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R0948
VR0907
VR0908 Q0952
U0941
C0905 R0917 R0916 R0926R0925
VR0902
C0902
Q0925
J0902 R0918 VR0903
VR0905
R0952
R0951
R0915 R0953 Q0951 R0954 Control Head ÔPÕ
Solder Side
Control Head P
PCB No. 8480479Z01
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2 1 2 1
BPO
BP I
B13
B14
B17
B18
B10
B12
B15
B19
B11
B16
B20
B21
B22
B23
B24
B25
B26
B27
B28
B30
B31
B32
B33
B29
B7
B1
B2
B3
B4
B5
B6
B8
B9
4 3 4 3
2 1 2 1
3 3
6 5 6 5
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Main Board -
Control Head P
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C0934 2113743K15 100nF 16V R0931 0662057A65 4k7 1/16W 5%
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C0935 2113741F49 10nF 50V R0932 0662057A73 10k 1/16W 5%
8.
C0942 2311049J23 TANT CP 10uF 10% 6V R0941 0662057A73 10k 1/16W 5%
16
D0925 4813833C02 DIODE DUAL SOT R0942 0662057A89 47k 1/16W 5%
MMBD6100
R0943 0662057A89 47k 1/16W 5%
D0941
D0942
4805729G73
4805729G73
LED SMT YEL
J0901 0902636Y01 CONN FLEX Side Entry R0953 0662057A73 10k 1/16W 5%
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MENT STATIC
Q0925 4880048M01 NPN DIG 47k/47k
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Q0942 4813824A10 NPN 40V .2A B=50-150 VR0902 4813830A14 5.1V 5% 225mW
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Q0943 4813824A10 NPN 40V .2A B=50-150 VR0903 4813830A27 14V 5% 225MW MMB
Q0944 4813824A10 NPN 40V .2A B=50-150 VR0904 4813830A27 14V 5% 225MW MMB
Q0951 4813824A10 NPN 40V .2A B=50-150 VR0905 4813830A27 14V 5% 225MW MMB
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Chapter 6
216-246MHz Specific Information
Table of Contents
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Chapter
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6.1 Model Chart and Technical Specifications
8.
6.2 Radio Tuning Procedure
16
6.3 Theory of Operation
6.4
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PCB/Schematic Diagrams and Parts Lists
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Chapter 6.1
Model Chart and Technical Specifications
Table of Contents
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Paragraph Page
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1.0 Overview ..................................................................................................... 1
8.
2.0 Model Chart ................................................................................................ 1
16
3.0 Technical Specifications ........................................................................... 2
3.1
3.2 io
General ........................................................................................................ 2
Transmitter................................................................................................... 2
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3.3 Receiver....................................................................................................... 3
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1.0 Overview
6.1
This chapter lists the 216-246 MHz models and technical specifications available for the GM950i
mobile radio.
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8.
Description
16
GM950i
216-246 MHzio
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X = Indicates one of each required
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AZM08MHF6AA2AN
AZM08MFF6AA3AN
AZM08MFF4AA3AN
AZM08MFF6AA2AN
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Model
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Item Description
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3.1 General
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Power Supply 10.8 to 15.6V dc, negative earth
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Dimensions 44x168x160 mm (HxWxD)
8.
Weight 1030g
16
Storage Temperature - 40°C to + 85°C
50Ω BNC
Antenna Connection
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- Mechanical Vibration IEC 68/2/27 and Shock IEC 28/2/6
European Dust & Water protection IP54
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ETS300-219 Signalling
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3.2 Transmitter
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3.3 Receiver
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Spurious Rejection >70dB ETS
8.
Hum and Noise (CCITT) >40dB (12.5kHz); >45dB (20/25kHz) CCITT
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Audio Response (300 - 3000 Hz) Flat or De-Emphasised
<25msec
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Audio Output Power 4W (internal speaker); <13W external
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Chapter 6.2
Radio Tuning Procedure
Table of Contents
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Paragraph Page
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1.0 216-246 MHz Tuning Procedure ................................................................ 1
8.
1.1 General ........................................................................................................ 1
16
1.2 PA Bias Voltage........................................................................................... 3
1.3 Battery Threshold ........................................................................................ 3
1.4
1.5
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Transmitter Power .......................................................................................
Reference Oscillator ....................................................................................
4
4
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1.6 Front-End Filter............................................................................................ 5
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1.1 General
The recommended hardware platform is a 386 or 486 DX 33 PC (personal computer) with 8 MBytes
RAM, MS-DOS™ 5.0, Windows™3.1, and RSS (Radio Service Software). These are required to
align the radio. Refer to your RSS Installation Manual for installation and setup procedures for the
required software; the user manual is accessed (and can be printed if required) via the RSS.
To perform the alignment procedures, the radio must be connected to the PC, RIB (Radio Interface
Box), and Universal Test Set as shown in figure 6.2-1.
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SERVICE MONITOR
30 dB PAD OR COUNTER
8.
TRANSMIT
30 dB PAD WATTMETER
16
RF GENERATOR
RECEIVE
BNC
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TEST SET AUDIO GENERATOR
MIC IN RADIO RTX-4005B/
GTF180B RX
SINAD METER
TEST CABLE
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GTF-376A
AC VOLTMETER
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Before going into the Service menu, the radio must first be read using the File / Read Radio menu (if
the radio has just been programmed with data loaded from disk or from a newly created codeplug,
then it must still be read so that the RSS will have the radio’s actual tuning values).
All Service windows read and program the radio codeplug directly; you do NOT have to use the RSS
Read Radio / Write Radio functions to program new tuning values.
CAUTION: DO NOT switch radios in the middle of any Service procedure. Always use the
Program or Cancel key to close the tuning window before disconnecting the radio.
Improper exits from the Service window may leave the radio in an improperly
configured state and result in seriously degraded radio or system performance.
The Service windows introduce the concept of the “Softpot”, an analog SOFTware controlled
POTentiometer used for adjusting all transceiver alignment controls. A softpot can be selected by
clicking with the mouse at the value or the slider or by hitting the TAB key until the value or the slider
is highlighted.
Each Service window provides the capability to increase or decrease the ‘softpot’ value with the
t
mouse, the arrow keys or by entering a value with the keyboard. The window displays the minimum,
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maximum, and step value of the softpot. In addition transmitter tuning windows indicate the
transmitter frequency and whether the radio is keyed.
8.
Adjusting the softpot value sends information to the radio to increase (or decrease) a DC voltage in
the corresponding circuit. For example, increasing the value in the Reference Oscillator tune window
16
instructs the radio microprocessor to increase the voltage across a varactor in the reference
oscillator to increase the frequency. Clicking the Program button stores all the softpot values of the
current window permanently in the radio.
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In ALL cases, the softpot value is just a relative number corresponding to a D/A (Digital-to-Analog)
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generated voltage in the radio. All standard measurement procedures and test equipment are
similar to previous radios.
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Refer to the RSS on-line help for information on the tuning software.
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Note: All tuning procedures must be performed at a supply voltage of 13.2V unless otherwise
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stated. The Modulation Analyser to measure the deviation should be set to frequency
modulation with de-emphasis switched off and all high pass filters switched off.
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Adjustment of the PA Bias is critical for proper radio operation. Improper adjustment will result in
poor operation and may damage the PA FET device. For this reason, the PA bias must be set before
the transmitter is keyed the first time.
Note: For certain radio models there are two bias voltage settings. For these radios both ‘ Bias 1
Voltage ’ and ‘ Bias 2 Voltage ‘ need to be adjusted when aligning the PA Bias. For models
that only have one bias voltage setting, the ‘ Bias 2 Voltage ‘ will be shown in grey on the
service menu.
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2. Select Bias Voltage to open the bias voltage tuning window. If the control voltage is out of
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range, an error message will be displayed. In this case the radio hardware has a problem and
tuning must be stopped immediately.
3. Click the Toggle Bias button to set the quiescent current temporarily to 0 mA. The status bar will
8.
indicate that the bias is switched off.
16
4. Measure the DC current of the radio. Note the measured value and add the specified quiescent
current shown in table 6.2-1. The result is the tuning target.
5. Click the Toggle Bias button to switch on the quiescent current again.
6.
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Adjust the current per the target calculated in step 4.
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7. Click the Program button to store the softpot value.
RF-Band Target
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216-246MHz 150mA±15%
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The radio uses 2 battery threshold levels Tx High and Tx Low to determine the battery condition.
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The Program buttons must only be activated when the power supply is set to the indicated voltage. If
the RSS detects that the voltage is not within the expected range for the threshold in question then a
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message will be displayed to warn that the radio may not be set up correctly for the alignment
operation.
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CAUTION: Inadvertant Use Of The Program Buttons May Result In Radio Failure.
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The radio has two power level settings, a high power level setting, and a low power level setting.
IMPORTANT: To set the transmitter power for customer applications use the Per Radio window
under the Edit menu and set the “Power 1” and “Power 2” powers to the desired
values. Only if the transmitter components have been changed or the transmitter
does not transmit with the power set in the Per Radio window, should the
following procedure be performed.
The advanced power setting technology employed in the radio makes use of two reference power
level settings along with parameters describing the circuit behaviour. To determine these parameters
the RSS requires the power values measured for two different settings.
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1. From the Service menu, select Tx Alignments.
2. Select RF Power to open the RF power tuning window. The window will indicate the transmit
8.
test frequencies to be used.
3. Select the Point 1 value of the first frequency.
16
4. Click the Toggle PTT button to key the radio. The status bar will indicate that the radio is
transmitting.
5.
6.
Measure the transmitter power on your power meter.
Enter the measured value in the box Point 1. io
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7. Select the Point 2 value of the first frequency.
8. Measure the transmitter power on your power meter.
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11. Repeat steps 3 - 10 for all test frequencies shown in the window.
12. Click the Program button to store the softpot values.
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Adjustment of the reference oscillator is critical for proper radio operation. Improper adjustment will
not only result in poor operation, but also a misaligned radio that will interfere with other users
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operating on adjacent channels. For this reason, the reference oscillator should be checked every
time the radio is serviced. The frequency counter used for this procedure must have a stability of
0.1ppm (or better).
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2. Select Reference Oscillator to open the reference oscillator tuning window. The tuning window
will indicate the target transmit frequency.
3. Click the Toggle PTT button to key the radio. The status bar will indicate that the radio is
transmitting.
4. Measure the transmit frequency on your frequency counter.
5. Adjust the reference oscillator softpot in the tuning window to achieve a transmit frequency
within the limits shown in table 6.2-2.
6. Click the Toggle PTT button again to dekey the radio and then click the Program button to store
the softpot value.
RF-Band Target
Alignment of the front-end pre-selector is normally not required on these radios. Only if the radio has
poor receiver sensitivity or the pre-selector parts have been replaced the following procedure should
be performed. The softpot value sets the control voltage of the pre-selector. Its value needs to be set
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at 7 frequencies across the frequency range. If the radio supports 20 or 25 kHz channel spacing
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selection, use the parameters for 25 kHz channel spacing.
1. Set the test box (GTF180) meter selection switch to the “Audio PA” position and connect a
8.
SINAD meter to the “METER” port.
2. From the Service menu, select Rx Alignments.
16
3. Select Front End Filter to open the pre-selector tuning window. The window will indicate the
receive test frequencies to be used.
4.
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Select the first test frequency shown, and set the corresponding value to the start value shown
in table 6.2-4.
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5. Set the RF test generator to the receive test frequency, and set the RF level to 10µV modulated
with a 1kHz tone at the normal test deviation shown in table 6.2-3.
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6. Measure the RSSI voltage at accessory connector pin 15 with a dc voltmeter capable of 1mV
resolution and at least 1Mohm input impedance.
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7. Change the softpot value by the stepsize shown in table 6.2-4 and note the RSSI voltage.The
target softpot value is achieved when the measured RSSI voltage change between step 6 and
step 7 is lower than the tuning target for the first time. The tuning target, shown in table 6.2-4, is
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expressed as the percentage of the measured RSSI voltage and must be recalculated for every
tuning step. If the measured RSSI voltage decreases before the target value has been
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achieved, approximation should be stopped and the current softpot value should be used as
target value. Set test box (GTF180) audio switch to the “SPKR” position. The 1 kHz tone must
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The rated volume softpot sets the maximum volume at normal test modulation.
1. Set test box (GTF180) meter selection switch to the “AUDIO PA” position and the speaker load
switch to the “MAXAR” position. Connect an AC voltmeter to the test box meter port.
2. From the Service menu, select Rx Alignments.
3. Select Rated Volume to open the rated volume tuning window. The screen will indicate the
receive test frequency to be used.
4. Set the RF test generator to the receive test frequency, and set the RF level to 1mVolt
modulated with a 1kHz tone at the normal test deviation shown in table 6.2-3. Set test box
(GTF180) audio switch to the “SPKR” position. The 1kHz tone must be audible to make sure
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the radio is receiving.
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5. Adjust the value of the softpot to obtain rated audio volume (as close to 3.87 Vrms)
Note: The voltage at the meter port of the testbox GTF180 is only half the voltage at the
8.
speaker.
6. Click the Program to store the softpot value.
16
1.8 Squelch
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The squelch softpots set the signal to noise ratio at which the squelch opens. The squelch value
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needs to be set at 7 frequencies across the frequency range. If the radio supports 20 or 25 kHz
channel spacing selection, the radio stores separate tuning data for 20 kHz and 25 kHz channel
spacing. Therefore, both sets of tuning data should be tuned independently.
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1. Set the test box (GTF180) meter selection switch to the “Audio PA” position and connect a
SINAD meter to the “METER” port.
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12.5kHz radios and the 25kHz data for 20/25kHz radios. The window will indicate the receive
test frequencies to be used.
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4. Select the first test frequency shown, and set the corresponding value to 0.
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5. Set the RF test generator to the test frequency and modulate the signal generator at the normal
test deviation shown in table 6.2-3, with 1kHz tone. Adjust the generator for a 8-10 dB SINAD
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The transmit deviation limit softpot sets the maximum deviation of the carrier. The deviation limit
needs to be set at 7 frequencies across the frequency range. Unlike other radios, the deviation limit
for 216-246MHz is set using low frequency (PL) rather than the usual 1 kHz tone. No audio signal
must be injected, the radio generates a 82.5 Hz tone while the deviation limit alignment window is
open. This tone is used to set the maximum deviation. If the radio supports 20 or 25 kHz channel
spacing selection, the radio stores separate tuning data for 20 kHz and 25 kHz channel spacing.
Therefore, both sets of tuning data should be tuned independently
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the transmit test frequencies to be used.
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3. Select the first test frequency shown in the window.
4. Click the Toggle PTT button to key the radio. The status bar will indicate that the radio is
8.
transmitting.
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5. Adjust the transmitter deviation to the value shown in table 6.2-5.
6. Click the Toggle PTT button to dekey the radio.
7. Repeat steps 3-6 for the remaining test frequencies.
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Click the Program button to store the softpot values.
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9. If the radio supports 20 or 25 kHz channel spacing selection repeat steps 1- 8 for 20 kHz
channel spacing using the ‘Deviation Limit (20 kHz)’ window.
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Compensation alignment balances the modulation sensitivity of the VCO and reference modulation
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(synthesizer low frequency port) lines. Compensation algorithm is critical to the operation of
signalling schemes that have very low frequency components (e.g. PL) and could result in distorted
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waveforms if improperly adjusted. The compensation value needs to be set at 7 frequencies across
the frequency range and for every channel spacing supported by the radio.
6. Click the Toggle PTT button to key the radio. The status bar will indicate that the radio is
transmitting.
7. Measure the transmitter deviation.
8. Adjust the transmitter deviation to the value shown in table 6.2-6.
9. Click the Toggle PTT button to dekey the radio.
10. Repeat steps 5 - 9 for the remaining test frequencies.
11. Click the Program button to store the softpot values.
12. If the radio supports 20 or 25 kHz channel spacing selection repeat steps 1- 11 for 20 kHz
channel spacing using the ‘Modulation Balance (20kHz)’ window.
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Channel Spacing Deviation
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20 kHz 3.4-3.6 kHz
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25 kHz 4.3-4.6 kHz
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Chapter 6.3
Theory of Operation
Table of Contents
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Paragraph Page
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1.0 Overview..................................................................................................... 1
8.
2.0 Controller.................................................................................................... 2
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2.1 General ........................................................................................................ 2
2.2 Voltage Regulators ...................................................................................... 2
2.3 io
Electronic On/Off ......................................................................................... 3
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2.4 Mechanical On/Off ....................................................................................... 3
2.5 Ignition ......................................................................................................... 3
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Paragraph Page
5.0 Transmit Signalling Circuits ................................................................... 10
5.1 Sub-audible Data (PL/DPL) ....................................................................... 10
5.2 High Speed Data and DTMF ..................................................................... 11
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6.3 Audio Amplification Speaker (+) Speaker (-) ............................................. 13
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6.4 Handset Audio ........................................................................................... 14
6.5 Filtered Audio ............................................................................................ 14
8.
6.6 Discriminator Audio (Unfiltered)................................................................. 14
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6.7 Option Board Audio .................................................................................... 14
1.0 Overview
6.3
This section provides a detailed theory of operation for the radio and its components.
The main radio is designed to accept one additional option board. This may provide functions such
as secure voice/or a signalling decoder.
The control head is mounted directly on the front of the radio. The control head contains a speaker,
LED indicators, a microphone connector, buttons and dependant of radio type, a display. These
provide the user with interface control over the various features of the radio.
In addition to the power cable and antenna cable, an accessory cable can be attached to a
connector on the rear of the radio. The accessory cable provides the necessary connections for
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items such as external speaker, foot operated PTT, ignition sensing, etc.
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2.0 Controller
2.1 General
■ Digital Control
■ Audio Processing
■ Power Control
■ Voltage Regulation
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The digital control section of the radio board is based upon a closed architecture controller
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configuration.
The digital section consists of a microprocessor, support memory, support logic, signal MUX ICs, the
8.
On/Off circuit, and general purpose Input/Output circuitry.
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The closed architecture controller uses the Motorola 68HC11E9 (U0101) for a GM950E radio and
the 68HC11E20 for a GM950i radio. In this configuration RAM and ROM are contained within the
microprocessor itself. The only external memory device in the closed architecture controller is an
EEPROM (2KByte for GM950i radio).
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Note: From this point on the 68HC11E9 or E20 microprocessor will be referred to as E9/20µP or
µP. References to a Control Head will be to radio model A3 (Display radio).
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Voltage regulation for the controller is provided by 3 separate devices; U0631 (LP2951CM) +5V,
U0601 (LM2941T) +9.3V, and UNSW 5V (a combination of R0621 and VR0621). An additional
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Voltage regulation providing 5V for the digital circuitry is done by U0631. Input and output capacitors
(C0631/0632 and C0633-0635) are used to reduce high frequency noise and provide proper
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operation during battery transients. This regulator provides a reset output (pin 5) that goes to 0 volts
if the regulator output goes out of regulation. This is used to reset the controller to prevent improper
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operation. Diode D0631 prevents discharge of C0632 by negative spikes on the 9V3 voltage
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Regulator U0601 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors (C0601-0603 and C0604/0605) are used to
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reduce high frequency noise. R0602/R0603 sets the output voltage of the regulator. If the voltage at
pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 volts
the regulator output increases. This regulator output is electronically disabled by a 0 volt signal on
pin 2. Q0601 and associated circuitry (R0601/0604/0605 and C0606) are used to disable the
regulator when the radio is turned off.
UNSW 5V is only used in a few areas which draw low current and requires 5 V while the radio is off.
UNSW 5V CL is used to buffer the internal RAM. C0622 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Diode D0621 prevents radio
circuitry from discharging this capacitor.
The voltage 9V3 SUPP is only used in the VHF radio to supply the drain current for the RF MOS
FET in the PA.
The voltage SW B+ is monitored by the µP through the voltage divider R0641/R0642. Diode VR0641
limits the divided voltage to 5.1V to protect the µP.
Diode D5601 (UHF) / D3601 (VHF) located on the PA section acts as protection against transients
and wrong polarity of the supply voltage.
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off
without direct user action. For example, automatic turn on when ignition is sensed and off when
ignition is off.
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Q0611 is used to provide SW B+ to the various radio circuits. Q0611 acts as an electronic on/off
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switch controlled by Q0612. The switch is on when the collector of Q0612 is low. When the radio is
off Q0612 is cutoff and the voltage at Q0611-base is at A+. This effectively prevents current flow
8.
through Q0611 from emitter to collector. When the radio is turned on the voltage at the base of
Q0612 is high (about 0.6V) and Q0612 switches on (saturation) and pulls down the voltage at
Q0611-base. With Transistor Q0611 now enabled current flows through the device. This path has a
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very low impedance (less than 1 ohm) from emitter to collector. This effectively provides the same
voltage level at SWB+ as at A+.
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The electronic on/off circuitry can be enabled by the microprocessor (through AFIC port GCB1, line
B+ CONTROL), the mechanical On/Off button on the control head (line ON OFF CONTROL), or the
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ignition sense circuitry (line IGNITION CONTROL). If any of the 3 paths cause a low at the collector
of Q0612, the electronic ON is engaged.
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This refers to the on/off button, located on the control head, and which turns the radio on and off. If
the radio is turned off and the on/off button is pressed, line ON OFF CONTROL goes high and
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switches the radio on as long as the button is pressed. The microprocessor is alerted through line
ANALOG 3 which is pulled to low by Q0925 (Control Head Model A3) while the on/off button is
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pressed. If the software detects a low state it asserts B+ CONTROL via AFIC pin 39 low which
keeps Q0612 and Q0611, and in turn the radio switched on.
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If the on/off button is pressed and held while the radio is on, the software detects the line ANALOG
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3 changing to low and switches the radio off by setting B+ CONTROL to low.
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2.5 Ignition
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Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is
not running.
When the IGNITION input (J0400- 10) goes above 6 volts Q0421 and Q0612 turn on. This turns on
SW B+ by turning on Q0611 via line IGNITION CONTROL and Q0612 and the microprocessor
starts execution. The software reads the line IGNITION SENSE, determines from the level that the
IGNITION input is active and sets the B+ CONTROL output of the AFIC pin 39 to high to latch on
SW B+.
When the IGNITION input goes below 6 volts, Q0421 switches off and R0426, R0427 pull line
IGNITION SENSE high. The software is alerted by line IGNITION SENSE to switch off the radio by
setting B+ CONTROL to low. The next time the IGNITION input goes above 6 volts the above
process will be repeated.
2.6 Hook
The HOOK input is used to inform the µP when the Microphone´s hang-up switch is engaged.
The signal is routed from J0101-3 and transistor Q0137 to the E9/20µP U0101-56. The voltage
range of HOOK in normal operating mode is 0-5V. If a rear GP input line is set as HOOK then the
front HOOK signal is overriden.
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2.7 Microprocessor Clock Synthesizer
The controller uses the oscillator in the microprocessor E9/20µP along with some external
8.
components (C0115-C0117, L0114, R0115, Y0114) to generate the clock. Q0114 is used to alter
the clock frequency slightly under software control if there is a possibility of harmonics of this clock
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source interfering with the desired radio receive frequency.
(E9/20µP:U0101-53) and chip select lines going to the various IC’s, connected on the SPI PORT
(BUS). This BUS is a synchronous bus, in that the timing clock signal CLK is sent while SPI data
(SPI TRANSMIT DATA or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on
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either SPI TRANSMIT DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The
SPI TRANSMIT DATA is used to send serial from a µP to a device, and SPI RECEIVE DATA is used
to send data from a device to a µP. The only device from which data can be received via SPI
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On the controller there are three ICs on the SPI BUS, AFIC (U103-33), EEPROM (U0108-1) and
D/A (U0731-6). In the RF sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The
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SPI TRANSMIT DATA and CLK lines going to the RF section are filtered by L0194/L0195 to
minimize noise. The chip select lines for the IC´s are decoded by the address decoder U102.
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The SPI BUS is also used for the control head. U0104-1,2 buffer the SPI TRANSMIT DATA and CLK
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lines to the control head. U0104-3 switches off the CLK signal for the LCD display if it is not selected
via LCD CE.
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When the µP needs to program any of these IC’s it brings the chip select line for that IC to a logic 0
and then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different, for example the FRAC-N can receive up to 13 bytes (97 bits) while the DAC can receive up
to 3 bytes (24 bits). After the data has been sent the chip select line is returned to a logic 1.
The Option board interfaces are different in that the µP can also read data back from devices
connected.
The timing and operation of this interface is specific to the option connected, but generally follows
the pattern:
The SBEP serial interface allows the radio to communicate with the Radio Service Software (RSS).
This interface connects to the Microphone connector (J0903/J0803) via Control Head connector
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(J0101) and comprises BUS+ (J0101-15). The line is bi-directional, meaning that either the radio or
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the RSS can drive the line.
8.
When the RSS needs to communicate with the radio, an interrupt is generated by the BUS+ signal
through R0104. The µP then starts serial data communication on BUS+ by sending data from pin 50
through D0101 and receiving data at pin 47 through R0104. While the radio is sending serial data at
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pin 50 it receives an ”echo” of the same data at pin 47.
GP3,5,6 are bidirectional. The software and the hardware configuration of the radio model define the
function of each port. Some ports are not connected on the 4ch radio, refer to appendix B.
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GP1 can be used as external PTT input or others, set by the RSS.
GP2 can be used as normal output (Q0441 placed) or external alarm output (Q0442 placed). The
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GP4 can be used as normal input (D0471, R0477 not placed) or emergency input (D0471, R0477
placed).
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GP3,5,6 are bidirectional and use the same circuit configuration. Each port uses an output transistor
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controlled by µP port PB5,4,7 and an input transistor read by µP port PC2,5,3. To use one of the
GP´s as input the µP must turn off the corresponding output transistor.
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In addition the signals from GP3-6 are fed to the option board connectors J0102, J0103.
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The 470pF and 10nF capacitors serve to filter out any AC noise which may ride on the GP lines.
The E9/20µP (U0101) contains internal 12 (E9) or 20 (E20) Kilobytes ROM, 512 (E9) or 768 (E20)
bytes SRAM and 512 bytes EEPROM.
The E9/20µP RAM is always powered to maintain parameters such as the last operating mode. This
is achieved by maintaining 5V at U0101-25. Under normal conditions, when the radio is off UNSW
+5V is formed by FLT A+ running to D0621.
C0622 allows the battery voltage to be disconnected for a couple of seconds without losing RAM
parameters. Diode D0621 prevents radio circuitry from discharging this capacitor.
U0101-22 is the high reference voltage for the A/D ports on the E9/20µP. Resistor R0105 and
capacitor C0105 filter the +5V reference. If this voltage is lower than +5V the A/D readings will be
incorrect. Likewise U0101-21 is the low reference for the A/D ports. This line is normally tied to
ground. If this line is not connected to ground, the A/D readings will be incorrect.
The MODB (U0101-25) input of the E9/20µP must be at a logic 1 for it to start executing correctly.
The XIRQ (U0101-45) and the IRQ (U0101-46) pins should also be at a logic 1.
Optional external EEPROM (U0108) is available on some radio models. The external EEPROM is
accessed through a serial connection. The E9/20µP generates SPI CLK (U0101-53), SPI
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TRANSMIT DATA (MOSI) (U0101-52) and SPI RECEIVE DATA (MISO) (U0101-51) to read or write
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EEPROM. On a read of EEPROM the E9/20µP continues generating the clock and the EEPROM
places the requested data on the SPI RECEIVE DATA (MISO) line. On a write the message is
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followed by the data to be written to the EEPROM.
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2.12 Control Head Model A2 or A3
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Two Control Head versions (A2 or A3) are available for user interface. Both Control Heads contain
the internal speaker, the microphone connector, several buttons to operate the radio and several
indicator LEDs to inform the user about the radio status. Additionally the Control Head model A3
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uses a 3 digit, 7 segment, LCD display for the channel number.
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The On/Off button when pressed switches the voltage regulators on by pulling ON OFF CONTROL
to high and connects the base of Q0925(A3), Q0825(A2) to FLT A+. This transistor pulls the line
ANALOG 3 to low to inform the µP that the On/Off button is pressed. If the radio is switched off, the
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µP will switch it on and vice versa. All other buttons work the same way. If a button is pressed, it will
connect one of the 3 lines ANALOG 1,2,3 to a resistive voltage divider connected to +5V. The
voltages of the lines are A/D converted inside the µP and specify the pressed button.
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All the back light and indicator LEDs are driven by current sources and controlled by the µP via
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SERIAL PERIPHERAL INTERFACE (SPI) interface. The LED status is stored in shiftregister
U0941(A3), U0841(A2). Line LED CE enables the serial write process via Q0941(A3), Q0841(A2)
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while line LED CLCK BUF shifts the data of line SPI DATA BUF into the shiftregister.
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In addition Control Head Model A3 contains the LCD display H0931. The display data of line SPI
DATA BUF is shifted into the display driver by clock signal LCD CLCK BUF.
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3.0 General
The AFIC (U0103) used in the controller performs RX/TX audio shaping, i.e. filtering, amplification,
attenuation.
The AFIC is programmable through the SPI BUS (U0103-30/31/33), normally receiving 6 bytes. This
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programming sets up various paths within the AFIC to route audio signals through the appropriate
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filtering, gain and attenuator blocks. The AFIC also has 4 General Control Bits GCB1,3-5 which are
CMOS level outputs. GCB1 is used to switch the radio on and off under µP control via line B+
CONTROL. GCB3 is used to switch the audio PA on and off (AUDIO PA ENABLE). GCB4 selects
8.
between the UNATTEN RX OUT audio signal and the unfiltered DET AUDIO signal. GCB5 HIGH
LOW BAND can be used to switch between band splits.
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3.2 Audio Ground
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VAG is the dc bias used as an audio ground for the Op-amps that are external to the Audio Filter IC
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(AFIC). U0105-1 forms this bias by dividing 9.3V with resistors R0171, R0172 and buffering the
4.65V result with a voltage follower. VAG emerges at pin 1 of U0105-1. C0172 is a bypass capacitor
for VAG. The AFIC generates its own 2.5 V bias for its internal circuitry. C0153 is the bypass for the
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AFIC’s audio ground dc bias. Note that while there are AFIC VAG, and BOARD VAG (U0105-1) each
of these are separate. They do not connect together.
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The radio supports 2 distinct microphone paths known as internal and external mic and an auxiliary
path (FLAT TX AUDIO). The microphones used for the radio require a DC biasing voltage provided
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by a resistive network.
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These two microphone audio inputs are connected together. Following the internal mic path; the
microphone is plugged into the radio control head and is connected to the controller board via
J0101-16. From here the signal is routed to C0142. R0141 and R0142 provide the 9.3VDC bias.
R0142 and C0141 provide a 1kΩ AC path to ground that sets the input impedance for the
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier
circuit.
The MIC signal is routed to the AFIC´s TX IN input (U0103-10) through R0146 and R0145 (GM950E
radio) or through Op-amp buffer U0106-2 and option board connector J0103-3,1 (GM950i radio).
The audio signal at the output of U0106-2 should be approximately 80mV deviation with 25kHz
channel spacing.
The FLAT TX AUDIO signal from accessory connector U0400-5 is buffered by Op-amp U0106-1 and
fed to the AFIC U0103-13 through gate U0107-1. Gate U0107-1 is controlled by the µP port PC7
(U0101-42) and selects between FLAT TX AUDIO or signalling signal created by the µP.
J0101
J0103-3 J0103-1
IN OUT
OPTION
BOARD
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MIC
CONTROL HEAD 10 TX IN
CONNECTOR
FILTERS AND
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PREEMPHASIS
J0400
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ASFIC LIMITER
U0201
2
EXT MIC
AUX
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5 13 TX IN SPLATTER
FLAT TX
FILTER
AUDIO
16
ACCESSORY
CONNECTOR
21 TX OUT
14
4-BIT
DEVIATION
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ATTENUATOR TO
MOD IN RF
SECTION
(SYNTHESIZER)
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5-BIT 20
15
DEVIATION
ATTENUATOR
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GEPD 5427-1
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The external microphone signal enters the radio on accessory connector J0400 pin 2 and connects
to the standard microphone input through R0421.
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Mic PTT is sensed by the µP U0101 pin 22. An external PTT can be generated by grounding pin 3
on the accessory connector if this input is programmed for PTT.
The MIC signal is routed to the AFIC (U0103) through R0146 and R0145 (GM950E radio) or through
Op-amp buffer U0106-2 and option board connector J0103-3,1 (GM950i radio). R0145, C0145, the
amplifier inside the AFIC (pins 9,10) and gain setting resistor R0147 pre-emphasise the MIC audio
signal. After further limiting and filtering the modulation signal emerges from the AFIC at U0103-19/
20. Both signals are weighted by resistors R0181, R0182 and add up to signal MOD IN.
The audio coming from the microphone (J0101-16) or the external microphone (J0400-2) is routed
through Op-amp buffer U0106-2 (GM950i only) to the option board connector J0103-3. After option
board processing the signal emerges at J0103-1. The source resistor of the option board output and
C0145, the amplifier inside the AFIC (U0103-9,10) and gain setting resistor R0147 pre-emphasise
the signal. Inside the AFIC the signal follows a path identical to conventional transmit audio. The
modulation signal emerges from the AFIC at J0103-19/20. Both signals are weighted by resistors
R0181, R0182 and add up to signal MOD IN.
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1. Sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signal-
ling,
2. DTMF data for telephone communication in trunked and conventional systems, and
3. Audible signalling including Select 5, MPT-1327, MDC, Single Tones.
All three types are supported by the hardware while the radio software determines which signalling
type is available. Currently only PL/DPL and Single tones are supported in the software.
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62
8.
54 13 AUX TX SPLATTER
IN FILTER
58
MICRO
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CONTROLLER
42
U0101 ASFIC U0201
57
PL
GEPD_5432
32 CLOCK
STROBE
PL
ENCODER io LS
SUMMER
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TO RF
19, 20
ATTENUATOR SECTION
MOD IN (SYNTHESIZER)
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GEPD 5432-1
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Sub-audible data implies signalling whose frequency is below 300Hz. Although it is referred to as
”sub-audible data,” the actual frequency spectrum of these waveforms may be as high as 250 Hz,
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which is audible to the human ear. However, the radio receiver filters out any audio below 300Hz, so
these tones are never heard in the actual system.
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Only one type of sub-audible data can be generated by U0103 (AFIC) at any one time. The process
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is as follows, using the SPI BUS, the µP programs the AFIC to set up the proper low-speed data
deviation and select the PL or DPL filters. The µP then generates a square wave which strobes the
AFIC PL / DPL encode input PL CLOCK STROBE U0103-32 at twelve times the desired data rate.
For example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0103 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice
or data. The resulting summed waveform then appears on U0103-19,20 (MOD IN), where it is sent
to the RF board as previously described for transmit audio.
The High Speed Data and DTMF waveforms are created by the µP U0101 using summer U0105-3.
Op-amp U0105-3 and resistors R0121-R0124 add up the three signals coming from the µP pins 58,
59 and 62. The output signal of U0105-3 is routed to the AFIC (U0103-13) through gate U0107-1.
Inside the AFIC the signal enters the conventional transmitter audio path at the splatter filter input.
Gate U0107-1 controlled by µP port PC7 (U0101-42) selects between data signal and FLAT TX
AUDIO signal. Microphone audio is muted during High Speed Data signalling.
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ACCESSORY
CONNECTOR
11
FLT RX AUDIO
J0400
1
AUDIO 4 SPKR + 16
PA EXTERNAL
SPKR - 1
U0401 SPEAKER
9 6
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INT
SPKR-
INT
SPKR+ CONTROL
HEAD
CONNECTOR
8.
ATTEN.
2
INTERNAL
1 SPEAKER
J0101
14 HANDSET
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AUDIO
23
RX AUD OUT
UNAT
IN 2 J0103-4
22 RX OUT
OPTION VOLUME
BOARD
IN 1
OUT
J0103-2
8
AUX
6 RX IN
FILTER AND
PL IN DEEMPHASIS
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ATTEN.
AFIC
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J0103-5
U0103
7 RX IN
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SQUELCH ATTENUATOR
IF IC DET AUDIO
(DISCRIMINATOR
AUDIO)
DET AUDIO 28
SQ IN SQ OUT
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23 16 18
SQ LIM OUT
20
SQ RECT IN
MICRO CONTROLLER
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15 U0101
CSQ DET
15
CSQ DET
18
FAST SQ
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GEPD 5429-1
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The IF IC controls the squelch characteristics of the radio. With a few external parts (R5222, C5229,
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C5230, R5223) the squelch tail, hysteresis, attack and delay are optimized for the radio. To set the
squelch threshold the signal from IF IC pin 23 (line SQ ATT IN) is routed to the squelch attenuator
input of the AFIC (U0103-16). The attenuated signal (line SQ ATT OUT) from the AFIC (U0103-18)
enters the IF IC at pin 20 and is used to create a squelch indicator signal available at pin 15 (line
CSQ DET).
The microprocessor controlled ADAPT signal at pin 22 activates the fast squelch indicator signal at
IF IC pin 18 (FAST SQ). Both squelch indicator signals CSQ DET (pin 15) and FAST SQ (pin 18) are
combined, weighted by resistors R0111 / R0112 and fed to one of the microprocessor´s ADCs
(U0101-15) for interpretation. From the voltage weighted by the resistors the µP determines whether
CSQ DET, FAST SQ or both are active.
The receiver audio signal enters the controller section from the IF IC (U5201-28) on DET AUDIO.
The signal is AC coupled by C0181 and enters the AFIC via the RX IN pin U0103-7.
Inside the AFIC the signal entering RX IN (U0103-7) goes through the audio path while the signal
entering PL DPL IN (U0103-8) via C0182 goes through the PL/DPL path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, then a LPF filter to remove any frequency components above 3000Hz and then an
HPF to remove any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
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is set depending on the value of the volume control. Finally, the filtered audio signal passes through
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an output buffer within the AFIC. The audio signal exits the AFIC at RX AUDIO U0103-23.
8.
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/
maximum settings of the attenuator are set by codeplug parameters.
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Since sub-audible signalling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signalling enters the AFIC from the IF
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IC at PL DPL IN U0103-8. Once inside it goes through the PL/DPL path. The signal first passes
through one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is
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then filtered and goes through a limiter and exits the AFIC at PL DPL DECODER OUT U0103-27. At
this point the signal will appear as a square wave version of the sub-audible signal which the radio
received. The microprocessor (U0101-64) will decode the signal directly to determine if it is the tone/
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The output of the AFIC´s digital volume pot, U0103-23 is routed through a voltage divider formed by
R0401 and R0402 to set the correct input level to the audio PA (U0401). This is necessary because
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the gain of the audio PA is 46 dB, and the AFIC output is capable of overdriving the PA unless the
maximum volume is limited.
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The audio then passes through C0401 which provides AC coupling and low frequency roll-off.
C0402 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the audio
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The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+ / SPK- (U0401-4/6). The inputs for each of these amplifiers are pins 1
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and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via AUDIO PA ENABLE signal from the AFIC (U0103-40). When the base
of Q0401 is low, the transistor is off and U0401-8 is high, using pull up resistor R0406, and the Audio
PA is ON. The voltage at U0401-8 must be above 8.5VDC to properly enable the device. If the
voltage is between 3.3 and 6.4V, the device will be active but has its input (U0401-1/9) off. R0404
ensures that the base of Q0401 is high on power up. Otherwise there may be an audio pop due to
R0406 pulling U0401-8 high before the software can switch on Q0401.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT
A+ (U0401-7). FLT A+ of 11V yields DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V. If
either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ and
SPK- are routed to the accessory connector (J400-16 and 1) and to the control head (connector
J0101-1 and 2).
Certain hand held accessories have a speaker within them which require a different voltage level
than that provided by U0401. For those devices HANDSET AUDIO is available at J0101-14.
The received audio from the output of the AFIC´s digital volume attenuator is also routed to U0105-
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4 pin 9 where it is amplified 15 dB; this is set by the 10k/68k combination of R0154 and R0155. This
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signal is routed from the output of the Op-amp U0105-4 pin 8 to J0101-14. The control head sends
this signal directly out to the microphone jack. The maximum value of this output is 6.6Vp-p.
8.
6.5 Filtered Audio
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The AFIC has an audio whose output at U0103-22 has been filtered and de-emphasized, but has
not gone through the digital volume attenuator. From AFIC U0103-22 the signal is routed through
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gate U0107-2 and AC coupled to U0106-4. The gate controlled by AFIC port GCB4 (U0103-2)
selects between the filtered audio signal from the AFIC or the unfiltered discriminator signal from the
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IF IC U5201.The output at U0106-4 is then routed to J0400-11. Note that any volume adjustment of
the signal on this path must be done by the accessory.
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Note that discriminator audio DET AUDIO from the IF IC U5201, in addition to being routed to the
AFIC, is also routed to the option connector J0103-5 (See Secure Rx description blocks for further
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information).
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Discriminator or filtered audio, enters the option board at connector J0103-5 and J0103-4. On the
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option board, the signal may be processed and then fed back through (J0103-2) to AUX RX IN of the
AFIC (U0103-6). From then on it follows a path identical to conventional receive audio, where it is
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CENTRE SLICER
U0105-2
22
1
UNATTEN
RX OUT
PL CLOCK 32 57
STROBE
AFIC MICRO
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U0103 CONTROLLER
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U0101
PL
8 DPL PL DPL 27 64
DET AUDIO FILTER LIMITER
IN DECODER
DISCRIMINATOR AUDIO
GEPD_5430 OUT
8.
FROM RF SECTION
(IF IC)
DPL TPL
25 24
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GEPD 5430
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Figure 6.3-4 Receive Signalling Path.
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The receiver audio signal entering the AFIC U0103 at pin 8 first passes through the Tone PL filter or
the Digital PL filter, depending on the PL option selected for the current operating mode. Filtered PL
is then coupled to the PL detector circuit, with detected PL output at U0103-27. At this point the
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signal will appear as a square wave version of the sub-audible signal which the radio received. The
microprocessor U0101-64 will decode the signal directly to determine if it is the tone / code which is
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The unattenuated receiver audio signal from U0103-22 is AC coupled to the input of centre slicer
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circuit U0105-2. The non-inverting input of Op-amp U0105-2 is fed through resistor R0162.
Capacitor C0164 sets a low-pass corner frequency of 3.3kHz. The inverting input of Op-amp U0105-
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2 is fed through resistor R0163. Capacitor C0163 sets a low-pass corner frequency of 16Hz.
During operation, R0163 / C0163 establish an average DC offset level at U0105-2 pin 6 dependent
on the average DC level of the undetected signal to set the “trigger” threshold of U0105-2. R0162 /
C0164 provide high audio frequency roll-off to improve falsing immunity, but passes 600 or 1200
baud signals. The detected output from the centre slicer circuit is buffered and inverted by Q0161
and then coupled to the µP U0101-1 where algorithms perform the final decoding.
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status , it sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0103 which sets up the audio path to the speaker for alert
tones. The alert tone itself is generated by the AFIC.
The allowable internal alert tones are 410, 820, and 1640Hz. In this case a code contained within
the SPI BUS load to the AFIC sets up the path and determines the tone frequency, and at what
volume level to generate the tone. (It does not have to be related to the voice volume setting).
Inside the AFIC, this signal is routed to the alert tone generator; the output of the generator is
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summed into the audio chain just after the RX audio de-emphasis block. Inside U0103 the tone is
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amplified and filtered, then passed through the 8-bit digital volume attenuator, which is typically
loaded with a special value for alert tone audio. The tone exits at U0103-23 and is routed to the
8.
audio PA like receive audio.
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Two crystal filters in the first IF section and two ceramic filters in the second IF section provide the
required selectivity. The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The
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processing of the demodulated audio signal is performed by an audio processing IC located in the
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controller section.
8.
8.1 Front-End Band-Pass Filter and Pre-Amplifier
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A two pole pre-selector filter tuned by the dual varactor diode D3301 pre-selects the incoming signal
(PA RX) from the antenna switch to reduce spurious effects to following stages. The tuning voltage
(FE CNTL VLTG) ranging from 2 volts to 8 volts is controlled by a Digital to Analog (D/A) converter
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(U0731-11) in the controller section. A dual hot carrier diode (D3303) limits any inband signal to
0dBm to prevent damage to the pre-amplifier.
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The RF pre-amplifier is an SMD device (Q3301) with collector base feedback to stabilize gain,
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impedance, and intermodulation. The collector current of approximately 11-16 mA, drawn from the
voltage 9V3, is controlled by a current source composed of Q3302, R3302, R3300, and R3311 -
R3313. In transmit mode the high K9V1 signal fed through diode D3300 switches off the current
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source and in turn the pre-amplifier. In receive mode K9V1 must be low to switch on the current
source. A 3 dB pad (R3306 - R3308 and R3316 - R3318) stabilizes the output impedance and
intermodulation performance.
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A second two pole varactor tuned bandpass filter provides additional filtering to the amplified signal.
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The dual varactor diode D3313 and D3314 are controlled by the same signal which controls the pre-
selector filter.
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If the radio is configured for a base station application, R3318 is not placed and TP3301 and TP3302
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are shorted.
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The signal coming from the front-end is converted to the first IF (45.1 MHz) using a double balanced
schottky diode mixer (D3331). Its ports are matched for incoming RF signal conversion to the
45.1MHz IF using high side injection. The injection signal (VCO MIXER) coming from the mixer
buffer (Q3770) is filtered by the lowpass consisting of (L3333, L3334, C3331 - C3333) and has a
level of approximately 10 dBm.
The mixer IF output signal (RX IF) from transformer T3301 pin 2 is fed to the first two pole crystal
filter Y5201. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q5201 is actively biased by a collector base feedback (R5201, R5202) to a current
drain of approximately 5 mA drawn from the voltage 5V STAB. The output impedance is matched to
the second two pole crystal filter Y5202. A dual hot carrier diode (D5201) limits the filter output
voltage swing to reduce overdrive effects at RF input levels above -27 dBm.
8.3 IF IC (U5201)
The first IF signal from the crystal filters feeds the IF IC (U5201) at pin 6. Within the IF IC the
45.1MHz first IF signal mixes with the second local oscillator (LO) at 44.645MHz to the second IF at
455 kHz. The second LO uses the external crystal Y5211. The second IF signal is amplified and
filtered by two external ceramic filters (FL5201, FL5202). Back in the IF IC the signal is demodulated
in a phase-lock detector and fed from IF IC pin 28 to the audio processing circuit AFIC U0103
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located in the controller section (line DET AUDIO).
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The IF IC also controls the squelch characteristics of the radio. With a few external parts (R5222,
8.
C5229, C5230, R5223) the squelch tail, hysteresis, attack and delay were optimized for the radio. To
set the squelch threshold the signal from IF IC pin 23 (line SQ ATT IN) is attenuated by a
microprocessor controlled audio processing IC AFIC (U0103) located in the controller section. The
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attenuated signal from the AFIC (line SQ ATT OUT) enters the IF IC at pin 20 and is used to create
a squelch indicator signal available at pin 15 (CSQ DET).
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The microprocessor controlled ADAPT signal at pin 22 activates the fast squelch indicator signal at
IF IC pin 18 (FAST SQ). Both squelch indicator signals CSQ DET (pin 15) and FAST SQ (pin 18) are
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combined, weighted by R0111 / R0112 and fed to the microprocessor U0101 pin 15 for
interpretation. From the voltage weighted by the resistors the µP determines whether CSQ DET,
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At IF IC pin 11 an RSSI signal is available with a dynamic range of 70 dB. The RSSI signal is
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The transmitter is able to cover the range from 216 to 246 MHz.
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The radio’s 5-25 W PA is a four stage amplifier used to amplify the output from the exciter to the
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radio transmit level. It consists of four stages in the line-up. The first (Q8510) is a bipolar stage that is
controlled via the PA control line. It is followed by another bipolar stage (Q8520), a MOS FET stage
(Q8530, Q8531) and a final bipolar stage (Q8540). Devices Q8510, Q8520,Q8530 and Q8531 are
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surface mounted. Bipolar Transistor Q8540 is directly attached to the heat sink.
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The first stage (Q8510) amplifies the RF signal from the VCO (line EXCITER PA) and controls the
output power of the PA. The output power of the transistor Q8510 is proportional to its collector
current which is adjusted by a voltage controlled current source consisting of Q8612 and Q8621.
The collector current of Q8510 causes a voltage drop across the resistors R8623 and R8624.
Transistor Q8612 adjusts the voltage drop across R8621 through PA control line (PWR CNTL). The
current source Q8621 adjusts the collector current of Q8510 by modifying its base voltage until the
voltage drop across R8623 and R8624 plus VBE (0.6V) equals the voltage drop across R8621 plus
VBE (0.6V) of Q8611. If the voltage of PWR CNTL is raised, the base voltage of Q8612 will also rise
causing more current to flow to the collector of Q8612 and a higher voltage drop across R8621. This
in turn results in more current driven into the base of Q8510 by Q8621 so that the current of Q8510
is increased. The collector current settles when the voltage over the series configuration of R8623
and R8624 plus VBE of Q8621 equals the voltage over R8621 plus VBE (0.6V) of Q8611.
By controlling the output power of Q8510 and in turn the input power of the following stages the ALC
loop is able to regulate the output power of the transmitter. Q8611 is used for temperature
compensation of the PA output power.
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9.2 PA Stages
8.
The bipolar transistor Q8520 is driven by Q8510. To reduce the collector-emitter voltage and in turn
the power dissipation of Q8510 its collector current is drawn from the antenna switch circuit.
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In transmit mode the base of Q8520 is slightly positive biased by a divided K9V1 signal. This bias
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along with the RF signal from Q8510 allows a collector current to be drawn from the antenna switch
circuit and in turn switches the antenna switch to transmit, while in receive mode the low K9V1
signal with no RF signal present cuts off the collector current and in turn switches the antenna
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switch to receive.
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The following stage uses two enhancement mode N-Channel MOS FET devices (Q8530, Q8531)
and requires for each device a positive gate bias and a quiescent current flow for proper operation.
The voltages of the lines BIAS VLTG and BIAS VLTG 2 are set in transmit mode by two Digital to
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Analog (D/A) converters (U0731-4, U0731-11) and fed to the gates of Q8531 and Q8530 via two
resistive dividers. The bias voltages are tuned in the factory. If one or both transistor are replaced,
the bias voltages must be tuned with the Service Software (RSS). Care must be taken, not to
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damage any device by exceeding the maximum allowed bias voltage. The collector currents are
drawn from the supply voltage A+ via L8531 and L8532.
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The final stage uses the bipolar device Q8540 and operates off the A+ supply voltage. For class C
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operation the base is DC grounded by two series inductors (L8533, L8534). A matching network
consisting of C8541-C8544 and two striplines transform the impedance to 50 Ohms and feed the
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directional coupler.
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The directional coupler is a microstrip printed circuit which couples a small amount of the forward
power off the RF power from Q8541. The coupled signal is rectified to an output power proportional
negative DC voltage by the diode D8553 and sent to the power control circuit in the controller
section via the line PWR DETECT for output power control. The power control circuit holds this
voltage constant, thus ensuring the forward power out of the radio to be held to a constant value.
The antenna switch is switched synchronously with the K9V1 voltage and feeds either the antenna
signal coming through the harmonic filter to the receiver or the transmitter signal coming from the PA
to the antenna via the harmonic filter.
In transmit mode, this K9V1 voltage is high and biases Q8520 and, along with the RF signal from
Q8510, allows a collector current to be drawn. The collector current of Q8520 drawn from A+ flows
via L8542, L8541, directional coupler, D8551, L8551, D8631, L8631, R8616, R8617 and L8611 and
switches the PIN diodes D8551 and D8631 to the low impedance state.
D8551 leads the RF signal from the directional coupler to the harmonic filter. The low impedance of
D8631 is transformed to a high impedance at the input of the harmonic filter by the resonant circuit
formed by L8551, C8633 and the input capacitance of the harmonic filter.
In receive mode the low K9V1 and no RF signal present from Q8510 turn off the collector current of
Q8520. With no current drawn by Q8520 and resistor R8615 pulling the voltage at PIN diode D8631
to A+ both PIN diodes are switched to the high impedance state. The antenna signal, coming
through the harmonic filter, is channelled to the receiver via L8551, C8634 and line PA RX.
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A high impedance resonant circuit formed by D8551 in off state and L8554, C8559 prevents an
influence of the receive signal by the PA stages. The high impedance of D8631 in off state doesn´t
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influence the receiver signal.
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9.5 Harmonic Filter
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The transmitter signal from the antenna switch is channelled through the harmonic filter to the
antenna connector J8501.The harmonic filter is formed by inductors L8552, L8553, and capacitors
C8551 through C8554. This network forms a low-pass filter to attenuate harmonic energy of the
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transmitter to specifications level. R8550 is used for electro-static protection.
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The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
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MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
using a Digital to Analog (D/A) converter (U0731). The microprocessor writes the data into the D/A
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converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
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time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
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The microprocessor controls K9V1 ENABLE (U0101-6) to switch on the first and the second PA
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stage via transistors Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the
collector current of the second PA stage. In TX mode the front-end control D/A (U0731-11) is used
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for BIAS VOLTAGE 2 (via R0736) and K9V1 ENABLE pulls signal FE CNTL VLTG to ground via
Q0743. PA DISABLE, also microprocessor controlled (U0101-54), sets BIAS VLTG (U0731-4) and
VLTG LIMIT SET (U0731-13) via D0731 and BIAS VLTG 2 via D0733 in receive mode to low to
switch off the biases of the MOS FET devices Q8530, Q8531 and to switch off the power control
voltage (PWR CNTL).
Through an Analog to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA control
voltage (PWR CNTL) during the tuning process.
The ALC loop regulates power by adjusting the PA control line PWR CNTL to keep the forward
power voltage PWR DETECT at a constant level.
Op-amp U0701-2 and resistors R0701 to R0703 and R0731 subtract the negative PWR DETECT
voltage from the PA PWR SET D/A output U0731 pin 2. The result is connected to Op-amp inverting
input U0701-4 pin 9 which is compared with a 4.6 volt reference VAG present at noninverting input
U0701-4 pin 10 and controls the output power of the PA via pin 8 and control line PWR CNTL. The
4.6 volt reference VAG is set by a resistive divider circuit (R0171, R0172) which is connected to
ground and 9.3 volts, and buffered by Op-amp U0105-1.
During normal transmitter operation the voltages at the Op-amp inputs U0701-4 pins 9 and 10
should be equal to 4.6 volts and the PA control voltage output at pin 8 should be between 4 and 7
volts. If power falls below the desired setting, PWR DETECT becomes less negative, causing the
output at U0701-2 pin 7 to decrease and the Op-amp output U0701-4 pin 8 to increase.
A comparator formed by U0701-4 increases the PA control voltage PA CNTL until PWR DETECT is
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at the desired level. The power set D/A output voltage PA PWR SET (U0731-2) at U0701-2 pin 5
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adjusts power in steps by adjusting the required value of PWR DETECT. As PA PWR SET (U0731-
2) decreases, transmitter power must increase to make PWR DETECT more negative and keep the
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inverting input U0701-4 pin 9 at 4.6 volts.
Loop frequency response is controlled by Op-amp feedback components R0712 and C0711. Op-
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amp U0701-3 compares the power control voltage PWR CNTL divided by resistors R0717 to R0719
with the voltage limit setting VLTG LIMIT SET from the D/A converter (U0731-13) and keeps the
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control voltage constant via Q0711 if the control voltage, reduced by the resistive divider (R0717 to
R0719), approaches the voltage of VLTG LIMIT SET (U0731-13).
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Rise and fall time of the output power during transmitter keying and dekeying is controlled by the
comparator formed by Op-amp U0701-3.
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During normal transmitter operation the voltage at U701-3 pin 13 is higher than the voltage at pin 12
causing the output at pin 14 being low and switching off transistor Q0711. Diode D0732 reduces the
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bias voltages BIAS VLTG, BIAS VLTG 2 for low control voltage levels.
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The temperature of the PA area is monitored by Op-amp U0701-1 using thermistor R8641 (located
in the PA section). If the temperature increases, the resistance of the thermistor decreases,
decreasing the voltage PA TEMP. The inverting amplifier formed by U0701-1 amplifies the PA TEMP
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voltage and if the voltage at Op-amp pin 1 approaches 4.6 V plus the voltage (ON) across D0721,
U701-1 simulates an increased power which in turn decreases the power control voltage until the
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voltage at U0701-4 pin 9 is 4.6V again. During normal transmitter operation the output voltage of
Op-amp U701-1 pin 1 is below 4.6V. Diode D8601 located in the PA section acts as protection
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The Reference Oscillator (Y3702) contains a temperature compensated crystal oscillator with a
frequency of 16.8 MHz. An analog to digital (A/D) converter internal to U3701 and controlled by the
microprocessor via serial interface (SRL) sets the voltage at the warp output of U3701 pin 16 to set
the frequency of the oscillator. The output of the oscillator (pin 2 of Y3702) is applied to pin 14
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(XTAL1) of U3701 via a RC series combination.
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In applications were less frequency stability is required the oscillator inside U3701 is used along with
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an external crystal Y3701, the varactor diode D3702, C3708, C3710 and R3704.
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10.2 Fractional-N Synthesizer (U3701)
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The FRAC-N synthesizer IC (U3701) consists of a pre-scaler, a programmable loop divider, control
divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
modulation, a balance attenuator to balance the high frequency analog modulation and low
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frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
finally a super filter for the regulated 9.3 volts.
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A voltage of 9.3V applied to the super filter input (U3701 pin 22) supplies an output voltage of 8.6
VDC at pin 18. It supplies the VCO (Q3741 / Q3751), VCO modulation bias circuit (R3714) and the
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synthesizer charge pump resistor network (R3723, R3724). The synthesizer supply voltage is
provided by the 5V regulator U3801.
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In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U3701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
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(D3701-1-3, C3716, C3717). This voltage multiplier is basically a diode capacitor network driven by
two (1.05 MHz) 180 degrees out of phase signals (U3701-9 and -10).
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Output LOCK (U3701-2) provides information about the lock status of the synthesizer loop. A high
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level at this output indicates a stable loop. IC U3701 divides the 16.8 MHz reference frequency down
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
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The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U3701-5),
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clock line SPI CLK (U3701-6), and chip enable line FRACN CE (U3701-7).
The Voltage Controlled Oscillator (VCO) uses 2 colpitts oscillators, FET Q3741 for transmit and FET
Q3751 for receive. The appropriate oscillator is switched on or off by FRAC-N IC output AUX3
(U3701-1) using transistors Q3742 and Q3752. In RX mode AUX3 is nearly at ground level and
Q3742 enables a current flow from the source of FET Q3751 while Q3752 is switched off. In TX
mode AUX3 is about 5V DC and Q3742 is switched off. Q3752 is switched on and enables a current
flow from the source of FET Q3741 while Q3751 is switched off. When switched on the FETs draw a
drain current of 8 mA from the FRAC-N IC super filter output. The frequency of the receive oscillator
is mainly determined by L3752, C3752, C3754 - C3756 and varactor diodes D3751 / D3752.
Diode D3754 controls the amplitude of the oscillator. The frequency of the transmit oscillator is
mainly determined by L3734, C3736 - C3740 and varactor diodes D3732 / D3733. Diode D3739
controls the amplitude of the oscillator. With a steering voltage from 3V to 10V at the varactor diodes
the RX frequency range from 181.1 MHz to 219.1 MHz and the TX frequency range from 136 MHz
to 174 MHz are covered. In TX mode the modulation signal coming from the FRAC-N synthesizer IC
(U3701 pin 28) modulates the TX VCO via varactor diode D3731.
Both oscillator outputs are combined and buffered by the VCO Buffer Q3760. Q3760 draws a
collector current of 13 mA from the stabilized 5V (U3801) and drives the Mixer Buffer Q3770. Q3770
draws a collector current of 17 mA from the 9V3 voltage and drives the PA Buffer Q3780 (Pout =
13dBm) and the Pre-scaler Buffer Q3790. Q3790 draws a collector current of 8 mA from the
stabilized 5V (U3801) and drives the pre-scaler internal to the FRAC-N IC. In transmit mode Q3780
is switched on by the K9V1 signal and draws a collector current of 19 mA from the K9V1 voltage.
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The injection signal VCO MIXER with a level of 10dBm feeds the mixer through R3774. The buffer
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stages Q3760, Q3770, Q3780 and the feedback amplifier Q3790 provide the necessary gain and
isolation for the synthesizer loop.
8.
10.4 Synthesizer Operation
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The complete synthesizer subsystem works as follows. The combined output signal of the RX VCO
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(Q3751) and TX VCO (Q3741) is buffered by VCO Buffer Q3760, Mixer Buffer Q3770 and Pre-scaler
Buffer Q3790. To close the synthesizer loop, the collector of Q3790 is connected to the PREIN port
of synthesizer U3701 (pin 20). The output of (Q3770) also provides signals for the mixer (via VCO
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MIXER) and the PA Buffer (Q3780).
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The pre-scaler in the synthesizer (U3701) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
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of the loop divider is connected to the phase detector, which compares the loop divider´s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y3702).
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The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
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The charge pump outputs a current at pin 29 (I OUT of U3701). The loop filter (which consists of
R3715 - R3717, C3723 - C3725, C3727) transforms this current into a voltage that is applied to the
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varactor diodes D3732, D3733 (TX), D3751, D3752 (RX) and alters the output frequency of the TX
VCO (Q3741) and RX VCO (Q3751). The current can be set to a value fixed in the FRAC-N IC or to
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a value determined by the current flowing into CPBIAS 1 (U3701-27). The current is set by the value
of R3723 and R3724. The selection of the two different bias sources is done by software
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programming.
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To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT line (U3701-31) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the FRACN CE line. When the synthesizer is within the lock range the current is
determined only by the resistors connected to CPBIAS 1 or the internal current source.
A settled synthesizer loop is indicated by a high level of signal LOCK DET (U3701-2). This signal is
routed to µP U0101-17 for further processing.
In order to modulate the PLL the two spot modulation method is utilized. Via pin 8 (MODIN) on
U3701 the audio signal is applied to both the A/D converter (low freq path) as well as the balance
attenuator (high freq path). The A/D converter converts the low frequency analog modulating signal
into a digital code that is applied to the loop divider, thereby causing the carrier to deviate.
The balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency
modulating signals. The output of the balance attenuator is present at the MODOUT port (U3701-
28) and connected to the VCO modulation diode D3731.
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Chapter 6.4
PCB/Schematic Diagrams and Parts Lists
Table of Contents
t
Description Page
ne
216-246MHz Diagrams and Parts Lists
8.
PCB Layout Component Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
16
PCB Layout Solder Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
80ch Model, Closed Controller Schematic Diagram 1 of 2 . . . . . . . . . . . . . . . . . . . . . . 3
io
80ch Model, Closed Controller_IO Schematic Diagram 2 of 2 . . . . . . . . . . . . . . . . . . . 5
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/6
ad
Supply Voltage Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
yr
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Control Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
.m
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Amplifier 5-25W Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
w
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
w
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RX-FE Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
tp
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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R105
R138
R137
C104
C5230
R5223
J101
R115
C5238
4 3 C105 C5229
C103
L114 E3701
Y114
C3726 R3724 R3703
C116 C117 2 1 R5222
Q137
18
C3801
C3707
Q114 C137 R160 R3723
C115 2 3
R127
R104 C110 C3727 C5226
4
R125
R102 R3705
C127
C114
5
C126
C125
33 17 R126 R103
R114
C118 R116 8 7 Y3702
8 5 R5221
FL5202
C3702 R3702
C3802
C194
D101
R119 Q138 U3801
R113 1 C5235
C134
C102 4
C3701
2
U104 1 4 L5206
D3702
R3701 C3713
R5217
C3709
R110
R134
U101
1
R106 C3724 R5206
14 1 16 9 C3706
R107 U102 C3803
h
1
R109 8 R3801 FL5201
C101 R3709
R108 R131 R130 C5214
Q161 R167
49 1 C181 6
R101
C3704
2
C162
C163 R163 R5212 C5213
4
tt p
R122
R121
C5212 1
R192
R120
C121R123
C3735 D3731
R128
R162 16 9
D3733
C3731
R187
L3733
C161 U107 Y5201 Y5202
R5211
R166 R164 1 C634 L5201
C3333
C622
8 L3732 C3733
R161
R191R124
C122
C164 C171 R185 5 4
C635 D3732
C3734
C3766
:/ R3769
R172
R165
L5211
R3731 T3302
1
2
3
1
2
3
R171 R183 C131 L3731
R184
L3334
1 Y5211
C3739 C3737
2 3
C3738 C3736
C184
R186 C631 Q3742
L3734
C633
C182 4
C5211
4 R188 1 R3767
/
1 U631 R3739
C132
w
C641
C3317
C3316
C3315
C632
1 5 8 C191
C3320
U105 R604 R3763
L3741
L3333
8 5
R3752
Q601
R3743
8 E3301
C3307
14 D621 D3739 U3741 R3741
R601 C3763
C3319
D731 D3331
C3306
D3311 C3305
C3304
C3744 4 L3331 R3302 C3310
C3331
Q731
w
L3761
C141
L3750
C155 C3745 R3331
R3308
C3353
C3354
R3315
C3311
C3352
R155 C172 C142 R3742
C3351
Q3301
R621
L3302
D3313
R143
R3306
D3752 D3751 L3754
L3751
R154 9 8 C3764
R721
R3314
D3314
C3757
Q741
D3312
R135 D733
C3761
R146 R142 C3754
R3753
L3332 R3307
C154 Q3760
C3752
w
R741
3 2 1
R145
R3305
D3754 Q3751
C3334 C3314 C3302
T3301 R3303
C3309
C3355 C3312
R735 C3762
R156
C3318
R3762 C3308
C3301
7 L3752 R3754 C3313
C721 L3304 L3303 R3304 D3303 L3301 L3300
C133
1 R153 C3756
C3755
.m
U106 Q742 R3321 C3321
C156
C732
R732
R715 E3731
U601
C151
y
R404 R405 Q401
C403 C8502
L401
L402
r
R8501 C8503 C8547 C8633
C404 R407 R401 C8611 C8634
R8624
D8551
R8502
a
C8528
C8622 R8623
C419 C420
R406
R402 C8546
C8524
D8631
L8554
L8501
Q8621
C407
C8613
L8503
C401 R8541
d
C402 C8501 L8551
C8632
C8559
C8617
C8616
L8532
C8623
C8530
L8541 C8544
L8631
C8548
L8542
i
8 5
Q8510 C8532
o
1
L8611
4
C8642
R8514 4
9
L8531
1
C8511
1
R8614
C8553
C8513 1 C8555
C8512
R8641
R8512 C8552
6
U401 3 Q8520 1 L8553
R8511 C8541
C8521
L8552
C8551
C8620
C8534
8
C8535 C8536
L8600 C8600
2 C8554
.
Q421 SH8501
R426
R8550
VR445
C8533
R427 C8529
n
C8542
C445
VR411 R432
C455 VR431
VR420
2 3
t
VR464 R446
C405
C422 2
C412 C431 C8543
C464
R454
16 2
J400
GM950EI008-A
VR471
R8531
VR421
R451 D8601 C8522
R456
R8522
VR435
1
6
R455 R450
Q8530
C8525 L8533
3
1
2
VR450
R8525
C450
Q8540
4
2
R8527
h
C8601
L8534
C8602
L8601
C8603
Q8531
3
1
2
C8527
C8538
tt p
R8523
5
R441 R443
TP8203
C8604 C8523
C441
D482
Q441
Q442
C411 Q411
C8539
:/
Q482
L8539
R411
C463
R477 R442
R414 R412 R8617
R464
/
R483 R8615
Q471 R478
Q412 C462 C8619 C8556
R415
TP8202
R8621
Q462 C8631
w
R475 Q8611 R8532 R8535
C413 R463 Q481 R482 R8616 C8618 C8531 R8551
R8613 C8615
TP8201
R413 R8552
R8553
R465
D481
C8558
R8612 Q8612
Q461
C8614
R8529
D8553
R437
R462
w
R8528 R8533 R8534 TP8204
R436
R8611
R461
Q433
C8612
R8521
D471
w
C438
R472 R100
R435
R438 R471
C435
2 8
C471
R738
C733
R439
R716
J102 R712
1 R718
.m
C716
R719
C439
TP3732
C714 R717 D3300
C711
R713
R704
C738
Q711
R714
R3330
C603
E3732
C604
R3318 R3312
8
C723 C712
14 C705 C3303
y
R3775
C3786
R705
R3776
R3785
Q3780
C3781 R3779
R3311
R711 U701 R3786C3782 C3322
R3317
1 R701
R3778 C3777
R3316
R3774 R3777
7 R3782 C3300
VR641
Q3302
D721
C741
R702
r
C3780 C3775
C605
C722
C3785
R724
a
R737
R3795
C3774
TP3302
TP3301
L3781
C703 C601
R722 Q732
L3773
R703 R606 L3783
C613
d
C3784
TP111
R725
R736
D631
R631 R3792
i
R3791 L3768
R3793
R3768
Q3790
R632
R3772
C3772
C3773
C3792
o
L5202
C5202
C3791
C5200
R5207
Q611 C3790 C5201
C5203
1
C5205
C5206
D5201
R3740
R3714
C3743
L5203
TP3704
C3725 R3715 R5201
C611
D611
6
R3716R3718 C3722 R5205
R614 Q5201 C5208
R5202
C5204
R3717 R5204
R3712
R3713
C5207
R5203
C174
L3742 C3723
8
C5223
TP107
C170
C5222
C5228
TP110
TP105
L170
R3708
C5221
.
TP3701
C149
C3712
TP108
R150
TP104
D3701
n
C3719
C146
5 36
6 1 35 E3703
R147
12
C5215
5
C145 C148 C3703
R3704
e
C3711
C3716
C5225
R149 C3710
C173
R3710
TP3702
E3702
R3711
TP106
C3721
C3715
t
U5201
C147 U103
1
C196
C3717
TP109
C3708
C5224 C5216
C157
C199
R148
Y3701
C5236
R175
R139
C198
17
9
26 C3720 C5239
15
U3701
C175 16 25 C153 C3705
VR160
TP3703
C5227
L194
2 8
23
30
R173 C112
VR3701
R181
R182
C150
C5231
C109
C176
C152
J103
1 L195 R111 25
1
7 C5237
VR118
C3718
R112 C5233
R117
C111 R5216
R118
C119
R157 R5225
C5234
C5232
R5224
C5220
C197
GM950EI007-O
J0102
MIC_PTT
+5V +5V
1
2 SPI_MISO R116 R117 R118 +5V
3 J0102_3 (GP6) 270 270 4.7K R113
4 SPI_MOSI C118 C119
5 10K
OPTION_BD_CE 470pF 470pF +5V
6 VR118 C164 L170
SPI_CLCK_SRC 4700pF 33uH
7 R164 C170
J0102_7 (GP4) +2V5 1uF
8 NU
+5V
R114 R167
47K R161
L114 4.7K
OUT 4
33uH 100K
Q114 C162
R162 0.1uF
GND1 C116 R165 10K
R115 3 3.6pF Q161 47K 11
1.8MEG 5 C174
GND UNATTEN_RX_OUT 0.1uF
17
VDDL 38
2 C114 C161
1
7 R150
IN
33pF
VDDH1
VDDH2
4 6 0.1uF R183
h
R163 51K
R166 5
1
Y114 U105-2 100K 10K +5V
32 PBIAS 2
C115 10K HIGH_LOW_BAND_5
C163 GCB4
TP108 22pF 31 PL_CLK 3
0.1uF SPI_CLCK_SRC GCB5 HIGH_LOW_BAND
+5V R110 30 SERIAL_CLK U103 40
10K SPI_MOSI GCB3 AUDIO_PA_ENABLE
C117 C105 4 SERIAL_DATA 39
tt p
33pF +5V R105 0.1uF 6 WDT_DISABLE
GCB1
9
B+_CONTROL
10K AUX_RX_IN PRE_EMPHASIS SQ_ATT_OUT_5
R107 7 AUX_RX 18 R181
100 8 SQ_ATTEN_OUT 19 30K SQ_ATT_OUT
TP107 R108 +5V RX_IN
R109 10 4BIT_ATTEN_OUT 20 R182 MOD_IN_5
47K PL
47K R119 11 5BIT_ATTEN_OUT 36 10K MOD_IN
TX_IN
:/
1K ADAPT_5 +2V5 XTAL_OUT
VDD 55
VRH 22
VRL 21
35
44
48
60
61
12 VAG_VOLUME 29 C173
RESET ADAPT C131 (SOURCE) TIMING_CAP
13 EXT_ALERT 27 1uF
NC6
NC7
NC8
NC9
NC10
PL_DECODER C199
0.1uF
16
29 U107 14 AUX_TX 25 470pF
STRA_AS 28 C102 PL_CAP C198
/
+5V CLK_E 30 6 15 4BIT_ATTEN_IN 24 470pF
VCC
C104 STRB_RW* 470pF EN SQ_ATT_IN_5 DPL_CAP
R106 .01uF 31 12 16 5BIT_ATTEN_IN 23
EXTAL X0 RX_OUT
w
2.2K 33 1 14 28 SQ_ATTEN_IN 22 C196
XTAL PA0_IC3 13 X 11 SQ_ATT_IN 35 UNATTEN_RX 21
U101 64 U105-4 VAG_BYPASS 470pF
PA1_IC2 +2V5 X1 A TX_OUT RESET
46 IRQ 63 2 33 XTAL_IN 34
PA2_IC1 PA2 (GP4_IN) R121 Y0 C197 RESET
45 XIRQ 62 160K C121 11 15 470pF AFIC_CE CHIP_SELECT
PA3_OC5_OC1 Y
GND
C103 TP106 43 RESET 59 R122 .039uF 12 1 10
NC
3.3uF PA4_OC4_OC1 68K 5 Y1 B C148
58 14
R102 PA5_OC3_OC1 Z0 4 470pF R139 C150
27 57 13 4 R124
26
37
4.7K MODA_LIR* PA6_OC2_OC1 R123 Z 9 240K C153 C152 0.47uF
25 56 6.8K 3 2_1MHZ_5 0.1uF 1uF
USW_+5V_CL MODB_VSTBY PA7_PA1_OC1 100K Z1 C
GND
VEE
TP109
R111 C122 2_1MHZ
w
CSQ_DET_5 13 PE0_AN0 PC0_AD0 34 PC0 (GP2_OUT) R173
33K 4700pF TP110
15 36 +5V
7
CSQ_DET PE1_AN1 PC1_AD1 PC1 (GP1_IN) 0
FAST_SQ_5 17 PE2_AN2 PC2_AD2 37 PC2 (GP3_IN) C149
19
(IGNITION_SENSE) 38 33pF R175
FAST_SQ PE3 PE3_AN3 PC3_AD3 PC3 (GP6_IN) R136
14
14 39 R130 150K C175 C176
.m
LOCK_DET_5 R112 BATTERY_VOLTAGE PE4_AN4 PC4_AD4 C134
68K 16 40 0 1000pF 3.3uF VCC
LOCK_DET PE5_AN5 PC5_AD5 PC5 (GP5_IN) 33K 0.1uF
18 PE6_AN6 PC6_AD6 41 R131 U104-5
VLTG_LIMIT R135 2 4 0
C110 20 PE7_AN7 PC7_AD7 42 GND
470pF FLAT_TX_AUDIO 1
7
47 12 47K 3
C111 PD0_RXD PB0_A8 C185
470pF 50 11 11 U106-1 100pF
PD1_TXD PB1_A9 +2V5 R188
y
C109 SPI_MISO 51 10 0
PD2_MISO PB2_A10
470pF 52 9 R189
PD3_MOSI PB3_A11 82K R147 12
53 PD4_SCK PB4_A12 8 PB4 (GP5_OUT)
54 7 R148 180K C147 11
r
+5V PD5_SS* PB5_A13 K9V1_ENABLE_5 PB5 (GP3_OUT) U106-3
C112 6 470K 1000pF 13 U104-4
23 VSS1
24 VSS2
49 VSS3
PB6_A14 K9V1_ENABLE
NC1
NC2
NC3
NC4
NC5
5 9 4
a
1000pF PB7_A15 PB7 (GP6_OUT) C184
+5V C181 R185 R187 8
30K 0 1uF C146
TP105 TP104 R120 R184 10
2
3
4
26
32
d
27K VAG
R128 C182 0
10K 0.1uF DET_AUDIO_5
R100 9V3 9V3
i
0
PA_DISABLE DET_AUDIO +5V +5V
o
+5V
FLT_A+ PA_ENABLE_5 R157
R104 C157 DAC_CE_5
+5V 470pF 15K
J0101 33K DAC_CE DAC_CE
C101
FLT_A+ 17
+5V 9
D101
1 6
R101
10K 0.1uF J0103
5
7
RX_AUDIO_SEND
GP3
C145
SPI_MOSI
SPI_CLCK_SRC
SPI_DATA_SRC_5
SPI_CLCK_SRC_5
SPI_DATA_SRC
SPI_CLCK_SRC
VCC 16
(GP3) J0103_7 1000pF
R103 (GP5) J0103_8 8 GP5 L194
C125 Y0 15 6 270nH SPI_CLK_5
10K 0.1uF R125 +5V 9V3 GROUND
C126 200K 6 Y1 14 EEPROM_CE SPI_CLCK_SRC SPI_CLK
8
SPI_MOSI 0.1uF 4 EN_CS1 Y2 13 AFIC_CE R145
5 EN_CS2 R146 L195
BUS+ 15 BUS+ SPI_CLCK_SRC Y3 12 DAC_CE 30K 270nH SPI_DATA_5
R126 EN_CS3 11 R141 0 R144
ANALOG_1 10 200K Y4 FRACN_CE SPI_MOSI SPI_DATA
.
8 GND
1K
LED_CE 12
LED_CE 1 3 A1 Y7 7 6 4
1 TX_AUDIO_RET
3 +5V A2 LCD_CE 7
SPI_DATA_BUF 6 U104-1 2 R160 C142 R143 5 3 TX_AUDIO_SEND C194
100 47K
e
6 47K
LED_CLCK_BUF 5 U104-2 5
LCD_CLCK_BUF 8 R134
10K R138 C156 C155
7 9 4.7K 33pF
47uF
GND 19 8
20 U104-3 10
C133 C191 R155
0.1uF +5V +5V 0.1uF R156 68K TP111
C132 0
HOOK 3 9V3 0.1uF C154
9V3 R154
MIC_PTT 4 MIC_PTT R153 R191 10K 0.1uF
C137 4 9
.01uF U106-4 4.7K 10K VAG_5 RX_AUDIO
8
8
5 1uF
MIC SI R172 C171
MIC 16 SPI_MOSI 47.5K 10uF
R151 GM950EI006-O
4
HANDSET_AUDIO 14 U108
INT_SPKR+ 1 INT_SPKR+ 10K 9V3
INT_SPKR- 2 INT_SPKR-
ON_OFF_CONTROL 18 ON_OFF_CONTROL
R192
0
C0101 2113743E20 0.1uF, 10% C0153 2113743E20 0.1uF, 10% C0401 2113743A19 100nF 16V C0472 2113741F17 470pF 50V
C0102 2113741F17 470pF 50V C0154 2113743E20 0.1uF, 10% C0402 2113741F37 3.3nF 50V D0101 4813833C02 DIODE DUAL SOT
MMBD6100
h
C0103 2311049A42 TANT CP 3.3uF 10% 6V C0155 2113740F39 33pF 5% 50V C0404 2311049A99 47uF
J0101 0902636Y01 Connector Flex Side Entry
C0104 2113741F49 10nF 50V C0157 2113741F17 470pF 50V C0405 2113741F25 1nF 50V
tt p
J0102 0904424J06 CONNECTOR, DOUBLE
C0105 2113743E20 0.1uF, 10% C0161 2113743E20 0.1uF, 10% C0406 2113741F25 1nF 50V ROW
:/
C0109 2113741F17 470pF 50V C0162 2113743E20 0.1uF, 10% C0407 2109720D14 CER LOW DIST 100nF J0103 0904424J06 CONNECTOR, DOUBLE
/
ROW
C0110 2113741F17 470pF 50V C0163 2113743E20 0.1uF, 10% C0411 2113741F49 10nF 50V
w
J0400 2804503J01 Accessory Connector 16
C0111 2113741F17 470pF 50V C0164 2113741F41 4.7nF 50V C0412 2113741F17 470pF 50V
w
L0114 2460578C43 INDUCTOR CHIP 33.0UH
C0112 2113741F25 1nF 50V C0170 2311049A07 TANT CP 1uF 10% 16V C0413 2113741F49 10nF 50V
L0170 2462587K26 CHIP IND 33000 NH
w
C0114 2113740A41 33pF 5% 50V C0171 2311049J23 TANT CP 10uF 10% 6V C0414 2113741F17 470pF 50V
L0194 2462587Q40 COIL CHIP 270nH
C0115 2113740A37 22pF 5% 50V C0172 2311049A07 TANT CP 1uF 10% 16V C0419 2113741F25 1nF 50V
.m
L0195 2462587Q40 COIL CHIP 270nH
C0116 2113740G16 Ceramic Chip 3.6 P C0173 2311049A07 TANT CP 1uF 10% 16V C0420 2113741F25 1nF 50V
L0401 2484657R01 Ferrite Bead
y
C0117 2113740A41 33pF 5% 50V C0174 2113743E20 0.1uF, 10% C0421 2113741F17 470pF 50V
L0402 2484657R01 Ferrite Bead
r
C0118 2113741F17 470pF 50V C0175 2113741F25 1nF 50V C0422 2113741F17 470pF 50V
a
Q0114 4880214G02 MMBT3904
C0119 2113741F17 470pF 50V C0181 2113743E20 0.1uF, 10% C0431 2113741F17 470pF 50V
d
Q0137 4880048M01 TSTR NPN DIG 47k/47k
C0121 2113743K05 39nF 16V C0182 2113743E20 0.1uF, 10% C0435 2113741F49 10nF 50V
+5V +5V
+5V +5V
R413 R412
(GP3) R431
47K
R432
4.7K
R461 R462
47K 4.7K 47K 4.7K
PC1
PC5
Q461
(GP5) PC2 Q412
(GP3) Q431
47K
C461
.01uF 47K C413 47K 47K
.01uF
47K 47K
h
R414 C431
R463 470pF VR431
270 VR464 270
C464 C412
470pF 470pF VR411
R465 R411
R464
0 10K
10K
tt p
+5V FLT_A+
PB4 PB5
C463
.01uF R415
C411
.01uF
Q411
D471
(GP3) R442
4.7K
R443
4.7K
:/
0
EMERGENCY_CONTROL
R441 Q441
J0103_8 10K
/
J0103_7 C442
PC0 470pF
w
C462 C414 Q442 VR441
470pF 470pF +5V C441
FLT_A+ .01uF
(GP4)
w
R474 R475
+5V 47K 4.7K
R472 R477
0 3.3K
w
PA2 R444
R436 R437 R478 270
47K 4.7K 0 BUS+
(GP6) R471 R473
Q471
47K
.m
0 68K 47K C444
PC3 Q432 470pF
R476
C435 47K 270 VR444
.01uF C472
VR435 470pF VR471
47K
R435 J0102_7
y
270
C436 C471
470pF 470pF JO40D
R438
r
10K 3 (IN)
PB7 4 (OUT)
a
6 BUS+
C438 Q433 8 GP3 (IN/OUT)
.01uF 12 GP5 (IN/OUT)
d
R439
0 14 GP6 (IN/OUT)
15 RSSI
16 EXT_SPKR+
i
1 EXT_SPKR-
J0102_3 MIC 2 EXTERNAL_MIC_AUDIO
o VR421 10 IGNITION
C439 9 GP4 (IN)
C421 FLAT_TX_AUDIO 5 FLAT_TX_AUDIO
470pF 470pF
FLT_A+
1 6
VR445
C445
0.47uF
R446
C446
470pF
C454
11
13
7
FLT_RX_AUDIO
ANALOG_GND/SW_B+
GROUND
100K R456
0 470pF
8
R455
R401 C401 C407 C450 R450 9V3 FLT_A+ 0
4.7K 0.1uF 0.1uF 47uF Q481
560
+5V
.
RX_AUDIO FLT_RX_AUDIO
C402
n
C419
3300pF 1000pF R426 C451 R481 D481
R402 R451 1K
SW_B+ U401 VR450 470pF
7
+5V 0 R482
R406 PE3 560
9 INV OUT1 4 L401
Q421 Q482
22K C405 (IGNITION_SENSE)
t
1 NINV R454
R407 3 1000pF 1K
15K RR FLT_A+
R404 47K
8 M_SS OUT2 6 VR419
10K
GND2
GND1
R423
4.7K 470pF
C404 D482
C403 R422 VR454
0.1uF 47uF C420 1000pF R483
10K
1000pF C406 1.5K
IGNITION_CONTROL
VR420
C422 R425
470pF 10K
INT_SPKR-
VR422
INT_SPKR+
9V3 9V3
GM950EI009-O
FLT_A+ FLT_A+
+5V +5V
R0103 0662057A73 10k 1/16W 5% R0142 0662057A49 1k 1/16W 5% R0405 0662057A73 10k 1/16W 5% U0102 5113805A30 IC 10F8 DCDR/REMUX
74HC138
R0104 0662057A85 33k 1/16W 5% R0143 0662057A89 47k 1/16W 5% R0406 0662057A81 22k 1/16W 5%
U0103 5105165R77 CHIP CAR 40 PIN W/63G
R0105 0662057A73 10k 1/16W 5% R0144 0662057A89 47k 1/16W 5% R0407 0662057A77 15k 1/16W 5%
U0104 5105492X36 74AC08 4 AND GATES
R0106 0662057A57 2k2 1/16W 5% R0145 0662057A84 30k 1/16W 5% R0411 0662057A73 10k 1/16W 5%
U0105 5183222M49 IC QUAD OPAMP_3403_
h
R0107 0662057A25 100 1/16W 5% R0147 0662057B04 180k 1/16W 5% R0412 0662057A65 4k7 1/16W 5%
U0106 5183222M49 IC QUAD OPAMP_3403_
R0108 0662057A89 47k 1/16W 5% R0148 0662057B14 470k 1/16W 5% R0413 0662057A89 47k 1/16W 5%
tt p
U0107 5184704M60 IC-CMOS 04M60 ANALOS
R0109 0662057A89 47k 1/16W 5% R0149 0662057B47 0 1/16W R0414 0662057A35 270 1/16W 5%
U0108 5105462G78 IC EEPROM !&K SPEI
:/
R0110 0662057A73 10k 1/16W 5% R0150 0662057A90 51k 1/16W 5% R0422 0662057A73 10k 1/16W 5% CMOS
/
R0111 0662057A85 33k 1/16W 5% R0151 0662057A73 10k 1/16W 5% R0425 0662057A73 10k 1/16W 5% U0401 5109699X01 AUDIO PA TDA1915C
w
R0112 0662057A93 68k 1/16W 5% R0152 0662057A73 10k 1/16W 5% R0426 0662057A89 47k 1/16W 5% VR0118 4813830A14 DIODE 5.1V 5% 225mW
w
R0113 0662057A73 10k 1/16W 5% R0154 0662057A73 10k 1/16W 5% R0427 0662057B47 0 1/16W VR0411 4813830A27 DIODE 14V 5% 225mW
w
R0114 0662057A65 4k7 1/16W 5% R0155 0662057A93 68k 1/16W 5% R0431 0662057A89 47k 1/16W 5% VR0421 4813830A27 DIODE 14V 5% 225mW
R0115 0662057B28 1.8M 1/16W 5% R0156 0662057B47 0 1/16W R0432 0662057A65 4k7 1/16W 5%
.m
VR0422 4813830A14 DIODE 5.1V 5% 225mW
R0116 0662057A35 270 1/16W 5% R0157 0662057A77 15k 1/16W 5% (12.5kHz) R0435 0662057A35 270 1/16W 5% VR0431 4813830A27 DIODE 14V 5% 225mW
0662057A84 30k 1/16W 5% (20/25kHz)
y
R0117 0662057A35 270 1/16W 5% R0436 0662057A89 47k 1/16W 5% VR0435 4813830A27 DIODE 14V 5% 225mW
R0161 0662057A97 100k 1/16W
r
R0118 0662057A65 4k7 1/16W 5% R0437 0662057A65 4k7 1/16W 5% VR0441 4813830A40 SOC23 AUTO SDN
a
R0162 0662057A73 10k 1/16W 5%
R0119 0662057A49 1k 1/16W 5% R0438 0662057A73 10k 1/16W 5% VR0444 4813830A14 DIODE 5.1V 5% 225mW
d
R0163 0662057A97 100k 1/16W
R0120 0662057A73 10k 1/16W 5% R0441 0662057A73 10k 1/16W 5%
i
VR0445 4813830A27 DIODE 14V 5% 225mW
R0165 0662057A89 47k 1/16W 5%
R0121
R0122
0662057B03
0662057A93
160k 1/16W 5%
68K
R0166
1
0662057A73 10k 1/16W 5%
o R0443
R0444
0662057A65
0662057A35
4k7 1/16W 5%
270 1/16W 5%
VR0450
VR0454
4813830A27
4813830A27
DIODE 14V 5% 225mW
R0125 0662057B05 200k 1/16W R0451 0662057A97 100k 1/16W Y0114 4880113R01 CRYSTAL 7.9488
e
R0137 0662057A89 47k 1/16W 5% R0189 0662057A95 82K R0472 0662057B47 0 1/16W
R0138 0662057A65 4k7 1/16W 5% R0401 0662057A65 4k7 1/16W 5% R0474 0662057A89 47k 1/16W 5%
R0139 0662057B07 240k 1/16W R0402 0662057A49 1k 1/16W 5% R0475 0662057A65 4k7 1/16W 5%
R0141 0662057A25 100 1/16W 5% R0404 0662057A73 10k 1/16W 5% U0101 5102898X66 64MC68HC711E20
FLT_A+
USW_+5V
R621 +5V
FLT_A+_8 2.2K USW_+5V_CL
FLT_A+
D621
C621 C622
h
470pF 47uF
VR621
tt p
:/
R606 9V3
U601
/
0 9V3_1_8 9V3_8
4 5
w
VIN VOUT 9V3
1 R631 D631
R601 2 10
ON_OFF ADJ
w
10K C605
GND
C603 R602 C604 U631
10uF 7.5K 33uF 0.1uF 8
C601 C602 1
INPUT OUTPUT +5V
470pF
3
0.1uF 7 5
FEEDBACK ERROR
w
3 2
R632 SHUTDOWN SENSE
10 C631 C632 6 C633 C634 C635
5V_TAP .022uF 47uF 0.1uF
0.1uF 33uF
GND
.m
R603
1.2K
4
Q601
y r
R604 R605
1K 6.8K
d a
RESET
i o SW_B+
1 6
SW_B+_8
SW_B+
8
C613
470pF
R641
.
30K
e n
BATTERY_VOLTAGE
Q611
t
ON_OFF_CONTROL
R642 C641
R614 10K 0.1uF
B+_CONTROL 1K
VR641
IGNITION_CONTROL
C611
D611 47uF
EMERGENCY_CONTROL
+5V +5V
GM950EI010-O
216-246MHz Supply Voltage Schematic Diagram
h
C0603 2380090M24 LYT 10uF 50V 20%
tt p
C0605 2113743E20 0.1uF, 10% R0632 0662057A01 10 1/16W 5%
:/
C0611 2311049A99 47uF R0641 0662057A84 30k 1/16W 5%
/
C0612 2113743K15 100nF 16V R0642 0662057A73 10k 1/16W 5%
w
C0613 2113741F17 470pF 50V U0601 5105625U25 IC 9.3V REG 2941
w
C0621 2113741F17 470pF 50V U0631 5105469E65 IC VLTG REGLTR LP2951C
w
C0622 2311049A99 47uF VR0621 4813830A14 5.1V 5% 225mW
.m
C0632 2311049A97 33uF
y
C0633 2113743E07 22nF 16V
r
C0634 2311049A99 47uF
a
C0635 2113743E20 0.1uF, 10%
d
C0641 2113743E20 0.1uF, 10%
i o
D0611 4813833C02 DUAL SOT MMBD6100 1
D0621 4813833C02 DUAL SOT MMBD6100
6
D0631 4813833C02 DUAL SOT MMBD6100
8
Q0601 4880214G02 MMBT3904
. n
VAG_7
(CNTL) VAG
C711 R712
C705 R705 .039uF 0
R702
4700pF 12K 47K
h
PA_PWR_SET C712
43pF
R716 R717
R703 U701-4 560K 33K
tt p
10K
R714
12K 11
12
14
:/
4 13 C716
Q711 2200pF R718
R713 68K
VAG 3.3K
/
IF2
VLTG_LIMIT (CNTL)
w
9V3_7 C714
0.1uF
(SV) 9V3 9V3 R719
R725 68K
w
10K
R715 D732
D721 22K
R731
w
22K R720
R721 100K
C722 C723
10K 100pF
R724 100pF
11 U701-1
.m
100K
PA_TEMP_7 3
R722
1 9V3
(PA) PA_TEMP
2 4
22K R723 R738
47K BIAS_VLTG_2_7
C721 47K 9V3 BIAS_VLTG_2
y
100pF C731 R734 R736
0.1uF 4.7K
15K Q732
r
C703 C738
0.1uF 0.22uF
a
SW_B+_7
(SV) SW_B+
16
SPI_CLCK_SRC_7 R733
d VDD
10 2 47K BIAS_VLTG_7
(CNTL) SPI_CLCK_SRC CLK Q1
4
DAC_CE_7
6
Q2
11
BIAS_VLTG (PA)
i
(CNTL) DAC_CE EN Q3
13
SPI_DATA_SRC_7 Q4 C732
o
1
(CNTL) SPI_DATA_SRC D_IN 100pF
3 D731
R1
5
1 6
8
9
NC
R2
R3
R4
12
14
R732
4.7K
C733
0.22uF
NC1
GND
15
D_OUT
R737
8
U731 7 1K FE_CNTL_VLTG_7
FE_CNTL_VLTG (FE)
PA_ENABLE_7
.
(CNTL) PA_ENABLE
n
Q731 10K
R735
e t
D733
9V3
Q742 K9V1_7
K9V1 (PA)
C741
R742 100pF
1K
Q741 R741
1K
K9V1_ENABLE_7 GM950EI005-O
(CNTL) K9V1_ENABLE
C742
0.1uF
h
C0711 2113741A59 CL2 R0718 0662057A93 68k 1/16W 5%
tt p
C0712 2113740F42 43pF 5% 50V R0719 0662057A93 68k 1/16W 5%
:/
C0713 2113740F51 100pF 5% 50V R0721 0662057A73 10k 1/16W 5%
/
C0714 2113743A19 100nF 16V R0722 0662057A81 22k 1/16W 5%
w
C0716 2113741F33 2200pF R0723 0662057A89 47k 1/16W 5%
w
C0721 2113740F51 100pF 5% 50V R0724 0662057A97 100k 1/16W
w
C0722 2113740F51 100pF 5% 50V R0725 0662057A73 10k 1/16W 5%
.m
C0731 2113743E20 0.1uF, 10% R0732 0662057A65 4k7 1/16W 5%
y
C0732 2113740F51 100pF 5% 50V R0733 0662057A89 47k 1/16W 5%
r
C0733 2113743A23 220nF 16V R0734 0662057A65 4k7 1/16W 5%
a
C0736 2113743A23 220nF 16V R0735 0662057A73 10k 1/16W 5%
d
C0741 2113740F51 100pF 5% 50V R0736 0662057A77 15k 1/16W 5%
i o
C0742 2113743E20 0.1uF, 10% R0738 0662057A89
1 47k 1/16W 5%
Q0711 4880214G02 MMBT3904 U0731 5113811G02 IC D/A CONV & BIT 4 CHAN
e
W/SPI
Q0731 4880048M01 TSTR NPN DIG 47k/47k
t
h
tt p
:/ / w
w
w
100
.m
120pF
75
62pF 150
120 75 13
y
39nF
36pF
30pF
91
r
1nF 75
a
20pF 62pF
d i
1 o
12pF
68 . n
38.13nH 38.13nH
e
GM950EI001-O
C8501 2113740F34 20pF 5% 50V C8558 2113740F20 5.1pF 5% 50V L8541 2460591X01 COIL SQUARE R8551 0662057A73 10k 1/16W 5%
C8502 2113741F49 10nF 50V C8600 2113740A67 330pF 5% 50V L8542 2484657R01 Ferrite Bead R8552 0662057A18 51 1/16W 5%
C8503 2113741F49 10nF 50V C8602 2113740F51 100pF 5% 50V L8551- 2460591M77 COIL SQUARE 38nH R8553 0683962T51 120 1W 5%
h
L8553
C8512 2113740F41 36pF 5% 50V C8603 2113741F25 1nF 50V R8611 0662057A73 10k 1/16W 5%
tt p
L8600 2484657R01 Ferrite Bead
C8514 2113741A33 3.3nF 50V C8604 2311049A45 TANT CP 10uF 10% 35V R8612 0662057A56 2k 1/16W 5%
L8601 2484657R01 Ferrite Bead
:/
C8521 2113740A40 30pF 5% 50V C8611 2113741F49 10nF 50V R8613 0662057A49 1k 1/16W 5%
L8611 2484657R01 Ferrite Bead
/
C8522 2113741F49 10nF 50V C8612 2113741F49 10nF 50V R8614 0662057A18 51 1/16W 5%
w
L8631 2462587T23 COIL CHIP 470nH
C8523 2113741F49 10nF 50V C8615 2113741F25 1nF 50V R8615 0662057A65 4k7 1/16W 5%
w
Q8510 4813827A26 TSTR RF NPN MRF8372
C8524 2113741F25 1nF 50V C8617 2113740A67 330pF 5% 50V R8616 0680194M01 10 1W 5%
Q8520 4813827D13 4pin MRF557T
w
C8525 2113740A50 62pF 5% 50V C8618 2311049A08 TANT CP 1uF R8617 0680194M01 10 1W 5%
Q8530 4813827A36 TSTR MRF 5003
C8527 2113740A50 62pF 5% 50V C8619 2113740F51 100pF 5% 50V R8621 0662057A41 470 1/16W 5%
.m
Q8531 4813827A36 TSTR MRF 5003
C8528 2113741F25 1nF 50V C8620 2113740F29 12pF R8623 0662057C19 4R7 1/10W 5%
Q8540 4880225C30 TS TR MRF650
y
C8529 2113740A55 100pF C8621 2113741F25 1nF 50V R8624 0662057C19 4R7 1/10W 5%
Q8611 4813824A17 TSTR PNP 40V .2A
r
C8530 2311049A01 TANT CP 100nF 10% 35V C8622 2113741F49 10nF 50V R8641 0680149M02 Thermistor 100K @25C
a
Q8612 4880214G02 MMBT3904
C8531 2113741F49 10nF 50V C8623 2113740F51 100pF 5% 50V SH8501 2602642Y01 Heat Spreader
d
Q8621 4813824A17 TSTR PNP 40V .2A
C8532 2113740A67 330pF 5% 50V C8631 2113741F25 1nF 50V
i
R8501 0662057C19 4R7 1/10W 5%
C8534
C8535
2111078B31
2113740A59
36pF
150pF 5% 50V
C8632
C8633
2111078B44
1
2113740F36
120pF
h
tt p
:/ / w
w
w
.m
680
y
5.6K
ra
d i
1 o
68 . n
e t
GM950EI003-A
h
R3712 0662057A59 2k7 1/16W 5%
C3704 2113741F49 10nF 50V
tt p
R3713 0662057A67 5.6k 1/16W
C3705 2113741F49 10nF 50V
R3714 0662057B02 150k 1/16W
:/
C3706 2113743E20 0.1uF, 10%
R3715 0662057A41 470 1/16W
/
C3707 2113741F49 10nF 50V (12.5kHz)
w
R3716 0662057A49 1k 1/16W
C3708 2113740F59 220pF 5% 50V (12.5kHz)
w
R3717 0662057A25 100 1/16W 5%
C3709 2113743K15 100nF 16V (12.5kHz)
2113740F13 2.7pF 5% 50V (20/25kHz) R3718 0662057A25 100 1/16W 5%
w
C3710 2113740F43 47pF 5% 50V (20/25kHz) R3723 0662057A73 10k 1/16W 5%
.m
C3711 2311049J23 TANT CP 10uF 10% 6V R3724 0662057B16 560k 1/16W 5%
C3712 2311049J26 TANT CP 10uF 20% 16V U3701 5105457W72 CC CONT 5105191W59
y
C3713 2113741F25 1nF 50V VR3701 4813830A23 10V 5% 20mA 350mW
ra
C3716 2113743K15 100nF 16V Y3701 4802081B71 Crystal Quartz 16.8 MHZ
TEMPUS (20/25kHz)
d
C3717 2113743K15 100nF 16V
i
Y3702 4809863M01 Crystal Quartz 16.8 MHZ
C3718 2113743K15 100nF 16V
o
6
C3720 2113741F49 10nF 50V
8
C3722 2311049A07 1uF 10% 16V
.
L3742
F
1uH
h
C3737 C3738 D C3771 .001uF
36pF R3763 R3781
1pF
G 150 100
U3741
D3732 0.1uF C3781
R3771
tt p
C3763
R3739 S 150
L3733 L3734 C3739 D3739 27K .01uF
1uH 22nH 5.6pF R3741 C3745 .01uF
470pF L3761 R3778 L3781 TP3732
68 2.7K L3783 C3785 R3785
:/
L3732 68nH 22nH 7.5pF
D 56nH 10 EXCITER_PA_4
1uH C3764 C3767 R3768 L3768
.01uF 2.7K 120nH C3775 R3776 C3777
L3773 EXCITER_PA
/
D3733 33nH 470pF 39 470pF
C3735 C3740 5.6pF Q3780
w
470pF 5.6pF L3741 C3786
C3783 C3784 R3786
1uH C3765 C3766 13pF NU
R3766 R3779 NU 150
C3761 Q3770
6.8pF C3773 R3775 R3777 1.5K
22 C3774
12pF
w
100pF 12pF 13pF 270 150 R3782
Ud R3761 100
R3769 C3782
1.5K R3765 R3767
1K 100pF
270 270
w
Q3760 C3772
R3743 Q3742 R3772
100pF 100
4.7K 2DTC143ZK
Q3752 R3762
R3752 470 R3774
.m
5 1 10
2.2K C3762
5.6pF
4
y
3 2
r
Ud
d a
R3754
C3752 C3754 D
20pF 24pF 39
i
G C3758 5V_STAB
Q3751
o
.001uF C3792
L3750
1uH R3751 S
1
L3752 C3755 D3754 27K .01uF
12.5nH 10pF R3753 C3757 R3791
D3751 100 470pF 270
L3751
6
1uH
D3752
8
C3751 C3756 C3791 R3792
.01uF 10pF L3754 2.7K C3793
Q3790
.
C3790
16pF 470
e
R3793
1K R3794
NU
t
GM950EI002-A
U3801
LP2951CM
R3801 5V_STAB_4
9V3 8 INPUT OUTPUT 1 5V_STAB (SOURCE)
7 FEEDBACK ERROR 5
22
SHUTDOWN SENSE 2
3 5V_TAP 6
C3801 C3802 C3803
.220uF GND .022uF 10uF
4
E3731 E3732
Circuit Motorola C3777 2113741F17 470pF 50V L3761 2462587T13 COIL CHIP 68nH
Description
Ref Part No. C3780 2113741F25 1nF 50V L3768 2462587T16 COIL CHIP 120nH
C3731 2113741F25 1nF 50V C3781 2113741F49 10nF 50V L3773 2462587N47 COIL CHIP 33nH
C3733 2113740F25 8.2pF 5% 50V C3782 2113740F51 100pF 5% 50V L3781 2462587T38 16 IDCTR, 22nH
C3734 2113740F03 1pF 5% 50V C3783 2113740F30 13pF 5% L3783 2462587N50 COIL CHIP 56nH
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C3735 2113741F17 470pF 50V C3784 2113740F27 10pF 5% Q3742 4805921T09 XSTR DUAL ROHM FMG8
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C3736 2113740F33 18pF 5% 50V C3785 2113740F24 7.5pF 5% Q3751 4813823A05 N-CH RF JFET
MMBU310LT1
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C3737 2113740F03 1pF 5% 50V C3790 2113740F32 16pF 5%
Q3752 4880214G02 MMBT3904
/
C3738 2113740F40 36pF 5% 50V C3791 2113741F49 10nF 50V
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Q3760 4813827A07 NPN SML SIG MMBR9
C3739 2113740F21 5.6pF 5% 50V C3792 2113741F49 10nF 50V
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Q3770 4813827A07 NPN SML SIG MMBR9
C3740 2113740F21 5.6pF 5% 50V C3793 2113741F49 10nF 50V
Q3780 4813827A07 NPN SML SIG MMBR9
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C3743 2113743K15 100nF 16V C3801 2113743A23 220nF 16V
Q3790 4813827A07 NPN SML SIG MMBR9
C3744 2113741F25 1nF 50V C3802 2113743E07 22nF 16V
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R3731 0662057A21 68 1/16W 5%
C3745 2113741F17 470pF 50V C3803 2311049A63 TANT CP 10uF 10% 10V
R3739 0662057A83 27k 1/16W 5%
C3751 2109720D01 LOW DIST 10nF
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D3731 4805649Q13 VCTR 1SV228 SOT23
R3740 0662057A09 22 1/16W 5%
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C3752 2113740F34 20pF 5% 50V D3732 4805649Q13 VCTR 1SV228 SOT23
a
R3741 0662057A21 68 1/16W 5%
C3754 2113740F36 24pF 5% 50V D3733 4805649Q13 VCTR 1SV228 SOT23
d
R3742 0662057A15 39 1/16W 5%
C3755 2113740F27 10pF 5% 50V D3739 4813825A05 MMBD301
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R3743 0662057A65 4k7 1/16W 5%
C3756
C3757
2113740F27
2113741F17
10pF 5% 50V
470pF 50V
D3751
D3752
4805649Q13
1
4805649Q13 o
VCTR 1SV228 SOT23
3.9pF
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R3340 R3341
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NU NU NU
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C3351 C3352 C3353 C3354
11pF 11pF 11pF 11pF
11pF
D3311 D3312 C3355 D3313 D3314 NU
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11pF
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33pF 43pF 33pF 39pF
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8.2nH 10nH
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GM950EI004-A
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D3303 4880154K03 Dual Schottky SOT23 T3301 2505515V03 XFMR JEDI MIXER SMD 4:1
Circuit Motorola
Description
Ref Part No. D3311 4802245J22 VCTR IT363 T3302 2505515V03 XFMR JEDI MIXER SMD 4:1
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C3303 2113741F37 3.3nF 50V D3331 4880174R01 QUAD SOIC 8 PIN
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C3304 2113740F45 56pF 5% 50V L3302 2462587T23 COIL CHIP 470nH
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C3305 2113740F39 33pF 5% 50V L3331 2462587T23 COIL CHIP 470nH
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C3306 2113740F42 43pF 5% 50V L3332 2462587T17 COIL CHIP 150nH
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C3307 2113741F37 3.3nF 50V L3333 2462587N40 COIL CHIP 8.2nH 5%
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C3308 2113741F25 1nF 50V L3334 2462587N41 COIL CHIP 10nH 5%
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C3309 2113741F13 330pF 50V Q3301 4813827A07 NPN SML SIG MMBR9
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C3311 2113741F37 3.3nF 50V R3300 0662057A55 1k8 1/16W 5%
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C3312 2113741F25 1nF 50V R3301 0662057A97 100k 1/16W
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C3313 2113740F45 56pF 5% 50V R3302 0662057A37 330 1/16W 5%
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C3314 2113740F24 7.5pF 5% 50V R3303 0662057A49 1k 1/16W 5%
d
C3315 2113740F45 56pF 5% 50V R3304 0662057A53 1k5 1/16W 5%
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C3316 2113740F39 33pF 5% 50V R3306 0662057A35
1 270 1/16W 5%
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C5200 2113740F35 22pF 5% 50V FL5202 9180097D04 Filter CER 6-EL 455kHz
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C5202 2113740F31 15pF 5% 50V
C5203 2113743A19 100nF 16V X7R L5211 2483411T74 Inductor Chip Shielded
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C5204 2113743A19 100nF 16V X7R Q5201 4813827A07 MMBR941
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C5205 2113740F33 18pF 5% 50V R5201 0662057A73 10k 1/16W 5%
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C5208 2113743A19 100nF 16V R5202 0662057A85 33k 1/16W 5%
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C5211 2113740F31 15pF 5% 50V R5203 0662057A69 6k8 1/16W 5%
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C5212 2113740F31 15pF 5% 50V R5204 0662057A25 100 1/16W 5%
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C5213 2113740F40 36pF 5% 50V R5205 0662057A56 2k 1/16W 5%
.m
C5220 2113741F49 10nF 50V R5211 0662057A47 820 1/16W 5%
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C5221 2311049A63 TANT CP 10uF R5212 0662057A67 5k6 1/16W 5%
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C5222 2113743A23 0.22uF R5216 0662057A73 10k 1/16W 5% (12.5kHz)
a
0662057A65 4k7 1/16W 5% (20/25kHz)
C5223 2113743E20 100nF 16V
d
R5221 0662057B02 150k 1/16W
C5224 2113741F29 1.5nF 50V
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R5222 0662057A97 100k 1/16W 5%
C5225
C5226
2311049J11
2113743K07
TANT CP 4.7uF 10% 16V
47nF 16V
R5223
1
0662057A83 27k 1/16W 5%
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6
R5224 0662057A76 13k 1/16W 5%
C5227 2311049J11 TANT CP 4.7uF 10% 16V
8
R5225 0662057A25 100 1/16W 5% (12.5kHz)
C5228 2113743K15 100nF 16V 0662057A57 2k2 1/16W 5% (20/25kHz)
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12.5KHz 80dB
C5231 2311049A07 TANT CP 1uF 10% 16V
9102652Y01 XTAL FLTR 45.1MHZ
C5232 2113740F51 100pF 5% 50V 20/25KHz 80dB
Appendix A
PL/DPL Codes
Table of Contents
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1.0 PL Codes and Digital PL (DPL) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
8.
2.0 Self-Quieting Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
16
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The following PL Codes have been tested and are acceptable for programming into any transmit or
receive frequency.
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1Z 100.0 1A 103.5 YA 85.4
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1B 107.2 2Z 110.0 ZZ 91.5
2A 114.8 2B 118.8 ZB 97.4
8.
3Z 123.0 3A 127.3 5B 162.2
3B 131.8 4Z 136.5 8Z 206.5
4A 141.3 4B 146.2
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5Z 151.4 5A 156.7
6A 173.8 6Z 167.9
7Z
M1
M3
186.2
203.5
218.1
6B
7A
M2
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179.9
192.8
210.7
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Self-quieting frequencies are frequencies that are also generated by the radio and cause internal
interference. On these frequencies the interference caused by the self-quieter spur is great enough
that a radio will not meet its receiver sensitivity speciÞcation.
The frequencies are: UHF 403.2, 420, 436.8 and 453.6MHz.
VHF 151.2 and 168.0MHz
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Appendix B
External Device Connectors
Table of Contents
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1.0 Accessory Connector Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
8.
2.0 Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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A2 A3
Pin Name Type
4-Channel 128-Channel
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4 GP2 Digital output ✕ ✓
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5 Flat TX Audio Analogue input ✕ ✓
8.
6 BUS+ Digital i/o ✓ ✓
7 GND Ground ✓ ✓
16
8 GP3 Digital i/o ✕ ✓
10
GP4
Ignition sense io
Digital ip. capture
Digital input
✕
✓
✓
✓
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11 RX Audio Analogue output ✕ ✓
✕ ✓
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Speaker - and Speaker + (Pin 16) are used to connect an external speaker. The audio PA is a bridge
ampliÞer with a minimum load resistance of 3.2 ohms. The internal speaker can be disabled by
removing the control head. Disconnect the internal speaker and assemble the control head back to
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the radio.
Pin 2. - Microphone audio
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This microphone signal input is common with the microphone signal input on the microphone con-
nector and is connected to the microphone path input of the AFIC. The nominal input level is 80mV
for 60% deviation. The DC impedance is 1100 ohms and the AC impedance is 1000 ohms
Note: Only one microphone should be connected at any one time.
Pin 3. - General Purpose 1 (GP 1)
This is a digital input only. The RSS details which functions may be assigned to this pin by the code-
plug. The primary use for this pin will be external PTT. (See Note 1).
Pin 4. - General purpose 2 (GP2)
This is a digital output only. The RSS details which functions may be assigned to this pin by the
codeplug. The primary use for this pin is as external alarm output (See Note 3).
Pin 5. - Flat TX audio
This input is for injecting signals into the transmit path that should not be Þltered, e.g. the output of a
modem. The nominal input level is 150mVRMS for 60% deviation. The impedance is greater than
25kohms.
Pin 6. - BUS+
This connects to the radioÕs SCI serial bus which is used for programming and tuning the radio. The
line is also available at the microphone connector Pin 7.
Pin 7. - Ground
Used as ground for both analogue and digital signals.
Pin 8. - General purpose 3 (GP3)
This is a digital input/output and is also available on the internal option connector (J0103:7). The
RSS details which functions may be assigned to this pin by the codeplug. (See Notes 1 and 2).
Pin 9. - General purpose 4 (GP4)
This is a digital input only. It is also available on the internal option connector (J0102:7) and is used
in input capture mode when a serial type option board is Þtted. The RSS details which functions may
be assigned to this pin by the codeplug. (See Note 1).
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Pin 10.- Ignition sense
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Connecting this line to the ignition line of the vehicle will automatically turn the radio on when the
ignition of the vehicle is turned on. When ignition is connected, the radio cannot be turned off as long
as the ignition is active. When this line is at 0V or not connected, power on/off is under manual
8.
control. Resistor R0423, 4.7kW, which is not Þtted as standard will cause the radio to be permanently
on whenever 12V is connected to the main power connector.
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Pin 11.- RX Audio Discriminator/Filtered (Analogue output)
The signal routed to this pin is controlled by AFIC. There are two possible outputs; continuous
discriminator audio or continuous Þltered RX audio output of AFIC. The output mode can be selected
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by the RSS, however, this mode may be overridden during certain tuning operations. For
discriminator audio, the nominal ouput level is 330mVRMS for 60% deviation. The impedance is
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600ohms. For Þltered audio, the nominal ouput level is 600mV for 60% deviation. The impedance is
600ohms.
Pin 12.- General purpose 5 (GP5)
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This is a digital input/output and is also available on the internal option connector (J0103:8). The
RSS details which functions may be assigned to this pin by the codeplug. (See Notes 1 and 2).
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short circuiting this output to ground, which will damage the radio.
CAUTION: The maximum continuous current allowed is 300mA. A suitable external fuse must be
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RSS details which functions may be assigned to this pin by the codeplug. (See Notes 1 and 2).
Pin 15.- RSSI
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The radio is Þtted with an 8-pin ÔTelcoÕ connector which is connected as follows:
1 - - -
2 - - -
4 GND Ground -
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5 Mic. Audio Analogue input AFIC TX IN
8.
7 BUS+ Digital i/o Port D0 and Port D1
16
8 HANDSET Analogue output Buffered RX audio
Pin 1. - No connection.
Pin 2. - No connection. io
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Pin 3. - Microphone (or internal) Hook
This port reads Ô0Õ when the microphone is on-hook and Ô1Õ when the microphone is off-hook. It is
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assumed that the hook is a mechanical switch, so the software will always debounce this input.
Pin 4. - Ground
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The microphone PTT is active low and so this port reads Ô0Õ when the PTT is pressed and Ô1Õ when
the PTT is released. It is assumed that this PTT is a mechanical switch, so the software will always
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The microphone PTT line is also available at the internal connector (J0102:1) as a bi-directional line,
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i.e. an internal option can use the line, both to key-up the radio, and to know when the radio is
already keyed-up. For this to work, microprocessor port C4 has to be reconÞgured as an output and
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driven low whenever any other signal, other than the microphone PTT, e.g. external PTT, causes the
radio to key-up.
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Pin 7. - BUS+
This line carries the data for the single line serial comms system used in the radio. The RSS will pro-
gram the radio through this socket. The line is also available at the accessory connector Pin 6.
Pin 8. - Handset Audio
This line provides buffered audio for a handset.
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Appendix C
Radio Conversion
Table of Contents
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1.0 How to alter the radio for Base Station Operation . . . . . . . . . . . . . . . . . . . 1
8.
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