VLSI implementation of a novel sensor architecture

for Industrial Wireless Sensor Networks

Bharath Keshavamurthy, Abhay Narasimha, Asif Ahmad A S and Poornima G
Department of Electronics and Communication Engineering
BMS College of Engineering
Bangalore, India
[email protected], [email protected], [email protected], [email protected]

Abstract—Wireless Sensor Networks (WSNs) are distributed (SOSUS) which was used to track and detect Soviet
sensing ecosystems equipped with computational intelligence and submarines. The SOSUS consists of an interconnected network
radio communication capabilities. The ‘neurons’ of a typical of acoustic sensors on the ocean bottom, a system still used
WSN referred to as Sensor Nodes or Motes are tiny, low-cost, today by NOAA (National Oceanic and Atmospheric
resource-efficient modules with embedded intelligence facilitating Administration) for monitoring and recording seismic activity.
ultra-fast deployment, flexibility and energy-efficiency in their Later, in the 1960s and 1970s, the US Defense Advanced
operations. Industrial Wireless Sensor Networks or IWSNs Research Projects Agency (DARPA) in association with
feature hundreds and thousands of sensors placed in and around Carnegie Mellon University and MIT Lincoln Labs [3] enabled
the plant to enable remote monitoring, maintenance and
progressive advancements in the Distributed Sensor Networks
troubleshooting. In this article, we present a full custom design of
a sensor node for Industrial Wireless Sensor Networks with the
(DSN) which subsequently led to the penetration of the concept
primary focus on the architectural aspects of the implementation. of wireless sensor networking into the commercial and
The proposed sensor architecture consists of a 4-channel 12-bit industrial arena. Numerous initiatives such as the Zigbee
Delta-Sigma ADC, a controller subsystem with SPI Master-Slave Alliance, the UCB PicoRadio program, the NASA Sensor
interfaces and an OFDM RF Transmitter subsystem. The Webs and the UCLA Wireless Integrated Network Sensors
architecture outlined in this article is a novel modular design were aimed at analyzing the tradeoffs involved in WSNs
characterized by an OFDM baseband processing RF subsystem thereby facilitating faster deployment scenarios with a
facilitating reliable monitoring of plant variables which is a significant performance increase. The advancements in Sensing
crucial parameter in Industrial Wireless Sensor Networks. The technologies, Semiconductor devices, Networking protocols
proposed system has been subjected to Front-end RTL and Energy Harvesting techniques [3] are the primary driving
simulation and synthesis using an array of EDA tools and the forces behind the popularity of WSNs in the industrial,
subsequent results have been critically examined in this article. academic and commercial space.
Keywords—IWSNs; Delta Sigma ADC; SPI; PLL; OFDM. Realizing the importance of WSNs, the Ministry of
Communication and Information Technology, Government of
India published a detailed roadmap outlining the implications
I. INTRODUCTION
of WSNs to the industries in India and abroad. The research
The domain of Wireless Sensor Networks (WSNs) has article “Wireless Sensor Networks: Technology Roadmap”
quickly turned out to be a highly sought after field primarily brought out by the MCIT, DIT, Govt. of India in association
due to the plethora of research opportunities embedded in it. with IIT-Bombay [4] talks about the Current R&D trends,
Wireless Sensor Networks constitute hundreds and thousands WSN Hardware, Investments in R&D, Potential applications
of sensors (if not more), deployed in and around the facility of and Survey results detailing the objectives and promises of this
interest in order to monitor, maintain and troubleshoot critical lucrative field.
operations. The inherent complexities of WSNs arise from the
fundamental fact that Sensor Design and associated Understanding these facets of WSNs, the research
Networking involve design constraints in Wireless presented in this paper revolves around the design and
Communication Methodologies, Networking Techniques, development of a sensor node for Industrial WSNs while
Security Protocols and System Design & Manufacture, analyzing the numerous tradeoffs inherent in it.
prompting engineers and researchers to examine various The sensor node architecture detailed in this article
tradeoffs involved in their large-scale deployment. However, constitutes a 4-channel 12-bit Delta Sigma ADC, a controller
recent advances in semiconductor technology and wireless subsystem with SPI Master-Slave interfaces and an OFDM RF
communications have led to significantly efficient, robust and Transmitter subsystem. The 4-channel ADC enables
cheap sensor nodes facilitating a much-needed global outreach connecting and configuring four different sensors (Temperature
enabling ubiquitous deployment, further accelerating potential sensors, Pressure sensors, etc.) in order to provide a holistic
applications of WSNs. approach to the monitoring capabilities of the node. The sensor
The popularity of WSNs can be traced back to their origin node design focusses on remote monitoring of plant
in the 1950s: The US Military’s Sound Surveillance System parameters, for instance, the sensor node can be used to gather
information regarding the temperature and pressure within a

978-1-5090-0612-0/16/$31.00 ©2016 IEEE

 2016 IEEE International Conference on Computational Intelligence and Computing Research

gas turbine and report these parameters to a monitoring station enables remote access and control of sensor activity. The size
for further actions, if needed. The controller subsystem serves and cost constraints involved in sensor node design imposes
as the ‘Brains’ of the operation facilitating data transfer corresponding constraints on other design features such as
between the ADC and the RF Tx subsystem. The RF memory, energy consumption, computational speed and
Transmitter subsystem enables digital baseband processing of bandwidth. The features of a typical sensor node include,
the collected data from the controller and forwards it to the Resilience, Minimum power consumption, Mobility and
Analog front-end module for transmission toward the remote Heterogeneity, Scalability and Low cost. Along with these
monitoring station. generic characteristics, a sensor node should cope with harsh
environmental conditions, should be easy to deploy and
Although a whole lot of research exists in the domain of maintain and above all the transmission capabilities should
Wireless Sensor Networks, there is a lack of literature on the feature security measures, especially in the military and
end-to-end design of a comprehensive sensor node for IWSNs. industrial environments.
In this article, we present the design and development of an
Analog-to-Digital Converter, an 8051-controller based Wireless sensor nodes generally constitute a sensor
processing subsystem along with its associated interfaces and subsystem, a general-purpose microcontroller and a wireless
an OFDM Baseband processing subsystem for reliable transceiver, with an event-based operating system such as
communications between the node (which is deployed in the TinyOS. The design of a sensor-node for WSN-based
industrial ecosystem) and the remote monitoring station. This applications requires deep insight into the Hardware and
article details a modular architecture characterized by three Software development aspects. The methodologies adopted in
major features which are extremely relevant in today’s WSN their design can either be application-specific or generalized.
landscape. Firstly, the provision of a multiplexer in the ADC For instance, [2] details a VLSI architecture for a sensor node
subsystem facilitating a 4-channel operation of the Delta- employed in a Wireless Image Sensor Network (WiSN). The
Sigma ADC accounts for the versatility of our design, i.e. a SoC-based design methodology outlined in [2] consists of a
wide array of sensors can be connected to the system enabling general-purpose embedded microcontroller along with
simultaneous monitoring of various performance indices of the dedicated hardware accelerators for image processing and
industrial ecosystem. Secondly, the RF subsystem of the wireless communication. In contrast to this, [5] talks about a
proposed design constitutes an OFDM Baseband processing customizable modular event-driven architecture facilitating the
module which accounts for the reliability and efficiency of addition or removal of event dispatchers and event handlers in
communications between the sensor node and the monitoring order to suit the corresponding WSN application, thereby
station. Finally, the processing subsystem based on the 8051- presenting a more generalized topology of sensor-node design.
controller core is advantageous to our design primarily because However, both emphasize on the use of hardware-based
of its smaller physical size and smaller program and data space. functionalities to facilitate faster and more-efficient execution
of computationally intensive tasks.
The next section of the article gives an overview of the
Architecture and Characteristics of the proposed design while The energy harvesting and consumption aspects of sensor
the subsequent sections detail individual subsystems and their nodes in Wireless Sensor Networks have recently drawn in
implementation. Section III talks about the design and significant research from both the industry and academia. Low
implementation of the ADC, Controller and RF Tx subsystems. Power VLSI design techniques are of primary importance in
Section IV details the design parameters and simulation results this arena where everyone is trying to reduce the ‘energy
of the proposed architecture and Section V presents a footprint’ of their node. While the low-power modular VLSI
concluding argument validating the research perspective implementations have their advantages, an energy-efficient
presented in this article. design at the top-level facilitates a relatively higher
improvement. For instance, a Battery Aware Task Scheduling
II. DESIGN OVERVIEW: ARCHITECTURE AND FEATURES (BATS) technique detailed in [6] enables 60mW maximum
power consumption in full-working mode (180nm technology
Wireless Sensor Networks constitute a group of spatially node). Reference [7] outlines a ‘Wake-up’ architecture for the
distributed autonomous sensors used to monitor various radio front-end, using an OFDM frequency footprint which
parameters such as temperature, pressure, acoustics, velocity, enables activation of only the required components. The
images, et cetra and to cooperatively pass the data along to the novelty of the research presented in [7] lies in its simplicity: It
central monitoring station. These autonomous modules termed employs two multi-band filters to facilitate specific wake-up
‘sensor nodes’ typically consist of the following parts: A radio calls while avoiding complex processor-based decision
transceiver, a microcontroller, an electronic circuit to interface techniques, thereby enabling a reduction in energy-
the sensor with a suitable energy source and some form of pre- consumption of the node. Looking further into the small-size,
processing capabilities to acquire the data in the required low-power comprehensive designs, [13] talks about the
format (for instance, we employ an ADC to gather data from development of hardware prototypes of Multimedia sensor
analog sensors monitoring the plant environment and convert nodes for smart farming applications. Furthermore, [13]
them into their equivalent digital representation for further discusses the benefits of integrating all the required hardware
processing). The data acquired is processed by the node and components on a single, compact PCB thereby facilitating the
transmitted to the adjoining node in the network. The nodes in development of sensor nodes with small form factors.
the network then cooperatively pass along the data to the
Gateway Node which then forwards it to the central monitoring Considering the state-of-the-art in the arena of Wireless
station. Some WSNs exhibit a bi-directional architecture which Sensor Networks, this article focusses on the VLSI front-end
 2016 IEEE International Conference on Computational Intelligence and Computing Research

description of the above-mentioned subsystems and their constitutes a pulse-wave representation of the analog input
relevant interfaces. Fig. 1 depicts the proposed architecture of signal at a sampling rate of ‘fs’. This pulsed-representation of
the sensor node. The next section of the article talks about the the time-varying input is then averaged to obtain a digital
three major subsystems of the proposed design while Section equivalent of the analog input. The high speed 1-bit output of
IV lays down the results by means of simulations and obtained the DSM containing noise at higher frequencies is passed
performance metrics. through the Digital Filter/Decimator block. The Digital Filter
functionality in a low-pass configuration attenuates the high
frequency noise while the Decimator functionality slows down
the high output data rate. The Digital filter implementation
constitutes a weighted averaging filter configuration commonly
found in numerous industrial applications [9]. The Decimator
reduces the output data rate by discarding redundant data
samples in order to bring the output to a more manageable data
rate. The parameter of interest in this Digital filter/Decimator
configuration is the Decimation Ratio (DR) defined as shown
in (1).
Decimation Ratio (DR) = fs/fd (1)
where, fs = Delta Sigma Modulator’s sampling rate and
Fig. 1. Proposed Architecture of the Sensor Node.
fd= Decimator’s output data rate.

III. DETAILED DESCRIPTION OF THE PROPOSED DESIGN B. The processor subsystem

The processor subsystem is the ‘brains’ of the sensor node
A. The sensor subsystem comprising a general-purpose controller tasked with
The Analog-to-Digital Converter (ADC) constitutes the maintaining the data transfer functionalities between the sensor
primary component of this subsystem tasked with converting subsystem and the radio transmitter subsystem. Standard SPI
the data obtained from the generic sensor modules into their Master-Slave interfaces are employed to define data transfer
equivalent digital representation and transferring them into the protocols between the concerned subsystems. A conventional
processing subsystem for further operations. The sensor 8051-microcontroller core is optimized to incorporate a
subsystem also consists of an Analog multiplexer (4x1) minimum number of I/Os, SPI Master-Slave interface support,
employed to enable a 4-channel ADC operation in order to interrupts, pipelining strategies and low-power sleep modes.
facilitate a variety of sensors to be interfaced with the node and The 8051-microcontroller core is an advantageous choice for
thus enhancing the versatility of its application. The 12-bit sensor node design primarily because of its smaller program
Delta-Sigma ADC presented in Fig. 2 consists of a Delta- and data space and also because of its smaller physical size [6].
Sigma Modulator and a Digital/Decimation filter. The
advantages of the Delta-Sigma ADC include better noise The SPI module forms the interface for data transfer
shaping capabilities making it best suited for low-frequency, between the sensor subsystem and the radio transmitter
high-accuracy applications; a high resolution output stream and subsystem. The Serial Peripheral Interface (SPI) is a de-facto
a wide frequency range of conversion [8]. serial synchronous communication interface consisting of a
single master driving one or more slaves. The SPI bus
The Delta-Sigma modulator (DSM) constitutes a constitutes four logic signals namely, Serial Clock (SCLK),
Difference Amplifier, an Integrator, a Comparator and a 1-bit Slave Select (SS), Master-Out Slave-In (MOSI) and Master-In
DAC. The input to the DSM is a time-varying analog signal Slave-Out (MISO). The design metrics and implementation
from the sensor(s) connected to the sensor subsystem. The results are presented in the Section IV of this article.
DSM is responsible for digitizing the analog input and
reducing the noise at low frequencies by pushing the noise to The Clock Management Unit is another significant part of
higher frequencies wherein they are removed by the subsequent the node categorized under the processor subsystem. This
digital filter stage. The time-varying input and the output of the module constitutes a PLL-based clock distribution logic which
DAC are differentiated as shown in Fig. 3 and this output is fed is the norm in modern high-performance digital circuits. The
into the Integrator whose output possesses either a positive or a implementation details of an All-Digital Phase Locked Loop
negative slope based on the sign and magnitude of its analog (ADPLL) are discussed in Section IV of this article.
input. If the output of the integrator is equal to the reference
signal, the comparator output switches (either from positive to
negative or from negative to positive) depending on its
previous state. The comparator output is progressed onto the
Digital/Decimation filter stage along with feeding it back to the
1-bit DAC whose output changes accordingly thereby
prompting the integrator output to progress in the opposite
direction and hence causing a corresponding switch in the
output of the comparator. Thus, the output of the DSM Fig. 2. Block Diagram of the Delta Sigma ADC.
 2016 IEEE International Conference on Computational Intelligence and Computing Research

starting point of each OFDM symbol to mitigate any residual

impact of Inter-Symbol Interference that may arise due to
Multi-Path propagation. These parallel data streams are then
converted to a serial output stream for propagation into the RF
front-end. The design description and simulation results of the
OFDM-baseband processing of the data stream are depicted in
the next section of the paper.

Fig. 3. A First Order Delta Sigma Modulator.

C. The radio transmitter subsystem

Orthogonal Frequency Division Multiplexing (OFDM) is a
multi-carrier transmission scheme in which data is carried
over several parallel streams by orthogonal sub-carriers, each
sub-carrier modulated by conventional modulation schemes Fig. 4. Architecture of the OFDM Baseband Processor.
such as QAM or QPSK. The wideband channel is divided into
overlapping yet orthogonal narrowband sub-channels thereby
eliminating the need for guard intervals between the channels
and hence rendering OFDM highly spectrally efficient. This
orthogonal multicarrier technique offers numerous advantages
over conventional single-carrier schemes such as the ability of
OFDM systems to cope with Multipath Fading, Inter-Symbol
Interference (ISI) and Inter-Carrier Interference (ICI). The
sub-carriers are spaces in such a way that they can be easily
separated at the receiving end- a boon for the constraint-heavy
WSN domain. The first OFDM patent was filed by R. Chang
of Bell Labs which proposed an analog implementation
employing arrays of signal generators and demodulators [10]. Fig. 5. Spectral Efficiency of OFDM (b) as opposed to conventional
The application of Discrete Fourier Transform (DFT) realized multicarrier modulation (a).
using the WFT or FFT techniques allowed research on the
potential applications of OFDM to really take off. A In OFDM, as hinted at earlier, the frequency-selective
significant amount of research has been dedicated to the VLSI wideband channel is divided into non-frequency selective
design of OFDM transceiver architectures including numerous narrowband sub-channels. These sub-channels are overlapping
FPGA-based generic implementations as presented in [1]. and orthogonal, which removes the need for guard bands,
Reference [1] details a flexible OFDM baseband transmitter thereby making it spectrally efficient when compared to
architecture presented with system modelling, simulation, conventional multi-carrier techniques, as portrayed in Fig. 5.
synthesis and its subsequent mapping onto an FPGA. High data rate streams typically encounter problems of ISI
Similarly, [11] and [12] talk about the FPGA-based because the symbol duration ‘Ts’ is smaller than the channel
implementation of an OFDM digital baseband transmitter. delay spread ‘Td’. The presence of ISI calls in the need for
However, we present the OFDM baseband strategy in the complex equalization procedures at the receiving end.
perspective of sensor nodes and their application in Industrial Moreover, the complexity of the equalization process at the
Wireless Sensor Networks (IWSNs). Looking into receiver increases with the square of the channel impulse
environments similar to IWSNs, [14] lays down the design of response length. In order to mitigate ISI and the subsequent
a high-speed OFDM modem for high-speed underwater receiver equalization complexity, the high data rate stream is
acoustic communications. The use of OFDM enables high- Serial-to-Parallel converted onto M subcarriers. This process
speed reliable communication capabilities making it highly ensures that the symbol duration on each subcarrier is much
suitable for numerous aquatic applications as detailed in [14]. greater than the channel delay spread, i.e. Ts>Td, thereby
simplifying the receiver implementation. The mathematical
In the OFDM transmitter subsystem (as shown in Fig. 4), representation of processes involved in the OFDM RF Tx
the input data stream is Serial to Parallel converted onto M subsystem are detailed below.
subcarriers which are independently modulated using QPSK
(or 16QAM). These M-modulated sub-carriers are the inputs The M parallel data streams of the input serial high data
to the N-point IFFT module to generate N-complex time- rate stream are defined as shown in (2).
domain samples. The output of the IFFT block is fed to a
Cyclic Prefix module in order to add a guard band at the S [k] = [S0[k], S1[k], S2[k]........, SM-1[k]]T (2)
 2016 IEEE International Conference on Computational Intelligence and Computing Research

X [k] = [X0[k], X1[k], X2[k]......., XM-1[k]]T (3)

x [k] = [x0[k], x1[k], x2[k]........, xN-1[k]]T (4)

where, ‘k’ is the index of the OFDM symbol.

These M parallel data streams are independently

modulated using QPSK (Quadrature Phase Shift Keying)
resulting in a complex vector defined as shown in (3). The
vector depicted in (3) is then subjected to N-point IFFT
processing (256-point IFFT in the architecture presented in Fig. 6. Simulation results of the ADC subsystem (12-bit Output of the ADC).
this paper) which results in a vector of N complex time-
domain samples as shown in (4). Cyclic prefix addition forms
the next crucial operation in a typical OFDM system which
includes copying the last ‘G’ samples of the Inverse FFT
output and adding them to the beginning of x[k]. The purpose
of doing this is to mitigate any remaining impacts of ISI due to
multipath propagation (Fading due to the reception of signals
from a variety of paths in any typical terrestrial environment).

At the receiver, the inverse procedures are carried out

subject to time and frequency synchronization in order to
optimally recover the ‘message’ signal (data stream from the
controller subsystem). The FFT-IFFT algorithmic pair
incorporated in OFDM is a faster and a simpler alternative to Fig. 7. Simulation results of the ADC subsystem (Analog input)
computing the DFTs or IDFTs directly. If x0, x1, x2, ……, xN-1
is a complex time domain sequence, the Discrete Fourier
Transform (DFT) is given by (5) and intuitively it’s inverse:
the Inverse Discrete Fourier Transform (IDFT) is depicted in
(6).
N-1
Xk = ∑ xn e-j2πnk/N , for k=0 to N-1 (5)
n=0

N-1
xn = ∑ Xk ej2πnk/N , for n=0 to N-1 (6)
k=0

We can deduce from (5) and (6) that the direct

computation of DFT/IDFT is slow and laborious. FFT-IFFT
bring down the complexity of computing DFT from O(n2) to
O(nlog n). Hence, computerized implementations where speed
Fig. 8. An 8051-controller based processing subsystem.
and processing power are of primary importance, incorporate
FFT and IFFT-based approaches of DFT computation.
The radio transmitter subsystem consists of an OFDM
based baseband processor employing QPSK modulation
IV. RESULTS AND DISCUSSIONS
schemes and a 256 point IFFT module described in Verilog
The architecture presented in this article encompasses a HDL. The RTL description of the design is simulated for
comprehensive modular design methodology with the entire functional verification. Prior to the actual hardware
system divided into three major subsystems. The sensor description of the radio transmitter subsystem, the design is
subsystem constituting a 4-channel 12-bit Delta Sigma ADC is modelled in Matlab and Simulink for the validation of the
described using Verilog AMS in the Cadence AMS Design functional correctness of the chosen parameters. The
suite (Cadence Virtuoso design environment and Spectre corresponding results are depicted in Fig. 11.
simulator). The simulation results of the sensor subsystem are
depicted in Fig. 6 and Fig. 7. The processor subsystem
architectural metrics are portrayed in Fig. 8. The general-
purpose controller configuration is described in Verilog HDL
and the corresponding simulation results are presented in Fig. 9
and Fig. 10.
 2016 IEEE International Conference on Computational Intelligence and Computing Research

V. CONCLUSION
The proposed architecture of a sensor node for
application in Industrial Wireless Sensor Networks (IWSNs)
constitutes three major subsystems: a sensor subsystem, a
processor subsystem and a radio transmitter subsystem. The
optimized 8051 controller core serves as the general-purpose
processor coupled with SPI Master-Slave interfaces with the
other two subsystems. The sensor subsystem constitutes a four
channel 12-bit Delta-Sigma ADC allowing interfaces with a
variety of sensors employed to monitor key parameters in the
industrial ecosystem. The radio transmitter subsystem consists
of an OFDM baseband processor providing numerous
advantages over other communication strategies, as described
in Section III of this article. Future works on the system
include the design of the RF front end, System Verilog based
Verification, Synthesis, Physical Design and more importantly
Fig. 9. Simulation results of the SPI Master-Slave module. enabling energy efficiency of the node through system-level
strategies facilitating reduced energy consumption.

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