Bq24725A 1-4 Cell Li+ Battery Smbus Charge Controller With N-Channel Power Mosfet Selector and Advanced Circuit Protection
Bq24725A 1-4 Cell Li+ Battery Smbus Charge Controller With N-Channel Power Mosfet Selector and Advanced Circuit Protection
Bq24725A 1-4 Cell Li+ Battery Smbus Charge Controller With N-Channel Power Mosfet Selector and Advanced Circuit Protection
bq24725A
SLUSAL0B – SEPTEMBER 2011 – REVISED NOVEMBER 2018
bq24725A 1-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET
Selector and Advanced Circuit Protection
1 Features 3 Description
1• SMBus Host-Controlled NMOS-NMOS The bq24725A is a high-efficiency, synchronous
Synchronous Buck Converter with Programmable battery charger, offering low component count for
space-constraint, multi-chemistry battery charging
615kHz, 750kHz, and 885kHz Switching
applications.
Frequencies
• Automatic N-channel MOSFET Selection of The bq24725A utilizes two charge pumps to
System Power Source from Adapter or Battery separately drive n-channel MOSFETs (ACFET,
RBFET and BATFET) for automatic system power
Driven by Internal Charge Pumps
source selection.
• Enhanced Safety Features for Over Voltage
Protection, Over Current Protection, Battery, SMBus controlled input current, charge current, and
Inductor and MOSFET Short Circuit Protection charge voltage DACs allow for very high regulation
accuracies that can be easily programmed by the
• Programmable Input Current, Charge Voltage, system power management micro-controller.
Charge Current Limits
The bq24725A uses internal input current register or
– ±0.5% Charge Voltage Accuracy up to 19.2V external ILIM pin to throttle down PWM modulation to
– ±3% Charge Current Accuracy up to 8.128A reduce the charge current.
– ±3% Input Current Accuracy up to 8.064A The bq24725A charges one, two, three or four series
– ±2% 20x Adapter Current or Charge Current Li+ cells.
Amplifier Output Accuracy
• Programmable Battery Depletion Threshold, and Device Information(1)
Battery LEARN Function PART NUMBER PACKAGE BODY SIZE (NOM)
• Programmable Adapter Detection and Indicator bq24725A VQFN (20) 3.50mm x 3.50mm
• Integrated Soft Start (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Integrated Loop Compensation
• Real Time System Control on ILIM pin to Limit RAC
Adapter SYS
Charge Current 4.5-24V Enhanced Safety:
OCP, OVP, FET Short
N-FET Driver
• AC Adapter Operating Range 4.5V-24V
N-FET Driver
• 5µA Off-State Battery Discharge Current Adapter Detection
bq24725A
• 0.65mA (0.8mA max) Adapter Standby Quiescent Battery
SMBus Controls V & I Hybrid Power Pack
Current with high accuracy
Boost Charge
RSR
Controller 1S-4S
20-pin 3.5 x 3.5 mm2 VQFN Package
SMBus
•
HOST
2 Applications Integration:
Loop Compensation; Soft-Start
• Portable Notebook Computers, UMPC, Ultra-Thin Comparator
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24725A
SLUSAL0B – SEPTEMBER 2011 – REVISED NOVEMBER 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.5 Register Maps ......................................................... 22
2 Applications ........................................................... 1 9 Application and Implementation ........................ 28
3 Description ............................................................. 1 9.1 Application Information............................................ 28
4 Revision History..................................................... 2 9.2 Typical Application .................................................. 28
9.3 Application Curves .................................................. 35
5 Pin Configuration and Functions ......................... 3
9.4 System Examples .................................................. 35
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 36
6.2 ESD Ratings.............................................................. 5 11 Layout................................................................... 37
6.3 Recommended Operating Conditions....................... 5 11.1 Layout Guidelines ................................................. 37
6.4 Thermal Information .................................................. 5 11.2 Layout Example ................................................... 38
6.5 Electrical Characteristics........................................... 6 12 Device and Documentation Support ................. 39
6.6 Timing Characteristics............................................. 10 12.1 Third-Party Products Disclaimer ........................... 39
6.7 Typical Characteristics ............................................ 10 12.2 Trademarks ........................................................... 39
7 Parameter Measurement Information ................ 12 12.3 Receiving Notification of Documentation Updates 39
12.4 Community Resources.......................................... 39
8 Detailed Description ............................................ 13
12.5 Electrostatic Discharge Caution ............................ 39
8.1 Overview ................................................................. 13
12.6 Glossary ................................................................ 39
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 16
Information ........................................................... 39
4 Revision History
Changes from Revision A (August 2014) to Revision B Page
RGR Package
Top View
PHASE
HIDRV
REGN
BTST
VCC
20 19 18 17 16
ACN 1 15 LODRV
ACP 2 14 GND
ACDRV 4 12 SRN
ACOK 5 11 BATDRV
6 7 8 9 10
ACDET
IOUT
SDA
ILIM
SCL
Pin Functions
PIN
DESCRIPTION
NO. NAME
1 ACN Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-
mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode
filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3 CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and
RBFET (Q2) limits the in-rush current on CMSRC pin.
4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET
(RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC
pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be
turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET
limits the in-rush current on ACDRV pin.
5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when
voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is
275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above
conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to
the pull-up supply rail.
6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times
the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to
GND.
8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pull-
up resistor according to SMBus specifications.
9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM
pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the
control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled
when ILIM pin rises above 105mV.
11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to
turn on BATFET to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power
system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on
BATDRV pin.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VALUE UNIT
MIN MAX
SRN, SRP, ACN, ACP, CMSRC, VCC –0.3 30
PHASE –2 30
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK –0.3 7
Voltage range BTST, HIDRV, ACDRV, BATDRV –0.3 36
LODRV (2% duty cycle) –4 7 V
HIDVR (2% duty cycle) –4 36
PHASE (2% duty cycle) –4 30
Maximum difference SRP–SRN, ACP–ACN –0.5 0.5
voltage
Junction temperature range, TJ –40 155 °C
Storage temperature range, Tstg –55 155 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Battery depletion rising hysteresis, VSRN ChargeOption() bit [12:11] = 01 240 325 430 mV
VBATDEPL_RHYST
rising ChargeOption() bit [12:11] = 10 255 345 450 mV
ChargeOption() bit [12:11] = 11 (Default) 280 370 490 mV
Battery Depletion Rising Deglitch Delay to turn off ACFET and turn on BATFET during
tBATDEPL_RDEG 600 ms
(Specified by design) LEARN cycle
BATTERY LOWV COMPARATOR (BAT_LOWV)
VBATLV_FALL Battery LOWV falling threshold VSRN falling 2.4 2.5 2.6 V
VBATLV_RHYST Battery LOWV rising hysteresis VSRN rising 200 mV
IBATLV Battery LOWV charge current limit 10 mΩ current sensing resistor 0.5 A
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT Thermal shutdown rising temperature Temperature rising 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20 °C
ILIM COMPARATOR
VILIM_FALL ILIM as CE falling threshold VILIM falling 60 75 90 mV
VILIM_RISE ILIM as CE rising threshold VILIM rising 90 105 120 mV
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold 0.8 V
VIN_ HI Input high threshold 2.1 V
IIN_ LEAK Input bias current V=7V –1 1 μA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO Output saturation voltage 5 mA drain current 500 mV
IOUT_ LEAK Leakage current V=7V –1 1 μA
ANALOG INPUT (ACDET, ILIM)
IIN_ LEAK Input bias current V=7V –1 1 μA
PWM OSCILLATOR
FSW PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz
(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(3) User can adjust threshold via SMBus ChargeOption() REG0x12.
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(2) User can adjust threshold via SMBus ChargeOption() REG0x12.
,
CH1: Vin, 10V/div , CH2: LODRV, 5V/div, CH3: PHASE, 10V/div
CH1: ILIM, 1V/div
CH4: inductor current, 2A/div, 2ms/div
CH4: inductor current, 1A/div, 4us/div
Figure 3. Current Soft-Start
Figure 4. Charge Disable by ILIM
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH1: PHASE, 10V/div, CH2: LODRV, 5V/div
CH3: HIDRV, 10V/div CH3: HIDRV, 10V/div
CH4: inductor current, 2A/div, 400ns/div CH4: inductor current, 1A/div, 400ns/div
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH2: battery current, 2A/div, CH3: adapter current, 2A/div
CH4: inductor current, 2A/div, 4us/div CH4: system load current, 2A/div, 100us/div
Figure 7. 100% Duty and Refresh Pulse Figure 8. System Load Transient (Input DPM)
8 Detailed Description
8.1 Overview
The bq24725A is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry
portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources
from 4.5V to 24V, and 1-4 cell battery for a versatile solution.
The bq24725A supports automatic system power source selection with separate drivers for n-channel MOSFETS
on the adapter side and battery side.
The bq24725A features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter over-
loading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating.
The SMBus controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits.
bq24725A
135mV
1.07
MASTER TO SLAVE
SLAVE TO MASTER
A B C D E F G H I J K
tLOW t HIGH
SMBCLK
SMBDATA
A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE
B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION
C = LSB OF ADDRESS CLOCKED INTO SLA VE G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION
D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER
The bq24725A has three loops of regulation: input current, charge current and charge voltage. The three loops
are brought together internally at the error amplifier. The maximum voltage of the three loops appears at the
output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO
(see Figure 10) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-
cycle.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh
cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve
duty cycle of up to 99.5%.
The SRP and SRN pins are used to sense RSR with default value of 10mΩ. However, resistors of other values
can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy;
but, at the expense of higher conduction loss. If the current sensing resistor value is too high, it may trigger an
over current protection threshold because the current ripple voltage is too high. In such a case, either a higher
inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level.
A current sensing resistor value no more than 20mΩ is suggested.
To provide secondary protection, the bq24725A has an ILIM pin with which the user can program the maximum
allowed charge current. Internal charge current limit is the lower one between the voltage set by
ChargeCurrent(), and voltage on ILIM pin. To disable this function, the user can pull ILIM above 1.6V, which is
the maximum charge current regulation limit. Equation 2 shows the voltage set on ILIM pin with respect to the
preferred charge current limit:
VILIM = 20 × (VSRP - VSRN ) = 20 ´ ICHG ´ RSR (2)
Figure 15. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
15 14 13 12 11 10 9 8
Not in use Not in use Not in use Charge Charge Charge Charge Charge
Current, Current, Current, Current, Current,
DACICHG 6 DACICHG 5 DACICHG 4 DACICHG 3 DACICHG 2
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Charge Charge Not in use Not in use Not in use Not in use Not in use Not in use
Current, Current,
DACICHG 1 DACICHG 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 17. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
15 14 13 12 11 10 9 8
Not in use Not in use Not in use Input Current, Input Current, Input Current, Input Current, Input Current,
DACIIN 5 DACIIN 4 DACIIN 3 DACIIN 2 DACIIN 1
R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Input Current, Not in use Not in use Not in use Not in use Not in use Not in use Not in use
DACIIN 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Q6
Reverse
R12 BSS138W U2
Input
1M EN IMD2A
Protection
R13
3.01M D2
BAT54C
Q1 (ACFET) Q2 (RBFET)
FDS6680A FDS6680A RAC 10m?
Adapter + SYSTEM
C17
Ri
2?
* 2200pF
C16
0.1µF R9
Total
Csys
C1 C3 10 Ω *
Adapter -
Ci* 0.1µF 0.1µF C5
220µF
2.2µF
1µF
C2 ACN VCC
0.1µF R6
R10 4.02 kW
R11
4.02 kW 4.02 kW ACP BATDRV Q5 (BATFET)
C15 FDS6680A
C6
1µF 0.01µF
CMSRC
REGN
ACDRV D1
R1 BAT54 C9
BTST C8
430 kW 10uF
10uF
ACDET
R2 Q3
R8 HIDRV
66.5 kW Sis412DN RSR
100 kW ILIM C7
R7 U1 0.047µF 10m?
316 kW bq24725A PHASE Pack +
L1
+3.3V C10 C11
R3 R4 R5 4.7µH 10µF 10µF
10 kW 10 kW 10 kW LODRV Q4
Sis412DN
SDA Pack -
HOST SMBus GND
SCL
SRP
Dig I/O ACOK R14
* C13
10 Ω 0.1µF
PowerPad SRN
ADC IOUT
C14
R15
C4
7.5 W
* 0.1µF
100 pF
Dig I/O EN
Fs = 750kHz, IADPT = 4.096A, ICHRG = 2.944A, ILIM = 4A, VCHRG = 12.592V, 90W adapter and 3S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversely battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversely connection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Ri and Ci for adapter hot
plug-in voltage spike damping. See application information about input filter design.
(1) Refer to adapter specification for settings for Input Voltage and Input Current Limit.
(2) Refer to battery specification for settings.
The bq24725A has charge under current protection (UCP) by monitoring charging current sensing resistor cycle-
by-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge for a
10mΩ charging current sensing resistor. When the average charging current is less than 125mA for a 10mΩ
charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh the
charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current.
1
Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ f s
2 (9)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
Q Q
t on = SW , t off = SW
Ion Ioff (10)
where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
1
QSW = QGD + ´ QGS
2 (11)
Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt Vplt
Ion = , Ioff =
Ron Roff (12)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) x ICHG 2 x RDS(on) (13)
When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the
freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss
depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D).
PD = VF x INONSYNC x (1 - D) (14)
The maximum charging current in non-synchronous mode can be up to 0.25A for a 10mΩ charging current
sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery
voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the
maximum non-synchronous mode charging current.
D1
R2(1206)
R1(2010) 10-20 Ω
Adapter 2Ω
connector VCC pin
C1
2.2μF C2
0.47-1μF
In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage
drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch
short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source and
can trig low side switch over current comparator. bq24725A senses the low side switch voltage drop through the
PHASE pin and GND pin.
The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not
only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace
voltage drop from ACN terminal of RAC to charger high side switch drain. Usually, there is a long trance between
input sensing resistor and charger converting input, a careful layout will minimize the trace effect.
To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is
very important. Figure 21 shows a improvement PCB layout example and its equivalent circuit. In this layout, the
system current path and charger input current path is not separated, as a result, the system current causes
voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point is
after charger input; as a result all system current voltage drops are counted into over current protection
comparator. The worst case for IC is when the total system current and charger input current sum equals the
DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant
current by reducing the charging current.
I DPM
R AC System Path PCB Trace
System current I SYS
R AC R PCB
I CHRGIN
Charger input current
Charger Input PCB Trace
ACP ACN Charger I BAT
To ACP To ACN
Figure 22 shows the optimized PCB layout example. The system current path and charge input current path is
separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the
possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high
system current application.
R AC System Path PCB Trace I DPM
System current I SYS
The total voltage drop sensed by IC can be express as the following equation.
Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK (15)
where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB
trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side
MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the
best layout shown in Figure 22 where the PCB trace only goes through charger input current while k equals 1
means the worst layout shown in Figure 21 where the PCB trace goes through all the DPM current. The total
voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut
down in normal operation.
The low side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command.
ChargeOption() bit[7] =0, 1 set the low side threshold 135mV and 230mV respectively. The high side MOSFET
short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8] = 0, 1 disable
the function and set the threshold 750mV respectively. For a fixed PCB layout, host should set proper short
circuit protection threshold level to prevent unintentional charger shut down in normal operation.
98
97
96
95
Efficiency - %
94
93 3-cell 12.6 V
4-cell 16.8 V
2-cell 8.4 V
92
91
90 VIN = 20 V,
F = 750 kHz,
89 L = 4.7 mH
88
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Charge Current
CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div
CH3: LODRV, 10V/div
CH4: inductor current, 2A/div, 400us/div
Fs = 750kHz, IADPT = 2.816A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 12.592V, 65W adapter and 3S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversely battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversely connection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Ri and Ci for adapter hot
plug in voltage spike damping. See application information about input filter design.
Figure 25. Typical System Schematic with One NMOS Selector and Schottky Diode
Q1 (ACFET) Q2 (RBFET)
FDS6680A FDS6680A RAC 10 mW
Adapter + SYSTEM
C17 C16 Total
2200pF R9
0.047µF
C1 C3 4.7 W
Csys *
0.1 µF 0.1µF 220 µF
Adapter - C5
Din* 1µF Q5 (BATFET)
BAT54A C2 ACN VCC R6 Si4435DDY
0.1µF 4.02 kW
R10
R11
4.02 kW ACP BATDRV D2
4.02 kW
C6 R12 SL42
CMSRC 1µF 100 kW
REGN
ACDRV D1
R1 BAT54 C9
BTST C8
430 kW 10uF
10uF
ACDET
R2 Q3
R8 HIDRV
487 kW Sis412DN RSR
100 kW ILIM C7
R7 U1 0.047µF 10 mW
549 kW bq24725A PHASE Pack +
+3.3V L1 C10 C11
R3 R4 R5 4.7µH 10 µF 10 µF
10 kW 10 kW 10 kW LODRV Q4
Sis412DN
SDA Pack -
H OST SMBus
GND
SCL
SRP
Dig I/O ACOK R14
* C13
10 W 0.1µF
IOUT PowerPad SRN
ADC
R15 * C14
C4 0.1µF
100 pF 7.5 W
Fs = 750kHz, IADPT = 2.048A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 4.200V, 12W adapter and 1S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversely battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversely connection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Din for reverse input
protection. See application information about reverse input voltage protection. When using a different Q1 and Q2 that
have a lower VGS(TH), a 500-kΩ resistor in parallel with C16 is required.
11 Layout
PHASE L1 R1 VBAT
High
VIN Frequency BAT
Current
Path GND C2
C1
12.2 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Oct-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ24725ARGRR ACTIVE VQFN RGR 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ25A
& no Sb/Br)
BQ24725ARGRT ACTIVE VQFN RGR 20 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ25A
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Oct-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2018
Pack Materials-Page 2
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