TSS721A

www.ti.com SLAS222B – APRIL 1999 – REVISED NOVEMBER 2010

METER-BUS TRANSCEIVER
Check for Samples: TSS721A

1FEATURES
D PACKAGE
• Meter-Bus Transceiver (for Slave) Meets (TOP VIEW)
Standard EN1434-3
BUSL2 1 16 BUSL1
• Receiver Logic With Dynamic Level
VB 2 15 GND
Recognition
• Adjustable Constant-Current Sink via Resistor STC 3 14 RIS

• Polarity Independent RIDD 4 13 RXI

• Power-Fail Function PF 5 12 RX
• Module Supply Voltage Switch SC 6 11 VDD
• 3.3-V Constant Voltage Source TXI 7 10 VS
• Remote Powering TX 8 9 BAT
• Up to 9600 Baud in Half Duplex for UART
Protocol
• Slave Power Support
– Supply From Meter-Bus via Output VDD
– Supply From Meter-Bus via Output VDD or
From Backup Battery
– Supply From Battery – Meter-Bus Active for
Data Transmission Only

DESCRIPTION
TSS721A is a single chip transceiver developed for Meter-Bus standard (EN1434-3) applications.
The TSS721A interface circuit adjusts the different potentials between a slave system and the Meter- Bus
master. The connection to the bus is polarity independent and supports full galvanic slave isolation with
optocouplers.
The circuit is supplied by the master via the bus. Therefore, this circuit offers no additional load for the slave
battery. A power-fail function is integrated.
The receiver has dynamic level recognition, and the transmitter has a programmable current sink.
A 3.3-V voltage regulator, with power reserve for a delayed switch off at bus fault, is integrated.

Table 1. ORDERING INFORMATION (1) (2)

TA PACKAGE ORDERABLE PART NUMBER
0°C to 70°C SOIC – D Reel of 2500 TSS721ADR

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TSS721A
SLAS222B – APRIL 1999 – REVISED NOVEMBER 2010 www.ti.com

FUNCTIONAL DESCRIPTION

VB
CS1 ICI2 IBUS

TC2 PF
RIDD ICS3
BAT
ISTC VF
BUSL1
BR
ISTC_use ICI1 BUSL2
STC
CS2

TX
TC3
TXI
VS
TC1 SC
IMS
IVDD
VDD
VVDD REF2 REF1 CS3 ECHO RX
3.3 V 1.3 V 7V TC4
RXI
RVS
RIS
GND

Figure 1. Functional Schematic

Table 2. Terminal Functions

TERMINAL
DESCRIPTION
NAME NO.
BUSL2 1 Meter-Bus
VB 2 Differential bus voltage after rectifier
STC 3 Support capacitor
RIDD 4 Current adjustment input
PF 5 Power fail output
SC 6 Sampling capacitor
TXI 7 Data output inverted
TX 8 Data output
BAT 9 Logic level adjust
VS 10 Switch for bus or battery supply output
VDD 11 Voltage regulator output
RX 12 Data input
RXI 13 Data input inverted
RIS 14 Adjust input for modulation current
GND 15 Ground
BUSL1 16 Meter-Bus

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Data Transmission, Master to Slave

The mark level on the bus lines VBUS = MARK is defined by the difference of BUSL1 and BUSL2 at the slave. It
is dependent on the distance of Master to Slave, which affects the voltage drop on the wire. To make the
receiver independent, a dynamic reference level on the SC pin is used for the voltage comparator TC3 (see
Figure 2).
VBUS
IBUS IBUS
VB to IC VMARK = 20.8 V to 42 V

VT
VSPACE = VMARK – 10 V

TX IBUS = Constant
BUSL1 TC3
BR TXI
BUSL2
ISCcharge
SC
VTX
ISCdischarge
CSC

GND VTXI
CBUSL1-BUSL2 = 30 pF typ
VB = 25 V, fmeas = 1 MHz

Figure 2. Data Transmission, Master to Slave

A capacitor CSC at pin SC is charged by a current ISCcharge and is discharged with a current ISCdischarge where:
ISCcharge
ISCdisharge =
40 (typ) (1)
This ratio is necessary to run any kind of UART protocol independent of the data contents. (for example, if an
11-bit UART protocol is transmitted with all data bits at 0 and only the stop bit at 1). There must be sufficient time
to recharge the capacitor CSC. The input level detector TC3 detects voltage modulations from the master,
VBUS = SPACE/MARK conditions, and switches the inverted output TXI and the non-inverted output TX.

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Data Transmission, Slave to Master

The device uses current modulation to transmit information from the slave to the master while the bus voltage
remains constant. The current source CS3 modulates the bus current and the master detects the modulation.
The constant current source CS3 is controlled by the inverted input RXI or the non-inverted input RX. The current
source CS3 can be programmed by an external resistor RRIS. The modulation supply current IMS flows in addition
to the current source CS3 during the modulation time.

IBUS VRX
VB to IC

ICS3 IMS

VRXI
CS3
BUSL1 RX
BR TC4
BUSL2 RXI
RIS VBUS
IBUS
VBUS = Constant
RRIS

GND ISPACE
IMC IMARK

IMC = IMS + ICS3

Figure 3. Data Transmission, Slave to Master

Because the TSS721A is configured for half-duplex only, the current modulation from RX or RXI is repeated
concurrently as ECHO on the outputs TX and TXI. If the slave, as well as the master, is trying to send
information via the lines, the added signals appear on the outputs TX and TXI, which indicates the data collision
to the slave (see Figure 1).
The bus topology requires a constant current consumption by each connected slave.
To calculate the value of the programming resistor RRIS, use the formula shown in Figure 4.
IMC
(mA) VRIS VRIS
RRIS = =
ICS3 IMC – IMS
20

VRIS = Voltage on pin RIS

15
RRIS = Programming resistor
ICS3 = Programmable current
10 IMC = Modulation current
Typical IMS = Modulation supply current (220 µA typ)
5

0 0.1 0.2 0.5 1 RRIS (kW)

Figure 4. Calculate Programming Resistor RRIS

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Slave Supply, 3.3 V

The TSS721A has an internal 3.3-V voltage regulator. The output power of this voltage regulator is supplied by
the storage capacitor CSTC at pin STC. The storage capacitor CSTC at pin STC is charged with constant current
ISTC_use from the current source CS1. The maximum capacitor voltage is limited to REF1. The charge current ISTC
has to be defined by an external resistor at pin RIDD.
The adjustment resistor RRIDD can be calculated using Equation 2.
V VRIDD
RRID = 25 RIDD = 25
ISTC ISTC_use + IIC1 (2)
Where,
ISTC = current from current source CS1
ISTC_use = charge current for support capacitor
ICI = internal current
VRIDD = voltage on pin RIDD
RRIDD = value of adjustment resistor
The voltage level of the storage capacitor CSTC is monitored with comparator TC1. Once the voltage VSTC
reaches VVDD_on, the switch SVDD connects the stabilized voltage VVDD to pin VDD. VDD is turned off if the
voltage VSTC drops below the VVDD_off level.
Voltage variations on the capacitor CSTC create bus current changes (see Figure 5).
IBUS
(mA)

916

914

912

910

1 2 3 4 5 6 7 8 VSTC (V)

Figure 5. Single Mode Bus Load

At a bus fault the shut down time of VDD (toff) in which data storage can be performed depends on the system
current IVDD and the value of capacitor CSTC. See Figure 6, which shows a correlation between the shutdown of
the bus voltage VBUS and VDD_off and toff for dimensioning the capacitor.
The output VS is meant for slave systems that are driven by the bus energy, as well as from a battery should the
bus line voltage fail. The switching of VS is synchronized with VDD and is controlled by the comparator TC1. An
external transistor at the output VS allows switching from the Meter-Bus remote supply to battery.

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Power On/Off
VBUS

VVB =VSTC + 0.6 V typical threshold voltage

for power fail PF

ton
VSTC

VDDon
VDDoff

VVS

VVDD

toff
VPF

V – VVDDoff
toff = CSTC STC
IVDD + ICI1

Figure 6. Power On/Off Timing

Power Fail Function

Because of the rectifier bridge BR at the input, BUSL1, and BUSL2, the TSS721A is polarity independent. The
pin VB to ground (GND) delivers the bus voltage VVB less the voltage drop over the rectifier BR. The voltage
comparator TC2 monitors the bus voltage. If the voltage VVB > VSTC + 0.6 V, then the output PF = 1. The output
level PF = 0 (power fail) provides a warning of a critical voltage drop to the microcontroller to save the data
immediately.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)
VMB Voltage, BUSL1 to BUSL2 ±50 V
RX and RXI –0.3 V to 5.5 V
VI Input voltage range
BAT –0.3 V to 5.5 V
TJ Operating junction temperature range –25°C to 150°C
TA Operating free-air temperature range –25°C to 85°C
TSTG Storage temperature range –65°C to 150°C
Power derating factor, junction to ambient 8 mW/°C

RECOMMENDED OPERATING CONDITIONS (1)

MIN MAX UNIT
Receiver 10.8 42
VMB Bus voltage, |BUSL2 – BUSL1| V
Transmitter 12 42
VB (receive mode) 9.3
VI Input voltage V
BAT (2) 2.5 3.8
RRIDD RIDD resistor 13 80 kΩ
RRIS RIS resistor 100 Ω
TA Operating free-air temperature –25 85 °C

(1) All voltage values are measured with respect to the GND terminal unless otherwise noted.
(2) VBAT(max) ≤ VSTC – 1 V

ELECTRICAL CHARACTERISTICS (1)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ΔVBR Voltage drop at rectifier BR IBUS = 3 mA 1.5 V
Voltage drop at current
ΔVCS1 RRIDD = 13 kΩ 1.8 V
source CS1
VSTC = 6.5 V, RRIDD = 13 kΩ 3
IBUS BUS current mA
IMC = 0 mA RRIDD = 30 kΩ 1.5
ΔIBUS BUS current accuracy ΔVBUS = 10 V, IMC = 0 mA, RRIDD = 13 kΩ to 30 kΩ 2 %
(2)
ICC Supply current VSTC = 6.5 V, IMC = 0 mA, VBAT = 3.8 V, RRIDD = 13 kΩ 650 µA
VSTC = 6.5 V, IMC = 0 mA, VBAT = 3.8 V, RRIDD = 13 kΩ,
ICI1 CI1 current 350 µA
VBUS = 6.5 V, RX/RXI = off (2)
IBAT BAT current –0.5 0.5 µA
IBAT + IVDD BAT plus VDD current VBUS = 0 V, VSTC = 0 V –0.5 0.5 µA
VVDD VDD voltage –IVDD = 1 mA, VSTC = 6.5 V 3.1 3.4 V
RVDD VDD resistance –IVDD = 2 to 8 mA, VSTC = 4.5 V 5 Ω
VDD = on, VS = on 5.6 6.4
VSTC STC voltage VDD = off, VS = off 3.8 4.3 V
IVDD < ISTC_use 6.5 7.5
RRIDD = 30 kΩ 0.65 1.1
ISTC_use STC current VSTC = 5 V mA
RRIDD = 13 kΩ 1.85 2.4
VRIDD RIDD voltage RRIDD = 30 kΩ 1.23 1.33 V
VVS VS voltage VDD = on, IVS = –5 µA VSTC – 0.4 VSTC V
RVS VS resistance VDD = off 0.3 1 MΩ
VVB = VSTC + 0.8 V, IPF = –100 µA VBAT – 0.6 VBAT
VPF PF voltage VSTC = 6.5 V VVB = VSTC + 0.3 V, IPF = 1 µA 0 0.6 V
VVB = VSTC + 0.3 V, IPF = 5 µA 0 0.9

(1) All voltage values are measured with respect to the GND terminal, unless otherwise noted.
(2) Inputs RX/RXI and outputs TX/TXI are open, ICC = ICI1 + ICI2
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ELECTRICAL CHARACTERISTICS(1) (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ton Turn-on time CSTC = 50 µF, Bus voltage slew rate: 1 V/µs 3 s

RECEIVER SECTION ELECTRICAL CHARACTERISTICS (1)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MARK MARK –
VT See Figure 2 V
– 8.2 5.7
VSC SC voltage VVB V
ISCcharge SC charge current VSC = 24 V, VVB = 36 V –15 –40 µA
–0.033 ×
ISCdischarge SC discharge current VSC = VVB = 24 V 0.3 µA
ISCcharge
High-level output voltage VBAT –
VOH ITX/ITXI = –100 µA (see Figure 2) VBAT V
(TX, TXI) 0.6
Low-level output voltage ITX/ITXI = 100 µA 0 0.5
VOL V
(TX, TXI) ITX = 1.1 mA 0 1.5
ITX
TX, TXI current VTX = 7.5, VVB = 12 V, VSTC = 6 V, VBAT = 3.8 V 10 µA
ITXI

(1) All voltage values are measured with respect to the GND terminal, unless otherwise noted.

TRANSMITTER SECTION ELECTRICAL CHARACTERISTICS (1)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IMC MC voltage RRIS = 100 Ω 11.5 19.5 mA
RRIS = 100 Ω 1.4 1.7
VRIS RIS voltage V
RRIS = 1000 Ω 1.5 1.8
(2) VBAT –
VIH High-level input voltage (RX, RXI) See Figure 3, see 5.5 V
0.8
VIL Low-level input voltage (RX, RXI) See Figure 3 0 0.8 V
VRX = VBAT = 3 V, VVB = VSTC = 0 V -0.5 0.5
IRX RX current µA
VRX = 0 V, VBAT = 3 V, VSTC = 6.5 V -10 -40
VRXI = VBAT = 3 V, VVB = VSTC = 0 V 10 40
IRXI RXI current µA
VRXI = VBAT = 3 V, VSTC = 6.5 V 10 40

(1) All voltage values are measured with respect to the GND terminal, unless otherwise noted.
(2) VIH(max) = 5.5 V is valid only when VSTC > = 6.5 V.

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APPLICATION INFORMATION
Remote Supply
RL1
11 1
VDD BUSL2
9
10
BAT 220
5
VS 2
12
PF TSS721A VB
13
RX
RXI RL2
8 16
TX BUSL1
7
TXI 220
CST Sensor System RIS SC GND RIDD STC
(e.g., MSP430)
14 6 15 4 3

T1

RRIS RRIDD

CSC + CSTC

Meter-Bus

RRIDD = 30 kW CSTC =< 220 µF single load 1UL

RRIDD = 13 kW CSTC =< 470 µF double load 2UL

NOTE: Transistor T1 should be a BSS84.

Figure 7. Basic Application Circuit Using Support Capacitor CSTC > 50 µF

RL1
11 1
VDD BUSL2
9 BAT
10 220
VS 2
5 PF VB
12 RX TSS721A
13 RXI RL2
8 TX 16
BUSL1
7 TXI
CSSC 220
+ BAT Sensor System
(e.g., MSP430)
14 6 15 4 3
Rload RRIS RRIDD
CVDD CSC + CSTC

Meter-Bus

CSSC - system stabilising capacitor RRIDD - slave-current adjustment resistor

CSTC - support capacitor RRIS - modulation-current resistor
CSC - sampling capacitor RL1,RL2 - protection resistors
CVDD - stabilising capacitor (100 nF) Rload - discharge resistor (100 kW recommended)
CSTC:CVDD >= 4:1

Figure 8. Basic Application Circuit for Supply From Battery

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Remote Supply
RL1
11
VDD BUSL2 1
9
BAT 220
10
VS
5
PF TSS721A VB 2
12
RX
13 RL2
RXI
8 TX BUSL1 16
7
TXI 220
CSSC Sensor System
(e.g., MSP430) RIS SC GND RIDD STC
14 6 15 4 3
RRIS RRIDD
CSC + CSTC

Remote Supply/Battery Support

RL1
11
VDD BUSL2 1
9 220
T1 BAT
10
VS
5
PF TSS721A VB 2
12
RX
13 RL2
RXI
8 TX BUSL1 16
7 220
TXI
+ BAT CSSC Sensor System
(e.g., MSP430) RIS SC GND RIDD STC
14 6 15 4 3
RRIS RRIDD
CSC + CSTC

Battery Supply RL1

11
VDD BUSL2 1
9
BAT 220
10
VS
5
PF TSS721A VB 2
12
RX
13 RL2
RXI
8 TX BUSL1 16
7
TXI 220
+ BAT CSSC Sensor System
(e.g., MSP430) RIS SC GND RIDD STC
14 6 15 4 3
Rload RRIS RRIDD

CVDD CSC + CSTC

Meter-Bus

NOTE: RDSon of the transistor T1 (BSS84) at low battery voltage must be considered during application design.

Figure 9. Basic Applications for Different Supply Modes

R3
RXI RL1
11
VDD BUSL2 1
9
BAT 220
10
R1 OC2 VS
5
PF TSS721A VB 2
C SSC Sensor System 12
+ BAT 13
RX
(e.g., MSP430) R4 RXI RL2
8
7
TX BUSL1 16
TXI 220
RIS SC GND RIDD STC
OC1 6 15
TXI 14 4 3

R2
Rload R RIS RRIDD
C VDD C SC + C STC

Meter-Bus

Figure 10. Basic Optocoupler Application

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 PACKAGE OPTION ADDENDUM

www.ti.com 18-Dec-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TSS721AD ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM TSS721A

& no Sb/Br)
TSS721ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM TSS721A
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
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