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TPS5430, TPS5431
SLVS632I – JANUARY 2006 – REVISED APRIL 2017

TPS543x 3-A, Wide Input Range, Step-Down Converter

1 Features 3 Description
1• Wide Input Voltage Range: The TPS543x is a high-output-current PWM converter
that integrates a low-resistance, high-side N-channel
– TPS5430: 5.5 V to 36 V MOSFET. Included on the substrate with the listed
– TPS5431: 5.5 V to 23 V features are a high-performance voltage error
• Up to 3-A Continuous (4-A Peak) Output Current amplifier that provides tight voltage regulation
accuracy under transient conditions; an undervoltage-
• High Efficiency up to 95% Enabled by 110-mΩ
lockout circuit to prevent start-up until the input
Integrated MOSFET Switch voltage reaches 5.5 V; an internally set slow-start
• Wide Output Voltage Range: Adjustable Down to circuit to limit inrush currents; and a voltage feed-
1.22 V with 1.5% Initial Accuracy forward circuit to improve the transient response.
• Internal Compensation Minimizes External Parts Using the ENA pin, shutdown supply current is
Count reduced to 18 μA typically. Other features include an
active-high enable, overcurrent limiting, over-voltage
• Fixed 500 kHz Switching Frequency for Small protection and thermal shutdown. To reduce design
Filter Size complexity and external component count, the
• Improved Line Regulation and Transient TPS543x feedback loop is internally compensated.
Response by Input Voltage Feed Forward The TPS5431 is intended to operate from power rails
• System Protected by Overcurrent Limiting, up to 23 V. The TPS5430 regulates a wide variety of
power sources including 24 V bus.
Overvoltage Protection and Thermal Shutdown
• –40°C to 125°C Operating Junction Temperature The TPS543x device is available in a thermally
Range enhanced, easy to use 8-pin SOIC PowerPAD™
package. TI provides evaluation modules and the
• Available in Small Thermally Enhanced 8-Pin SO Designer software tool to aid in quickly achieving
PowerPAD™ Package high-performance power supply designs to meet
• Create a Custom Design Using the TPS5430 With aggressive equipment development cycles.
the WEBENCH® Power Designer
Device Information(1)
2 Applications PART NUMBER PACKAGE INPUT VOLTAGE

• Consumer: Set-top Box, DVD, LCD Displays TPS5430 5.5 V to 36 V

HSOP (8)
TPS5431 5.5 V to 23 V
• Industrial and Car Audio Power Supplies
• Battery Chargers, High Power LED Supply (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• 12-V/24-V Distributed Power Systems

Simplified Schematic Efficiency vs Output Current

100
VIN VOUT
VIN PH 95
TPS5430/31 90

NC BOOT 85
Efficiency − %

80
NC
75
ENA VSENSE 70
GND VI = 12 V
65
VO = 5 V
60 fs = 500 kHz
o
55 TA = 25 C

50
0 0.5 1 1.5 2 2.5 3 3.5
IO - Output Current - A

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information............................................ 13
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 14
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 26
6 Specifications......................................................... 5 10 Layout................................................................... 26
6.1 Absolute Maximum Ratings ...................................... 5 10.1 Layout Guidelines ................................................. 26
6.2 ESD Ratings.............................................................. 5 10.2 Layout Example .................................................... 27
6.3 Recommended Operating Conditions....................... 5 11 Device and Documentation Support ................. 28
6.4 Thermal Information .................................................. 6 11.1 Device Support...................................................... 28
6.5 Electrical Characteristics........................................... 7 11.2 Related Links ........................................................ 28
6.6 Typical Characteristics .............................................. 8 11.3 Trademarks ........................................................... 28
7 Detailed Description ............................................ 10 11.4 Electrostatic Discharge Caution ............................ 28
7.1 Overview ................................................................. 10 11.5 Glossary ................................................................ 28
7.2 Functional Block Diagram ....................................... 10 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 11 Information ........................................................... 28

4 Revision History
Changes from Revision H (April 2016) to Revision I Page

• Added WEBENCH® Model ................................................................................................................................................... 1

• Changed Absolute Maximum Ratings PH (transient < 10 ns) spec MIN voltage from "–1.2" to "–4" .................................... 5

Changes from Revision G (February 2015) to Revision H Page

• Deleted "Recommended Land Pattern" figure from core data sheet. New drawings are furnished in the Mechanical,
Packaging, and Orderable Information section. ................................................................................................................... 27

Changes from Revision F (December 2014) to Revision G Page

• Fixed typo error TPS5430x to TPS513x ................................................................................................................................ 1

Changes from Revision E (September 2013) to Revision F Page

• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4

Changes from Revision D (January 2013) to Revision E Page

• Deleted SWIFT from the data sheet Title, Features, and Description.................................................................................... 1

Changes from Revision C (November 2006) to Revision D Page

• Replaced the DISSIPATION RATINGS with the THERMAL INFORMATION table............................................................... 5

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Changes from Revision B (August 2006) to Revision C Page

• Changed the Efficiency vs Output Current graph................................................................................................................... 1

• Changed the FUNCTIONAL BLOCK DIAGRAM .................................................................................................................. 10
• Added the Circuit Using Ceramic Output Filter Capacitors section...................................................................................... 24

Changes from Revision A (March 2006) to Revision B Page

• Added Note 3 to the ABSOLUTE MAXIMUM RATINGS table............................................................................................... 4

Changes from Original (January 2006) to Revision A Page

• Added Added device number TPS5431 ................................................................................................................................. 1

• Changed Figure 17............................................................................................................................................................... 22
• Added Figure 18 ................................................................................................................................................................... 23

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5 Pin Configuration and Functions

DDA Package
8-Pin SOIC with Thermal Pad
Top View

BOOT 1 8 PH

NC 2 7 VIN
PowerPAD
NC 3 6 GND

VSENSE 4 5 ENA

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH
BOOT 1 O
pin.
NC 2, 3 — Not connected internally.
VSENSE 4 I Feedback voltage for the regulator. Connect to output voltage divider.
ENA 5 I On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND 6 — Ground. Connect to PowerPAD.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR
VIN 7 —
ceramic capacitor.
PH 8 I Source of the high side power MOSFET. Connected to external inductor and diode.
PowerPAD — GND pin must be connected to the exposed pad for proper operation.

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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN –0.3 40 (3)
TPS5430
PH (steady-state) –0.6 40 (3)
VI Input voltage range
VIN –0.3 25
TPS5431
PH (steady-state) –0.6 25
ENA –0.3 7
BOOT-PH –0.3 10 V
VSENSE –0.3 3
PH (transient < 10 ns) –4
IO Source current PH Internally
Limited
Ilkg Leakage current PH 10 μA
TJ Operating virtual junction temperature range –40 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
TPS5430 5.5 36
VIN Input voltage range V
TPS5431 5.5 23
TJ Operating junction temperature –40 125 °C

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6.4 Thermal Information

TPS5430
TPS5431
(1) (2) (3)
THERMAL METRIC UNIT
DDA
8 PINS
(4)
RθJA Junction-to-ambient thermal resistance (2-layer custom board) 33
(5)
RθJA Junction-to-ambient thermal resistance (4-layer custom board) 26
RθJA Junction-to-ambient thermal resistance (standard board) 42.3
ψJT Junction-to-top characterization parameter 4.9
°C/W
ψJB Junction-to-board characterization parameter 20.7
RθJC(top) Junction-to-case(top) thermal resistance 46.4
RθJC(bottom) Junction-to-case(bottom) thermal resistance 0.8
RθJB Junction-to-board thermal resistance 20.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation may be limited by overcurrent protection
(3) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
(4) Test boards conditions:
(a) 3 in x 3 in, 2 layers, thickness: 0.062 inch.
(b) 2 oz. copper traces located on the top and bottom of the PCB.
(c) 6 thermal vias in the PowerPAD area under the device package.
(5) Test board conditions:
(a) 3 in x 3 in, 4 layers, thickness: 0.062 inch.
(b) 2 oz. copper traces located on the top and bottom of the PCB.
(c) 2 oz. copper ground planes on the 2 internal layers.
(d) 6 thermal vias in the PowerPAD area under the device package.

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6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VSENSE = 2 V, Not switching,
3 4.4 mA
IQ Quiescent current PH pin open
Shutdown, ENA = 0 V 18 50 μA
UNDERVOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO 5.3 5.5 V
Hysteresis voltage, UVLO 330 mV
VOLTAGE REFERENCE
TJ = 25°C 1.202 1.221 1.239
Voltage reference accuracy V
IO = 0 A – 3 A 1.196 1.221 1.245
OSCILLATOR
Internally set free-running frequency 400 500 600 kHz
Minimum controllable on time 150 200 ns
Maximum duty cycle 87% 89%
ENABLE (ENA PIN)
Start threshold voltage, ENA 1.3 V
Stop threshold voltage, ENA 0.5 V
Hysteresis voltage, ENA 450 mV
Internal slow-start time (0~100%) 6.6 8 10 ms
CURRENT LIMIT
Current limit 4 5 6 A
Current limit hiccup time 13 16 20 ms
THERMAL SHUTDOWN
Thermal shutdown trip point 135 162
°C
Thermal shutdown hysteresis 14
OUTPUT MOSFET
VIN = 5.5 V 150
rDS(on) High-side power MOSFET switch mΩ
110 230

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6.6 Typical Characteristics

530 3.5
VI = 12 V

520
f − Oscillator Frequency − kHz

I Q−Quiescent Current −mA

3.25
510

500

3
490

480
2.75

470

460
2.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
T − Junction Temperature − °C T J −Junction T emperature − °C

Figure 1. Oscillator Frequency vs. Junction Temperature Figure 2. Non-Switching Quiescent Current vs. Junction
Temperature
25 1.230
ENA = 0 V
−µ A

VREF - Voltage Reference - V

20 T J = 125°C 1.225
I SD −Shutdown Current

15 T J = 27°C 1.220

T J = –40°C
10 1.215

5 1.210
0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125
V I −Input V oltage −V TJ - Junction Temperature - °C

Figure 3. Shutdown Quiescent Current vs. Input Voltage Figure 4. Voltage Reference vs. Junction Temperature
180 9
V I = 12 V
170
TSS − Internal Slow Start Time − ms
DS(on) −On Resistance −mΩ

160
8.5
150

140
8
130

120

110 7.5
r

100

90 7
80 −50 −25 0 25 50 75 100 125
−50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C
T J −Junction Temperature − °C

Figure 5. On Resistance vs. Junction Temperature Figure 6. Internal Slow Start Time vs. Junction Temperature

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Typical Characteristics (continued)

Minimum Controllable On Time − ns 180 8

170
7.75

Minimum Duty Ratio - %

160

7.50
150

140
7.25

130
7
-50 -25 0 25 50 75 100 125
120 TJ - Junction Temperature - °C
−50 −25 0 25 50 75 100 125
TJ − Junction Temperature − °C

Figure 7. Minimum Controllable On Time vs. Junction Figure 8. Minimum Controllable Duty Ratio vs. Junction
Temperature Temperature

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7 Detailed Description

7.1 Overview
The TPS543x is a 3-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. The
TPS5431 is intended to operate from power rails up to 23 V and the TPS5430 up to 36 V. These devices
implement constant-frequency voltage-mode control with voltage feed forward for improved line regulation and
line transient response. Internal compensation reduces design complexity and external component count.
The integrated 110-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3-A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied
by a bootstrap capacitor connected from the BOOT to PH pins. The TPS543x reduces the external component
count by integrating the bootstrap recharge diode.
The TPS543x has a default input start-up voltage of 5.3 V typical. The ENA pin can be used to disable the
TPS543x reducing the supply current to 18 µA. An internal pullup current source enables operation when the
ENA pin is floating. The TPS543x includes an internal slow-start circuit that slows the output rise time during start
up to reduce in rush current and output voltage overshoot. The minimum output voltage is the internal 1.221-V
feedback reference. Output overvoltage transients are minimized by an Overvoltage Protection (OVP)
comparator. When the OVP comparator is activated, the high-side MOSFET is turned off and remains off until
the output voltage is less than 112.5% of the desired output voltage.
Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For
continuous overcurrent fault conditions the TPS543x will enter hiccup mode overcurrent limiting. Thermal
protection protects the device from overheating.

7.2 Functional Block Diagram

VIN

VIN

1.221 V Bandgap VREF SHDN Boot

UVLO Slow Start Regulator BOOT
Reference
HICCUP
5 µA
ENA ENABLE SHDN SHDN
VSENSE
Z1

Thermal
SHDN Error
Protection SHDN Z2
Amplifier

Ramp
NC VIN
Generator Feed Forward
Gain = 25

NC PWM HICCUP
SHDN
Comparator

GND Overcurrent
SHDN Oscillator Protection

SHDN
Gate Drive
VSENSE OVP Control
POWERPAD 112.5% VREF Gate
Driver
SHDN

BOOT PH

VOUT

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7.3 Feature Description

7.3.1 Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.

7.3.2 Voltage Reference

The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.

7.3.3 Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The
quiescent current of the TPS543x in shutdown mode is typically 18 μA.
The ENA pin has an internal pull-up current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms typically.

7.3.4 Undervoltage Lockout (UVLO)

The TPS543x incorporate an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the
internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start
threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates
until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.

7.3.5 Boost Capacitor (BOOT)

Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.

7.3.6 Output Feedback (VSENSE) and Internal Compensation

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS543x implements internal compensation to simplify the regulator design. Since the TPS543x uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications
section for more details.

7.3.7 Voltage Feed-Forward

The internal voltage feed-forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e.
Feed Forward Gain + VIN
Ramp
pk*pk (1)
The typical feed forward gain of TPS543x is 25.

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Feature Description (continued)

7.3.8 Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

7.3.9 Overcurrent Limiting

Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side
MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under
control of the slow start circuit.

7.3.10 Overvoltage Protection

The TPS543x has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from
output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage
and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side
MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side
MOSFET will be enabled again.

7.3.11 Thermal Shutdown

The TPS543x protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.

7.4 Device Functional Modes

7.4.1 Operation near Minimum Input Voltage
The TPS543x is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold is
5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage the device will not switch. If EN is floating or externally pulled up to greater up than 1.3 V, when
V(VIN) passes the UVLO threshold the TPS543x will become active. Switching is enabled and the slow-start
sequence is initiated. The TPS543x starts linearly ramping up the internal reference voltage from 0 V to its final
value over the internal slow-start time period.

7.4.2 Operation with ENA control

The enable start threshold voltage is 1.3 V max. With ENA held below the 0.5 V minimum stop threshold voltage
the TPS543x is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent
current is reduced in this state. If the ENA voltage is increased above the max start threshold while V(VIN) is
above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start sequence is
initiated. The TPS543x starts linearly ramping up the internal reference voltage from 0 V to its final value over the
internal slow-start time period.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS543x is a 3-A, step down regulator with an integrated high side MOSFET. This device is typically used
to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 3 A. Example
applications are: High Density Point-of-Load Regulators for Set-top Box, DVD, LCD and Plasma Displays, High
Power LED Supply, Car Audio, Battery Chargers, and other 12-V and 24-V Distributed Power Systems. Use the
following design procedure to select component values for the TPS543x. This procedure illustrates the design of
a high frequency switching regulator. Alternatively, use the WEBENCH software to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency

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8.2 Typical Applications

8.2.1 12-V Input to 5.0-V Output
Figure 9 shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3 A output
current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™
underneath the device must be soldered down to the printed-circuit board.
U1
TPS5430DDA C2 L1
10.8 - 19.8 V 7 0.01 mF 15 mH
VIN VIN 1 5V
5 BOOT VOUT
EN ENA
C1 2 8
NC PH D1 + C3
10 mF 3 R1
NC 4 B340A 220 mF 10 kW
6 VSNS
GND
PwPd
9
R2
3.24 kW

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Figure 9. Application Circuit, 12 V Input to 5.0 V Output

8.2.1.1 Design Requirements

For this design example, use the following as the input parameters:

DESIGN PARAMETER (1) EXAMPLE VALUE

Input voltage range 10.8 V to 19.8 V
Output voltage 5V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 3A
Operating frequency 500 kHz

(1) As an additional constraint, the design is set up to be small size and low component height.

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8.2.1.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS5430. This section presents
a simplified discussion of the design process.

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS5430 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Switching Frequency

The switching frequency for the TPS5430 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.

8.2.1.2.3 Input Capacitors

The TPS5430 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor, C1, is 10 μF. A high quality ceramic type X5R or X7R is
required. For some applications, a smaller value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.
This input ripple voltage can be approximated by Equation 2 :
I OUT(MAX) 0.25
DVIN +
C BULK ƒsw
ǒ
) I OUT(MAX) Ǔ
ESR MAX
(2)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CIN is the input capacitor value and
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 3 :
I
OUT(MAX)
I +
CIN 2 (3)
In this case the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that
the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5430 circuit is not located within about
2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to
handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage
is acceptable.

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8.2.1.2.4 Output Filter Components

Two components need to be selected for the output filter, L1 and C2. Since the TPS5430 is an internally
compensated device, a limited range of filter component types and values can be supported.

8.2.1.2.4.1 Inductor Selection

To calculate the minimum value of the output inductor, use Equation 4:
V
OUT(MAX)
V
IN(MAX)
ǒ
* V
OUT
Ǔ
L +
MIN V K I F
IN(max) IND OUT SW (4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak to
peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current
and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using
the TPS5430, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when paired with
the proper output capacitor, the peak switch current will be well below the current limit set point and relatively low
load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 12.5 μH. The next
highest standard value is 15 μH, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:

I
L(RMS)
+ Ǹ I2 )
1
OUT(MAX) 12 ǒ V
V
OUT
IN(MAX)
ǒVIN(MAX) * VOUTǓ
L
OUT
F
SW
0.8 Ǔ
2

(5)
and the peak inductor current can be determined with Equation 6:
V
OUT
ǒVIN(MAX) * VOUTǓ
I L(PK) + I )
OUT(MAX) 1.6 V IN(MAX) L F
OUT SW (6)
For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15 μH. It has a saturation current rating of 3.4 A and a RMS current rating
of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in
the range of 10 μH to 100 μH.

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8.2.1.2.4.2 Capacitor Selection

The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3
kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz
and also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover
frequency is related to the LC corner frequency by:
2
f LC
f CO +
85 VOUT (7)

And the desired output capacitor value for the output filter to:
C OUT + 1
3357 L OUT f CO V OUT
(8)
For a desired crossover of 18 kHz and a 15 μH inductor, the calculated value for the output capacitor is 220 μF.
The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be:
ESR MAX + 1
2p C OUT f CO
(9)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
ESRMAX x VOUT x ( VIN(MAX) - VOUT )
VPP (MAX) =
NC x VIN(MAX) x LOUT x FSW

where
• ΔVPP is the desired peak-to-peak output ripple.
• NC is the number of parallel output capacitors.
• FSW is the switching frequency. (10)
For this design example, a single 220 μF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3 A. An
additional small 0.1 μF ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54
kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:

ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ

ICOUT(RMS) + 1
Ǹ12 ȧVIN(MAX) LOUT FSW NCȧ
Ȣ Ȥ
where
• NC is the number of output capacitors in parallel.
• FSW is the switching frequency. (11)

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Other capacitor types can be used with the TPS5430, depending on the needs of the application.

8.2.1.2.5 Output Voltage Set-Point

The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R2 + R1 1.221
V * 1.221
OUT (12)
For any TPS5430 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.

8.2.1.2.6 BOOT Capacitor

The BOOT capacitor should be 0.01 μF.

8.2.1.2.7 Catch Diode

The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IOUT(MAX) plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.

8.2.1.2.8 Advanced Information

8.2.1.2.8.1 Output Voltage Limitations

Due to the internal design of the TPS543x, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX + 0.87 ǒǒVINMIN * I OMAX Ǔ Ǔ ǒ
0.230 ) VD * I OMAX Ǔ
RL * VD

where
• VINMIN = minimum input voltage
• IOMAX = maximum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance. (13)
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN + 0.12 ǒǒVINMAX * I OMIN Ǔ Ǔ ǒ
0.110 ) VD * I OMIN Ǔ
RL * VD

where
• VINMAX = maximum input voltage
• IOMIN = minimum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance. (14)

8.2.1.2.8.2 Internal Compensation Network

The design equations given in the example circuit can be used to generate circuits using the TPS543x. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited range
of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of
the TPS543x. Equation 15 gives the nominal frequency response of the internal voltage-mode type III
compensation network:
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ǒ1 ) 2p s
Fz1
Ǔ ǒ1 ) 2p s
Fz2
Ǔ
H(s) +
ǒ2p sFp0Ǔ ǒ1 ) 2p sFp1Ǔ ǒ1 ) 2p sFp2Ǔ ǒ1 ) 2p sFp3Ǔ
where
• fp0 = 2165 Hz, fz1 = 2170 Hz, fz2 = 2590 Hz
• fp1 = 24 kHz, fp2 = 54 kHz, fp3 = 440 kHz
• fp3 represents the non-ideal parasitics effect. (15)
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,
the closed loop transfer function can be derived.

8.2.1.2.8.3 Thermal Calculations

The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon = IOUT 2 x Rds(on) x VOUT/VIN
Switching Loss: Psw = VIN x IOUT x 0.01
Quiescent Current Loss: Pq = VIN x 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated Junction Temperature: TJ = TA + Rth x Ptot
Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX – Rth x Ptot

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8.2.1.3 Application Curves

The performance graphs (Figure 10 through Figure 16) are applicable to the circuit in Figure 9. Ta= 25 °C. unless
otherwise specified.

100 0.3

VI = 10.8 V 0.2
95 VI = 12 V
VI = 15 V

Output Regulation - %
0.1
Efficiency - %

90

VI = 19.8 V 0
VI = 18 V
85
-0.1

80
-0.2

75 -0.3
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3 3.5
IO - Output Current - A IO - Output Current - A

Figure 10. Efficiency vs. Output Current Figure 11. Output Regulation % vs. Output Current

0.1
VIN = 100 mV/Div (AC Coupled)
0.08

0.06

0.04 IO = 3 A IO = 1.5 A
Input Regulation - %

0.02

0 PH = 5 V/Div

-0.02
IO = 0 A
-0.04

-0.06

-0.08
-0.1
10.8 13.8 16.8 19.8 t -Time - 500 ns/Div
VI - Input Voltage - V

Figure 13. Input Voltage Ripple and PH Node,

Figure 12. Input Regulation % vs. Input Voltage IO = 3 A.

VOUT = 20 mV/Div (AC Coupled) VOUT = 50 mV/Div (AC Coupled)

PH = 5 V/Div IOUT = 1 A /Div

t - Time = 500 ns/Div t - Time = 200 μs/Div

Figure 14. Output Voltage Ripple and PH Node, Figure 15. Transient Response, IO
IO = 3 A Step 0.75 to 2.25 A.

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VIN = 5 V/Div

VOUT = 2 V/Div

t - Time = 2 ms/Div

Figure 16. Startup Waveform, VIN and VOUT.

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8.2.2 Wide Input Voltage Ranges with TPS5430

Figure 17 shows an application circuit using the wide input voltage range of the TPS5430.
U1 C2 L1
10-35 V TPS5430DDA 22 mH
0.01 mF 5V
VIN VIN
BOOT VOUT
C1 ENA ENA
C4 NC PH D1 + C3
4.7 mF
4.7 mF B340A 220 mF R1
NC
VSNS 10 kW
GND
PwPd

C3 = Sanyo POSCAP 10TP220M R2

3.24 kW

Copyright © Texas Instruments Incorporated

Figure 17. 10 V– 35 V Input to 5 V Output Application Circuit

8.2.2.1 Design Requirements

For this design example, use the following as the input parameters. This circuit is also designed with a larger
value output inductor and a lower closed loop crossover frequency.

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 10 V to 35 V
Output voltage 5V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 3A
Operating frequency 500 kHz

8.2.2.2 Detailed Design Procedure

The design procedure is similar to what is given for the design example in the 12-V Input to 5.0-V Output
Detailed Design Procedure section.

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8.2.2.3 Wide Input Voltage Ranges with TPS5431

Figure 18 shows an application circuit using the wide input voltage range of the TPS5431.
U1 C2 L1
9-21 V TPS5431DDA 18 mH
0.01 mF 5V
VIN VIN
BOOT VOUT
ENA ENA
C1 NC PH D1 + C3
B340A 220 mF R1
NC
VSNS 10 kW
GND
PwPd

C3 = Sanyo POSCAP 10TP220M R2

3.24 kW
Copyright © Texas Instruments Incorporated

Figure 18. 9 V – 21 V Input to 5 V Output Application Circuit

8.2.2.3.1 Design Requirements

For this design example, use the following as the input parameters. This circuit is also designed with a larger
value output inductor and a lower closed loop crossover frequency.

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 9 V to 21 V
Output voltage 5V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 3A
Operating frequency 500 kHz

8.2.2.3.2 Detailed Design Procedure

The design procedure is similar to what is given for the design example in the 12-V Input to 5.0-V Output
Detailed Design Procedure section.

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8.2.3 Circuit Using Ceramic Output Filter Capacitors

Figure 19 shows an application circuit using all ceramic capacitors for the input and output filters.

U1 C2 L1
VIN 10-24 V TPS5430DDA
0.01 mF 15 mH
7 3.3 V
VIN VIN 1
5 BOOT VOUT
EN ENA
C1 2 8
4.7 mF NC PH D1 C3
3 MRBS340 100 mF
NC 4
6 VSNS
GND PwPd
9

R1
C7 10 kW
0.1 mF
C4 R2
150 pF 5.9 kW
R3 C6
549 W 1500 pF

Copyright © Texas Instruments Incorporated

Figure 19. Ceramic Output Filter Capacitors Circuit

8.2.3.1 Design Requirements

For this design example, use the following as the input parameters. This circuit is also designed with a ceramic
output filter capacitor.

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 10 V to 24 V
Output voltage 3.3 V
Input ripple voltage 300 mV
Output current rating 3A
Operating frequency 500 kHz

8.2.3.2 Detailed Design Procedure

The design procedure is similar to what is given for the design example in the 12-V Input to 5.0-V Output
Detailed Design Procedure section, except for the selection of the output filter capacitor values and the design of
the additional compensation components required to stabilize the circuit.

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8.2.3.2.1 Output Filter Component Selection

Using Equation 11, the minimum inductor value is 12 μH. A value of 15 μH is chosen for this design.
When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than
7 kHz. Since the output inductor is already selected at 15 μH, this limits the minimum output capacitor value to:
1
CO (MIN) ³ 2
(2p x 7000) x LO (16)
The minimum capacitor value is calculated to be 34 μF. For this circuit a larger value of capacitor yields better
transient response. A single 100 μF output capacitor is used for C3. It is important to note that the actual
capacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to
3.3 V, minimizing this effect.

8.2.3.2.2 External Compensation Network

When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For this
circuit, the external components are R3, C4, C6, and C7. To determine the value of these components, first
calculate the LC resonant frequency of the output filter:
1
FLC =
2p Ö LO x CO (EFF) (17)
For this example the effective resonant frequency is calculated as 4109 Hz
The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
VO
Fp1 = 500000 x
FLC (18)
Fz1 = 0.7 x FLC (19)
Fz2 = 2.5 x FLC (20)
The final pole is located at a frequency too high to be of concern. The second zero, fz2 as defined by
Equation 20 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3 V output voltage as
calculated using Equation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ. With Fp1 = 401 Hz, Fz1 = 2876 Hz
and Fz2 = 10.3 kHz, the values of R3, C6 and C7 are determined using Equation 21, Equation 22, and
Equation 23:
1
C7 =
2p x Fp1 x (R1 || R2) (21)
1
R3 =
2p x Fz1 x C7 (22)
1
C6 =
2p x Fz2 x R1 (23)
For this design, using the closest standard values, C7 is 0.1 μF, R3 is 549 Ω, and C6 is 1500 pF. C4 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C4 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5430, TPS5431 or other wide voltage range
devices, see SLVA237 Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors

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9 Power Supply Recommendations

The TPS5430 is designed to operate from an input voltage supply range between 5.5 V and 36 V. The TPS5431
is designed to operate from an input voltage supply range between 5.5 V and 23 V. This input supply should
remain within the input voltage supply range. If the input supply is located more than a few inches from the
TPS543x converter bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 μF is a typical choice.

10 Layout

10.1 Layout Guidelines

Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS543x ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 20, use a via connection to a different layer to route to the ENA
pin.

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10.2 Layout Example

PH
CATCH
DIODE
BOOT
CAPACITOR
INPUT INPUT
BYPASS BULK
BOOT PH CAPACITOR FILTER
OUTPUT
INDUCTOR
NC VIN
Vin

NC GND

RESISTOR VSENSE ENA

DIVIDER

VOUT OUTPUT
FILTER TOPSIDE GROUND AREA
CAPACITOR

Route feedback VIA to Ground Plane

trace under output
filter capacitor or on Signal VIA
other layer

Figure 20. Design Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS5430 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

PRODUCT TECHNICAL TOOLS & SUPPORT & REFERENCE
PARTS SAMPLE & BUY
FOLDER DOCUMENTS SOFTWARE COMMUNITY DESIGN
TPS5430 Click here Click here Click here Click here Click here
TPS5431 Click here Click here Click here Click here Click here

11.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Documentation Feedback Copyright © 2006–2017, Texas Instruments Incorporated

Product Folder Links: TPS5430 TPS5431

 TPS5430, TPS5431
www.ti.com SLVS632I – JANUARY 2006 – REVISED APRIL 2017

PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.1 0.25
2.5 GAGE PLANE

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0

4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.

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Copyright © 2006–2017, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS5430 TPS5431
TPS5430, TPS5431
SLVS632I – JANUARY 2006 – REVISED APRIL 2017 www.ti.com

EXAMPLE BOARD LAYOUT

DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9

6X (1.27)

5
4

( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK

(1.3) TYP

(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221637/B 03/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

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Product Folder Links: TPS5430 TPS5431

 TPS5430, TPS5431
www.ti.com SLVS632I – JANUARY 2006 – REVISED APRIL 2017

EXAMPLE STENCIL DESIGN

DDA0008J PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8

8X (0.6)

(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62

4221637/B 03/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

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Product Folder Links: TPS5430 TPS5431
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Aug-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

HPA00295DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5431
& no Sb/Br)
TPS5430DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 0 5430
& no Sb/Br)
TPS5430DDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5430
& no Sb/Br)
TPS5430DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5430
& no Sb/Br)
TPS5430DDARG4 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5430
& no Sb/Br)
TPS5431DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5431
& no Sb/Br)
TPS5431DDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5431
& no Sb/Br)
TPS5431DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5431
& no Sb/Br)
TPS5431DDARG4 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 5431
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Aug-2017

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS5430 :

• Automotive: TPS5430-Q1
• Enhanced Product: TPS5430-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Mar-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS5430DDAR SO DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
TPS5431DDAR SO DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Mar-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5430DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
TPS5431DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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