6.2 Introduction To Op Amps: Objective

Introduction to Op Amps (7/17/00) Page 1
6.2 INTRODUCTION TO OP AMPS

INTRODUCTION
Objective
The objective of this presentation is:
1.) Characterize the operational amplifier
2.) Illustrate the analysis of both BJT and MOS op amps
3.) Illustrate the design of both BJT and MOS op amps
Outline
• Introduction and Characterization of Op Amps
• Compensation of Op Amps
General principles
Miller, Nulling Miller
Self-compensation
Feedforward
• Simple Op Amps
Two-stage
Folded-cascode
• Design of Op Amps
• Summary
ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000
INTRODUCTION AND CHARACTERIZATION OF OP AMPS
High-Level Viewpoint of an Op Amp

Block diagram of a general, two-stage op amp:
Compensation
Circuitry
v1 + Differential High vOUT Output vOUT'

Transconductance Gain Buffer
v2 - Stage Stage
Bias
Circuitry Fig. 6.1-1
• Differential transconductance stage:

Forms the input and sometimes provides the differential-to-single ended conversion.
• High gain stage:
Provides the voltage gain required by the op amp together with the input stage.
• Output buffer:
Used if the op amp must drive a low resistance.
• Compensation:
Necessary to keep the op amp stable when resistive negative feedback is applied.
Ideal Op Amp
Symbol:
i1 VDD
+
+ +
i2 vi
v1 - - +
+
VSS vOUT = Av(v1-v2)
v2
- - -
Fig. 6.1-2
Null port:
If the differential gain of the op amp is large enough then input terminal pair becomes a null port.
A null port is a pair of terminals where the voltage is zero and the current is zero.
I.e.,
v1 - v2 = vi = 0
and
i1 = 0 and i2 = 0
Therefore, ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current
flows into or out of the differential inputs.
General Configuration of the Op Amp as a Voltage Amplifier
R1
- R2
+ + +
vinn +
v2 vout
vinp v1
- - -
Fig. 6.1-3
Noniverting voltage amplifier:

R1+R2
vinn = 0 ⇒ vout =  R vinp
 1 
Inverting voltage amplifier:
R2 
vinp = 0 ⇒ vout = -R vinn
 1
Example 1 - Simplified Analysis of an Op Amp Circuit

The circuit shown below is an inverting voltage amplifier using an op amp. Find the voltage transfer function,
vout/vin.
R1 i1 i2 R2
+ + ii - +
vin vi + vout
- - -
Virtual Ground Fig. 6.1-4
Solution
If the differential voltage gain, Av, is large enough, then the negative feedback path through R2 will cause the
voltage vi and the current ii shown on Fig. 6.1-4 to both be zero. Note that the null port becomes the familiar
virtual ground if one of the op amp input terminals is on ground. If this is the case, then we can write that
vin
i1 = R
1
and
vout
i2 = R
2
Since, ii = 0, then i1 + i2 = 0 giving the desired result as

vout R2
vin = - R1 .
Linear and Static Characterization of the Op Amp

A model for a nonideal op amp that includes some of the linear, static nonidealities:
v1 Ricm IB2
CMRR en2
v2 * -
Rout vout
VOS * in2 Cid Rid
+
v1 Ideal Op Amp
Ricm IB1
Fig. 6.1-5
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
VOS = input-offset voltage
IB1 and IB2 = differential input-bias currents
IOS = input-offset current (IOS = IB1-IB2)
CMRR = common-mode rejection ratio
2
e n = voltage-noise spectral density (mean-square volts/Hertz)
2
i n = current-noise spectral density (mean-square amps/Hertz)
Linear and Dynamic Characteristics of the Op Amp

Differential and common-mode frequency response:
V1(s)+V2(s)
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s)  2

 
Differential-frequency response:
Av0 Av0 p1p2p3···
Av(s) =  = (s -p )(s -p )(s -p )···
s  s  s  1 2 3
p - 1p - 1p - 1···
 1  2  3 
where p1, p2, p3,··· are the poles of the differential-frequency response.
|Av(jω)| dB
Asymptotic
20log10(Av0) Magnitude
Actual -6dB/oct.
Magnitude
GB
ω2 ω3
0dB ω
ω1
-12dB/oct.
-18dB/oct. Fig. 6.1-6
Other Characteristics of the Op Amp

Power supply rejection ratio (PSRR):
∆VDD Vo/Vin (Vdd = 0)
PSRR = Av(s) =
∆VOUT Vo/Vdd (Vin = 0)
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary without influence the
differential performance
Slew rate (SR):
SR = output voltage rate limit of the op amp
Settling time (Ts):
Ts = time needed for the output of the op amp to reach a final value to with a predetermined tolerance when
excited by a small signal. (SR is large signal excitation)
vOUT(t)
Upper Tolerance
Final Value + ε
- ε
vOUT Final Value
vIN + ε Lower Tolerance
Final Value - ε
Settling Time
0 t
0 Ts Fig. 6.1-7
Classification of CMOS Op Amps

Categorization of op amps:
Conversion Hierarchy
Voltage Classic Differential Modified Differential

to Current Amplifier Amplifier
First
Voltage
Source/Sink Stage
Current Differential-to-single ended MOS Diode
to Voltage Load (Current Mirror) Current Loads Load
Current
Voltage Transconductance Transconductance Stage
to Current Grounded Gate Grounded Source
Second
Voltage
Current Class A (Source Class B Stage
to Voltage or Sink Load) (Push-Pull)
Table 6.1-1
Two-Stage Op Amp Architecture

Simple two-stage op amp broken into voltage-to-current and current-to-voltage stages:
VDD VCC
M3 M4 Q3 Q4
M6 Q6
-
vout vout vout
M1 M2 vin Q1 Q2
- + -
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- VSS - VEE
V→I I→V V→I I→V V→I I→V V→I I→V
OA01
Folded-Cascode Op Amp Architecture

Simple folded-cascode op amp broken into voltage-to-current and current-to-voltage stages:
VDD VCC
VBias VBias
M3 M10 M11 Q3 Q10 Q11
+ M1 M2 M8 M9 + Q1 Q2 Q8 Q9
vin vout - vin vout
- vout -
vin Q6 Q7
M6 M7 +
VBias
VBias
VBias
VBias
M4 M5 Q4 Q5
VSS VEE
V→ I I→I I→V V→ I I→I I→V OA015
COMPENSATION OF OP AMPS
GENERAL PRINCIPLES
Objective
Objective of compensation is to achieve stable operation when negative feedback is applied around the op
amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting
stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor.
Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over
the RHP zero.
2. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
3. Self compensating - Load capacitor compensates the op amp.
Single-Loop, Negative Feedback Systems

F(s)
-
Vin(s)
+ Σ A(s) Vout(s)
Fig. 6.2-1
A(s) = amplifier gain (normally the differential-mode voltage gain of the op amp)
F(s) = transfer function of the external feedback from the output of the op amp back to the input.
Definitions:
• Open-loop gain = L(s) = -A(s)F(s)
Vout(s) A(s)
• Closed-loop gain = V (s) = 1+A(s)F(s)
in
Stability Requirements:
The requirements for stability for a single-loop, negative feedback system is,
|A(jω0°)F(jω0°)| = |L(jω0°)| < 1
where ω0° is defined as
Arg[−A(jω0°)F(jω0°)] = Arg[L(jω0°)] = 0°
Another convenient way to express this requirement is
Arg[−A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)] > 0°
where ω0dB is defined as
|A(jω0dB)F(jω0dB)| = |L(jω0dB)| = 1
Illustration of the Stability Requirement using Bode Plots
|A(jω)F(jω)|
-20dB/decade
0dB ω
-40dB/decade
180°
Arg[-A(jω)F(jω)]
135°
90°
45°
ΦM
0° ω0dB ω
Fig. 6.2-2
Frequency (rads/sec.)
A measure of stability is given by the phase when |A(jω)F(jω)| = 1. This phase is called phase margin.
Phase margin = ΦM = Arg[-A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)]
Why Do We Want Good Stability?

Consider the step response of second-order system which closely models the closed-loop gain of the op amp.
1.4
45°
1.2 50°
55°
1.0
60°
65°
vout(t) 0.8 70°
Av0
0.6
0.4
0.2
0
0 5 10 15 Fig. 6.2-3
ωot = ωnt (sec.)
A “good” step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.
(A good rule of thumb for satisfactory stability is that there should be less than three rings.)
Uncompensated Frequency Response of Two-Stage Op Amps

Two-Stage Op Amps:
VDD VCC
M3 M4 Q3 Q4
M6 Q6
vout vout
- M1 M2 - Q1 Q2
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE OA016
Small-Signal Model:
D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)

+ + +
g v
gm1vin R1 C1 v1 m2 in v2 R3 C3 vout
2 gm4v1 R2 C2
2 - - gm6v2 -
OA03
Note that this model neglects the base-collector and gate-drain capacitances for purposes of simplification.
Uncompensated Frequency Response of Two-Stage Op Amps - Continued

For the MOS two-stage op amp:
1 1
R1 ≈ g ||rds3||rds1 ≈ g R2 = rds2|| rds4 and R3 = rds6|| rds7
m3 m3
C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7
For the BJT two-stage op amp:
1 1
R1 = g ||rπ3||rπ4||ro3 ≈ g R2 = rπ6|| ro2|| ro4 ≈ rπ6 and R3 = ro6|| ro7
m3 m3
C1 = Cπ3+Cπ4+Ccs1+Ccs3 C2 = Cπ6+Ccs2+Ccs4 and C3 = CL +Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
+ + + +
gm1vin v2 R3 C3 vout gm1Vin VI RII CII Vout
R2 C2 RI CI
- gm6v2 - - gmIIVI -
OA045
The locations for the two poles are given by the following equations
−1 −1
p’1 = R C and p’2 = R C
I I II II
where RI (RII) is the resistance to ground seen from the output of the first (second) stage and CI (CII) is the
capacitance to ground seen from the output of the first (second) stage.
Uncompensated Frequency Response of an Op Amp
Avd(0) dB
-20dB/decade
|A(jω)|
GB
0dB log10(ω)
Phase Shift -40dB/decade
-45°/decade
180°
Arg[-A(jω)]
135°
-45°/decade
90°
45°
0° log10(ω)
|p1'| |p2'| ω0dB Fig. 6.2-5
If we assume that F(s) = 1 (this is the worst case for stability considerations), then the above plot is the same as the
loop gain.
Note that the phase margin is much less than 45°.
Therefore, the op amp must be compensated before using it in a closed-loop configuration.
MILLER COMPENSATION
Two-Stage Op Amp
VDD VCC
M3 M4
Q3 Q4
CM M6 CM Q6
Cc vout Cc vout
M1 M2 Q1 Q2
- -
vin CI CII vin CI CII
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE OA046
The various capacitors are:

Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage
Simplification of the Compensated Two-Stage, Small-Signal Frequency Response Model

Use the CMOS op amp to illustrate:
1.) Assume that gm3 >> gds3 + gds1
gm3
2.) Assume that C >> GB
M
Therefore,
Cc
v1 v2
+
-gm1vin vout
2 1 gm2vin
rds1||rds3 CM gm3 2 gm4v1 C1 rds2||rds4 gm6v2 rds6||rds7 CL -
Cc
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- -
Fig. 6.2-5B
Same circuit holds for the BJT op amp with different component relationships.
General Two-Stage Frequency Response Analysis

Cc
V2 where
+ +
gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
Vin gmIVin Vout
CI RI gmIIV2 RII CII
- - and
Fig. 6.2-6
gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations:
-gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramer’s rule gives,
Vout(s) gmI(gmII - sCc)
=
Vin(s) GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
Ao[1 - s (Cc/gmII)]
=
1+s [RI(CI+CII)+RII(C2+Cc)+gmIIR1RIICc]+s2[RIRII(CICII+CcCI+CcCII)]
where, Ao = gmIgmIIRIRII
 s s 1 1 s2 s s2
In general, D(s) = 1 - p  1 - p  = 1 - s p + p  + p p→ D(s) ♠ 1 - p + p p , if |p2|>>|p1|
 1  2  1 2 1 2 1 1 2
-1 -1 gmII
∴ p1 = R (C +C )+R (C +C )+g R R C ♠ g R R C , z= C
I I II II II c mII 1 II c mII 1 II c c
-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII

p2 = RIRII(CICII+CcCI+CcCII) ♠ C C +C C +C C ♠ C where CII > Cc > CI.
I II c I c II II
Summary of Results for Miller Compensation of the Two-Stage Op Amp

There are three roots of importance:
1.) Right-half plane zero:
This root is very undesirable because it boosts the loop magnitude while decreasing the phase.
2.) Dominant left-half plane pole (the Miller pole):
gmII gm6
z1= C = C
c c
-1 -(gds2+gds4)(gds6+gds7)
p1 ♠ g =
mIIRIRIICc gm6Cc
This root accomplishes the desired compensation.
3.) Left-half plane output pole:
-gmII -gm6
p2 ♠ C ♠ C
II L
This pole must be beyond the unity-gainbandwidth or the phase margin will not be satisfied.
Root locus plot of the Miller compensation:
Closed-loop poles, Cc≠0 jω

Open-loop poles
Cc=0
σ
p2 p2' p1' p1 z1 Fig. 6.2-7A
Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
Avd(0) dB Uncompensated
|A(jω)F(jω)|
-20dB/decade
Compensated
GB
0dB log10(ω)
Phase Shift -40dB/decade
Uncompensated
180°
Arg[-A(jω)F(jω)|
-45°/decade
135°
90° -45°/decade
Compensated Phase
45°
No phase margin Margin
0° log10(ω)
|p1| |p1'| |p2'| |p2|
Fig. 6.2-7B
Note that the unity-gainbandwidth, GB, is

1 gmI gm1 gm2
GB = Avd(0)·|p1| = (gmIgmIIRIRII)g R R C = C = C = C
mII I II c c c c
Conceptually, where do these roots come from?

1.) The Miller pole: VDD
RII
Cc
1
|p1| ♠ R (g vout
I m6RIICc) RI
M6
vI
≈gm6RIICc
Fig. 6.2-9
2.) The left-half plane output pole:

VDD VDD
RII RII
Cc
vout vout gm6
1 |p2| ♠ C
M6 GB·Cc ≈ 0 M6 II
CII CII
Fig. 6.2-10
VDD
3.) Right-half plane zero (Zeros always arise from multiple paths from RII
the input to output): Cc
gm6  vout
-RII sC - 1
-gm6RII(1/sCc)  RII   c  M6
vout =  R + 1/sC  v’ + R + 1/sC  v’’ = R + 1/sC v
   v''
v'
 II c   II c II c
Fig. 6.2-11
where v = v’ = v’’.
Influence of the Mirror Pole

Up to this point, we have neglected the influence of the pole, p3, associated with the current mirror of the input
stage. If |p2| ≈ |p3|, we have problems in compensation. This pole is given approximately as
-gm3
p3 ♠ C
M
F=1 jω
Closed-loop poles
Avd(0) dB Cc = 0
-6dB/octave -p3
σ
-p2 -p z1
Open-loop poles 1
Cc ≠ 0
GB
0dB log10(ω)
Phase Shift Roll-off due to p3
-12dB/octave
0° Cc = 0
-45°/decade
45°
Cc ≠ 0
90° -45°/decade
Cc ≠ 0
135° Phase
Cc = 0 Margin
180° Phase margin log10(ω)
|p1| due to p3 |p3| |p2|
Excess Phase Fig. 6.2-11A
due to p3
Summary of the Conditions for Stability of the Two-Stage Op Amp (Assuming p3≥GB)
• Unity-gainbandwith is given as:
 1  gmI  1  gm1
GB = Av(0)·|p1| = (gmIgmIIRIRII)·g = = ( g m1 g m2 R1 R2 ) ·  =
 mIIRIRIICc Cc gm2R1R2Cc Cc
• The requirement for 45° phase margin is:
ω ω ω
±180° - Arg[AF] = ±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
Let ω = GB and assume that z ≥ 10GB, therefore we get,
GB GB GB
±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
GB GB
135° ≈ tan-1(Av(0)) + tan-1|p | + tan-1(0.1) = 90° + tan-1|p | + 5.7°
 2  2
GB GB
39.3° ≈ tan-1|p | ⇒ |p | = 0.818 ⇒ |p2| ε 1.22GB
 2 2
• The requirement for 60° phase margin:
|p2| ε 2.2GB if z ε 10GB
• If 60° phase margin is required, then the following relationships apply:
gm6 10gm1 gm6 2.2gm1
Cc > Cc ⇒ gm6 > 10gm1 and C2 > Cc ⇒ Cc > 0.22C2
Controlling the Right-Half Plane Zero

Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for stability.
jω
jω3
jω2
180° > θ1 > θ2 > θ3
θ3
jω1 θ2
θ1
σ Fig. 6.2-11B
z1
Solution of the problem:
If zeros are caused by two paths to the output, then eliminate one of the paths.
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model:
Cc
+1 Cc
VI
+ +
Inverting vOUT Vin gmIvin CI RI Vout Vout
gmIIVI RII CII
High-Gain - -
Stage
OA047
The transfer function is given by the following equation,

Vo(s) (gmI)(gmII)(RI)(RII)
=
Vin(s) 1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
−1 −1
p1 ≅ ≅g RR C
RICI + RIICII + RICc + gmIIRIRIICc mII I II c
and
−gmIICc
p2 ≅
CII(CI + Cc)
Comments:
Poles are approximately what they were before with the zero removed.
For 45° phase margin, |p2| must be greater than GB
For 60° phase margin, |p2| must be greater than 1.73GB
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of Ro.
Model:
Cc Ro
+1 Cc
VI
+ Vout +
vOUT Vin gmIvin CI RI Ro Ro Vout
Inverting
gmIIVI RII CII
High-Gain - -
Stage
OA0475
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected that another pole occurs at,
−1
p4 ≅
Ro[CICc/(CI + Cc)]
and a LHP zero at
−1
z2 ≅ R C
o c
Closer examination shows that if a resistor, called a nulling resistor, is placed in series with Cc that the RHP zero
can be eliminated or moved to the LHP.
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)†
Cc Rz
Cc Rz
VI
+ +
vOUT Vin gmIvin CI RI Vout
Inverting CII
gmIIVI RII
High-Gain - -
Stage
Fig. 6.2-13
Nodal equations:
VI  sCc  Vo  sCc 
gmIVin + R + sCIVI +   (V − V ) = 0
 I out gmIIVI + R + sCIIVout +   (V − V ) = 0
 out I
I 1 + sC R
c z II 1 + sC R
c z
Solution:
Vout(s) a{1 − s[(Cc/gmII) − RzCc]}
Vin(s) = 1 + bs + cs2 + ds3
where
a = gmIgmIIRIRII
b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]
d = RIRIIRzCICIICc
†
William J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of Calif., Santa Barbara,
CA.
Use of Nulling Resistor to Eliminate the RHP - Continued

If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of the above transfer function
can be approximated as
−1 −1
p1 ≅ ≅g R RC
(1 + gmIIRII)RICc mII II I c
−gmIICc −gmII
p2 ≅ ≅ C
CICII + CcCI + CcCII II
−1
p4 = R C
z I
and
1
z1 =
Cc(1/gmII − Rz)
Note that the zero can be placed anywhere on the real axis.
Conceptual Illustration of the Nulling Resistor Approach

VDD
RII
Cc Rz
Vout
M6
V''
V'
Fig. 6.2-14
The output voltage, Vout, can be written as
 1   gm6 
-gm6RIIRz + sC  -RIIgm6Rz + sC - 1
 c RII  c 
Vout = 1 V’ + 1 V” = 1 V
RII + Rz + sC RII + Rz + sC RII + Rz + sC
c c c
when V = V’ = V’’.
Setting the numerator equal to zero and assuming gm6 = gmII gives,
1
z1 =
Cc(1/gmII − Rz)
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1 −gmII jω
= C σ
Cc(1/gmII − Rz) II -p1
-p4 -p2 z1 OA0477
The value of Rz can be found as
Cc + CII
Rz =  C  (1/gmII)
 c 
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain stability, all that is
required is that
Av(0) gmI
|p4| > Av(0)|p1| = g =
mIIRIIRICc Cc
and
(1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc > gmII CICII
This procedure gives excellent stability for a fixed value of CII (≈ CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
Increasing the Magnitude of the Output Pole†

The magnitude of the output pole , p2, can be increased by introducing gain in the Miller capacitor feedback path.
For example,
VDD Cc
rds8
M11 M4 M7 + + +
Cc
vOUT Iin R1 V1 Vs8 R2 C2 Vout
g m8Vs8
- - gm6V1 -
M8 VBias Ignore rds8
M6 Cc
+ + +
M10 M9 Iin R1 V1 1 R2 C2 Vout
gm8 Vs8g V
VSS
- gm8Vs8 - m6 1 -
Fig. 6.2-15
The resistors R1 and R2 are defined as
1 1
R1 = g + g + g and R2 = g + g
ds2 ds4 ds9 ds6 ds7
where transistors M2 and M4 are the output transistors of the first stage.
Nodal equations:
 gm8sCc   gm8sCc 
Iin = G1V1 - gm8Vs8 = G1V1 - g + sC  Vout and 
0 = gm6V1 + G2 + sC2 + g + sC  Vout
 m8 c  m8 c
†
B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18, No. 6 (Dec.
1983) pp. 629-633.
Increasing the Magnitude of the Output Pole - Continued

Solving for the transfer function Vout/Iin gives,
 sCc 

Vout  -gm6  

1 + 
=

 gm8 
Iin G1G2
1 + s gCc + GC2 + GCc + gGm6GCc + s2 gCcCG2 
  m8 2 2 1 2   m8 2
Using the approximate method of solving for the roots of the denominator illustrated earlier gives
-1 -6
p1 = C ≈
Cc C2 gm6Cc gm6rds2Cc
c
gm8 + G2 + G2 + G1G2
and
gm6rds2Cc
- 6 gm8rds2G2 gm6 gm8rds
p2 ≈ C C =  
6  C2  =  3  |p2’|
c 2  
gm8G2
where all the various channel resistance have been assumed to equal rds and p2’ is the output pole for normal
Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by roughly gmrds.
Concept Behind the Increasing of the Magnitude of the Output Pole
VDD VDD
rds7 gm8rds8 rds7

Cc 3
vout vout
1
M8 GB·Cc ≈ 0 M6
CII
M6 CII
Fig. 6.2-16
 3  3
Rout = rds7||g  ♠
 m6gm8rds8 gm6gm8rds8
Therefore, the output pole is approximately,
gm6gm8rds8
|p2| ♠ 3CII
FEEDFORWARD COMPENSATION
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
RHP Zero Cc LHP Zero Cc LHP Zero using Follower
A -A Cc
Vi Vout Vi Vout Vi Vout

+1
Inverting Inverting
High Gain CII RII High Gain CII RII
Amplifier Amplifier
Cc
A
+ +
Vi gmIIVi CII RII Vout
- - Fig. 6.2-17
Vout(s) ACc  s + gmII/ACc 


=
Vin(s) Cc + CII s + 1/[RII(Cc + CII)]
To use the LHP zero for compensation, a compromise must be observed.
• Placing the zero below GB will lead to boosting of the loop gain which could deteriorate the phase margin.
• Placing the zero above GB will have less influence on the leading phase caused by the zero.
Note that a source follower is a good candidate for the use of feedforward compensation.
SELF-COMPENSATED OP AMPS
Self compensation occurs when the load capacitor is the compensation capacitor (can never be unstable for
resistive feedback)
|dB|
Rout(must be large) Av(0) dB

- + -20dB/dec.
vin Gm vout
+ -
Rout CL
Increasing CL
OA048 0dB ω
Voltage gain:
vout
vin = Av(0) = GmRout
Dominant pole:
-1
p1 = R
outCL
Unity-gainbandwidth:
Gm
GB = Av(0)·|p1| = C
L
Stability:
Large load capacitors simply reduce the GB and the phase is 90° at the unity gain frequency
SIMPLE TWO-STAGE OP AMPS

BJT Two-Stage Op Amp
Circuit:
VCC
I3 I4 Q6
IBias
Q3 Q4
I6
I1 I2
Cc
vOUT
Q1 Q2
-
vIN
+ CL
I7
Q5 I5
Q8 Q7
x1 x1 xn
VEE OA02
DC Conditions:
I5 = Ibias, I1 = I2 = 0.5I5 = 0.5Ibias, I7 = I6 = nIBias
Vicm(max) = VCC - VEB3 - VCE1(sat) + VBE1
Vicm(min) = VEE +VCE5(sat) + VBE1
Vout(max) = VCC - VEC6(sat)
Vout(min) = VEE + VCE7(sat)
Notice that the output stage is class A ⇒ Isink = I7 and Isource = βFI5 - I7
Two-Stage BJT Op Amp - Continued

Small Signal Performance:
Assuming differential mode operation, we can write the small-signal model as,
Cc
+ + +
g v
gm1vin R1 C1 v1 m2 in v2 R3 C3 vout
2 gm4v1 R2 C2
2 - - gm6v2 -
OA035
where,
1 1
R1 = g ||rπ3||rπ4||ro3 ≈ g R2 = rπ6|| ro2|| ro4 ≈ rπ6 and R3 = ro6|| ro7
m3 m3
C1 = Cπ3+Cπ4+Ccs1+Ccs3 C2 = Cπ6+Ccs2+Ccs4 and C3 = CL +Ccs6+Ccs7
Note that we have ignored the base-collector capacitors, Cµ, except for M6, which is called Cc.
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives
Cc
+ +
gm1vin v2 R3 C3 vout
R2 C2
- gm6v2 -
OA04
Two-Stage BJT Op Amp - Continued

Summary of the small signal performance:
Midband performance-
Ao = gmIgmIIRIRII ≈ gm1gm6rπ6(ro6||ro7) = gm1βF6(ro6||ro7), Rout = ro6||ro7, Rin = 2rπ1
Roots-
gmII gm6
Zero = C = C
c c
-1 -1 -gm1 -gmII -gm6

Poles at p1 ≈ g R R C = g r (r ||r )C = A C and p2 ♠ C ♠ C
mII I II c m6 π6 o6 o7 c o c II L
Assume that βF =100, gm1 = 1mS, gm6 = 10mS, ro6 = ro7 = 0.5MΩ, Cc = 5pF and CL = 10pF:
Ao = (1mS)(100)( 250kΩ) = 25,000V/V, Rin = 2(βF/gm1) 2(100kΩ) = 200kΩ, Rout = 250kΩ
10mS
Zero = 5pF = 2x109 rads/sec or 318.3MHz,
-1mS -2x108
p1 = (25,000)5pF = 25,000 = -8000 rads/sec or 1273Hz,
-10mS
and p2 = 10pF = 109 rads/sec or 159.15MHz
jω
-8x103
σ
-109 2x109 OA06
Slew Rate of the Two-Stage BJT Op Amp

Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as
dvC
Ilim = C dt where vC is the voltage across the capacitor C.
VCC VCC
Q6 Q6
Q3 Q4 I6 ICL Q3 Q4 I6=0
Cc I5 vout Cc I5 ICL
vout
- Q1 Q2 Assume a CL - Q1 Q2 Assume a CL
vin>>0 virtural I7 vin<<0 virtural I7
+ ground + ground
I5 I5
+ Q7 + Q7
VBias Q5 VBias Q5
- -
VEE VEE
Positive Slew Rate Negative Slew Rate OA07
 I5 I6-I5-I7 I5  I5 I7-I5 I5
SR = minC , C  = C because I6>>I5
+ SR = minC , C  = C if I7>>I5.
-
 c L  c  c L  c
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate of the two-stage op amp
should be,
I5
SR = C
c
Folded-Cascode BJT Op Amp

Circuit
VCC VCC
Q3
VBias
IC3 Q10 Q11 VBE + Q10 Q11
iC10 iC11 VCE(sat) iC10 iC11
+ Q1 Q2 Q8 Q9 i
vin out vout iout vout
Q8 Q9
-
iC1 iC2 Q6 Q7 Q6
VBias Q7
RA RB
IC4 IC5 VBE + Q4 IC4 Q5 IC5
VBias VCE(sat)
VBE
Q4 Q5
VEE VEE
Simplified circuit Biasing details of the output OA08
DC Conditions:
I3 = Ibias, I1 = I2 = 0.5I5 = 0.5Ibias, I4 = I5 = kIBias I10 = I11 = kIBias - 0.5Ibias (k>1)
Vicm(max) = VCC - VCE3(sat) + VEB1 Vicm(min) = VEE +VCE4(sat) + VEC1(sat) -VBE1
Vout(max) = VCC - VEC9(sat) - VEC11(sat) Vout(min) = VEE + VCE5(sat) + VCE7(sat)
Notice that the output stage is push-pull ⇒ Isink and Isource are limited by the base current.
Folded-Cascode BJT Op Amp - Continued

Small-Signal Analysis:
gm6vbe6 gm7vbe7
RA RB
i7
i10 +
- -
gm1vin gm2vin
rπ6 vbe6 ro6 1 vbe7 ro7 i vout
2 ro1 ro4 2 ro2 ro5 rπ7 10 βro11
+ gm10 + -
OA09
ro7+βPro11/2 rπ7
where RA ≈ 1/gm6 and RB ≈ 1+g r ♠ 2 if ro7 ≈ ro11
m7 o7
-gm1rπ6vin -gm1vin gm2rπ7vin gm2rπ7vin gm2vin
i10 ≈ 2(r +R ) ♠ 2 i7 ≈ 2(r +R ) ♠ 2(r +0.5r ) = 3
π6 A π7 B π7 π7
5 vout 5
∴ vout = (i7-i10)βPRoutvin = 6 (gm1βPRout)vin if gm1 = gm2 ⇒ vin = 6 (gm1βPRout)
Rout = βPro11|| [βΝ (ro5||ro2)] and Rin = 2rπ1
Assume that βFN =100, βFP =50, gm1 = gm2 =1mS, roN = 1MΩ, and roP = 0. 5MΩ:
vout
vin = 14,285V/V Rout = 14.285 MΩ and Rin = 100kΩ
Folded-Cascode BJT Op Amp - Continued

Frequency response includes only 1 dominant pole at the output (self-compensation),
-1
p1 = R C
out L
There are other poles but we shall assume that they are less than GB
If CL = 25pF, then |p1| = 2800 rads/sec. or 446Hz ⇒ GB = 6.371 MHz
Checking some of the nondominant poles gives:
1 gm6
|pA| = R C = C ⇒ 159MHz if CA = 1pf (the capacitance to ac ground at the emitter of Q6)
A A A
1 2
|pB| = R C = r C ⇒ 6.37MHz if CB = 1pf (the capacitance to ac ground at the emitter of Q7)
B B π7 B
This indicates that for small capacitive loads, this op amp will suffer from higher poles with respect to phase
margin. Capacitive loads greater than 25pF, will have better stability (and less GB).
Two-Stage CMOS Op Amp

Circuit:
VDD
VSG4 + VSG6 +
- -
M6
IBias I
3 M3 M4 I4 I6
vout
I1 I42
- M1 M2 CL
vin I7
+
I5
M8 M7
M5
x1 x1 xn
VSS OA10
DC Conditions:
I5 = Ibias, I1 = I2 = 0.5I5 = 0.5Ibias, I7 = I6 = nIBias
Vicm(max) = VDD - VSG3 + VT1
Vicm(min) = VSS +VDS5(sat) + VGS1
Vout(max) = VDD - VSD6(sat)
Vout(min) = VSS + VDS7(sat)
KN’W6
Notice that the output stage is class A ⇒ Isink = I7 and Isource = 2L (VDD-VSS-VT)2 - I7
6
DC Balance Conditions for the Two-Stage Op Amp

For best performance, keep all transistors in saturation. VDD
M4 is the only transistor that cannot be forced into saturation by VSG4 + VSG6 +
- -
internal connections or external voltages. M6
M3 M4 I4 Cc I6
Therefore, we develop conditions to force M4 to be in saturation. vout
1.) First assume that VSG4 = VSG6. This will cause “proper
- M1 M2 CL
mirroring” in the M3-M4 mirror. Also, the gate and drain of M4 vin I7
are at the same potential so that M4 is “guaranteed” to be in +
saturation. I5
M7
+ M5
VBias
Wi S6
2.) Let Si ≡ L , if VSG4 = VSG6, then I6 = S I4
-
VSS
i  4 Fig. 6.3-1A
S7 S7
3.) However, I7 = S I5 = S  2I4
 
( )
 5  5
S6 2S7
4.) For balance, I6 must equal I7 ⇒ S4 = S5 which is called the “balance conditions”
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
Small-Signal Performance of the Two-Stage CMOS Op Amp

VDD
VSG4 + VSG6 +
- -
M6
IBias I Cc
3 M3 M4 I4 I6
vout
I1 I42
- M1 M2 CL
vin I7
+
I5
M8 M7
M5
x1 x1 xn
VSS
Cc
v1 v2
+
-gm1vin vout
2 1 gm1vin
rds1||rds3 CM gm3 2 gm4v1 C1 rds2||rds4 gm6v2 rds6||rds7 CL -
gm3
gm3 > gds2+gds4 > GB
Cc CM
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- - OA11
Small-Signal Performance of the Two-Stage CMOS Op Amp

Summary of the small signal performance:
Midband performance-
Ao = gmIgmIIRIRII ≈ gm1gm6(rds2||rds4)(rds6||rds7), Rout = rds6||rds7, Rin = ∞
Roots-
gmII gm6
Zero = C = C
c c
-1 -(gds2+gds4)(gds6+gds7) -gmII -gm6

Poles at p1 ♠ g R R C = gm6Cc and p2 ♠ C ♠ C
mII I II c II L
Assume that gm1 = 100µS, gm6 = 1mS, rds2 = rds4 = 2MΩ rds6 = rds7 = 0.5MΩ, Cc = 5pF and CL = 10pF:
Ao = (100µS)(1MΩ)(1000µS)(0.25MΩ) = 25,000V/V, Rin = ∞, Rout = 250kΩ
1000µS 8
Zero = 5pF = 2x10 rads/sec or 31.83MHz,
-1
p1 = = -800 rads/sec or 127.3Hz, GB = 3.178MHz
(1mS)(1MΩ)(0.25MΩ)(5pF)
-1000µS
and p2 = 10pF = 108 rads/sec or 15.915MHz
jω
-8x102
σ
-108 2x108 OA12
Slew Rate of a Two-Stage CMOS Op Amp

Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as
dvC
Ilim = C dt where vC is the voltage across the capacitor C.
VDD VDD
M6 M6
M3 M4 I6 ICL M3 M4 I6=0
Cc I5 Cc I5 ICL
vout vout
- M1 M2 Assume a CL - M1 M2 Assume a CL
vin>>0 virtural I7 vin<<0 virtural I7
+ ground + ground
I5 I5
+ M7 + M7
VBias M5 VBias M5
- -
VSS VSS
Positive Slew Rate Negative Slew Rate Fig. 6.2-18
 I5 I6-I5-I7 I5  I5 I7-I5 I5
SR = minC , C  = C because I6>>I5
+ SR = minC , C  = C if I7>>I5.
-
 c L  c  c L  c
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate of the two-stage op amp
should be,
I5
SR = C
c
Folded Cascode, CMOS Op Amp
VDD
M14 M4 I4 M5 I5
A B
RA RB
I1 I2
M13 M6 I6 M7 I7
+ M1 M2 R1 vout
vin
- R2 CL
I3
M8 M9
+ M12
VBias M3
M10 M11
-
VSS Fig. 6.5-7
Comments:
• The bias currents, I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I5=I6=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating
• Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise
along with the input transistors. (Some first stage gain can be achieved if RA and RB are greater than gm1 or
gm2.
Small-Signal Analysis of the Folded Cascode Op Amp

Model:
gm6vgs6 gm7vgs7
RA RB
i7
i10 +
- -
gm1vin gm2vin
rds1 rds4 vgs6 rds6 1 rds2 rds5 vgs7 rds7 i vout
2 R2+g 2 10 RII
+ m10 + -
Fig. 6.5-8
Recalling what we learned about the resistance looking into the source of the cascode transistor,
rds6+R2+(1/gm10) 1 rds7 + RII RII
RA = 1 + gm6rgs6 ♠ gm6 and R =
B 1+g r ♠ gm7rds7 where RII ≈gm9rds9rds11
m7 ds7
The small-signal voltage transfer function can be found as follows. The current i10 is written as
-gm1(rds1||rds4)vin -gm1vin
i10 = 2[R + (r ||r )] ♠ 2
A ds1 ds4
and the current i7 can be expressed as
gm2(rds2||rds5)vin gm2vin gm2vin RII(gds2+gds4)
i7 =  = = where k=
RII   RII(gds2+gds5) 2(1+k) gm7rds7
2g r + (rds2||rds5) 21 + gm7rds7 
 m7 ds7  
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
vout gm1 gm2   2+k 
=  + R = 
2(1+k) out 2+2k gmIRout

vin  2
Frequency Response of the Folded Cascode Op Amp

The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as
-1
pout = R C
out out
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions for each pole is
-1
1.) Pole at node A: pA ♠ R C
A A
-1
2.) Pole at node B: pB ♠ R C
B B
-1
3.) Pole at drain of M6: p6 ♠ (R +1/g )C
2 m10 6
-gm8
4.) Pole at source of M8: p8 ♠ C
8
-gm9
5.) Pole at source of M9: p9 ♠ C
9
-gm10
6.) Pole at gate of M10: p10 ♠ C
10
where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance
seen to ground from a given node. One might feel that because RB is approximately rds that this pole might be too
small. However, at frequencies where this pole has influence, Cout, causes Rout to be much smaller making pB also
non-dominant.
Folded Cascode, CMOS Op Amp - Example

Assume that all gmN = gmP = 100µS, rdsN = 2MΩ, rdsP = 1MΩ, and CL = 10pF. Find all of the small-signal
performance values for the folded-cascode op amp.
0.4x109(0.3x10-6)
RII = 0.4GΩ, RA = 10kΩ, and RB = 4MΩ ∴ k= 100 = 1.2
vout 2+1.2
vin = 2+2.2 (100)(57.143) = 4,354V/V
 
Rout = RII ||[gm7rds7(rds5||rds2)] = 400MΩ||[(100)(0.667MΩ)] = 57.143MΩ

1 1
|pout| = R C = = 1,750 rads/sec. ⇒ 278Hz ⇒ GB = 1.21MHz
out out 57.143MΩ·10pF
Comments on the Folded Cascode, CMOS Op Amp:

• Good PSRR
• Good ICMR
• Self compensated
• Can cascade an output stage to get extremely high gain with lower output resistance (use Miller compensation
in this case)
• Need first stage gain for good noise performance
• Widely used in telecommunication circuits where large dynamic range is required
OP AMP DESIGN
Unbuffered, Two-Stage CMOS Op Amp
VDD
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig. 6.3-1
Notation:
Wi
Si = L = W/L of the ith transistor
i
Design Relationships for the Two-Stage Op Amp

I5
Slew rate SR = C (Assuming I7 >>I5 and CL > Cc)
c
gm1 2gm1
First-stage gain Av1 = =
gds2 + gds4 I5(λ2 + λ4)
gm6 gm6
Second-stage gain Av2 = =
gds6 + gds7 I6(λ6 + λ7)
gm1
Gain-bandwidth GB = C
c
−gm6
Output pole p2 = C
L
gm6
RHP zero z1 = C
c
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are ≥ 10GB.
I5
Positive ICMR Vin(max) = VDD − − |VT03|(max) + VT1(min))
β3
I5
Negative ICMR Vin(min) = VSS + + VT1(max) + VDS5(sat)
β1
2IDS
Saturation voltageVDS(sat) =
β
It is assumed that all transistors are in saturation for the above relationships.
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters are given.
1. Gain at dc, Av(0)
2. Gain-bandwidth, GB
Max. ICMR
3. Phase margin (or settling time)
and/or p3
VDD Vout(max)
4. Input common-mode range, ICMR + +
VSG4 VSG6
5. Load Capacitance, CL - -
M6 gm6 or
6. Slew-rate, SR M3 M4 Cc Proper Mirroring
I6
7. Output voltage swing g VSG4=VSG6
GB = m1
Cc vout
8. Power dissipation, Pdiss -
CL
vin Cc ≈ 0.2CL
M1 M2
(PM = 60°)
+
Min. ICMR I5 I5 = SR·Cc
Vout(min)
+
VBias M5 M7
-
VSS Fig. 6.3-2
Unbuffered Op Amp Design Procedure

This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input common mode range
(Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR), settling time (Ts), output voltage swing (Vout(max)
and Vout(min)), and power dissipation (Pdiss) are given. Choose the smallest device length which will keep the
channel modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase margin we use the
following relationship. This assumes that z ≥ 10GB.
Cc > 0.22CL
2. Determine the minimum value for the “tail current” (I5) from the largest of the two values.
VDD + |VSS|
I5 = SR .Cc or I5 ≅ 10 
 2 .Ts 
3. Design for S3 from the maximum input voltage specification.
I5
S3 = ≥1
K'3[VDD − Vin(max) − |VT03|(max) + VT1(min)]2
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (=0.67W3L3Cox) will not be dominant by assuming it to be
greater than 10 GB
gm3
2Cgs3 > 10GB.
5. Design for S1 (S2) to achieve the desired GB.
gm2
gm1 = GB . Cc ⇒ S2 = K' I
2 5
Unbuffered Op Amp Design Procedure - Continued

6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
I5 2I5
VDS5(sat) = Vin(min) − VSS − − VT1(max) ≥ 100 mV → S5 = K' [V (sat)]2
β1 5 DS5
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that VSG4 = VSG6.
gm6
gm6 = 2.2gm2(CL/Cc) → S6 = S4 g
m4
8. Calculate I6 from
gm62
I6 = 2K' S
6 6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
10.Check gain and power dissipation specifications.
2gm2gm6
Av = Pdiss = (I5 + I6)(VDD + |VSS|)
I5(λ2 + λ3)I6(λ6 + λ7)
11.If the gain specification is not met, then the currents, I5 and I6, can be decreased or the W/L ratios of M2 and/or
M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power
dissipation is too high, then one can only reduce the currents I5 and I6. Reduction of currents will probably
necessitate increase of some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.
Example 6.3-1 - Design of a Two-Stage Op Amp

Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that
shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1µm.
Av > 3000V/V VDD = 2.5V VSS = -2.5V 60° phase margin
GB = 5MHz CL = 10pF SR > 10V/µs
Vout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc, which is
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10 × 106) = 30 µA
3.) Next calculate (W/L)3 using ICMR requirements.
30 × 10-6
(W/L)3 = =3 → (W/L)3 = (W/L)4 = 3
(50x10-6)[2.5 − 2 − .85 + 0.55]2
4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB. Assume
the Cox = 0.4fF/µm2. The mirror pole can be found as
-gm3 - 2K’pS3I3
p3 ♠ 2C = 2(0.667)W L C = 6.79x109(rads/sec)
gs3 3 3 ox
or 1.08 GHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
Example 6.3-1 - Continued

5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2π)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
gm12 (94.25)2
(W/L)1 = (W/L)2 = 2K’ I = 2·110·15 = 2.79 ≈ 3.0 ⇒ (W/L)1 = (W/L)2 = 3
N 1
6.) Next calculate VDS5,

30x10-6
VDS5 = (−1) − (−2.5) − - .85 = 0.35V
110x10-6·3
Using VDS5 calculate (W/L)5 from the saturation relationship.
2(30 × 10-6)
(W/L)5 = = 4.49 ≈ 4.5 → (W/L)5 = 4.5
(110 × 10-6)(0.35)2
7.) For 60° phase margin, we know that
gm6 ≥ 10gm1 ≥ 942.5µS
Assuming that gm6 = 942.5µS and knowing that gm4 = 67µS, we calculate (W/L)6 as
942.5 × 10-6
(W/L)6 = 3 = 42.2 ≈ 40
(67 × 10-6)

(942.5 × 10-6)2
8.) Calculate I6 using the small-signal gm expression: I6 = = 211.5µA ≈ 212µA
(2)(50 × 10-6)(42)
If we calculate (W/L)6 based on Vout(max), the value is approximately 38. Since 42 exceeds the specification and
maintains better phase margin, we will stay with (W/L)6 = 42 and I6 = 212µA.
With I6 = 212µA the power dissipation is
Pdiss = 5V·(30µA+212µA) = 1.21mW.
9.) Finally, calculate (W/L)7
234 × 10-6
(W/L)7 = 4.5   = 35.1 ≈ 35 → (W/L)7 = 35
 30 × 10-6 
Let us check the Vout(min) specification although the W/L of M7 is so large that this is probably not necessary.
The value of Vout(min) is
2·234
Vout(min) = VDS7(sat) = 110·35 = 0.349V
which is less than required. At this point, the first-cut design is complete.
10.) Now check to see that the gain specification has been met
(92.45 × 10-6)(942.5 × 10-6)
Av = = 3,383V/V
15 × 10-6(.04 + .05)212 × 10-6(.04 + .05)
which barely meets specifications. We might want to consider decreasing the output current back to 190µA to
increase the second-stage gain by a factor of 1.1 or better yet, increase the channel length to 2µm causing a gain
increase of 20.
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp
Circuit:
VDD
M11 M3 M4 V
B
VA M6
M10 CM Cc vout
M8
VC vin- vin+
M1 M2
CL
IBias
M9 M5
M12 M7
VSS Fig. 6.3-4
We saw earlier that the roots were:

gm2 gm1 gm6
p1 = − A C = − A C p2 = − C
v c v c L
1 −1
p3 = − R C z1 =
z I RzCc − Cc/gm6
where Av = gm1gm6RIRII. (Note that p3 is the pole resulting from the nulling resistor compensation technique.)
Design of the Nulling Resistor (M8)

In order to place the zero on top of the second pole (p2), the following relationship must hold
1 CL + Cc Cc+CL 1
Rz = g  C  =  C 
m6  c   c  2K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active region because the dc current
through it is zero. Therefore, Rz, can be written as
vDS8 1
Rz = ⊆ =
iD8 V =0 K’PS8(VSG8-|VTP|)
DS8
The bias circuit is designed so that voltage VA is equal to VB.
W11 I10 W6
    
∴ |VGS10| − |VT| = |VGS8| − |VT| ⇒ VSG11 = VSG6 ⇒  L11  =  I6   L6 
    
In the saturation region
2(I10)
|VGS10| − |VT| = K'P(W10/L10) = |VGS8| − |VT|
1 K’PS10 1 S10
∴ Rz = K’ S 2I10 = S8 2K’PI10
P 8
Equating the two expressions for Rz gives

W8
   Cc  S10S6I6
 
 L8  = CL + Cc I10
   
Example 6.3-2 - RHP Zero Compensation

Use results of Ex. 6.3-1 and design compensation circuitry so that the RHP zero is moved from the RHP to
the LHP and placed on top of the output pole p2. Use device data given in Ex. 6.3-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I10. The first step in this
design is to establish the bias components. In order to set VA equal to VB, thenVSG10 must equal VSG6. Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 30µA which gives S11 = (30A/212µA)42 = 5.94 ≈ 6.
W11 = 6µm
The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1. There must be sufficient
supply voltage to support the sum of VSG11, VSG10, and VDS9. The ratio of I10/I5 determines the (W/L) of M9. This
ratio is
(W/L)9 = (I10/I5)(W/L)5 = (30/30)(4.5) = 4.5
W9 = 4.5µm
Now (W/L)8 is determined to be
 3pF  1·42·212µA
(W/L)8 = 3pF+10pF 30µA = 3.98
 
W8 = 3.98µm ≈ 4µm

It is worthwhile to check that the RHP zero has been moved on top of p2. To do this, first calculate the value
of Rz. VSG8 must first be determined. It is equal to VSG10, which is
2I10 2·30
VSG10 = K’PS10 + |VTP| = 50·1 + 0.7 = 1.795V
Next determine Rz.
1 106
Rz = K’ S (V = = 4.601kΩ
P 8 SG10-|VTP|) 50·3.97(1.795-.7)
The location of z1 is calculated as

−1
z1 = = -94.16x106 rads/sec
-12
3x10-12
(4.601 × 10 )(3x10 ) −
3
942.5x10-6
The output pole, p2, is
942.5x10-6
p2 = = -94.25x106 rads/sec
10x10-12
Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved
from the RHP to the LHP.
The results of this design are summarized below.
W8 = 4µm W9 = 4.5µm W10 = 1µm W11 = 6µm
An Alternate Form of Nulling Resistor
To cancel p2, VDD
Cc+CL 1 M11 M10

z1 = p2 → Rz = g =
m6ACC gm6B M3 M4
M6
Which gives vout
- M1 M2 M6B
 Cc 
gm6B = gm6AC +C  vin Cc CL
 c L +
+ M8 M9
In the previous example, M7
VBias M5
gm6A = 942.5µS, Cc = 3pF and CL = 10pF. -
VSS Fig. 6.3-4A
Choose I6B = 10µA to get

gm6ACc 2KPW6BI6B  Cc  2KPW6AID6
gm6B = C + C → L6B = C +C  L6A
c L  c L
or
W6B  3 2 I6A W6A  3 2 234
L6B = 13 I6B L6A = 13  10 (23) = 28.7 → W6B = 29µm
     
Implementation of Cc using a MOS Transistor

Two Approaches:
1.) Have to keep VGS ≥ VT
Cc
CGB CGS
VSS
VGS
VGS
VT Fig. 6.3-04B
2.) Better - VGS not restricted

Cc
CGS CGB VGS
VT VGS
Fig. 6.3-4C
Programmability of the Two-Stage Op Amp

The following relationships depend on the bias current, Ibias, in the VDD
following manner and allow for programmability after fabrication.
1 M6
Av(0) = gmIgmIIRIRII ∝ I M3 M4
Bias
gmI
GB = C ∝ IBias -
vout
c M1 M2
vin
Pdiss = (VDD+|VSS|)(1+K1+K2)IBias ∝ Ibias +
K1IBias IBias K2IBias
K1IBias
SR = Cc ∝ IBias
M7
1 1 M5
Rout = ∝I
2λK2IBias Bias VSS Fig. 6.3-04D
1 IBias2 103
|p1| = g R R C ∝ ∝ IBias1.5 Pdiss and SR |p1|
mII I II c IBias 102
gmII 101
|z| = C ∝ IBias GB and z
c 100
Illustration of the Ibias dependence → 10-1
Ao and Rout
10-2
10-3
1 10 100
IBias Fig. 6.3-4E
IBias(ref)
Simulation of the Electrical Design

Area of source or drain = AS = AD = W[L1 + L2 + L3]
where
L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5µm)
L2 = Width of a minimum size contact (5µm)
L3 = Minimum allowable distance from the contact in S/D to the edge of the S/D (5µm)
∴ AS = AD = Wx15µm
Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3)
∴ PD = PS = 2W + 30µm
Illustration:
L3 L2 L1 L1 L2 L3
Poly W
Diffusion Diffusion
L Fig. 6.3-5
Reduction of Parasitics
The major objective of good layout is to minimize the parasitics that influence the design.
Typical parasitics include:
Capacitors to ac ground
Series resistance
Capacitive parasitics is minimized by minimizing area and maximizing the distance between the conductor and ac
ground.
Resistance parasitics are minimized by using wide busses and keeping the bus length short.
For example:
At 2mΩ/square, a metal run of 1000µm and 2µm wide will have 1Ω of resistance.
At 1 mA this amounts to a 1 mV drop which could easily be greater than the least significant bit of an analog-
digital converter. (For example, a 10 bit ADC with VREF = 1V has an LSB of 1mV)
SUMMARY
Introduction and Characterization
• Ideal op amp, virtual ground at input when gain approaches infinity
• Characteristics are static and dynamic and time-independent and time-dependent
Op Amp Architectures
• Two stage
• Folded
• Many others
Compensation
• Designed so that the op amp with unity gain feedback (buffer) is stable
• Types
- Miller
- Miller with nulling resistors
- Self Compensating
- Feedforward
Simple Op Amps
• CMOS - two-stage and folded cascode
• BJT - two-stage and folded cascode
Op Amp Design
• CMOS only

6.2 Introduction To Op Amps: Objective

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6.2 Introduction To Op Amps: Objective

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Introduction to Op Amps (7/17/00) Page 1

6.2 INTRODUCTION TO OP AMPS

INTRODUCTION AND CHARACTERIZATION OF OP AMPS

High-Level Viewpoint of an Op Amp

v1 + Differential High vOUT Output vOUT'

• Differential transconductance stage:

General Configuration of the Op Amp as a Voltage Amplifier

Noniverting voltage amplifier:

Example 1 - Simplified Analysis of an Op Amp Circuit

Since, ii = 0, then i1 + i2 = 0 giving the desired result as

Linear and Static Characterization of the Op Amp

Linear and Dynamic Characteristics of the Op Amp

-18dB/oct. Fig. 6.1-6

Other Characteristics of the Op Amp

Classification of CMOS Op Amps

Voltage Classic Differential Modified Differential

Two-Stage Op Amp Architecture

Folded-Cascode Op Amp Architecture

Single-Loop, Negative Feedback Systems

Illustration of the Stability Requirement using Bode Plots

Why Do We Want Good Stability?

Uncompensated Frequency Response of Two-Stage Op Amps

D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)

Uncompensated Frequency Response of Two-Stage Op Amps - Continued

Uncompensated Frequency Response of an Op Amp

The various capacitors are:

Simplification of the Compensated Two-Stage, Small-Signal Frequency Response Model

General Two-Stage Frequency Response Analysis

-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII

Summary of Results for Miller Compensation of the Two-Stage Op Amp

Closed-loop poles, Cc≠0 jω

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp

Note that the unity-gainbandwidth, GB, is

Conceptually, where do these roots come from?

2.) The left-half plane output pole:

Influence of the Mirror Pole

Controlling the Right-Half Plane Zero

The transfer function is given by the following equation,

Use of Nulling Resistor to Eliminate the RHP - Continued

Conceptual Illustration of the Nulling Resistor Approach

The output voltage, Vout, can be written as

Increasing the Magnitude of the Output Pole†

Increasing the Magnitude of the Output Pole - Continued

Concept Behind the Increasing of the Magnitude of the Output Pole

rds7 gm8rds8 rds7

Vi Vout Vi Vout Vi Vout

Vout(s) ACc  s + gmII/ACc 

Rout(must be large) Av(0) dB

SIMPLE TWO-STAGE OP AMPS

Two-Stage BJT Op Amp - Continued

Two-Stage BJT Op Amp - Continued

-1 -1 -gm1 -gmII -gm6

Slew Rate of the Two-Stage BJT Op Amp

Folded-Cascode BJT Op Amp

Folded-Cascode BJT Op Amp - Continued

Folded-Cascode BJT Op Amp - Continued

Two-Stage CMOS Op Amp

DC Balance Conditions for the Two-Stage Op Amp

Small-Signal Performance of the Two-Stage CMOS Op Amp