IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 32, NO.

3, MAYIJUNE 1996 509

Multilevel Converters-A New Breed

of Power Converters
Jih-Sheng Lai, Senior Member, IEEE, and Fang Zheng Peng, Member, IEEE

Abstruct- Multilevel voltage source converters are emerging also due to voltage clamping requirement, circuit layout, and
as a new breed of power converter options for high-power packaging constraints. To date, hardware implementation has
applications. The multilevel voltage source converters typically only been reported up to six levels for a back-to-back intertie
synthesize the staircase voltage wave from several levels of dc
capacitor voltages. One of the major limitations of the multilevel application [9], in which the voltage unbalance problem has
converters is the voltage unbalance between different levels. been successfully overcome.
The techniques to balance the voltage between different levels The magnetic transformer coupled multipulse voltage source
normally involve voltage clamping or capacitor charge control. converter has been a well-known method and has been im-
There are several ways of implementing voltage balance in mul- plemented in 18- and 48pulse converters for battery en-
tilevel converters. Without considering the traditional magnetic
coupled converters, this paper presents three recently developed ergy storage and static condenser (STATCON) applications,
multilevel voltage source converters: 1) diode-clamp, 2) flying- respectively, [ 151, [16]. Traditional magnetic coupled mul-
capacitors, and 3) cascaded-inverters with separate dc sources. tipulsc converters typically synthesize the staircase voltage
The operating principle, features, constraints, and potential ap- wave by varying transformer turns ratio with complicated
plications of these converters will be discussed. zigzag connections. Problems of the magnetic transformer
coupling method are bulky, heavy, and lossy. The capacitor
I. INTRODUCTION voltage synthesis method is thus preferred to the magnetic

R ECENTLY the “multilevel converter” has drawn tremen-

dous interest in the power industry [I]-[12]. The general
structure of the multilevel converter is to synthesize a si-
coupling method. There are three reported capacitor volt-
age synthesis-based multilevel converters: 1) diode-clamp, 2)
flying-capacitors, and 3) cascaded-inverters with separated dc
nusoidal voltage from several levels of voltages, typically sources.
obtained from capacitor voltage sources. The so-called “mul- This paper will describe operating principles of these ca-
tilevel” starts from three levels. A three-level converter, also pacitor voltage synthesis multilevel converters. Based on the
known as a “neutral-clamped” converter, consists of two features and constraints, the application areas of these multi-
capacitor voltages in series and uses the center tap as the level converters will be addressed.
neutral [13]. Each phase leg of the three-level converter has
two pairs of switching devices in series. The center of each 11. DIODE-CLAMP
MULTILEVEL
CONVERTER
device pair is clamped to the neutral through clamping diodes.
The waveform obtained from a three-level converter is a A. Basic Principle
quasi-square wave output.
An m-level diode-clamp converter typically consists of
The diode-clamp method can be applied to higher level con-
m - 1 capacitors on the dc bus and produces m levels of the
verters [6].As the number of levels increases, the synthesized
phase voltage. Fig. 1 shows a single-phase full bridge five-
output waveform adds more steps, producing a staircase wave
level diode-clamp converter in which the dc bus consists of
which approaches the sinusoidal wave with minimum har-
four capacitors, (31, ( 3 2 , (33, and C,. For a dc bus voltage Vdc,
monic distortion [ 141. Ultimately, a zero harmonic distortion
the voltage across each capacitor is Vdr/4, and each device
of the output wave can be obtained by an infinite number of
voltage stress will be limited to one capacitor voltage level,
levels. More levels also mean higher voltages can be spanned
V&/4, through clamping diodes.
by series devices without device voltage sharing problems. To explain how the staircase voltage is synthesized, the
Unfortunately, the number of the achievable voltage levels is
negative dc rail, 0, is considered as the output phase voltage
quite limited not only due to voltage unbalance problems but
reference point. Using the 5-level converter shown in Fig. 1 as
Paper 95-81, approved by the Industrial Power Converter Committee of an example, there are five switch combinations to synthesize
the IEEE Industry Applications Society for presentation at the 1995 IEEE five level voltages across a and 0.
Industry Applications Scoiety Annual Meeting, Lake Buena Vista, FL, October
8-12. This work was supported by the Oak Ridge National Laboratory, Oak 1) For voltage level Va0 =- Vd,, turn on all upper switches
Ridge, TN, managed by Lockheed Martin Energy Research Corporation for the Sal through Sa4.
U.S. Department of Energy under contract DE-AC05-96OR22464. Manuscript
released for publication November 8, 1995. 2) For voltage level Vao = 3Vdc.4, turn on three upper
J . 3 . Lai is with the Division of Engineering Technology, Oak Ridge switches S,z through Sa4 and one lower switch S u l l .
National Laboratory, Oak Ridge, TN 37831-8058 USA. 3) For voltage level Va0 = Vd,/2, turn on two upper
F. Z. Peng is with the Department of Electrical and Computer Engineering,
Universitv of Tennessee. Knoxville. TN 37996-2100 USA. switches Sa3 and Sa4 and two lower switches Satland
Publisher Item Identifier S 0093-9994(96)02092-0. Sa’2.

0093-9994/96$05.00 0 1996 IEEE

510 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 32, NO. 3, MAY/JUNE 1996

Fig. 2. Phase and line voltage waveforms of a 5-level diode-clamp voltage

source converter.

need to have different voltage ratings for reverse voltage

blocking. Using Da,l of Fig. 1 as an example, when all lower
devices, Sa'l-Sa)4 are turned on, Da/l needs to block three
capacitor voltages, or 3Vdc/4. Similarly, Da2 and Da,2 need
Fig. 1. A diode-clamp 5-level converter circuit diagram. to block 2VdC/4, and Da3 needs to block 3Vdc/4. Assuming
TABLE I
that each blocking diode voltage rating is the same as the
DIODE-CLAMP
.%LEVEL CONVERTER VOLTAGE active device voltage rating, the number of diodes required
LEVELSAND THEIRSWITCH STATES for each phase will be ( m - 1) x ( m - 2). This number
Switch State represents a quadratic increase in m. When m is sufficiently
high, the number of diodes required will make the system
impractical to implement.
2) Unequal Device Rating: From Table I, it can be seen
that switch Sal conducts only during V,O = Vdc, while switch
Sa4 conducts over the entire cycle except during Va0 = 0.
Such an unequal conduction duty requires different current
ratings for switching devices. When the inverter design is to
use the average duty for all devices, the outer switches may
4) For voltage level Va0 = VdC/4, turn on one upper be oversized, and the inner switches may be undersized. If
switches Sa4 and three lower switches Sail through the design is to suit the worst case, then each phase will have
sa'3. 2 x ( m - 2) outer devices oversized. In comparison with the
5 ) For voltage level Va0 = 0, turn on all lower half switches traditional transformer coupling multipulse converters using
Sail through Saj4. six-step operation for each converter, such unequal conduction
Table I lists the voltage levels and their corresponding duty is indeed an advantageous feature because the six-step
switch states. State condition 1 means the switch is on, and operation needs maximum duty in each device and circulating
0 means the switch is off. Notice that each switch is only currents between converters through transformers.
switched once per cycle. There exist four complimentary 3) Capacitor Voltage Unbalance: In most applications, a
switch pairs in each phase. The complimentary switch pair power converter needs to transfer real power from ac to dc
is defined such that turning on one of the pair switches (rectifier operation) or dc to ac (inverter operation). When
will exclude the other from being turned on. Using phase- operating at unity power factor, the charging time for rectifier
leg a as the example, the four complementary pairs are operation (or discharging time for inverter operation) for each
(Sal,S a ' l ) , (Sa2,Saf2),( S a 3 , S a l 3 ) 3 and (Su4, Sa'4). capacitor is different, as shown in Fig. 3(a). Such a capacitor
Fig. 2 shows phase and line voltage waveforms of the ex- charging profile repeats every half cycle, and the result is
ample 5-level converter. The line voltage consists of a positive unbalanced capacitor voltages between different levels.
phase-leg a voltage and a negative phase-leg b voltage. Each The voltage unbalance problem in a multilevel converter can
phase voltage tracks one-half of the sinusoidal wave. The be solved by several approaches, such as replacing capacitors
resulting line voltage is a 9-level staircase wave. This implies by a controlled constant dc voltage source such as pulse-width
that an m-level converter has an m-level output phase voltage modulation (PWM) voltage regulators or batteries. The use of
and a (2m - 1)-level output line voltage. a controlled dc voltage will result in system complexity and
cost penalties. With the high power nature of utility power
systems, the converter switching frequency must be kept to
B. Features a minimum to avoid switching losses and electromagnetic
I ) High-Voltage Rating Required f o r Blocking Diodes: interference (EMI) problems.
Although each active switching device is only required to When operating at zero power factor, however, the capacitor
block a voltage level of Vdc/(m - l), the clamping diodes voltages can be balanced by equal charge and discharge in
 ~

LA1 AND PENG: MULTILEVEL CONVERTERS-A NEW BREED OF POWER CONVERTERS 511

(a) (b)
Fig. 3. Waveforms showing capacitor charging profile. (a) Voltage and
current in phase. (b) Voltage and current are 90" out of phase.

one-half cycle, as shown in Fig. 3(b). This indicates that the

converter can transfer pure reactive power without the voltage
unbalance problem.
In summary, advantages and disadvantages of a diode-clamp
multilevel voltage source converter are as follows. Fig. 4. Circuit diagram of a flying capacitor based 5-level single-phase
Advantages: voltage source converter.

When the number of levels is high enough, harmonic

content will be low enough to avoid the need for filters. 1) For voltage level Va0 = V d c , turn on all upper switches
Efficiency is high because all devices are switched at the Sal through Sa4.
fundamental frequency. 2) For voltage level Va0 = 3Vde/4, there are four combi-
Reactive power flow can be controlled. nations:
The control method is simple for a back-to-back intertie
system. a) sal,sa27 s a 3 , S a ' 4 ( K O = vdc - l/dc/4),
b) Saz, S a 3 , S a 4 , S a ) i ( V a o = 3Vdc/4),
Disadvantages:
Excessive clamping diodes are required when the number
c) s a l , S a 3 , Sa4, Sa'Z(va0 = vdc - 3 v d c / 4 vdc/2), +
and
of levels is high.
d) Sal,saz,s a 4 , Sa'Y(Va0 = v d c - v d c / 2 f v d c / 4 ) .
It is difficult to do real power flow control for the
individual converter. 3) For voltage level Va0 = Vde/2, there are six combina-
tions:
CONVERTER
111. MULTILEVEL USINGFLYING-CAPACITORS
a) s a 1 1 S a 2 1S a ' 3 , s(z'4(vaO = v d c - vdc/2),
b) Sa3,Sa4,Sa'llS(n'ZiVaO = vdc/2),
A. Basic Principle
c) S a l , S a 3 1S a ' 2 , Sa'4(vaO = vdc-3vdc/4$vdc/2-
Fig. 4 illustrates the fundamental building block of a single- vdc/4) 1

phase full-bridge flying-capacitor based 5-level converter [5]. d) S a l , Sa4, s a / z l S d ~ ( V a o= v d c- 3 V d c / 4 + Vdc/4),

Each phase-leg has an identical structure. Assuming that each e> Sa2iSa41Sa'l,Su'3(VaO = 3vdc/4 - vdc/2 +
capacitor has the same voltage rating, the series connection of v d c / 4 ) , and
capacitors in Fig. 4 is to indicate the voltage level between f) S a 2 , s a 3 , Sa'l, Su'4(vuO = 3 v d c / 4 - vdc/4).
the clamping points. Three inner-loop balancing capacitors for
phase leg a , CullCa2, and C a 3 are independent from those for 4) For voltage level Va0 = Vdc/4, there are four combi-
phase leg b. All phase legs share the same dc link capacitors, nations:
c1-c4. a) S a l , S a ' 2 , sa'3, Sa'Q(Vo0 = vdc - 3 v d c / 4 ) ,
The voltage level defined in the flying-capacitor converter b) S a 4 , S a ' l ] S a ' 2 , S a ' ~ ( V a 0= vdc/4),
is similar to that of the diode-clamp type converter. The phase C) S a 3 , Sati,S U ' ZS, ~ ~ Q (=Vv ~ d cO
/ 2 - v d c / 4 ) , and
voltage of an m-level converter has m levels including the d) Saz, Sari, S a ( 3 , S a f 4 ( V a 0 = 3 v d ~ / 4- vd,/2).
reference level, and the line voltage has ( 2 m - 1) levels.
Assuming that each capacitor has the same voltage rating as 5) For voltage level Va0 = 0, turn on all lower switches
the switching device, the dc bus needs ( m- 1) capacitors for Sa,l through Sat4.
an m-level converter. Table I1 lists a possible combination of the voltage levels
The voltage synthesis in a flying-capacitor converter has and their corresponding switch states. Using such a switch
more flexibility than a diode-clamp converter. Using Fig. 4 as combination, each device needs to be switched only once per
the example, the voltage of the 5-level phase-leg a output with cycle. According to the device turn-on time requirement listed
respect to the negative dc rail, Vue, can be synthesized by the in Table 11, the flying-capacitor multilevel converter also has
following switch combinations. unequal device duty problems.
512 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 32, NO. 3, MAYIJUNE 1996

B. Features TABLE I1
A POSSIBLE
SWITCHCOMBINATIONFOR THE
Besides the difficulty of balancing voltage in real power FLYING
CAPACITOR-BASED
5-LEVEL CONVERTER
conversion, the major problem in this inverter is the require-
ment of a large number of storage capacitors. Provided that Switch State I
the voltage rating of each capacitor used is the same as that
of the main power switch, an m-level converter will require a
total of ( m - 1) x ( m - 2)/2 auxiliary capacitors per phase
leg in addition to (m - 1) main dc bus capacitors. With the
assumption that all capacitors have the same voltage rating, an
m-level diode-clamp inverter only requires ( m- 1) capacitors.
In order to balance the capacitor charge and discharge, one
may employ two or more switch combinations for middle
voltage levels (i.e., 3 V 4 4 . V 4 2 , and VdC/4) in one or
several fundamental cycles. Thus, by proper selection of
switch combinations, the flying-capacitor multilevel converter
may be used in real power conversions. However, when it
involves real power conversions, the selection of a switch
combination becomes very complicated, and the switching
frequency needs to be higher than the fundamental frequency.
In summary, advantages and disadvantages of a flying-
capacitor multilevel voltage source converter are as follow s.
Advantages:
Large amount of storage capacitors provides extra ride
through capabilities during power outage.
Provides switch combination redundancy for balancing
different voltage levels.
0 When the number of levels is high enough, harmonic
content will be low enough to avoid the need for filters.
* Both real and reactive power flow can be controlled,
making a possible voltage source converter candidate for
high voltage dc transmission. (a) (b)

Disadvantages: Fig 5. Circuit diagram and the phase voltage waveform of a cas-
caded-inverters based converter with separate dc sources. (a) Circuit diagram.
An excessive number of storage capacitors is required (b) Waveform showing a 9-level converter phase voltage.
when the number of converter levels is high. High-level
systems are more difficult to package and more expensive can generate three level outputs, + v d c , O , and -v&.
This is
with the required bulky capacitors. made possible by connecting the dc sources sequentially to
* The inverter control will be very complicated, and the the ac side via the four gate-turn-off devices. Each level of
switching frequency and switching losses will be high the full-bridge converter consists of four switches, SI, S2,S3,
for real power transmission. and S4. Using the top level as the example, turning on S1 and
S4yields 211 = +V&. Turing on SZ and S3 yields v1 = -I&.
IV. MULTILEVEL
CONVERTERUSING Turning off all switches yields u1 = 0. Similarly, the ac output
CASCADED-INVERTERS
WITH SEPARATE
DC SOURCES voltage at each level can be obtained in the same manner.
Minimum harmonic distortion can be obtained by controlling
the conducting angles at different inverter levels.
A. Basic Principle With the phase current, i,, leading or lagging the phase
A relatively new converter structure, cascaded-inverters voltage v,, by 90°, the average charge to each dc capacitor
with separate dc sources (SDC’s) is introduced here. This is equal to zero over one line cycle, shown in Fig. 5(b).
new converter can avoid extra clamping diodes or voltage Therefore, all SDC capacitor voltages can be balanced.
balancing capacitors. Fig. 5(a) shows the basic structure of To comply with the definition of the previously mentioned
the cascaded-inverters with SDC’s, shown in a single-phase diode-clamp and flying-capacitor multilevel converters, the
configuration. Each SDC is associated with a single-phase “level” in a cascaded-inverters based converter is defined by
full-bridge inverter. The ac terminal voltages of different level m = 2s + 1, where m is the output phase voltage level, and s
inverters are connected in series. is the number of dc sources. For example, a 9-level cascaded-
Fig. 5(b) shows the synthesized phase voltage waveform of inverters based converter will have four SDC’s and four full
a 9-level cascaded inverter with four SDC’s. The phase output bridges.
voltage is synthesized by the sum of four inverter outputs, i.e., For a three-phase system, the output voltages of the three
+ +
w,, = w 1 f 112 v3 114.Each single-phase full bridge inverter cascaded inverters can be connected in either Y - or A-
LA1 AND PENG: MULTILEVEL CONVERTERS-A NEW BREED OF POWER CONVERTERS 513

._

1 - A T

I +lc
Multilevel Converter

L - 'I
Fig, 7. Circuit diagram showing a multilevel converter connected to a power
system for reactive power compensation.
Fig. 6. A three-phase Y -configured cascaded-inverters based converter.

configuration [7]. Fig. 6 illustrates the connection diagram for

a Y-configured 9-level converter using cascaded-inverters with
four SDC capacitors.
(a) (b)
B. Features Fig. 8. Phasor diagrams showing the relationship between the source and
For real power conversions, (ac to dc and dc to ac), the the converter voltages for reactive power compensation. (a) Leading current.
(b) Lagging current.
cascaded-inverter needs separate dc sources. The structure of
separate dc sources is well suited for various renewable energy
sources such as fuel cell, photovoltaic, and biomass, etc. step-down transformer. Fig. 7 shows the circuit diagram of
Connecting separated dc sources between two converters in a multilevel converter directly connected to a power system
a back-to-back fashion is not possible because a short circuit for reactive power compensation.
will be introduced when two back-to-back converters are not The relationship of the source voltage vector, VS, and the
switching synchronously. converter voltage vector, VC, is simply VS = VC + j I c X s ,
In summary, advantages and disadvantages of the cascaded- where IC is the converter current vector, and Xs is the
inverter based multilevel voltage source converter can be listed impedance of the inductor, L s . Fig. 8 illustrates the phasor
below. diagram of the source voltage, converter voltage, and the
Advantages: converter current. Fig. 8(a) indicates that the converter voltage
* Requires the least number of components among all is in phase with the source voltage with a leading reactive
multilevel converters to achieve the same number of current, while Fig. 8(b) indicates a lagging reactive current.
voltage levels. The polarity and the magnitude of the reactive current are
Modularized circuit layout and packaging is possible controlled by the magnitude of the converter voltage, VC,
because each level has the same structure, and there are which is a function of the dc bus voltage and the voltage
no extra clamping diodes or voltage balancing capacitors. modulation index.
Soft-switching can be used in this structure to avoid bulky All three multilevel converters can be used in reactive
and lossy resistor-capacitor-diode snubbers [ 171. power compensation without having the voltage unbalance
Disadvantages: problem. The operating principle has been verified with com-
puter simulations for all three types of multilevel converters. In
Needs separate dc sources for real power conversions,
hardware implementation, a 6-level diode clamp converter and
and thus its applications are somewhat limited.
an 11-level cascade-inverters based converter with 5 separate
dc sources have been constructed using the Insulated Gate
V. APPLICATIONS Bipolar Transistor (IGBT) as the switching device and a digital
signal processor, TMS320C31, as a fully digital controller.
A. Reactive Power Compensation Fig. 9 shows the simulation results of a 5-level flying
When a multilevel converter draws pure reactive power, capacitor based converter using the switch combination stated
the phase voltage and current are 90" apart, and the capacitor in Table I1 for reactive power compensation. The converter
charge and discharge can be balanced [ 2 ] , [4], [5], [SI. Such voltage, VC, is larger than the source voltage, Vs, and the
a converter, when serving for reactive power compensation, is converter current, IC, is 90" leading the source voltage. As
called a static var generator (SVG). The multilevel structure expected, different level capacitor voltages are well balanced
allows the converter to be directly connected to a high-voltage without the need to vary the switch combination for middle-
distribution or transmission system without the need of a voltage levels. In actual implementation, a pure 90" leading or
514 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 32, NO. 3, MAYIJUNE 1996

source &
Converter
Voltages
100 Vldi

Converter
Current
2 Aldiv

U
__- .3r:
U U

592s
Fig 10 Expenmental results of a diode-clamp 6-level converter for reactive
b1-S power compensation
(c)
17-Hay-95
Fig. 9. Simulated results of the flying capacitor based 5-level converter for 13:46:35
reactive power compensation. (a) Capacitor voltages at different levels. (b)
Converter line current. (c) Source and converter voltages.

lagging current may not be possible due to the lossy inductor

and the device voltage drop.
Fig. 10 shows the experimental voltage and current wave-
forms of a 3-phase 6-level diode-clamp based converter using
the switch combination listed in Table I for reactive power
compensation. The oscillogram indicates that the input source
line voltage, V S P a b , and the converter line voltage, V C - a b ,
are slightly out of phase. The source phase voltage and the
line current, IC, are not quite 90" apart. This slight phase
difference is due to the lossy component in the inductor and
the device voltage drops.
Fig. I 1 shows the experimental line voltage and current
waveforms of a 3-phase 11-level cascaded-inverters based con-

B. Back-to-Back Intertie source voltage. The converter voltage is phase-shifted from

When interconnecting two diode-clamp multilevel convert- the source voltage with a power angle, 6.If the source voltage
ers together with a "dc capacitor link," as shown in Fig. 12, is constant, then the current or power flow will be controlled
the left-hand side converter serves as the rectifier for utility by the converter voltage. For S = 0, the current is either
interface, and the right-hand side converter serves as the 90" leading or lagging, meaning that only reactive power is
inverter to supply the ac load. Each switch remains switching generated.
once per fundamental cycle. The result is a well-balanced A 6-level "back-to-back" intertie hardware unit has been
voltage across each capacitor while maintaining the staircase constructed and tested as a phase-shifter and a power flow
voltage wave, because the unbalance capacitor voltages on controller. This unit also employs the IGBT as the switching
both sides tend to compensate each other. Such a dc capacitor device and TMS32031 as the controller. The two intertie
link is categorized as the "back-to-back intertie." systems contain a total of 60 switching devices, 60 built-in
The purpose of the back-to-back intertie is to connect two diodes, and 120 blocking diodes.
asynchronous systems. It can be treated as 1) a frequency Fig. 14 shows experimental results of the utility input
changer, 2) a phase shifter, or 3) a power flow controller. source line voltage, VS-,b, the converter terminal line voltage,
The power flow between two systems can be controlled VCPabr and the source current, I s a , operating at a lagging
bidirectionally. power factor condition. The oscillogram indicates that the cur-
Fig. 13 illustrates the phasor diagram for real power trans- rent, Is,, is 54" lagging the line voltage VS-&. This implies
mission from the source end to the load end. This diagram that phase a current is 24" lagging phase a voltage
indicates that the source current can be leading or lagging the Fig. 15 shows experimental results at leading power factor
LA1 AND PENG: MULTILEVEL CONVERTERS-A NEW BREED OF POWER CONVERTERS 515

Rectifier Operation DC Link Inverter Operation

...
. . I

. . I

...
...
Fig. 12. General structure of a back-to-back intertie system using two diode-clamp multilevel converters.

(a) (b) (C)

Fig. 13. Phasor diagram of the source voltage, converter voltage, and current showing real power conversions. (a) Leading power factor. (b) Unity
power factor (c) Lagging power factor

the multilevel converter can be used for a utility compatible

% 188J T I - hn/av
adjustable speed drive (ASD) with the input from the utility
constant frequency ac source and the output to the variable
input
voltages frequency ac load. The major differences, when using the
100Vldiv same structure for ASD's and for back-to-back interties, are the
control design and the size o f the capacitor. Because the ASD
needs to operate at different frequencies, the dc link capacitor
needs to be well-sized to avoid a large voltage swing under
dynamic conditions.
input
Fig. 16 shows the simulated input and output voltages and
current
2Aldiv currents of a diode-clamp 5-level converter system for ASD
applications. The input frequency is 60 Hz, and the output
frequency is 50 Hz. The dc bus capacitor voltages are well
balanced in the steady state.
Fig 14 Oscillogram of a 6-level back-to back intertie system input line
voltages and current operating at a lagging power factor condition.
VI. DISCUSSION
AND CONCLUSION

condition. The line current is 20" lagging the line voltage A. Discussion
or 10" leading the phase voltage. These two experimental
The multilevel converters can immediately replace the exist-
results indicate that both real and reactive power flows can
ing systems that use traditional multipulse converters without
be controlled in a multilevel voltage source converter.
the need for transformers. For a 3-phase system, the relation-
To show the superiority of the harmonic performance of
ship between the number of levels, m, and the number of
the multilevel converter, the voltages and current obtained in
pulses, p , can be formulated by p = ( m - 1) x 6.
Fig. 15 were analyzed with the Fourier series analysis. The
The SVG is an excellent target for commercialization of
resulting total harmonic distortions (THD's) are as follows.
these multilevel converters i~nhigh-voltage high-power sys-
Utility source voltage,Vs-,b: THD = 1.39% tems. All three converters introduced in this paper can be used
Converter terminal voltage,VC-,b: THD = 7.19% as the static var generator. The second target could be the back-
Source current Isa: THD = 0.95% to-back intertie system for a unified power flow controller. The
structure that is most suitable for the back-to-back intertie is
These harmonic analysis results indicate that the THD's the diode-clamp type. The other two types may also be suitable
obtained from the multilevel converter are well within the for the back-to-back intertie, but they require more switchings
limits of IEEE Standard 519-1992 [18]. per cycle and more sophisticated control to balance the voltage.
Table I11 compares the power component requirements per
C. Utility Compatible Adjustable Speed Drives phase leg among the three multilevel voltage source converters
An ideal utility compatible system requires unity power mentioned above. This comparison assumes that all devices
factor, negligible harmonics, no EMI, and high efficiency. have the same voltage rating, but not necessarily the same
By extending the application of the back-to-back intertie, current rating, and that the cascaded-inverters type uses a full
516 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 32, NO. 3, MAYIJUNE 1996

input Converter Type diode-clamp flying- cascaded-

voltage
1OOIdiv
capacitors inverters
Main switching (m-l)x2 (m-l)x2 (m-l)x2

input
current
2Aldiv
/capacitors I 1 I I
verters not only solves harmonics and EM1 problems, but also
Fig. 15. Experimental results of a 6-level back-to-back intertie system input
avoids possible high frequency switching dvldt induced motor
line voltages and current operating at a leading power factor condition. failures.
With a balanced voltage stress in devices and utility com-
patible features, the multilevel converters have shed a light
in the power electronics arena and are emerging as a new
breed of power converters for high-voltage high-power appli-
cations.

SO& Voltage; 8 Cumnt at &e Secondary S i e REFERENCES

R. W. Menzies, P. Steimer, and J. K. Steinke, “Five level GTO inverters

for large induction motor drives,” in Con$ Rec. IEEE IASAnnu. Meeting,
1993, pp. 595-601.
F. Z. Peng and J. S. Lai, “A static var generator using a staircase
waveform multilevel voltage-source converter,” in Proc. PCIM/Power
-.
Quality, 1994, pp. 58-66.
^* r.+S tHas GO.* X*n In*-, ~ 2 3 m
-, “Power converter options for power system compatible mass
SoHr Voltages 8 Cumnt at the Primary Side transit systems,” in Proc. PCIM/Mass Transit System Compatibility,
1994, pp. 285-294.
Fig 16 Simulated voltage and current waveforms for a multilevel con N. S. Choi, G. C. Cho, and G. H. Cho, “Modeling and analysis of a static
verter-based variable frequency operation var compensator using multilevel voltage source inverter,” in Con$ Rec.
IEEE/IAS Annu. Meeting, 1993, pp. 901-908.
C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, “Comparison of
multilevel inverters for static var compensation,” in Con$ Rec. IEEE/IAS
bridge in each level as compared to the half-bridge version Annu. Meeting, 1994, pp. 921-928.
used in the other two types. The multilevel converter using M. Carpita and S. Teconi, “A novel multilevel structure for voltage
cascaded-inverters requires the least number of components source inverter,” in Proc. EPE 1991, pp. 90-94.
F. Z. Peng and J. S. Lai, “A multilevel voltage-source inverter with
and is most promising for utility interface applications because separate dc sources,” in Con$ Rec. IEEE/IAS Annu. Meeting, 1995,
of its capabilities of modularization and soft-switching. pp. 2541-2548.
F. Z. Peng and T. Fukao, “A multilevel inverter for static var generator
applications,” in IEE Jpn., Paper SPC-93-71, 1993.
B. Conclusion F. Z.Peng, J. S. Lai, J. W. McKeever, and J. VanCOevering,
“A multilevel voltage-source converter system with balanced dc
This paper has presented three transformerless multilevel voltages,” in Conf Rec. IEEE Power Electron. Specialists Con$, 1995,
voltage source converters that synthesize the converter voltage pp. 1144-1 150.
by equally divided capacitor voltages. All these converters S. Lefebvre, A. M. Gole, J. Reeve, L. Pilotto, N. Martins, and S.
Bhattacharya, “Working group on dynamic performance and modeling
have been completely analyzed and simulated. Two hardware of dc systems and power electronics for transmission systems,” IEEE
models have been built and tested to verify the concept. Both Paper 95WM 272-5 PWRD, 1995.
simulation and experimental results prove that these multilevel D. A. Woodford and R. W. Menzies, “Controlling a back-to-back link to
operate as a phase shift transformer,” CIGRE 1994, Paper 14-202, 1994.
converters are very promising for power system applications. M. Bahman et al., “Integration of small taps into existing HVDC links,”
The application that has been mentioned most frequently in IEEE Paper 9SWM 273-3PWRD, 1995.
A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
the literature is SVG. All three multilevel converters can be PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA-17, no. 5, pp.
applied to SVG’s without voltage unbalance problems because 518-523, Sep./Oct. 1981.
the SVG does not draw real power. P. M. Bhagwat and V. R. Stefanovic, “Generalized structure of a
multilevel PWM inverter,” IEEE Trans. Ind. Applicat., vol. 19, no 6,
The application on which the multilevel voltage source pp. 1057-1069, Nov./Dec. 1983.
converter may have the most impact is the adjustable speed L. Walker, “10-MW GTO Converter for battery peaking service,” IEEE
drive. The industry recently reported numerous ASD bear- Trans. Ind. Applicat., vol. 26, no. 1, pp. 63-72, Jan./Feb. 1990.
C. Schauder et al., “Development of a f l O O MVAR static condenser
ing failures and winding insulation breakdowns due to high for voltage control of transmission systems,” IEEE Paper 94SM479-
frequency switching PWM inverters. Using multilevel con- 6PWRD, 1994.
LA1 AND PENG: MULTILEVEL CONVERTERS-A NEW BREED OF POWER CONVERTERS 517

[17] J. S. Lai et al., “A novel resonant snubber based soft-switching inverter,” Fang Zheng Peng (M’93) was born in Hubei
in Con$ Rec. Appl. Power Electron. Con$, Dallas, TX, 1995, pp. Province, China. He received the B.S. degree
797-803. in electrical engineering from Wuhan University
[ 181 Recommended Practices and Requirements for Harmonic Control in of Hydraulic and Electrical Engineering, China,
Electric Power Systems, IEEE Standard 519, 1992. in 1983, and the M.S. and Ph.D. degrees in
electrical engineering from Nagaoka University of
Technology, Japan, in 1987 and 1990, respectively.
He joined Toyo Electric Manufacturing Com-
pany, Ltd., from 1990 to 1992. From 1992 to 1994,
Jih-Sheng Lai (S’84-M’87-SM’93) received M.S.
he worked with Tokyo Institute of Technology as
and Ph.D. degrees in electrical engineering from
a Research Associate. Since 1994, he has been a
University of Tennessee, Knoxville, in 1985 and
Research Assistant Professor at University of Tennessee, Knoxville, working
1989, respectively.
with Oak Ridge National Laboratory.
From 1980 to 1983, he was the Chairman of
the Department of Electrical Engineering, Ming-Chi
Institute of Technology, Taipei, Taiwan, where he
initiated a power electronics program and received
a grant from his college and a scholarship from
the National Science Council to study abroad. In
1986, he became a staff member at the University
of Tennessee, where he taught control systems and energy conversion courses.
In 1989, he joined the Electric Power Research Institute (EPRI) Power
Electronics Applications Center, where he managed EPRI-sponsored power
electronics projects. Since 1993, he has been with the Oak Ridge National
Laboratory as the Power Electronics Lead Scientist. His main research
areas are power electronics modeling and simulation, circuit design, and
microcomputer applications. He has published more than 50 technical papers
and two books and filed 12 invention disclosures with 4 patents awarded.
Dr. Lai is chairman of the IEEE Power Electronics Society Standards
Committee and a member of Phi Kappa Phi and Eta Kappa Nu honor societies.