Journal of Electron Devices, Vol. 12, 2012, pp.

713-718

© JED [ISSN: 1682 -3427 ]

PRE-SETTABLE SEQUENTIAL CIRCUITS DESIGN USING SINGLE-

CLOCKED ENERGY EFFICIENT ADIABATIC LOGIC
M. Chanda1, A. S. Chakraborty2, A. Dandapat3 and H. Rahaman4, IEEE Member
1,2
ECE Department, 1,2Meghnad Saha Institute of Technology, 1,2Kolkata
3
Jadavpur University and 4Bengal Engineering and Science University, 3ETCE 3Kolkata and 4IT 4Howrah
1
[email protected], [email protected], [email protected], [email protected]

Received 28/11/2011, online 15/12/2011

Abstract
In this paper, the design of pre-settable adiabatic flip-flops and Requirement of additional voltage and current sources
sequential circuits based on the newly proposed Energy efficient increase the complexity in SCAL and SCALD [1], [2]. To
adiabatic Logic (EEAL) is presented. EEAL is based on ensure correct operation auxiliary clocks are required in
differential cascode voltage swing (DCVS) logic, uses only a CAL which deteriorates the energy efficiency. Cascaded
single sinusoidal source as supply-clock. This not only ensures
lower energy dissipation, but also simplifies the clock design
PAL structure operates under complementary clocks and
which would be otherwise more complicated due to the signal suffer from undesired capacitive couplings, since the output
synchronization requirement. An adiabatic asynchronous nodes are kept floating instead of zero. Higher silicon area
sequential circuit with a reset line has been implemented using imposes limitation on the QAPG operation. In this paper we
EEAL style in a TSMC 0.18 μm CMOS technology. CADENCE proposed an energy efficient adiabatic logic (EEAL) based
simulation shows that EEAL based sequential circuit consumes on DCVS network. EEAL operates under a single sinusoidal
only 24%-36% of total energy consumed by others imperative source. As a parallel path is always provided between the
logic styles. Layouts of the proposed EEAL based D and JK Flip- clock supply and output nodes, floating output problems can
flops are given to estimate the silicon area clearly. be eliminated completely which in turns enhances the
Keywords: Adiabatic logic, Pre-settable flip-flops, single-clock,
energy efficiency.
energy efficient, adiabatic counter

I. INTRODUCTION
As the transistor count per chip increases rapidly in the
system-on-chip (SoC) era, significant reduction in power
overhead in dynamic switching and leakage is of particular
importance. Adiabatic logic style has emerged as a
promising approach to achieve ultra-low power without
sacrificing noise immunity and driving ability.
A plethora of adiabatic logic styles [1]-[10], which have
been proposed over the past decade depend on multiphase
clocking schemes. The problems with multiphase clocking
[2]-[4], [6], [7], [11] include complicated clock tree design
with clock skew, and increased energy dissipation with
power clock generators [2], [3], [6], [8], [11]. To ensure
signals that originate from different clock phases to be
synchronized, insertion of data buffers is required which
cause extra power dissipation and area cost [1], [9]. In order Figure 1. EEAL logic (a) Block diagram (b) Inverter/Buffer circuit (c)
to make these adiabatic logic circuits more feasible and Power supply (d) Cascading of Inverter/Buffer circuits
practical in VLSI applications, single-clock operation of the
circuits would be needed. Though few adiabatic logics Previously reported adiabatic logic styles focused mainly
including SCAL (Source coupled Adiabatic Logic) [1], on combinational logic designs such as CLA, ALU, and
SCALD (Source coupled Adiabatic Logic with diode) [2], processor [2], [7]-[9]. However, flip-flops and sequential
CAL (Clocked Adiabatic Logic) [3], PAL (Pass Transistor circuits cannot be also neglected in digital systems, as we
Adiabatic Logic) [4] and QAPG (Quasi Adiabatic Pass gate cannot build adiabatic sequential circuits by simply using
Logic) [5] have been reported on single clock operation yet
in practical cases they suffer in high frequency regime.
M. Chanda et al, Journal of Electron Devices, Vol. 12, 2012, pp. 713-718

conventional method. In this paper, we focus on the TSMC 0.18µm CMOS process is used to simulate the
design and analysis of adiabatic asynchronous sequential proposed EEAL Inverter/Buffer circuit. The CADENCE
circuits based on the single phase EEAL. Extensive simulation waveforms of the EEAL Inverter/Buffer are
CADENCE simulations have done to show the workability shown in Figure 2. These simulation results were obtained
of the proposed logic using 0.18µm CMOS technology in when a periodic sequence “1010 ...” was applied at the input
various frequency ranges. of Figure 1 (b). The frequency of the power-clock is
The rest of the paper is organized as follows. 100MHz, and its peak voltage 1.8V. W/L of the cross
Rudimentary operation of EEAL logic is discussed in coupled PMOS (M1 and M2) is taken with 12λ/2λ, and the
section II. Section III describes the design and operation of other NMOS transistors are taken with 6λ/2λ where
sequential circuit such as D, JK, T flip-flops and adiabatic λ=0.9µm.
decimal up counter using EEAL. Experimental results and Energy dissipation of the EEAL circuits includes mainly
comparison of performance of EEAL with CAL, QAPG and full-adiabatic energy loss on output nodes. In EEAL, as
static CMOS logic are also detailed in this section. Finally floating problem is solved by providing parallel paths
conclusions are given in section IV. between output nodes and supply clock, energy loss on
internal nodes due to leakage currents become negligible.
II. OPERATION OF EEAL Moreover in parallel paths either PMOS or NMOS any one
or both transistors are turned “ON” always. So the voltage
EEAL is a dual-rail adiabatic logic which consists of two drop across the path becomes very small (∆V≈ 0) which
DCVS network and a pair of cross-coupled PMOS devices reduces the threshold loss also. Thus the non-adiabatic loss
in each stage, as illustrated by Figure 1(a). To ensure correct is minimized significantly. The energy dissipation in
operation a sinusoidal ac supply, shown in Figure 1 (c) is charging process of the EEAL inverter/buffer can be
used. Figure 1 (b) shows the EEAL buffer/Inverter circuit expressed as:
which is based on Figure 1 (a).
As far as operation is concerned assuming “out” and E = {(RCL)/T} (CLVDD + ½ CL(∆V) 2 (1)
“outb” are initially low and φ ramps up from logic 0( “0” )
to logic 1( “VDD”) state. If now “in” = “0”and “inb”= “1”; Hence R is the turn-on resistance of the parallel path, CL is
N1, P1 are turned off and N2, M1 and P2 are turned ON. the output load capacitances and T is the charging time.
The “out” node is then charged by following φ closely ½CL(∆V shows the threshold loss [4], [9], [11]. Though
through the parallel combination of P2 and M1, whereas this loss is negligibly small yet it is included in the above
“outb” node is kept at ground potential, as N2 is “On”. equation to make the power consumption more realistic. In
When φ swings from “VDD” to ground, “out” node is EEAL as charging and discharging processes consume
discharged through the same charging path and “outb” is almost similar amount of energy, total energy dissipation for
kept at same ground potential. Resultantly we get full swing a complete cycle can be expressed as:
in “out” node and ground potential at “outb” node. So
floating output problem can be eliminated which in turn E = 2{(RCL)/T} (CLVDD) 2 + CL (∆V) 2 (2)
increases the energy efficiencies of EEAL based circuits.
The above calculation implies that we may dramatically
reduce the power dissipation by somehow prolonging T.
Hence during charging and discharging, PMOS/NMOS
transistors are operated in triode region as very small
voltage drop occurs between supply clock and output nodes.
So the turn-on resistance of the charging or discharging path
consists of parallel combination of PMOS/NMOS
transistors can be expressed as:

R={µnCox(W/L)n(½VDD-Vtn)+µpCox(W/L)p(½VDD-Vtp)} (3)

where µn and µp are the mobility of PMOS and NMOS; Vtn

and │Vtp│ are the threshold voltages of PMOS and NMOS
respectively; all the other terms have the usual meaning. For
0.18µm CMOS process, considering VDD=1.8V and
( )p=2( )n, the above expression gives R=1.02KΩ.
Figure 2. Output waveforms of EEAL Inverter/Buffer circuit at 100MHz Similarly the load capacitances (CL) associated with
with a load of 25fF at the output nodes
PMOS/NMOS transistors, operating in triode region can be
expressed by:

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M. Chanda et al, Journal of Electron Devices, Vol. 12, 2012, pp. 713-718

C= W (½L+∆L) Cox + CJ (4) where C1 and C2 are the output load capacitance of two
successive inverter stages. Assuming that the present and
where ∆L is the overlap capacitances and Cox is the gate next stage of adiabatic D flip-flop is Q and Q*. In case of T
oxide capacitances per unit area. In 0.18µm CMOS process, and JK flip-flop, output can be written as Q* = TQ'+QT' and
Cox is approximately 8.6fF/µm2. Capacitance CJ is due to the Q* = JQ'+ KQ. So the T and JK flip-flops can be realized by
junction between the source/drain diffusion and the bulk.
Comparing Figure 1 (b) with first order RC network
signal propagation delay can be expressed as:

τRC = (ln2) RCL (5)

In 0.18µm CMOS process considering 10fF output load,

RC time delay (τRC) of EEAL Inverter/buffer circuit
becomes almost 7.04 ps. Due to parallel resistive path signal
propagation in EEAL will be very faster compared to other
imperative logic styles.

III. ADIABATIC PRE-SETTABLE SEQUENTIAL

CIRCUIT DESIGN
In this section, we first describe the EEAL gates, and then
we present the design of adiabatic flip-flops and sequential
circuits using EEAL gates.
III.1 EEAL Complex Gate Design
Complex EEAL gate can be implemented easily by using
the general structure shown in Figure 1 (a). In Figure 1 (a), Figure 3. DCVS network of EEAL Gates (a) AND/NAND (b) OR/NOR (c)
replacing DCVS networks by the structures shown in Figure XOR/XNOR and (d) 2-1 MUX
3, we can implement 2 i/p AND, OR, XOR and 2-1 MUX.
Thus complex gate designs by EEAL logic become simple
and modular.
III.2 EEAL Pre-Settable Flip-Flop design
A few adiabatic logic architectures have been presented
for low power sequential circuit design [12]-[15] with a
single or multiphase clock scheme. Implementation of
complex control schemes, distribution of multiple clock
phases, management of data dependent clock capacitance
fluctuations make the multiphase clocking schemes
sensitive to clock skew. In previously proposed transistor
based adiabatic circuits; a complicated clocking rule must
be followed to form a chain of cascaded stages. These all
impose limitations on sequential circuit design by
multiphase clock based adiabatic logics. Hence we Figure 4. EEAL sequential circuits (a) D Flip-flop (b) T Flip-flop (c) JK
implement the adiabatic sequential circuit by EEAL logic Flip-flop
which uses a single sinusoidal clock source. Moreover
using the XOR and multiplexer to replace the first-EEAL
sinusoidal power-clocks have more practical significance
buffer stage in the adiabatic D flip-flop. The T and JK flip-
because it can be easily produced using simple LC circuits.
flops using two-stage EEAL are shown in Figure 4(b) and
This not only ensures low energy consumption yet enjoys
Figure 4 (c), respectively.
minimal control overhead also.
Adiabatic flip-flops with a reset line are more universal
To establish a simple sequential circuit, like D flip-flop,
and suitable for the design of adiabatic sequential circuits.
two cascaded inverter stages or a single buffer stage driven
To implement the pre-settable adiabatic flip-flops, second
by a single sinusoidal clock are required. According to this
stage of EEAL flip-flops will be replaced by the 2-1
method, the adiabatic D flip-flop using the EEAL circuits is
multiplexer. Figure 5 shows the pre-settable D flip-flop and
shown in Figure 4(a). The energy loss of a D flip-flop can
T flip-flop.
be expressed as,
E = 2{R (C1+C2)/T} (CLVDD + (C1+C2)(∆V (6)

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M. Chanda et al, Journal of Electron Devices, Vol. 12, 2012, pp. 713-718

Figure 5 Pre-settable adiabatic flip-flops (a) D flip-flop (b) T flip-flop

Figure 8. Output waveforms of EEAL JK flip-flop circuit at 100MHz with
Output waveform of EEAL based pre-settable D flip- a load of 25fF at the output nodes
flop are shown in Figure 6. Figure 7 shows that EEAL D
flip-flop performs better than the other imperative adiabatic
logic styles. At 100MHz frequency, EEAL based D flip-flop
consumes only 19.12%, 29%, 40% and 47% of total power
consumed by conventional CMOS, 2N2N2P, CAL and
CTGAL respectively. Simulated waveform of pre-settable T
flip-flop is also shown in Figure 8.

Figure 9. Schematics of decimal up counter based on EEAL logic

Figure 6 Output waveforms of EEAL pre-settable D flip-flop circuit at

100MHz with a load of 25fF at the output nodes

Figure 10. Output waveforms of EEAL Inverter/Buffer circuit at 100MHz

Figure 7. Comparison of energy consumption per cycle of EEAL, ECRL with a load of 25fF at the output nodes
[7], CTGAL [10 ], CAL, 2N2N2P [6] and static CMOS based D Flip-Flop

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M. Chanda et al, Journal of Electron Devices, Vol. 12, 2012, pp. 713-718

functionality of such logic, making it suitable for

implementing energy-aware and performance-efficient
III.3 EEAL Pre-Settable Flip-Flop design
sequential circuit.
Complex sequential circuits can be realized using the
schematic of a BCD code up counter which is implemented
by pre-settable flip-flops and EEAL gates. The proposed
pre-settable flip-flops and EEAL gates. Figure 9 shows
transition function of each flip-flop can be expressed as
Q0*= Q0', Q1*= (Q0 Q1) Q3', Q2* = (Q0Q1) Q2, Q3* =
((Q1Q2)Q0 + Q3Q0'). We can also realize the other counter
by modifying the „reset‟ signal in Figure 9. Simulated
waveforms of EEAL based decimal up counter are shown in
Figure 10. Therefore, the proposed pre-settable adiabatic
flip-flops are more universal and suitable for the design of
adiabatic counters. In Figure 11 CADENCE simulation
shows that EEAL based decimal up counter consumes only
24.5%, 35.5% and 26% of total power consumed by
conventional CMOS, 2N2N2P and CAL. Layouts of D and
JK Flip-flops are shown in Figure 12 to estimate the silicon
area clearly. In case of adiabatic logic style, as we are
getting complementary output simultaneously, the transistor
overheads and finally silicon area becomes larger. Still this
complementary logic design becomes efficacious in Figure 12. Layout of EEAL based (a) JK FLIP-FLOP and (b) D FLIP-
implementing the complex circuits like multiplier, complex FLOP
adder etc.

References
[1] S.Kim and M.C. Papaefthymiou. “Single-phase source-coupled
adiabatic logic,” in Proc. Int. Symp. Low-Power Electron. Design,
San Diego, CA, Aug. 1999, pp. 97–99.. A247, pp. 529–551, April
1955.
[2] S. Kim, C.H. Ziesler and M.C. Papaefthymiou. “A true single-phase
energy recovery multiplier,” IEEE Trans.onVLSI Systems, 11, .194-
207 (2003).
[3] D. Maksimovic and V. G. Oklobdzija, “Clocked CMOS adiabatic
logic with single ac power supply,” in 21st Eur. Solid State Circuits
Conf., Lille, France, Sept. 1995.
[4] Oklobdzija, V.G., Maksimovic, D., and Lin, F.C., „Pass-transistor
adiabatic logic using single power-clock supply,” IEEE Trans.
Circuits Syst II, Analog Digit. Signal Process, 44, 842–846 (1997).
[5] E. K. Loo, H. I. A. Chen, J. B. Kuo, and M. Syrzycki., “ Low-voltage
single phase clocked quasi adiabatic pass gate logic, ” in CCECE
2007, Vancouver, April 2000.
[6] A. Kramer, J. S. Denker, B. Flower, and J. Moroney, “2nd order
adiabatic computation with 2N-2P and 2N-2N2P logic circuits,” Proc
Figure 11. Comparison of energy consumption per cycle of EEAL, CAL, of the Intemational Symposium on Low Powr Electronics and Design,
2N2N2P and conventional CMOS logic based decimal up counter 1995.
[7] Y. Moon and D. K. Jeong, “An efficient charge recovery logic
circuit,” IEEE Joumal of Solid-state Circuits 31, 514-522 (1996).
IV. CONCLUSION [8] Jianping Hu, Tiefeng Xu, and Yinshui Xia, Proc. 48TH IEEE Inter,
Midwest Symposium on Circuits and Systems, pp.1398-1401 (2005).
This paper proposes a single clock based energy efficient
[9] Y. Ye and K. Roy, “QSERL: quasi-static energy recovery logic,”
adiabatic logic. Non-adiabatic loss can be minimized IEEE J. Solid-State Circuits 36. 239–248, (2001).
significantly by eliminating floating output problem. This [10] X. Jian, W. Peng-jun and Z. Xiao-yang, “Research of adiabatic
logic is also faster compared to other imperative logic styles multiplier based on CTGAL,” ASICON 2007, pp. 138-141.
as parallel path is provided between supply clock and output [11] J Neil H. E. Weste, David Harris, and Ayan Banerjee, CMOS VLSI
nodes. EEAL based pre-settable adiabatic flip-flops and Design: A circuits and system perspective (3rd edition), Pearson
Education 2008.
decimal up counter are also implemented. CADENCE
[12] M. Chanda, A. Dandapat, and H. Rahaman, “Ultra low power
simulation shows the high energy efficiencies of EEAL sequential circuit implementation by a quasi static single phase
logic. Both simulation and measurement results verify the

717
M. Chanda et al, Journal of Electron Devices, Vol. 12, 2012, pp. 713-718

adiabatic dynamic logic (SPADL),” IEEE-TENCON 2009, pp. 1-5, [14] Y. Wu, H. Dong, Y. Wang and J. Hu, “Low power adiabatic
Singapore, Nov. 2009. sequential using two phase power clock supply,” ASICON 2005,pp.
[13] J. Hu, Y. Xia and H. Dong, “Low power NMOS CPAL circuits and 185-188, 2005.
adiabatic sequential circuits,” IEEE 6th circuit and system symp. pp. [15] C.P Kumar, S.K Tripathy and R. Tripathi, “High performance
233-236, vol. 1, 31st May- 20th June 2004. sequential circuit with adiabatic complementary pass-transistor logics
(ACPL),” IEEE-TENCON 2009,pp. 1-4, 2009.

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