1

ANALOG ELECTRONICS

This Chapter “Analog Electronics” is taken from our:

ISBN : 9789386146267
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Quick Revision Material

PN JUNCTION D IODE
Diode Current Equation
V rZ
I I 0 (e .VT 1) V`Z
where, I = Forward Diode current +
I 0 = Reverse Saturation current VZ
–
V = External Voltage (Positive for forward and
negative for reverse)
= A constant (For Ge = 1 and Si = 2, wheras = 1 for Fig. : Practical zener diode equivalent circuit
rapidly increasing section of curve)
Diode Capacitance
VT = Volt equivalent temperature; its value is given by
T/11600, where T is absolute temperature. The two layers of impurity ions in depletion region act as plates
Effect of Temperature on Diode Characteristic of capacitor. This depletion layer capacitance is also known as
Diode current is a function of temperature and since the coefficent junction capacitance.
of temperature (VT) is in the denominator of the power of the K
exponential term, therefore, with an increase in the temperature, CT
VB Vr
the diode current exponentially decreases and vice-versa.
where CT = Junction capacitance
ZENER DIODE K = constant
Zener Diode is a special purpose silicon PN junction diode which VB = Barrier voltage (0.6 for Si and 0.2 for GE)
differs from other diodes in the sense that it operates in the reverse Vr = Reverse Voltage
biased mode. n = constant (depends upon the nature of junction)
Zener diode is also known as a voltage regulator or voltage
reference or breakdown diode. BJT-BIPOLAR JU NCTI ON TRA NSISTOR
Transistors are basic building blocks of electronics used for
A K
amplifiers and switching signals.
Anode Cathode The basic definition of BJT is "It is a three terminal device whose
(a) output voltage/current or power is controlled by its input
Symbol current."
Fig. : Symbol of Zener Diode It is a current-controlled current source device.
In common base configuration, the ratio of output current
to the input current is called Current Gain ( ) or Current
Forward Bias
Amplification Factor of a transistor.
Breakdown IF Region Current Gain is defined as "The ratio of change in
VZ VR 0
collector current to the change in emitter current at
VF constant collector - base voltage."
K IC
Reverse Bias IR
IE at VCB constant
Region
I
Collector current IC I B CBO
M 1 1
Base amplification factor ( ):-"It is defined as the ratio of
Fig. : V.I. characteristic of Zener Diode change in collector current to the change in base current."
IC
IB
 3

Collector Current IC IB IC ICBO 2. Voltage Shunt Feedback Amplifier

• Also called shunt voltage feedback amplifier.
Relation between and • Also called shunt-shunt feedback amplifier.
If = Vo;
1 Vo
IE Af = V
Current Amplification Factor: S
IB
• In ideal transresistance amplifier
1 Rif = 0; Rof = 0
Relation Between and :
1
Collector current: IC ( 1) I B ( 1) ICBO
Ii + Basic +
IS Vi Amplifier Vo RL
Comparison of Transistor Connections
– –

Common Common Common

Characteris tics
Bas e Emitter Collector Ro
R Rof =
In pu t res is tance Lo w Low Very Hig h Rif = i If D
Ou tp ut res is tance Very High Hig h Low D Feedback +
network V0
Vo ltage Gain 150 500 <1 –
with
A pp lication High A ud io Imp edance
Frequ en cy freq u ency M atchin g Fig. : Voltage shunt feedback amplifier
3. Current Shunt Feedback Amplifier
FEEDBACK AMPLIFIER • Shunt-Current feedback amplifier.
. Darlington Amplifier • Shunt-Series feedback amplifier.
Current Gain, = 1 2 If = Io
IE2 Io
I E1
Af = I
S
TYPES OF NEGATIVE FEEDBACK • In ideal current amplifier input resistance and output
1. Voltage-Series Feedback Amplifier resistance is
• Also called series voltage feedback amplifier. Rif = 0
• Also called series shunt feedback amplifier. Rof =

Vf = V0
Io
V
Af = 0 IS Ii Basic
RL
VS Amplifier
In ideal voltage amplifier.
Rif =
Rof = 0
Ri Rof = Ro.D
Rif = If
D Feedback
Basic + network
VS Vo RL I0
Amplifier with
–

Fig. : Current shunt feedback amplifier

R0 4. Current Series Feedback Amplifier
Rf = RiD Rof =
D • Also called series-current feedback amplifier.
+ Feedback +
Vf network Vo • Also called series-series feedback amplifier.
– with –
Vf = I0

Fig. : Voltage series feedback amplifier I0

Af = V
S
 4
• In ideal transconductance amplifier. 3. Colpitt's Oscillator
Rif = The basic configuration of the Colpitts Oscillator
Rof = resembles that of the Hartley Oscillator but the difference
Ii Io this time is that the centre tapping of the tank sub-circuit is
+
now made at the junction of a “capacitive voltage divider”
VS Basic
Vo RL network instead of a tapped autotransformer type inductor
Amplifier
– as in the Hartley oscillator.
The frequency of oscillations for a Colpitts Oscillator is
given as:
Rf = RiD Rof = Ro.D
+ Feedback 1
Vf network fr
– with 2 LCT
I0
Fig. : Current series feedback amplifier
+V
OSCILLATORS
R1 L2 RFC
Tank Circuit
Barkhausen criteria for oscillation condition combined C4 Output
for oscillation, A 1
C1 L

Types of Oscillators C3 TR1

C2
Vout
Feedback
1
1. Tuned LC Oscillator : f R2
2 L1C1
0v
where, L1 is the inductance in Henry
C1 is the capacitance is Farad
f is the output frequency in Hertz Fig. : Colpitt’s oscillator
4. Phase shift RC Oscillator :
R1 L2 L1 C1
VCC f 1
2 RC 2 N
C R2 S where N is the number of RC stages (N = 3)
RE CE

+VCC
Fig. : Tuned LC oscillator
Rb RC
2. Hartley Oscillator
C1 C2 C3
f 1 Output
2 LT C R1 R2 R3 R CE

where LT = L1 + L2 + 2M
Fig. (d) : Phase shift RC oscillator
The Hartley Oscillator consists of a parallel LC resonator
5. Crystal oscillator :
tank circuit whose feedback is achieved by way of an
inductive divider. f K
t
+VCC
1
RF Choke Series resonant frequency f s
R1 2 LC
Vout
L1
1
R2 C Parallel Resonant Frequency f p
RE CE 2 LCT
L2

where CT CCM
C Cm
Fig. : Hartley oscillator
 5

i2 R2
R1
C R1 V2 +V
–
R2 i1
Vin VO
CM +
–V

Fig. : Crystal oscillator

Fig. : A non-inverting amplifier
6. Wien Bridge Oscillator :
3. Voltage Follower
f 1
R2
2 R1 C1R2C2 Av 1 1 : - for voltage follower R1 R2 0
R1
or R = R1 = R2; C = C1 = C2

1 1 +V
f =
2 R C 2 2
2 RC -
+ Vo
-V
C3

R3 R1 R4 R5 R6 RR C5
C1 Fig. : Voltage follower
C2 C4
4. Summing Amplifier
T1 R7
LP R2 R9 T2
R4 R R
v0 ( * v1 ) ( 4 * v2 ) ( 4 * v3 )
R1 R2 R3

Fig. : Wien bridge oscillator If R1 = R2 = R3 = R,

OPERATIONAL AMPLIFIER Then output voltage is given as : v0 (v1 v2 v3 )

Types of Operational Amplifier R4

1. Inverting Amplifier: V1 R1 +V
-
V2 R2
+ Vo
i2 R2 V3 R3 R1 -V
Virtual
Ground +V
V2
– Fig. : Summing amplifier
i1 R1 5. Differential Amplifier :
VO
Vin +
V1 V2
–V R2 R4 R2
V0 = V1 1
R1 R3 R 4 R1

Fig. : Inverting amplifier

V2
R2 R4 R1 R 2
v0 R2 = V1
Voltage Gain, A v R1 R3 R 4 R1
vin R1
2. Non-Inverting Amplifier Put R1 = R3 & R4 = R2

R2 R2
Voltage gain, A v 1 Vout = R (V2 V1 )
R1 1
 6

R2 IC-555 Timer as Astable Multivibrator :

R1 +V The time during which the capacitor charges from 1/3 Vcc to 2/3
V1 - Vcc is equal to the time the output is high and given by
V2 R3 tc = 0.693 (R1 + R2) C1
R4
+ Vo
-V Similarly the time during which the capacitor discharges from
2/3Vcc to 1/3Vcc is equal to the time the output is low and is given
Fig. : Differential amplifier by
6. Integrator: As its name implies, the Op-amp Integrator is td = 0.693 R2 C1
an operational amplifier circuit that performs the mathematical Hence the total period of the output waveform is
operation of Integration. T = tc + td = 0.693 (R1 + 2 R2) C1
Ideal voltage output for the OP-amp Integrator as: +VCC

1 t 8 4
Vout Vin dt
R in C 0 R1
t dt
V
0 in R in .C 7
R2 3 Output
2 555
If C
+ –
Iin Rin VC 6
X VO
–
Vin A –Vout C1 1 5
+ VC
C

Fig. : Integrator Fig. : IC timer 555 in astable mode

7. Differentiator Amplifier: The differentiator amplifier circuit Duty cycle. The duty-cycle is the ratio of time in the high state to
performs the mathematical operation of Differentiation. the total period, T and is given by

Vo = –Rf C dVin tc R1 R 2
dt Duty cycle
T R1 2R 2
If Rf Frequency of oscillation. Frequency of oscillation is given by

Iin C 1 1 1.44
X – f Hz
Vin + – T 0.693 R1 2R 2 C1 R1 2R 2 C1
VC A –Vout
+
0v
VC
Fig. : Differentiator amplifier VCC
IC-555 TI MER 2
– VCC Discharging
3
1
– VCC
3
Ground 1 5 +VCC Charging
t
VO
tc td
Trigger 2 6 Discharge VCC
555
OV
Output 3 7 Threshold
t
1
T =–
Reset 4 8 Control Voltage f

8 Pin DIP Fig. : Voltage across capacitor C1 and output voltage

waveforms
Fig. : 8-PIN DIP 555 timer
 7
IC-555 Timer as Monostable Multivibrator Drain Current
The time during which output at pin 3 is high is given by 2
tc = 1.11 R1 C1 second VGS
ID IDSS 1
where C is in farad and R is in ohm. The equation clearly shows VP
that width of the output pulse depends on the values of R1 and
Where, ID = Drain Current
C1 only
IDSS = Shorted-gate drain current
VGS = Gate source voltage
VP = Pinch-off Voltage
2. MOSFET: Metal Oxide Semiconductor Field Effect
Transistor.
2
VGS
Drain current, ID IDSS 1
VP

MULTISTAGE AMPLIFIER OR CASCADED

AMPLIFIER
Fig. : IC 555 in monostable mode
* When amplifiers are connected such that the o/p of 1 is given
to the I/p of another, they are said to be cascaded.
* In the Multistage amplifier we get a larger GBW product
(i) Voltage Gain (Av*) :-

Av* Av3 Av2 Av1

* In a Multistage amplifier voltage gain is increase to a every
larger value and ut is equal to the product of individual voltage
gain.
* {Av* in dB = 2010 g10 |Av1| + 20 log10 |Av2| + --- }
(ii) Current Gain of Cascaded Amplifier (AI*) :-

Fig. : Output waveforms AI* AI3 .AI2.AI1

FIELD EFFECT TRANSISTOR (FET) (iii) Power Gain AP*:
Field effect transistor is a voltage controlled device in which * * *
output characteristics are controlled by the input voltage. Ap = Av AI
1. Junction Field Effect Transistor - JFET: A junction field Very larger value
effect transistor is a three terminal device in which
* In the Multistage GBW product is constant
conduction takes place only through one type of carrier i.e.
either through holes or through electrons. GBW of 2 stage Amp. GBW of single stage Amp.
 8

(a) Precision integrator

Conceptual MCQs (b) Hartely oscillator
(c) Butterworth high pass filter
1. Introducing a resistor in the emitter of a common amplifier
(d) Wien-bridge oscillator
stabilizes the dc operating point against variations in
4. Assume that the op-amp of the figure is ideal. If v1 is a
[2000, 1 Mark]
triangular wave, then v0 will be [2000, 1 Mark]
(a) only the temperature
(b) only the of the transistor R
(c) both temperature and
(d) none of the above
2. In the differential amplifier of the figure, if the source
resistance of the current source IEE is infinite, then the –
Vi
common-mode gain is [2000, 1 Mark] Vo
+
VCC

(a) square wave (b) triangular wave

(c) parabolic wave (d) sine wave
5. The most commonly used amplifier is sample and hold circuits
R R is [2000, 1 Mark]
(a) a unity gain inverting amplifier
(b) a unity gain non-inverting amplifier
Vin2 Vin1 (c) an inverting amplifier with a gain of 10
(d) an inverting amplifier with a gain of 100
6. The current gain of a BJT is [2001, 1 Mark]
gm
(a) gmr 0 (b)
r
IEE gm
(c) g m r (d)
r
–VEE
7. The ideal OP-AMP has the following characteristics.
(a) zero (b) infinite [2001, 1 Mark]
(a) Ri = , and A = , R0 = 0
Vi n1 Vin 2 (b) Ri = 0, A = , R0 = 0
(c) indeterminate (d) (c) Ri = , A = , R0 =
2VT
3. The configuration of the figure is a (c) Ri = 0, A = , R0 =
[2000, 1 Mark] 8. Consider the following two statements:
Statement 1:
A stable multivibrator can be used for generating square
R1 R1
wave.
Statement 2:
Bistable multivibrator can be used for storing binary
information. [2001, 1 Mark]
– (a) Only statement 1 is correct
Vo (b) Only statement 2 is correct
+ (c) Both the statements 1 and 2 are correct
R (d) Both the statements 1 and 2 are incorrect
9. In a negative feedback amplifier using voltage-series (i.e.,
C
voltage-sampling, series mixing) feedback. [2002, 1 Mark]
(a) Ri decreases and R0 decreases
R C (b) Ri decreases and R0 increases
(c) Ri increases and R0 decreases
(d) Ri increases and R0 increases
 9
10. Choose the correct match for input resistance of various (c) increase in input impedance and decrease in output
amplifier configurations shown below: [2003, 1 Mark] impedance
Configuration Input resistance (d) decrease in input impedance and increase in output
CB : Common Base LO : Low impedance
CC : Common Collector MO : Moderate
16. The input impedance (Zi) and the output impedance (Z0)
CE : Common Emmitter HI : High
(a) CB – LO, CC – MO, CE – HI of an ideal transconductance (voltage controlled current
(b) CB – LO, CC – HI, CE – MO source) amplifier are [2006, 1 Mark]
(c) CB – HI, CC – LO, CE – MO (a) Zi = 0, Z0 = 0 (b) Zi = 0, Z0 =
11. The circuit shown in the figure is best described as a (c) Zi = , Z0= 0 (d) Zi = , Z0 =
[2003, 1 Mark] 17. The correct full wave rectifier circuit is [2007, 1 Mark]

+ (a) (b)
– Output

(a) bridge rectifier (b) ring modulator

(c) frequency discriminator (d) voltage double
12. Generally, the gain of a transistor amplifier falls at high
frequencies due to the [2003, 1 Mark] (c) (d)
(a) internal capacitances of the device
(b) coupling capacitor at the input
(c) skin effect
(d) coupling capacitor at the output 18. In a transconductance amplifier, it is desirable to have
13. The oscillator circuit shown in the figure has an ideal [2007, 1 Mark]
inverting amplifier. Its frequency of oscillation (in Hz) is (a) a large input resistance and a large output resistance
[2003, 2 Marks] (b) a large input resistance and a small output resistance
(c) a small input resistance and a large output resistance
(d) a small input reistance and a small output resistance
19. The amplifier circuit shown below uses a silicon transistor.
The capacitor CC and CE can be assumed to be short at
signal frequency and the effect of output resistance R0
can be ignored. If CE is disconnected from the circuit,
C C C which one of the following statements is true?

R R R

1 1
(a) 2 6RC (b) 2 RC
1 6
(c) 6 RC (d)
2 RC
[2010, 1 Mark]
14 . An ideal op-amp is an ideal [2004, 1 Mark] (a) The input resistance Ri increases and the magnitude
(a) voltage controlled current source of voltage gian AV decreases
(b) voltage controlled voltage source
(c) current controlled current source (b) The input resistance Ri decreases and the magnitude
(d) current controlled voltage source of voltage gain AV decreases
15. Voltage series feedback (also called series-shunt feedback) (c) Both input resistance Ri and the magnitude of
results in [2004, 1 Mark] voltage gain AV decrease
(a) increase in both input and output impedances (d) Both input resistance Ri and the magnitude of
(b) decrease in both input and output impedances voltage gain AV increase
 10
20. In the ac equivalent circuit shown in the figure, if iin is the 23. The desirable characteristics of a transconductance amplifier
input current and RF is very large, the type of feedback is are [2014, Set-3, 1 Mark]
[2014, Set-1, 1 Mark] (a) high input resistance and high output resistance
(b) high input resistance and low output resistance
(c) low input resistance and high output resistance
(d) low input resistance and low output resistance
RD
24. The circuit shown represents [2014, Set-4, 1 Mark]
RD Vout
C2 +12 V
M2 vi –
M1
vo
small signal i
in
RF R2 +
input –12 V
R1
(a) voltage-voltage feedback –2 V C1
(b) voltage-current feedback
(c) current-voltage feedback (a) a bandpass filter
(d) current-current feedback (b) a voltage controlled oscillator
21. The feedback topology in the amplifier circuit ( the base bias (c) an amplitude modulator
circuit is not shown for simplicity) in the figure is (d) a monostable multivibrator
[2014, Set-2, 1 Mark] 25. For a given sample-and-hold circuit, if the value of the hold
VCC capacitor is increased, then [2014, Set-4, 1 Mark]
(a) droop rate decreases and acquisition time decreases
(b) droop rate decreases and acquisition time increases
Io (c) droop rate increases and acquisition time decreases
RC
(d) droop rate increases and acquisition time increases
Vo
Problem Based MCQs
26. In the circuit of the figure, Vo is [2000, 1 Mark]
RS
– + 15 V
RE
vo
VS
+1V + – 15 V
R

(a) Voltage shunt feedback (a) – 1 V (b) 2 V

(b) Current series feedback (c) + 1 V (d) + 15 V
(c) Current shunt feedback 27. The current gain of a bipolar transistor drops at high
(d) Voltage series feedback frequencies because of [2000, 1 Mark]
22. In the differential amplifier shown in the figure, the (a) transistor capacitances
magnitudes of the common-mode and differential-mode gains (b) high current effects in the base
are Acm and Ad, respectively. If the resistance RE is increased, (c) parasitic inductive elements
then [2014, Set-2, 1 Mark] (d) the Early effect
28. If the op-amp in the figure, is ideal, then v0 is
[2000, 1 Mark]
C

C
V1sin t –
Vo
V2sin t +
C
(a) Acm increases
(b) common-mode rejection ratio increases (a) zero (b) (V1 – V2) sin t
(c) Ad increases (c) – (V1 + V2) sin t (d) (V1 + V2) sin t
(d) common-mode rejection ratio decreases
 11
29. In the circuit of figure, assume that the transistor is in the 33. The oscillator circuit shown in the figure is
active region. It has a large and its base-emitter voltage is [2001, 2 Marks]
0.7 V. The value of Ic is [2000, 2 Marks]
–VCC
15 V

LC
RC
10 k
IC

L = 10 µH Vo
5k CC R1
430

C1 = 2pF C2 = 2pF
R2
(a) Indeterminate since Rc is not given Re Ce
(b) 1 mA
(c) 5 mA
(c) 10 mA (a) Hartely oscillator with foscillation = 79.6 MHz
30. If the op-amp in the figure has an input offset voltage of 5 (b) Colpitts oscillator with foscillation = 50.3 MHz
mV and an open-loop voltage gain of 10000, then Vo will be (c) Hartley oscillator with foscillation = 159.2 MHz
[2000, 2 Marks] (d) Colpitts oscillator with foscillation = 159.3 MHz
34. The inverting OP-AMP shown in the figure has an open-
+ 15 V loop gain of 100. [2001, 2 Marks]
R2 = 10
–
Vo
+ R1 = 1 k
–
VS +
– 15 V
Vi
– + Vo
(a) 0 V (b) 5mV
(c) + 15 V or – 15 V (d) + 50 V or – 50 V
31. An npn BJT has gm = 38 mA/V, C = 10–14 F, C = 4 × 10–13
F, and DC current gain, 0 = 90. For this transistor fT and f
are [2001, 2 Marks] V0
(a) fT = 1.64 × 108 Hz and f = 1.47 × 1010 Hz The closed-loop gain is
Vs
(b) fT = 1.47 × 1010 Hz and f = 1.64 × 108 Hz (a) – 8 (b) – 9
(c) fT = 1.33 × 1012 Hz and f = 1.47 × 1010 Hz (c) – 10 (d) – 11
(d) fT = 1.47 × 1010 Hz and f = 1.33 × 1012 Hz 35. In the figure assume the OP-AMPs to be ideal. The output
32. The transistor shunt regulator shown in the figure has a Vo of the circuit is [2001, 2 Marks]
regulated output voltage of 10 V, when the input varies from VS = 10 cos(100 t)
20 V to 30 V. The relevant parameters for the zener diode and
the transistor are: Vz = 9.5, VBE = 0.3 V, = 99, Neglect the
current through RB. Then the maximum power dissipated in
the zener diode (Pz) and the transistor (PT) are
[2001, 2 Marks]
20

IZ IC
Vin VZ
Vo = 10 V
20-30V + t
RB VBE –
(a) 10 cos (100 t) (b) 10 cos 100 d
0
(a) Pz = 75 mW, PT = 7.9 W t
(b) Pz = 85 mW, PT = 8.9 W 4 4 d
(c) Pz = 95 mW, PT = 9.9 W (c) 10 cos 100 d (d) 10 cos 100t
0 dt
(d) P2 = 115 mW, PT = 11.9 W
 1236.

36. A 741-type opamp has a gain-bandwidth product of 1 MHz. |Av|

A non-inverting amplifier using this op-amp and having a dB
voltage gain of 20 dB will exhibit a – 3 dB bandwidth of
[2002, 1 Mark] 0
(a) 50 kHz (b) 100 kHz
–3
1000 1000
(c) kHz (d) kHz (d)
17 7.07
37. Three identical RC-coupled transistor amplifiers are
cascaded. If each of the amplifier has a frequency response
as shown in the figure, the overall frequency response is as 10 Hz 0.5 kHz f
given in [2002, 1 Mark]
38. The circuit in the figure employs positive feedback and is
|Av| intended to generate sinusoidal oscillation. If at a frequency
dB Vf f 1
f0 , B f 0 , then to sustain oscillation at
V0 f 6
0
this frequency [2002, 1 Mark]
–3
R2

R1
–
20 Hz 1 kHz f
+
+
|Av|
Network Vo(f)
dB +
Vo(f) B(f)
– –
0
–3
(a) (a) R2 = 5R1 (b) R2 = 6R1
R1 R1
(c) R 2 (d) R 2
f 6 5
40 Hz 0.5 kHz
39. An amplifier using an opamp with a slew-rate SR = 1 V/ sec
has a gain of 40 dB. If this amplifier has to faithfully amplify
|Av| sinusoidal signals from dc to 20 kHz without introducing
dB any slew-rate induced distortion, then the input signal level
must not exceed. [2002, 1 Mark]
0 (a) 795 mV (b) 395 mV
(c) 79.5 mV (d) 39.5 mV
–3
40. A zener diode regulator in the figure is to be designed to
(b) meet the specifications: IL = 10 mA V0 = 10 V and Vin varies
from 30 V to 50 V. The zener diode has Vz = 10 V and Izk
(knee current) = 1 mA. For satisfactory operation
[2002, 1 Mark]
40 Hz 1 kHz f
I R1
|Av|
IZ IL = 10 mA
dB

0 Vin RL
DZ VO
–3
(c)

(a) R1 1800 (b) 2000 R1 2200

40 Hz 2 kHz f (c) 3700 R1 4000 (d) R1 4000
 13
41. The voltage gain Av = V0 of the JFET amplifier shown in the (a) (2V, 2 mA) (b) (3 V, 2 mA)
figure is IDSS = 10 mA Vp = – 5 V(Assume C1, C2 and C8 to be (c) (4 V, 2 mA) (d) (4 V, 1 mA)
very large [2002, 1 Mark]
46. The output voltage of the regulated power supply shown in
VDD = + 10 V the figure is [2003, 2 Marks]

(3 k ) RD 1k
C2 +
15 V DC
Vo Unregulated
C1 Power Source VZ = 3V –
40 k
VS RC Regulated
(2.5 k ) RS CS 20 k DC output
(1 M )
(a) 3 V (b) 6 V
(c) 9 V (d) 12 V
47. If the op-amp in the figure is ideal, the output voltage Vout
will be equal to [2003, 2 Marks]
(a) + 16 (b) – 16
(d) + 8 (d) – 6 5k

42. If the input to the ideal comparators shown in the figure is

sinusoidal signal of 8. V (peak to peak) without any DC 1k
component, then the output of the comparators has a duty 2V –
cycle of [2003, 1 Mark] vout
1k
3V +
Input +
Output 8k
Vref = 2 –

(a) 1/2 (b) 1/3

(c) 1/6 (d) 1/2 (a) 1 V (b) 6 V
(c) 14 V (d) 17 V
43. If the differential voltage gain and the common mode voltage 48. Three identical amplifiers with each one having a voltage
gain of a differential amplifier are 48 dB and 2 dB respectively, gain of 50, input resistance of 1 k andoutput resistance of
then common mode rejection ratio is [2003, 1 Mark] 250 are cascaded. The opened circuit voltages gain of the
(a) 23 dB (b) 25 dB combined amplifier is [2003, 2 Marks]
(d) 46 dB (d) 50 dB (a) 49 dB (b) 51 dB
(c) 98 dB (d) 102 dB
44. An amplifier without feedback has a voltage gain of 50, input 49. An ideal sawtooth voltages waveform of frequency of 500
resistance of 1 k and output resistance of 2.5 k . The Hz and amplitude 3 V is generated by charging a capacitor of
input resistance of the current-shunt negative feedback 2 F in every cycle. The charging requires [2003, 2 Marks]
amplifer using the above amplifier with a feedback factor of (a) Constant voltage source of 3V for 1 ms
0.2, is [2003, 2 Marks] (b) Constant voltage source of 3V for 2 ms
(c) Constant current source of 1 mA for 1 ms
1 1 (d) Constant current source of 3 mA for 2 ms
(a) k (b) k
11 5
(c) 5 k (d) 11 k 50. The circuit in the figure is a [2004, 1 Mark]
45. In the amplifier circuit shown in the figure, the values of R1
and R2 are such that the transistor is operating at VCE = 3V
and IC = 1.5 mA when its is 150. For a transistor with of –
200, the operating point (VCE, IC) is [2003, 2 Marks] R vo
R
VCC = 6 V vi +
R1 R2
C C

(a) low-pass filter (b) high-pass filter

(c) band-pass filter (d) band-reject filter
 14
51. Abipolar transistor is operating in the active region with a 54. In the voltage regulator shown in the figure, the load current
collector current of 1 mA. Assuming that the of the can vary from 100 mA to 500 mA. Assuming that the Zener
transistor is 100 and the thermal voltage (VT) is in the common diode is ideal (i.e., the Zener knee current is negligibly small
emitter configuration, are [2004, 2 Marks] and Zener resistance is zero in the breakdown region).
(a) gm = 25 mA/V and r = 15.625 k [2004, 2 Marks]
(b) gm = 40 mA/V and r = 4.0 k R
(c) gm = 25 mA/V and r = 2.5 k
(d) gm = 40 mA/V and r = 2.5 k
52. The value of C required for sinusoidal oscillations of
frequency 1 kHz in the circuit of the figure is Variable load
[2004, 2 Marks] 12 V +
– 5V 100 to 500 mA

1k 2.1 k

(a) 7 (b) 70
– 70
(c) (d) 14
3
+ 55. In a full-wave rectifier using two ideal diodes, Vdc and Vm
C are the dc and peak values of the voltage respectively across
a resistive load. If PIV is the peak inverse voltage of the
1k diode, then the appropriate relationships for this rectifier are
[2004, 2 Marks]
Vm
(a) Vdc , PIV 2Vm
1k C
Vm
(b) Idc 2 , PIV 2Vm

Vm
1 (c) Vdc 2 , PIV Vm
(a) F (b) 2 F
2
Vm
1 (d) Vdc , PIV Vm
(c) F (d) 2 6 F
2 6 56. Assume that the of transistor is extremely large and
53. In the op-amp circuit given in the figure, the load current iL VBE = 0.7 V, IC and VCE in the circuit shown in the figure
is [2004, 2 Marks] [2004, 2 Marks]

R 5V
1

R
1 IC
Vs –
Vo 2.2 k
+ 4k
+
VEC
–
R2 R2 1k
iL RL 300

Vs Vs
(a) (b) (a) IC = 1 mA, VCE = 4.7 V
R2 R2
(b) IC = 0.5 mA, VCE = 3.75 V
Vs Vs (c) IC = 1 mA, VCE = 2.5 V
(c) RL
(d)
R1 (d) IC = 0.5 mA, VCE = 3.9 V
 15
57. The input resistance Ri of the amplifier shown in figure is Which of the following Q-points will give the highest
transconductance gain for small signals?
(a) VGS = – 6V (b) VGS = – 6V
(c) VGS = 0 (d) VGS = 3 V
61. For the Zener diode shown in the figure, the Zener voltage
at knee is 7 V, the knee current is negligible and the Zener
dynamic resistance is 10 . If the input voltage (Vi) range
is from 10 to 16 V, the output voltage (V0) range from
[2007, 2 Marks]

[2005, 1 Mark]
30
(a) k (b) 10 k
4
(c) 40 k (d) infinite
58. For the circuit shown below, assume that the zener diode
is ideal with a breakdown voltage of 6 Volts. The waveform
observed across R is [2006, 2 Marks] (a) 7.00 to 7.29 V (b) 7.14 to 7.29 V
(c) 7.14 to 7.43 V (d) 7.29 to 7.43 V
62. In the Op-Amp circuit shown, assume that the diode
current follows the equation I = Is exp (V/VT). For Vi = 2
V, Vo = Vo1, and for Vi = 4 V, Vo = Vo2.The relationship
between Vo1 and Vo2 is [2007, 2 Marks]

(a) (b)

(c) (d) (a) Vo2 2Vo1 (b) Vo2 e 2 Vo1

59. For the circuit shown in the following figure, the capacitor (c) Vo2 Vo1 n2 (d) Vo1 Vo2 VT n 2
C is initially uncharged. At t = 0, the switch S is closed. The 63. In the CMOS inverter circuit shown, if the
voltage VC across the capacitor at t = 1 millisecond is transconductance parameters of the NMOS and PMOS
W Wp
transistors are kn = kp = nCox n p C ox = 40 A/V2
Ln Lp
[2006, 2 Marks]
and their threshold voltages are Vthn = |Vthp| = 1V, the
current I is [2007, 2 Marks]

(In the figure shown above, the op-amp is supplied with

± 15 V and the ground has been shown by the symbol )
(a) zero (b) 6.3 V
(c) 9.45 V (d) 10 V
60. An n-channel depletion MOSFET has following two
points on its ID – VGS curve [2006, 1 Mark]
(i) VGS = 0 at ID = 12 mA and (a) zero (b) 25 A
(ii) VGS = – 6 V at ID = 0 (c) 45 A (d) 90 A
 16
64. For the BJT circuit shown, assume that the of the The equivalent gm of the pair is
transistor is very large and VBE = 0.7 V. The mode of (a) the sum of individual gm’s of the transistors
operation of the BJT is [2007, 2 Marks] (b) the product of individual gm’s of the transistors
(c) nearly equal to the gm of M10
(d) nearly equal to gm/go of M2

68.

(a) cut-off (b) saturation

The OPAMP circuit shown above represents a
(c) normal active (d) reverse active [2008, 2 Marks]
65. For the op-amp circuit shown in the figure, Vo is (a) high pass filter (b) low pass filter
[2007, 2 Marks] (c) band pass filter (d) band reject filter
69. Consider the following circuit using an ideal OPAMP. The
I-V characteristics of the diode is described by the relation
v

I = I0 e vT 1 where V = 25 mV, I = 1 A and V is the

T o

voltage across the diode (taken as positive for forward

bias) [2008, 2 Marks]
(a) – 2 V (b) – 1 V
(c) – 0.5 V (d) 0.5 V
66. Consider the Schmidt trigger circuit shown below

For an input voltage VS = – 1 V, the output voltage Vo is

(a) 0V (b) 0.1 V
(c) 0.7 V (d) 1.1 V
[2008, 2 Marks] 70. For the circuit shown in the following figure, transistors
A triangular wave which goes from – 12 V to 12 V is M1 and M2 are identical NMOS transistors. Assume the
applied to the inverting input of the OPAMP. Assume that M2 is in saturation and the output is unloaded.
the output of the OPAMP swings from +15V to –15V. The
voltage at the non-inverting input switches between
(a) –12V and +12V (b) –7.5V and –7.5V
(c) –5V and +5V (d) 0V and 5V
67. Two identical NMOS transistors M1 and M2 are connected
as shown below. Vbias is chosen so that both transistors
are in saturation. The equivalent gm of the pair is defined
Iout
to be V at constant Vout [2008, 2 Marks]
i

[2008, 2 Marks]
The current Ix is related to Ibias as
(a) Ix = Ibias + Is
(b) Ix = Ibias
(c) Ix = Ibias – Is
Vout
(d) Ix = Ibias – VDD
RE
 17
71. An astable multi-vibrator circuit using IC 555 timer is 75. In the circuit below, the diode is ideal. The voltage V is
shown below. Assume that the circuit is oscillating given by [2009, 2 Marks]
steadily. [2008, 2 Marks]

(a) min (Vi, 1) (b) max (Vi, 1)

(c) min (– Vi, 1) (d) max (–Vi, 1)
76. A small signal source Vi(t) = A cos 20t + B sin 106t applied
to a transistor amplifier as shown below. The transistor
has = 150 and hie = 3 k . Which expression best
approximates Vo (t)? [2009, 2 Marks]

The voltage VC across the capacitor varies between

(a) 3 V to 5 V (b) 3 V to 6 V
(c) 3.6 V to 6 V (d) 3.6 V to 5 V
72. The measured transconductance gm of an NMOS transistor
operating in the linear region is plotted against the gate
voltage VG at constant drain voltage VD. which of the
following figures represents the expected dependence of
gm on VG? [2008, 2 Marks]

(a) Vo(t) = – 1500 (A cos 20t + B sin 106 t)

(b) Vo(t) = – 150 (A cos 20t + B sin 106 t)
(a) (b) (c) Vo(t) = – 1500 B sin 106 t
(d) Vo(t) = – 150 B sin 106 t
77. In the following astable multi-vibrator circuit, which
properties of Vo(t) depend on R2? [2009, 2 Marks]

(c) (d)

73. In the following limiter circuit, an input voltage Vi = 10 sin

100 t is applied. Assume that the diode drop is 0.7 V
when it is forward biased. The Zener breakdown voltage
is 6.8V. The maximum and minimum values of the output
voltage respectively are [2008, 1 Mark]

(a) Only the frequency

(b) Only the amplitude
(c) Both the amplitude and the frequency
(d) Neither the amplitude nor the frequency
78. The transfer characteristic for the precision rectifier circuit
(a) 6.1 V, – 0.7 V (b) 0.7 V, – 7.5 V
shown below is (assume ideal OP-AMP and practical
(c) 7.5 V, – 0.7 V (d) 7.5 V, – 7.5 V diodes) [2010, 2 Marks]
74. The drain current of a MOSFET in saturation is given by
lD = K (VGS – VT)2 where K is a constant. The magnitude
of the transconductance gm is [2008, 1 Mark]
K(VGS VT )2
(a) (b) 2K (VGS – VT)
VDS

lD K(VGS VT )2
(c) VGS VDS (d)
VGS
 18
81. In the circuit shown below for the MOS transistors, nCOX
= 100 A/V2 and the threshold voltage VT = 1V. The
voltage Vx at the source of the upper transistor is
(a)
[2011, 2 Marks]

(b)

(c)
(a) 1 V (b) 2 V
(c) 3 V (d) 3.67 V
82. The circuit below implements a filter between the input
current i and the output voltage vo. Assume that the
(d) opamp is ideal. The filter implemented is a [2011, 1 Mark]

79. Assuming the OP-AMP to be ideal, the voltage gain of the

amplifier shown below is

(a) low pass filter (b) band pass filter

(c) band stop filter (d) high pass filter
83. In the circuit shown below, capacitors C1 and C2 are very
R2 R3 large and the short at the input frequency Vi is a small
(a) R1 (b) R1 [2010, 1 Mark] signal input. The gain magnitude |Vo/Vi| at 10 Mrad/s is
R 2 || R 3 R 2 R3
(c) R1 (d) R1
80. In the silicon BJT circuit shown below, assume that the
emitter area of transistor Q1 is half that of transistor Q2.

The value of current Io is approximately[2010, 1 Mark] [2011, 1 Mark]

(a) 0.5 mA (b) 2 mA (a) maximum (b) minimum
(c) 9.3 mA (d) 15 mA (c) unity (d) zero
 19
84. The circuit shown is a [2012, 2 Marks] (a) 250 (b) 27.5
(c) 22.5 (d) 25
88. In the circuit shown below, the op-amps are ideal. Then
Vout in Volts is [2013, 2 Marks]
1k 1k
–2V +15V
+15V
–
+
+ Vout
–
1k –15V
1 –15V
(a) low pass filter with f3dB = (R rad / s
1 R 2 )C +1V 1k
1k
1
(b) high pass filter with f3dB = rad / s
R1C
1
(c) low pass filter with f3dB = rad / s (a) 4 (b) 6
R1C (c) 8 (d) 10
1 89. In the circuit shown below, Q 1 has negligible
(d) high pass filter with f3dB = (R R )C rad / s collector-to-emitter saturation voltage and the diode drops
1 2
85. The voltage gain AV of the circuit shown below is negligible voltage across it under forward bias. If VCC is +5
V, X and Y are digital signals with 0 V as logic 0 and VCC
as logic 1, then the Boolean expression for Z is
+VCC

R1

R2
X Q1
[2012, 2 Marks] Diode
(a) | A V | 200 (b) | A V | 100
(c) | A V | 20 (d) | A V | 10
86. The i-v characteristics of the diode in the circuit given
Y
below are [2012, 1 Mark]
[2013, 2 Marks]
v 0.7
i= A,v 0.7V (a) XY (b) XY
500 (c) XY (d) XY
90. In the circuit shown below, the silicon npn transistor Q has
a very high value of . The required value of R2 in k to
produce IC = 1 mA is [2013, 2 Marks]
VCC
3V

The current in the circuit is R1 IC

(a) 10 mA (b) 9.3 mA 60 k
(c) 6.67 mA (d) 6.2 mA
87. The current ib through the base of silicon npn transistor
is 1 + 0.1 cos (10000 t) mA. At 300 K, the r in the small Q
signal model of the transistor is [2012, 1 Mark]
R2
RE
500

(a) 20 (b) 30
(c) 40 (d) 50
 20
91. In the circuit shown below, the knee current of the ideal
Zener diode is 10 mA. To maintain 5 V across RL, the
minimum valueof RL in and the minimum power rating
of the Zener diode in mW respectively are
RD
10 k
100 1 F
v0

+ I Load
10 V –
vi C RL
RL M 10 k
VZ = 5V

[2013, 2 Marks] [2013, 2 Marks]

(a) 125 and 125 (b) 125 and 250 (a) 8 (b) 32
(c) 250 and 125 (d) 250 and 250 (c) 50 (d) 200
dVB 94. In the circuit shown below, what is the output voltage
92. The small-signal resistance i.e., in k offered by (Vout) in Volts if a silicon transistor Q and an ideal op-amp
dID
are used?
the n-channel MOSFET M shown in the figure below, at a
bias point of VB = 2 V is (device data for M: device
transconductance parameter kN = nC'ox (W/L) = 40 A/V2,
threshold voltage VTN = 1 V, and neglect body effect and Q
+15 V
channel length modulation effects) 1k
–
C
VB + Vout
5V + A
– –15 V
ID

[2013, 1 Mark]
(a) –15 (b) –0.7
M (c) +0.7 (d) +15
95. In the circuit shown, the op-amp has finite input impedance,
infinite voltage gain and zero input offset voltage. The
output voltage Vout is [2014, Set-1, 2 Marks]

R2
[2013, 2 Marks]
(a) 12.5 (b) 25
(c) 50 (d) 100 R1 l1
93. The ac schematic of an NMOS common-source stage is –
Vout
shown in the figure below, where part of the biasing circuits +
has been omitted for simplicity. For the n-channel l2
MOSFET M, the transconductance gm = 1 mA/V, and body
effect and channel length modulation effect are to be
neglected. The lower cutoff frequency in Hz of the circuit (a) –I2 (R1 + R2) (b) I2R2
is approximately at (c) I1R2 (d) –I1 (R1+ R2)
 21
96. For the n-channel MOS transistor shown in the figure, the (a) –0.3 Ve < Vi × 4 < 1.3 V
threshold voltage VTh is 0.8 V. Neglect channel length (b) –0.3 Ve < Vi × 4 < 2 V
modulation effects. When the drain voltage VD=1.6 V, the (c) –1.0 Ve < Vi × 4 < 2.0 V
drain current ID was found to be 0.5 mA. If VD is adjusted to (d) –1.7 Ve < Vi × 4 < 2.7 V
be 2 V by changing the values of R and VDD, the new value 100. Consider the common-collector amplifier in the figure (bias
of ID (in mA) is [2014, Set-2, 2 Marks] circuitry ensures that the transistor operates in forward active
VDD region, but has been omitted for simplicity). Let IC be the
R collector current, VBE be the base-emitter voltage and VT be
the thermal voltage. Also, gm and ro are the small-signal
D transconductance and output resistance of the transistor,
G respectively. Which one of the following conditions ensures
S a nearly constant small signal voltage gain for a wide range
of values of RE? [2014, Set-4, 2 Marks]
(a) 0.625 (b) 0.75
(c) 1.125 (d) 1.5 VCC
97. In the circuit shown, the silicon BJT has = 50. Assume VBE
= 0.7 V and VCE(sat) = 0.2 V. Which one of the following
statements is correct? [2014, Set-3, 2 Marks] Vin
Vout
10V
RC RE

50 k
5V (a) g m RE 1 (b) IC RE VT
RB
(c) gm ro 1 (d) VBE VT

(a) For RC = 1 k , the BJT operates in the saturation region Common Data MCQs
(b) For RC = 3 k , the BJT operates in the saturation region
(c) For RC =20 k , the BJT operates in the cut-off region Common Data Questions 101 to 103
(d) For RC =20 k , the BJT operates in the linear region Given, r d = 20 k , IDSS = 10 mA, VP = – 8V
98. Assuming that the Op-amp in the circuit shown is ideal, Vo [2005, 2 Marks Each]
is given by [2014, Set-3, 2 Marks]

3R
–
V1
R V0
2R V2 +
R

5 5
(a) V1 3V2 (b) 2V1 V2
2 2
3 7 11
(c) V1 V2 (d) 3V1 V2
2 2 2 101. Zi and Z0 of the circuit are respectively
99. Two silicon diodes, with a forward voltage drop of 0.7 V, are 20
used in the circuit shown in the figure. The range of input (a) 2M and 2 k (b) 2M and k
voltage Vi for which the output voltage V0 = Vi, is 11
[2014, Set-4, 1 Mark] 20
(c) Infinity and 2 k (d) infinity and k
R 11
+ + 102. ID and VDS under DC conditions are respectively
(a) 5.625 mA and 8.75 V (b) 7.500 mA and 5.00 V
D1 D2 (c) 4.500 mA and 11.00 V (d) 6.250 mA and 7.50 V
Vi 103. Transconductance in milli-Siemens (mS) and voltage gain
VO
of the amplifier are respectively
–1V + + 2V
(a) 1.875 mS and 3.41 (b) 1.875 mS and – 3.41
(c) 3.3 mS and – 6 (d) 3.3 mS and 6
 22
Common Data for Questions 104 to 106
In the transistor amplifier circuit shown in the figure below, the Linked Answer Type MCQs
transistor has the following parameters [2006, 2 Marks Each]
DC = 60, VBE = 0.7 V, Statement for Linked Answer Questions 109 and 110
The capacitance CC can be assumed to be infinite. A regulated power supply, shown in figure below, has an
unregulated input (UR) of 15 Volts and generates a
regulated output Vout . Use the component values shown in
the figure. [2006, 2 Marks Each]

In the figure above, the ground has been shown by the symbol
.
104. Under the DC conditions, the collector-to-emitter voltage
drop is
(a) 4.8 V (b) 5.3 V
(c) 6.0 V (d) 6.6. V
105. I DC is increased by 10% the collector-to-emitter voltage In the figure above, the ground has been shown by the symbol .
drop 109. The power dissipation across the transistor Q1 shown in
(a) increases by less than or equal to 10% the figure is
(b) decreases by less than or equal to 10% (a) 4.8 mW (b) 5.0 mW
(c) increases by more than 10% (c) 5.4 mW (d) 6.0 mW
(d) decreases by more than 10% 110. If the unregulated voltage increases by 20% then power
106. The small-signal gain of the amplifier is dissipation across the transistor Q1
(a) – 10 (b) – 5.3 (a) increases by 20% (b) increases by 50%
(c) 5.3 (d) 10 (c) remains unchanged (d) decreases by 20%
Common Data for Questions 107 and 108
Statement for Linked Answer Questions 111 and 112
Consider the common emitter amplifier shown below with the
Consider the Op-Amp circuit shown in the figure.
following circuit parameters : [2010, 2 Marks Each]
= 10, gm = 0.3861 A/V [2007, 2 Marks Each]
R0 = , RE = 259 k , RS = 1k
RB = 93 k , RC = 250
RL = 1k , C1 = and C2 = 4.7 mF

111. The transfer function V0(s)/Vt(s) is

1 sRC 1 sRC
(a) (b)
1 sRC 1 sRC

1 1
(c) (d)
1 sRC 1 sRC
107. The resistance seen by the source VS is
112. If Vi = V1 sin ( t) and V0 = V2 sin ( t + ) then the
(a) 258 (b) 1258
(c) 93 k (d) infinite minimum and maximum values of (in radians) are
108. The lower cut-off frequency due to C2 is respectively
(a) 33.9 Hz (b) 27.1 Hz (a) – /2 and /2 (b) 0 and /2
(c) 13.6 Hz (d) 16.9 Hz (c) – and 0 (d) – /2 and 0
 23
Statement for Linked Answer Questions 113 and 114
In the following transistor circuit VBE = 0.7 V, r = 25 mV/lE, and Numerical Answer Questions
and all the capacitances are very large.[2008, 2 Marks Each]
117. (a) For given figure, Plot vo under steady state conditions,
with and without C. Assume that the diode is ideal.
(b) Design a circuit using two ideal diodes, one resistor
and two voltage sources that would convert the input
voltage of figure n to the output voltage of fourth figure.
The resistor value need not be specified.
[2000, 5 Marks]

Vi Vi Vc

R C
t
113. The value of DC current lE is
(a) 1 mA (b) 2 mA
(c) 5 mA (d) 10 mA
114. The mid-band voltage gain of the amplifier is approximately 118. For the amplifier of given figure, IC = 1.3 mA, RC = 2 k , RE
(a) – 180 (b) – 120 KT
(c) – 90 (d) – 60 = 500 , VT 26 mV, = 100, VCC = 15 V, vs = 0.01
q
Statement for Linked Answer for Questions 115 and 116:
Consider the CMOS circuit shown, where the gate voltage VG sin ( t) V and Cb = CE = 10 F. [2000, 5 Marks]
of the n-MOSFET is increased from zero, while the gate voltage VCC
of the p-MOSFET is kept constant at 3 V. Assume that, for both
transistors, the magnitude of the threshold voltage is 1 V and
W
the product of the transconductance parameter and the RC
L R1 IC VO
ratio,
W Cb
i.e. the quantity Cox V–2. [2009, 2 Marks Each]
is 1 mAV
L VS R2 RE CE

(a) What is the small-signal voltage gain, Av = vo/vs?

(b) What is the approximate Av, if CE is removed?
(c) What will vo be if Cb is short circuited?
119. The figure shows a common base amplifier.
[2000, 1 Mark]
VCC

115. For small increase in VG beyond 1V, which of the following

gives the correct description of the region of operation of RC
each MOSFET? R1 IC VO
(a) Both the MOSFETs are in saturation region
(b) Both the MOSFETs are in triode region
(c) n-MOSFET is in triode and p-MOSFET is in saturation Cb
region
VS R2 RE CE
(d) n-MOSFET is in saturaton and p-MOSFET is in
triode region
116. Estimate the output voltage V0 for VG = 1.5 V.
1 1
(a) 4 (b) 4 V
2 2 (a) Write expressions for the time-constants associated
with the capacitors, CB and CS.
3 3 (b) What is the approximate lower cut-off frequency of the
(c) V (d) 4 V
2 2 amplifier?
 24
120. An emitter-follower amplifier is shown in the figure, Zi is the
impedance looking into the base of the transistor and Z0 is 0.5 k D1
the impedance looking into the emitter of the transistor. + +
[2001, 5 Marks]
D2 1k
Vi(t) V0t
+ 1.5 k
7V +
– 5V
–
– –

(a) Determine the output V0(t).

(b) Neatly sketch the output waveform superimposed on
the input Vi(t) and label the key points.
123. In the low-pass filter shown in the figure, for a cut-off
frequency of 5 kHz , the value of R2 (in k ) is __________.
[2014, Set-1, 1 Mark]

R2

(a)Draw the small signal equivalent circuit of the amplifier. C

(b)Obtain an expression for Zi.
(c)Obtain an expression for Z0. 1k 10 nF
(d)Determine Zi and Z0 if a capacitor CL is connected Vi –
across RL. R1 V°
+
121. Assume that the OP-AMP in the figure, ideal
[2001, 5 Marks]

124. In the voltage regulator circuit shown in the figure, the

op-amp is ideal. The BJT has VBE = 0.7 V and 100, and the
zener voltage is 4.7 V. For a regulated output of 9 V, the value
of R (in ) is ___________. [2014, Set-1, 2 Marks]
V1 = 12V V0 = 9V

1k +
– 1k

(a) Obtain an expression for v0 in terms of vs, R, and the VZ = 4.7V R

reverse saturation current Is of the transistor.
(b) If R = 1 , Is = 1pA and the thermal voltage VT = 25 m
V, then what is the value of the output voltage vo for 125. For the amplifier shown in the figure, the BJT parameters are
an input voltage vs = 1V? VBE = 0.7 V, = 200, and thermal voltage VT = 25 mV. The
(c) Suppose that the transistor in the feedback path is voltage gain (vo/vi) of the amplifier is _________.
replaced by a p-n junction diode with a reverse [2014, Set-1, 2 Marks]
saturation current of Is. The p-side of the diode is
connected to node A and the n-side to node B. Then VCC= +12V
what is the expression for v0 in terms of vs, R and Is? RC
122. A triangular voltage waveform Vi(t) first figure applied at R1 5k
the input to the circuit of second figure. Assume the diodes 33k v0
to be ideal. [2002, 5 Marks] 1 F
1 F
V1

V1(t) R2
11k RS
10
12 V
RE CE
t 1k 1 mF
0
 25
126. A cascade connection of two voltage amplifiers A1 and A2 130. An analog voltage in the range 0 to 8 V is divided in 16 equal
is shown in the figure. The open-loop gain Av0, input intervals for conversion to 4-bit digital output. The maximum
resistance Rin, and output resistance Ro for A1 and A2 are as quantization error (in V) is _________
follows: [2014, Set-2, 1 Mark] [2014, Set-3, 1 Mark]
A1 : Av0 = 10, Rin = 10 k , R0 = 1 k . 131. The slope of the ID vs VGS curve of an n-channel MOSFET
A2 : Av0 = 5, Rin = 5 k , R0 = 200 k . in linear region is 10–3 –1 at VDS = 0.1 V. For the same
The approximate overall voltage gain vout/vin is. device, neglecting channel length modulation, the slope of
+ + the I D vs. VGS curve (in A / V ) under saturation region
is approximately _________. [2014, Set-3, 2 Marks]
Vin A1 A2 RL Vout 132. An ideal MOS capacitor has boron doping-concentration of
1k 1015 cm-3 in the substrate. When a gate voltage is applied,
– – a depletion region of width 0.5 m is formed with a surface
(channel) potential of 0.2 V. Given that 0 = 8.854 × 10-14 F/
127. For the MOSFETs shown in the figure, the threshold voltage cm and the relative permittivities of silicon and silicon dioxide
are 12 and 4, respectively, the peak electric field (in V/ m) in
1 W the oxide region is [2014, Set-3, 2 Marks]
|Vt| = 2 V and K Cox = 0.1 mA/V2. The value of ID
2 L
(in mA) is ___________. [2014, Set-2, 2 Marks] 133. For the MOSFET M1 shown in the figure, assume W/L = 2,
VDD = 2.0 V, n Cox =100 A/V2 and VTH = 0.5 V. The
VDD = + 12V transistor M1 switches from saturation region to linear region
when Vin (in Volts) is__________. [2014, Set-3, 2 Marks]
R1 VDD
10 k

R2 R = 10 k
ID
10 k
Vout
Vin M1

VSS = –5V
128. In the circuit shown, the PNP transistor has |VBE| = 0.7 V and 134. A BJT in a common-base configuration is used to amplify a
= 50. Assume that RB = 100 k . For V0 to be 5 V, the value signal received by a 50 antenna. Assume kT/q = 25 mV.
of RC (in k ) is _______ The value of the collector bias current (in mA) required to
match the input impedance of the amplifier to the impedance
of the antenna is________. [2014, Set-4, 2 Marks]
RC 135. For the common collector amplifier shown in the figure, the
BJT has high , negligible VCE(sat), and VBE = 0.7 V. The
VO maximum undistorted peak-to-peak output voltage vo (in
Volts) is _______. [2014, Set-4, 2 Marks]
VCC = + 12V
RB
VEE = 10V

1 F
129. The figure shows a half-wave rectifier. The diode D is ideal.
The average steady-state current (in Amperes) through the
1 F
diode is approximately ____________.
[2014, Set-3, 1 Mark]
D

10 sin t R
f = 50 Hz 100 4 mF
 26

13. (a) The given circuit is a R – C phase shift oscillator and

CONCEPTUAL MCQs
frequency of its oscillation is
1. (c) With the addition of RE the DC bias currents and
voltages remain closer to the point where they were set 1
f
by the circuit when the outside condition such as 2 6RC
temperature and transistor parameter change. 14 . (b) An ideal OPAMP is an ideal voltage controlled voltage
2. (a) Common mode gain is source.
RC 15. (c) In voltage series feed back amplifier, input impedance
AC increases by factor (1 + A ) and output impedance
R EE
decreases by the factor (1 + A ).
Since source resistance of the current source is infinite
REE = , common mode gain AC = 0 R if Ri 1 A
3. (d) There is R – C, series connection in parallel with parallel
R – C combination. So, it is a wein bridge oscillator Ro
R of
because two resistors R1 and R2 is also in parallel with 1 A
them.
4. (a) The given circuit is a differentiator, so the output of 16. (d)
triangular wave will be square wave.
5. (b) In sampling and hold circuit the unity gain non-
inverting amplifier is used.
6. (c) The current gain of a BJT is
h fe g m
7. (a) The ideal op-amp has the following characteristic:
Ri For ideal transconductance amplifier, output current
Ro 0 is proportional to the signal voltage independent of
and A the magnitudes of RS and RL.
8. (c) Both statements are correct because 17. (c) Full wave rectifier is
(1) A stable multivibrator can be used for generating
square wave, because of its characteristic
(2) Bi-stable multivibrator can store binary information, and
this multivibrator also give help in all digital kind of
storing.
9. (c) In voltage-amplifier or voltage-series amplifier, the Ri
increase and Ro decrease because because
R if R i 1 A (1) during +ve cycle of input

Ro
R of
1 A
10. (b) For the different combinations the table is as follows
CE CE CC CB
Ai High High Unity
Av High Unity High
Ri Medium High Low (2) during –ve cycle of input
Ro Medium Low High
11. (d) This circuit having two diode and capacitor pair in
parallel, works as voltage doubler.
12. (b) The gain of amplifier is
gm
Ai
gb j C
Thus the gain of a transistor amplifier falls at high
frequencies due to the internal capacitance that are In both cases current passes through RL is in same
diffusion capacitance and transition capacitance. direction (rectification).
 27
18. (a) A practical transconductance amplifier has large R1 5
input resistance (Ri >> Rs) and provide high output VT VC 15 5V
resistance (Ro >> RL). R1 R 2 10 5
Since is large is large, IC IE , IB 0 and
VT VBE
IE
RE
5 0.7 4.3
= 10 mA
0.430k 0.430k
30. (c) The output voltage will be input offsent voltage
multiplied by open loop gain. Thus
So V0 = 5 mV × 10,000 = 50 V
But V0 15 V in saturation condition
19. (a)
So, it can never be exceeds 15 V
20. (b)
21. (b) Current series feedback So, V0 Vsat 15 V
hte he
22. (b) CMRR = 31. (b) If fT is the frequency at which the short circuit common
Rs hie
emitter gain attains unity magnitude then
If Re is increased then CMRR is also increased
3
23. (a) gm 38 10
24. (d) fT
2 C C 14 13
2 10 4 10
25. (b)
PROBLEM BASED MCQs = 1.47 × 1010 Hz
If fB is bandwidth then we have
26. (d) In positive feed back it is working as OP-AMP in
saturation region, and the input applied voltage is + fT1.47 1010
fB 1.64 108 Hz
ve. 90
So, V0 = + Vsat = 15 V 32. (c) If we neglect current through RB then it can be open
27. (a) At high frequency circuit as shown in fig.
gm
Ai I 20
g bc j C
1 IZ IC
or, Ai
Capacitance Vin IB
VZ +
1 VCE Vo = 10 V
and Aid 2-30 V +
frequency VBE – –
RB
Thus due to the transistor capacitance current gain of a
bipolar transistor drops.
28. (c) As OP-AMP is ideal, the inverting terminal at virtual Maximum power will dissipate in Zener diode when
ground due to ground at non-inverting terminal. current through it is maximum and it will occur at Vin =
Applying KCL at inverting termianl. 30 V
sC (v1sin t – 0) + sC (V2sin t – 0) + sC (Vo – 0) = 0 Vin Vo 30 10
or Vo = (– V1 + V2) sin t I 1A
20 20
29. (d) The Thevenin equivalent is shown below
I IC IZ IB IZ Since IC = IB
VCC = 15 V
= IZ IZ 1 IZ Since IB = IZ
I1
RC IC or IZ 0.01A
1 99 1
IB RT Power dissipated in zener diode is
PZ VZ IZ 9.5 0.01 95mW
+
IE
VBE – IC IZ 99 0.01 0.99A
VT + 430
VCE Vo 10V
–
Power dissipated transistor is
PT VC IC 10 0.99 9.9W
 28
33. (b) From the figure it may be easily seen that the tank circuit 3
is having 2-capacitors and one-inductor, so it is colpits V1 jL 100 10 10 j
j
oscillator and frequency is VS R 10 10
1
f jVS
2 LCeq V1 jcos100t
10
C1C2 2 2 Applying KCL at inverting terminal of second OP-AMP we
Ceq 1 pF have
C1 C2 4
V0 1/ j C
1 1 109
f 50.3MHz V1 100
2 10 10 6 10 12 2 10
34. (d) The circuit is as shown below. 1
= j10
6
j100 10 10 100
R2 = 20
or V0 j10V2 j10 jcos100t

R1 = 1 k V0 10cos100t
–
VS +
Vi 36. (b) Let x be the gain and it is 20 db, therefore
– + Vo 20 log x = 20
or x = 10
Since Gain bandwidth product is 106 Hz, thus
So, bandwidth is
Let V be the voltage of inverting terminal, since non
inverting termimal at ground, the output voltage is 106 106
BW 105 Hz 100kHz
Vo = AOL V– ...(1) Gain 6
Now applying KCL at inverting terminal we have
37. (a) In multistage amplifier bandwidth decrease and overall
V Vs V V0 gain increase. From bandwidth point of view only
0
R1 R2 option (a) may be correct because lower cutoff
From (1) and (2) we have frequency must be increased and higher must be
decreased. From following calculation we have
VO R2 We have fL = 20 Hz and fH = 1 kHz
ACL
Vs R 2 R1 For n stage amplifier the lower cutoff frequency is
R1
R OL
fL 20
Substituing the values we have f Ln 39.2 40 Hz
1 1
10k 1000 2n 1 23 1
ACL 11
10k 1k 89
1k The higher cutoff frequency is
100k
35. (a) The first OP-AMP state is the differentiator and second 1
OP-AMP stage is integrator. Thus if input is cosine f Hn fH 23 1 0.5 kHz
term, output will be also cosine term. Only option (a) is
cosine term. Other are sine term. Other are sine term. 38. (a) As per Barkhousen criterion for sustained oscillations
However we can calculate as follows. The circuit is |A | 1 and phase shift must be or 2 n.
shown in figure. VO f R2
Now from circuit A Vf f
1
R1
10 mH 10 F

1 Vf f
VS = 10 cos (100 t) 10 f 0
– 100 6 VO f
–
+ V1 Thus from above equation for sustained oscillation
+ V0
R2
6 1
R1

Applying KCL at inverting terminal of first OP-AMP we have or R2 = 5R1

 29
39. (c) Let the gain of OP-AMP be Av then we have V0
20log A v 40dB AV gm R D
Vi
or Av = 100
So, = – 2ms × 3k = – 6
Let input be Vi = Vm sin t then we have
VO A V Vi Vm sin t 42. (b) If the input is sinusoidal signal of 8 V (peak to peak)
then
dVO
Now AV Vm cos t Vi = 4 sin t
dt The output of comparator will be high when input is higher
dVO than Vref = 2 V and will be low when input is lower than
Slew Rate AVVm AVVm 2 f Vref = 2 V. Thus the waveform for input is shown below.
dt max
Vi
SR 1
or Vm
A V 2 f 10 6 100 2 20 103
4
or VM = 79.5 mV
40. (a) The circuit is shown as below 2

I R1
t1 t2 t
IZ IL = 10 mA

Vin RL
DZ VO

Vi

I = I Z + IL 4
For satisfactory operations 2
Vin V0
I Z IL [IZ + IL = 1]
R1 t2
t1 t
When Vin = 30 V,
30 10
10 1 mA
R1
20 From fig, first crossover is at t1 and second crossover is at
or 1 mA
R1 t2 where 4 sin t1 = 2V

or R1 1818 1
Thus t1 sin 1
2 6
50 10
When Vin = 50 V R 10 1 mA 5
1 t2
6 6
40
11 10 3 5
R1 1
Duty Cycle = 6 6
or R1 3636 Thus R1 1818 2 3
1
41. (d) We have Thus the output of comparators has a duty cycle of
IDSS = 10 mA and VP = – 5 V 3
Now VG = 0 Ad
and VS = IDRS = 1 × 2.5 = 2.5 V 43. (c) CMMR Ac
Thus VGS VG VS 0 2.5 2.5 V
or 20 log CMMR = 20 log Ad – 20 log Ac = 48 – 2 = 46 dB
2IDSS 2.5 Where Ad Differential Voltage Gain
gm 1 2mS and AC Common Mode Voltage Gain
VP 5
 30
44. (a) We have Ri = 1 k , = 0.2, A = 50 V 2 V Vo
0
Ri 1 1 5
Thus, R if 1 A 11
k
or Vo = 6V – 10
45. (a) The DC equivalent circuit is shown as below. This is 8
fixed bias circuit operating in active region. =6 10 6V
3
VCC = 6 V 48. (c) The equivalent circuit of 3 cascade stage is as shown
in figure.
R1 R2 IC 0.25 k 0.25 k 0.25 k

IB + +
+ + +
VCE V1 1 k 50 V1 + 1 k
–
V2 50 V2 +– 1 k V3 50 V3 +
–
V0
– – – –
–

1k
V2 50V1 40V1
In first case VCC – IC1R2 – VCE1 = 0 1k 0.25k
or 6 – 1.5 m R2 – 3 = 0 1k
Similarly V3 50V2 40V2
IC1 1.5m 1k 0.25k
IB1 0.01mA
1 150 or V3 = 40 × 40 V1
Vo = 50 V3 = 50 × 40 × 40V1
In second case IB2 will be equal to IB1 as there is no in
R1. Vo
or AV 50 40 40 8000
Thus IC2 2 IB2 200 0.01 2mA V1
VCE2 VCC IC2 R 2 6 2m 2k 2V or 20log A V 20log 8000 98dB
49. (d) If a constant current is made to flow in a capacitor, the
46. (c) output voltage is integration of input current and that
If we see the figure we find that the voltage at non-inverting is sawtooth waveform as below:
terminal is 3V by the zener diode and voltage at inverting t
terminal will be 3V. Thus Vo can be get by applying voltage 1
VC idt
division rule, i.e., C
0
20 The time period of wave form is
Vo 3
20 40
1 1
or V0 9V T 2 m sec
f 500
47. (b) The circuit is as shown below
2 10 3
1
5k Thus 3 6
idt
2 10 0

3 6
1k or i 2 10 0 6 10
2V – or i = 3 mA
vout Thus the charging require 3 mA current source for 2 m
1k
+ sec.
3V 50. (a)
8k

–
R A R vo
vi I
8 8 +
V 3 k
1 8 3
C C
8
V V V
3
Now applying KCL at inverting terminal we get
By Voltage Divider Rule at mode (A)
 31

XC
Applying KCL at non-inverting terminal
Vo .Vi V V Vo
XC R IL 0
R2 R2
1
or 2V Vo IL R 2 0 ...(2)
j C
Vo .Vi
1 Since V V , from (1) and (2) we have
R
j C Vs IL R 2 0
Vo 1 Vs
or IL
Vi 1 j RC R2
54. (d) If IZ is negligible the load current is
Vo 1
1 12 Vz
Vi 0
1 0 IL
R
Vo 1 as per given condition
0
Vi 1 12 VZ
0 100 mA 500 mA
Hence, the given OP-A mp circuit is Low Pass Filter. R
51. (d) When |IC| >> |ICO| 12 5
At IL = 100 mA = 100 mA VZ = 5 V
IC 1mA R
gm 0.04 40mA / V or R = 70
VT 25mV
12 5
100 At IL = 500 mA = 500 mA VZ = 5 V
r 2.5 k R
gm 40 10 3 or R = 14
52. (a) The given circuit is wein bridge oscillator. The frequecy Thus taking minimum we get
of socillation is R = 14
55. (b) In full wave rectifier
1
2 f 2Vm
RC VDC
1 1 1 P1V = 2Vm
or C
2 Rf 2 103 103 2 56. (c) The Thevenin equivalent is shown below.
53. (a) The circuit is as shown below.
VCC = 15 V
R
1

R
1V IC
Vs
– 2.2 k
–
IB RT
Vo
V+ +
+
VBE
–
VT + 300 IE
–
R2 R2
iL RL

R1 1
We know that for ideal OPAMP VT VCC 5 1V
R1 R 2 4 1
V V
Applying KCL at inverting terminal Since is large is large, IC I E , IB 0 and
V Vs V V0 VT VBE 1 0.7
0 IE 3 mA
R1 R1 RE 300
or 2V Vo Vs ...(1) Now VCE 5 2.2kI C 300IE
= 5 – 2.2k × 1m – 300 × 1 m = 2.5 V
 32

VS VA VS
57. (b) From virtual ground, VA; lS = 60. (d) Transfer (lD – VGS) curve of n-channel depletion
10k 10k
MOSFET.
VS VS As shown in curve when VGS is made more, the lD
Input resistance Ri = l 10k
S (VS / 10k) increasing rapidly.
Hence, choosing Q point at VGS = 3V will give
58. (a) highest transconductance gain.

61. (c)

When Vi = 10 V,i = 10 7 3 amp

210 210
3
During 0 < t Vo1 = 7 + 10i = 7 + 10. = 7.14 volts
6 210
Diode is OFF, No conduction
then, VR = 0 volts 9
When Vi = 16V, i = amp
210
In the interval, t
6 9
Zener diode voltage, VZ = 6 volts V02 = 7 + 10 = 7.43 volts
then, V0 = 12 sin t – VZ = 12 sin t – 6 210
In the interval, < t < 2 , zener diode is in 62. (d) This is a circuit diagram of log amplifier
conducting state, V2 = 0 V0 = – VT n Vi + C
then, V0 = 12 sin t
V01 = – VT n Vi1 + C
V01 = – VT n2 + C
and V02 = –VT n Vi2 + C
V02 = – VT n 4 + C
V01 – V02 = – VT n 2 + VT n 4
= VT n 2
63. (d) Given that
(VT)PMOS = (VT)NMOS = 1V
59. (d)
W W
K= 40 A / V 2
L PMOS L NMOS

VGS = 2.5V

From concept of virtual ground, the potential at 1 is

10 V.
Applying KCL at node 1,
0 10 dVC
C
1K dt
dVC
10 × 10–3 = 1 × 10–6
dt A
ID = K(VGS – VT)2 = 40 (2.5 1) 2
3 t 3
V2
10 10
VC = 6
dt = 10 10 × 1 × 10–3 = 10 V ID = 90 A
1 10 6
0 1 10
 33

g m1g m2 g m1g m2
gm =
64. (b) g m1 g m2 g
g m2 1 m1
g m2
But gm >> gm1
gm2 = gm1
2
Vo RF
68. (b)
Vi Ri
Assuming BJT is in active region, 1 R2
RF = R 2 ||
2 VBE 2 0.7 sC R 2 Cs 1
lE = RE 1k = 1.3 mA Ri = R1 + sL
Vo K
As B is large,
lE = lC = 1.3 mA Vi (R1 sL)(R 2 Cs 1)
Applying KVL in collector emitter loop, K
10 – 10lE – VCE – lC = 0 =
VCE = – 4.3 k f f
1 j 1 j
VBC = VBE – VCE = 0.7 – (– 4.3) = 5V f H' f H''
Since, VBC > 0.7V
Vo
Transistor in saturation. As = 0, it is a low pass filter..
Vi
0
1
65. (c) 69. (b) I= 10 A
100k
I0 = 1 A
VD
e 25 1
10 A = 1 A

VD = 60 mV
Voltage drop across 4K resistance
1 V1 = 4K × 10 A = 40 mV
VA = (1V) = 0.5 V (from voltage divider rule) Total voltage output = V1 + VD
1 1
Applying KCL at node B, = (40 + 60) mV = 0.1 volts
70. (b) In saturation region, drain current for M1
1 VB VB Vo C W 2
1k 2k ID1 = n ox (VGS1 VT ) I Bias and for M2,
2L
From virtual group concept,
n C ox W
VB = VA = 0.5 V I D2 (VGS2 VT ) 2
2L
1 0.5 0.5 Vo As VGS1 = VGS2 for this circuit and the two transis-
1k 2k tors are identical,
ID1 = ID2 = Ibias
1 = 0.5 – Vo
or, Ix = Ibias
Vo = – 0.5 V 71. (b) The output voltage
66. (c) When output is +15V, let voltage at non inverting
terminal is V0
V0 15 V0 15
2 0
10 10
V0 = +5 volts
When output is –15V
V0 15 V 15
2 0 0
10 10
V0 = – 5 volts
1 1 1
67. (c) gm g m1 g m2
M2 is always saturated due to bias but gm1
changes according to Vi
 34
The output Voltage 74. (b) Given, ID = K (VGS – VT)2
dlD
Transconductance gm =
dVGS
VDS constant
d 2
= dV K(VGS VT )
GS
= 2 K (VGS – VT)
75. (a) Voltage at 1 is in negative direction of Vi and it is
the maximum value of (–Vi, 1) because diode is in
reverse bias.
76. (b) The output voltage
h fe R C
V0 Vi
The capacitor is periodically charged and discharged h ie
RC
2 1 V0 Vi
between VCC and VCC . h ie
3 3
150 3 103
1 2 V0 Vi V0 150Vi
VC varies between 9 and 9 , i.e., between 3 3 103
3 3
and 6. V0 150(A cos 20t Bsin106 t)
72. (c) We know that 77. (a) The output amplitude
lD = K (VGS – VT)2 R4
The transconductance V0 = R R ( Vsat )
4 3
lD 1
gm = The output frequency f = 2R C
VGS 2

gm = 2K (VGS – VT) Hence, only frequency of V0 depends on R2.

Hence, gm varies linearly with VGS.
73. (c) In positive half cycle
78. (b)

Point A will be at zero volt, so 20 V source supply

current,
20
I=
R
Case 1 : i 0,
i will supply current
D1 and D2 will be in forward bias, so
D1 is forward bias
0=0
D2 is reverse bias Case 2 : – 5 i < 0,
(V0)maximum = 0.7 + 6.8 + 20 V source will supply current to both i source
= 7.5 V and circuit and diodes D1 and D2 will still in forward
In negative half cycle bias. So,
D2 is forward bias 0=0
D1 is Reverse bias Case 3 : i < – 5,
(V0) min. = VD2 = – 0.7 Volt 20
So i will sink current more than =I
Alternately R
During positive cycle, D1 is ON and D2 is OFF, So, D1 and D2 will be in reverse bias
V0 = VZ + VD 0 i
1
= 6.8 + 0.7 = 7.5V
During negative cycle,
D1 is OFF and D2 is ON So
V0 = – VD2 = – 0.7V
 35
79. (a) As V2 – V1 = V2 – V3
R2 and R3 in parallel,
Using KCL at mode (1), we have 83. (a)

0 vi 1 1
0 v0 0
R1 R2 R3

v0 R 2 || R 3
or, vi R1
80. (b) Let both transistors are in active region, therefore
voltage at Q1 base
(VBase)Q1 = 0.7 – 10 = – 9.3 V
Current through R,
For finding gain we have to make its equivalent
9.3V
IR = 1mA IC hybrid model
9.3k
1
Since emitter area of Q1 = [emitter area of Q2]
2
A Q2
i.e. AQ1 =
2
( 2)effective = 2 × 2 = 1430
Since effective of Q2 is double of Q1, so collector From this we can write
current also will be double nearly. V0 = lb (R || X L || XC || R L )
I0 = IC2 2 × IC1 2 mA
Vi
= (R || X L || X C || R L )
81. (c) lD1 lD2 h ie

W W V0 R || X L || X C || R L
K' (VGs1 V1 ) 2 K' (VGs2 VT ) 2 A= V re
L 1 L 2
i
Let R || XL || XC || RL = r
1
K’ = ox Cox which is same for both MOS 1 1 1 1
2 Then Z j C
4[(5 – Vx) – 1]2 = 1[Vx – 1]2 R j L RL
2[4 – Vx] = ± [Vx – 1]
1
Vx = 3,7 Z= 1 1 j
j C
R RL L

1
=
1 1 1
j C
R RL L
Value of Z is maximum when
1
C=
L
1 1 1
Here, 7 is not possible because VCC = 6V = LC 6 9 10 7
10 10 1 10
Hence, Vx = 3V
= 107 rad/s
82. (d) When = 0; inductor acts as a short circuit so,
means of = 10 M rad/s value of Z is maximum.
V0 = 0
Hence, at this value of
When = , inductor acts as open circuit
V0 = i1R1 Z
|A| = is also maximum.
So, it acts as a high pass filter. re
 36

89. (b) VCC

R2
84. (b) V0(s) = – Vi (s)
1
R1
CS
R 2 CS
V0(s) = – Vi (s) X
(R1CS 1) Z
1
Thus cut-off frequency is R C and filter in high
1 X Q1
pass filter.
85. (d)
86. (d) Using KVL around the loop, we get
10 – 1000i – V = 0 ...(1)
V 0.7
Given i =
500 Y
or, V = 500i + 0.7 ...(2)
Putting equation (2) in equation (1), we have Z X Y
10 – 1000i – (500i + 0.7) = 0
90. (c)
10 0.7
or, i= 6.2 10 3 A = 6.2mA
1500
87. (d) For the given signal model of transistor,
VCC = 3 V
IC
gm = V , VT = 25 mV at 300 K IC = 1mA
T 60 k = R1
= gmr
As IC = IE
VT VT
or r = VB Q Since B
gm IC Ib IB = 0
DC value of Ib = 1mA
3 R2
25 10
then, r = 3
25 RE = 500
1 10
88. (c)

1k 1k
–2V +15V
+15V
– VB = VBE + REIE = VBE + REIC
1 + VB = 0.7 + 1 × 10–3 × 500 = 1.2
+ 2 Vout
– R2
1k –15V VB = 1.2v = 3
–15V 60k R 2
1.2 (60 + R2) = 3R2
+1V 1k
1k 1.2 60
R2 40k
1.8
91. (b) Is = Iz + IL
Is – I z = I L
Two extreme condition:
1 1 1 If Iz (min), then IL (max)
Vout 1V 1 2 1 If Iz (max), then IL (min) = 0
1 1 1
10 5
Iz (max) = Is = = 50 mA
10
Gain of Gain of Gain of Iz (min) = Is – IL (max)
non- non- non-
inverting inverting inverting IL (max) = Is – Iz (min) =Is – Iz = (50 – 10) = 40 mA
aplifier aplifier aplifier V 5
R L min 103 125
= [1 × 2 + 2] × 2 V = 8V I L max 40
 37

92. (b) VG VD VGS VDS Divide (2) by (1)

So, VGS Vt VDS ID ( 1.2) 2

=
NMOS is in Saturation region 0.5 ( 0.8)2
93. (a) lower cutoff frequency,
I D = 1.125 mA
1 97. (b)
0 ( Req = R0 + R1)
C Req 98. (d)
99. (d) Only (d) option is possible for which both the diodes
1 D1 and D2 are forward biased.
f0
2 C RD RL
100. (b)
1
f0 6
COMMON DATA MCQs
2 10 20 10 –3
101. (b) Drawing small signal model for the given circuit.
x 7.97 8Hz
94. (b) Using the concept of “virtual ground” in an operational
amplifier, we can set the voltage at the point to zero
volts since the non inverting terminal (+ ve) is
grounded.
Once VA = 0, VC will also be zero.
We know that for a silicon n–p–n transitor,
VBE = VB –VE = 0.7V Fig (A)
Zi = 2 m
Since, VB = 0
Zo = RL ||rd = 20 k || 2 k
VE = –0.7 V
Hence the output voltage is the same as the emitter (20k )(2k ) 20
= k
voltage 22k 11
So, Vout = –0.7 V 102. (a) Under DC conditions, capacitors gets open circuited
vout 0 VGS = – 2 volts
95. (c) I1 VP = – 8 volts
R2
96. (c) VDS = VDG + VGS
Here VS = 0 & VGD = 0
VD = VG

VDD

R
D

G S

2
VGS
ID = IDSS 1
VT
N-channel MOSFET requires zero or negative gate
2 bias and +ve drain voltage for to operate in active
VD region.
ID = IDSS 1
0.8 Now, drain current
2
1.6
2 VGS
0.5 = IDSS 1 ...(1) ID = IDSS 1
0.8 VP

2 2
2 2
I D = IDSS 1 ...(2) ID = 10 × 10–3 1 = 5.625 mA
0.8 8
 38
103. (b) Transconductance 107. (b) The low frequency model
25mV
VGS re =
gm = gm0 1 ...(A) 1C = 2.59
VP
The resistance seen by the source VS
Drain to source current Zin = RS + (RB || re)
2
VGS RB re
IDS = IDSS 1 ...(B) = RS +
VP RB re

IDS 2I DSS VGS 2IDSS IDS 93 103 100 2.59

1 = 103 +
gm = VGS VP VP VP IDSS 93 103 (100 2.59)
103 + 258 1258
2 IDSS ·I DS 108. (b) The lower cut-off frequency
gm = 1
VP
fL = 2 (R R C )C2
L
2 IDSS .IDS 3 3 1
gm = 10 10 5.625 10
| VP | 8 = 3
2 (10 250)(4.7 10 6 )
= 1.875 ms
1
From figure (A), = 6 = 27.1 Hz
2 1250 4.7 10
Vi R L g m rd Vi R L
V0 = R LINKED ANSWER TYPE MCQs
L rd R L rd

Vo g m rd R L 3 20 109. (c)
1.875 10 103 3.41
Vi R L rd 11
104. (c) Under DC condition, the circuit becomes

Voltage across 24k resistor = V2 = 6V

V0 24
then, V2 = 6 = Vout = 9 volts
12 24
V0
Applying KVL in collector-emitter circuit, and IC = 900.25mA
(12k 24k) ||10
12 – 1k (lC + lB) – VCE = 0 ...(i)
Using KVL in transistor circuit, we have
and in base loop, Vin – VCE – V0 = 0
VCC – 1k (lC + lB) – 5lB – VBE = 0 ...(ii) VCE = Vin – V0 = 15 – 9 = 6 volts
IC = l B …(iii) Power discipation across transistor Q1
Solving Eqs. (i), (ii) and (iii), we get = VCEIC = 9 × 900.25 × 10–3 = 5.4 watts
VCE = 5.95 V. 110. (b) If unregulated voltage Vin increased by 20%, then
105. (b) As given increased by 10%. V’in = 15 ×1.2 = 18 volts
10 As output voltage is regulated, therefore it remains
Now = 60 + 60 × = 66 same.
100
Then, VCE = V’in – V0 = 18 – 9 = 9 volts
Calculating VCE for = 66 as in previous question for Further collectors current also remains unchanged.
= 60. Then, power discipation across Q1 is
VCE = 5.69 V = VCE × IC = 9 × 900.25 mn = 8.1 watts
5.69 5.95 Hence, % change in power discipation
% change = 100 = – 4.37%
5.95 8.1 5.4
106. (a) = × 100 = 50%
5.4
 39
114. (d) The small signal model
1
Vi (s)
111. (a) V+(s) = sC
1
R
sC
Vi (s)
V+(s) = ...(1)
1 sRC
For Op-amp, V+ V–
KCL at node V–
V0 V V Vi | IC | IE 1mA 1 A
R1 R1 gm = V VT 25mV 25 V
T
2V– = V0 + Vi
1
2Vi (s) V0 = – gm Vin (3 k || 3k) = – Vin 1.5k
Vi (s) V0 (s) ..... ( V– V+) 25
1 sRC
V0
2 sRC 1 Vo (s) Vo (s) 1 sRC AV = V = – 60
sRC 1 Vi (s) Vi (s) 1 sRC in

112. (c) Given, Vi = V1 sin t and V0 = V2 sin ( t + ) 115 & 116. Assuming both transistors in saturation, then,
Drain current
Vo (s) 1 sRC
T(s) = V (s) 1 sRC n C0 W 12
i ID1 VGS1 VTn (1.5 1)2
=
2L 2
= T(s) = – 2 tan–1 (sRC)
This phase is added by the system to the input = 0.125 mA [Assuming VUS1= 1.5 V]
signal (substitute s = j ) p C0 W 2 1
and I D2 VGS2 VTP = (3 5 1)2
1 2L 2
When , =–2 lim tan RC =– = 0.50 mA
Since the gate currents being zero, the drain currents
min = – have to be equal to satisfy KCL. Further saturation
When 0, = lim0 – 2 tan–1 ( RC) currents are not equal both the MOSFET’s, both
= –2 × (0) = 0 can’t be in saturation simultaneously. Thus NMOS
which has saturation current of 0.125 mA, can never
max = 0
Hence = – to 0 carry 0.50 mA. Hence PMOS is not in saturation.
113. (a) For DC analysis all capacitors become open circuited. Now, assume that NMOS is in saturation and PMOJ
The venin equivalent of circuit. is in triode then,
ID1 0.125mA

p C0 W 1
= I D2 VGS2 VTP VDS2 VDS2
L 2

VD 5
0.125 = 1 3 5 1 (VD 5)
2
VD 5
0.125 = 1 (VD 5)
2
10 VD2 8VD 15
When, VTh = × 9V 0.25 = (– VD + 3) (VD – 5) =
10 20
(from voltage divider rule) 1
= 3V VD2 8VD 15 0
4
10 20
and RTh = 6.67k 61
10 20 VD2 8VD 0 ...(A)
As is very large, IB can be ignored. 4
Applying KVL in base emitter loop, Solution of this quadratic equation (A) is given by
VTh – VBE = IERE
61
V VBE 8 64 4 3
IE = Th = 1 mA 4 = 4 volts
RE VD 2
2
 40

3 Vo RC
For VD 4 118. (a) Av
2 Vs re
PMOS will be in saturation as
26mV
VDS VD 5 re
VDS VGC VTP IE
VGS 3 5 2
IC 1.3
3 IE IC 1.3 1.313mA
Hence, VD = 4 which will cause PMOS to put 100
2
26
in triode region as VDS VGC VT re 19.80
1.313
115. (d)
116. (d) 2000
Av 101
NUMERICAL ANSWER QUESTIONS 19.80
RC 2000
117. (a) V1 (b) Av
RE 500
=–4
(c)
V0 A v Vs
= – 101 × 0.01 sin ( t)
= – 1.01 sin ( t) V
119. (a) Time constant associated with CB, is 1 = RCB where R
t
= hib | | R2 and hib = input impedance of circuit
Time constant associated with Cs, t2 = C2 (RS + hib)
(a) Sinusoidal input
(b) Approximate lower cut-off frequency of the amplifier,
VD 1
FLC
2 Rs h ib CS

120.
C ZO –
RS VCC
t + +
(b) Output with C B
E
VD +
VS
V1
–
Z1 RL VO

–
t
(c) Output without C Its small-signal equivalent depicted in the following circuit:
(a)

RS B Lic ie
E
(b) +
+ ib + iL

+ +
VS Vbc LrcVCC hic ib Loc Vec RL VL
– –

– – –
C
Zo
Zin
 41
(b) From the above circuit,
Vbc i b hic h rc Vec ...(i) Q E IE
121. + – –
ie h oc Vec h fc i v ...(ii)
R
ie h oc R L ie h fci b +
–
A B
ie 1 h oc RL h fc i b VS +
– + VO
h fci b –
ie ...(iii)
1 h oc R L

From equation (i), Vbc i b h ic h rc R Lie

h rc R L i b (a) For transistor Q, its emitter-base voltage and emitter

= i b h ic current is related by,
1 h OC R L
VBE
Vbc h rc R L h fc VT ...(i)
= Zi h ic IE Is e
ib 1 h oc R L
where Is = reverse saturation current
Ie Vs 0
(c) Y0 [Output admittance] IE
V0 Also, KCL at node A,
R

h fei b h oc V0 VBE
= [Setting the load RL to ]. Vs VT
V0 Is e
R
h fei b
= V h oc ...(iv) Vs
ec IE
R
Setting the source voltage zero.
Putting this in equation (i), we get
R s ib h rc Vec h icib 0
VBE
= R s ib h rc Vec h icib 0 Vs VT
Is e
R
ib h
Vec h ic R s VBE
VT Vs
e
h fc h rc Is R
From equations (iv), Y0 h oc
hic R s Taking logrithm both sides, we have
Vs
1 1 v BE VT In
Z0 Is R
Y0 h fc h rc
h oc
h ic R s
Vs IR
V0 VT In VT In s
RL Is R Vs
(d) ZL
R L j CL 1 (b) From part (a), we have
From equation (ii), substituting ZL for RL, we get IR
V0 VT In s
h rc R L h fc Vs
Zi hic
R L j CL 1 h oc R L
12
10 1
= 25 10 3 In
1 1
Z0
h fc h rc = – 300 × 10–3 V
h oc output impedance unaffected
h ic R s = – 0.3 volt
 42

VD VD
Using KVL, Vi – 5 = 0.5 I + (I – I1)
VT VT = 1.5 I – I1 ...(i)
ID Is e 1 Is e and – 1.5 I1 + 5 + (I – I1) = 0
(c) As,
or 5 + I = 2.5 I1 ...(ii)
From (i) and (ii)
1.5 Vi 25
V0 1.5I1
2.75
when, V0 reaches 7 volt,
Vi = 10.33 volts
For V0 > 7 volt, both diode conducts and V0 = 7 volts.
(b)

12 Vi
V0 VD 0
10.33
Vs
Also, i D .
R
Then from equation (i), we have
VD 3
Vs VT
Vo
Is e t
R 0
Vs
VD / VT
e Is R Output waveform superimposed on the input Vi(t) shown
below.
Vs 123. 3.18 k
Thus, V0 VT In
Is R
Is R
R2
= VT In
Vs

C
122. (a) Let, diode D1 and D2 are off and the circuit will be as
shown.
10nF
+ + 1k
Vi – V0
R1 +
1k 1.5 k Vo(t)
Vi(t)
+
+
7v 5v
– –
– –
1
Let RF = R2 ||
5 sC
Vo (1.5) 3v
2.5
1
When Vi > 5 V, upper diode conducts and circuit will R2
be as, RF sC
1
R2
0.5 k sC
+ +
R2
RF
I I1 1 sCR2
I – I1 1k 1.5 k
Vi(t) Vo(t)
+ R2
+
7v RF 1 sCR2
5v Av H ( s)
– – R1 R1
– –
 43

R1 R2
H(s) =
1 2 fCR2
RC
1 V0
Here fc =
2 CR2

1
5 × 103 = 9
2 10 10 R2
RB VEE = 10
1
R2 =
2 5 103 10 8

10 –10 + VEB + RB IB = 0
R2 = 103 3.18k
–10 – VBE + RB IB = 0
124. 1093 –10 + 0.7 + RB IB = 0
VA = VB = 4.7V = VR RB IB = 9.3
100 IB = 9.3
V1 = 12V V0 = 9V IB = 0.093 mA
IC = IB = 4.65 mA
5 – 0 = RCIC
1k 1k 5 = RC (4.65 mA)
+ RC = 1.075 k
A – 129. 0.08 to 0.12
B
130. 0.24 to 0.26
Vz = 4.7V R 131. 0.07 A / V
Under Linear Region
W
ID = x cox [(VGS VT )VDS ]
R 9 L
VR = (By voltage divider rule)
R 1000 ID
= KVDS
9R VGS
4.7 = –3
R 1000 10 = K × 0.1
–2
4700 + 4.7R = 9R K = 10
4700 = 4.3R Under Saturation Region
4700 1 2
R= = 1093 ID = K [VGS VT ]
4.3 2
vout = I1R2 1
125. –235 ID = K [VGS VT ]
126. 35 2
127. 0.9mA ID
VGS = VG – VS = 0 – (– 5) 1 1 2
= K 10 0.07 A / V
VGS = 5v VGS 2 2
ID = K (VGS – Vt)2 132. 2.3 to 2.5
ID = 0.1 (5 – 2)2 133. 1.4 to 1.6
ID = 0.9mA 134. 0.49 to 0.51
135. 9.39 to 9.41
128. 1.075 k