CS302LecturewiseQuestions PDF

CS302 Lecture Wise Questions By Virtualians.
pk
Q)How to count Result of binary encoding?
Like
+024 00011000
or
-015 10001111
Answer:
Binary of 024 is: 00011000
2’s complement arithmetic is commonly used in computers to handle negative numbers.
For example, we want to represent decimal number -015 in 2's complement form.
First, write the binary of +015
00001111
Now, take its 1's complement (by inverting the bits)
11110000
Finally, the 2's complement (by adding 1 to its 1's complement)
11110001
So, decimal -015 = 11110001 2's complement
•
Q) Rule for Octal Addition?
In Octal addition, same rules are followed as used in decimal or binary addition. The only
difference is if the sum exceeds the octal range (0 to 7), then subtract 8 from the sum until the
result is reached to one of the octal digits from 0 to 7. The carry 1 is generated for the left most
significant digits.
Example: The addition between two octal numbers (8 A 5 C) 16 and (F 3 9 A) 16
Carry 1 1
4 5 6
1 2 3
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CS302 Lecture Wise Questions By Virtualians.pk
6 0 1
(As 6 + 3 = 9, so 9 – 8 = 1. We write 1 in answer and carry 1 to the left most significant bit. And
so on)
The resulting octal number is (601) 8

The term mapping is used in K-Maps. It means to fill the K-Map with either 1 or 0 on the basis
of minterms or maxterms present in the function.
Q)How Hexadecimal addition is done?
Hexadecimal addition can be achieved through repeated subtraction of 16 from the decimal sum
of same place values of hex numbers until the result is reached to one of the hex digits from 0 to
F. The carry increases by 1 where each time the number 16 is subtracted from the hex numbers
decimal sum.
The below example lets you understand how to perform hex numbers addition
Example: The addition between two hex numbers (8 A 5 C) 16 and (F 3 9 A) 16
Carry 1 0 0 1
8 A 5 C
F 3 9 A
1 7 D F 6

(As C + A = 22, so 22 – 16 = 6. We write 6 in answer and carry 1 to the left most significant bit.
And so on)
The resulting hexadecimal number is (17DF6) 16
In hexadecimal subtraction, borrow is 16 (as borrow is 10 in decimal number system) if the first
number is smaller than the second number.
Borrow 1 1 1
9 2 B 5
2 A C 6
6 7 E F
(As 5 is smaller than 6. So it will take borrow (16) from the left. So it will become 5 + 16 = 21.
Now, 21 – 6 = 15. And so on)
The resulting hexadecimal number is (67EF) 16
Q) What is Flip flop?

Flip flop is the storage element in sequential circuits. It has two stable states and a feedback path
that allows it to store a bit of information. A flip-flop only changes state when a control signal
goes from high to low or low to high. There are many types of flip-flops like SR Flip-flop, JK
Flip-flop, D Flip-flop, etc.
Q) What is Parity Generator?
Parity Generator is a circuit that generates parity bit both in Even and Odd parity modes. The
function table of odd-parity generator circuit shows the Parity bit set to 1 in P column of table
14.1 ,when the 16, 4-bit data input combinations have even number of 1s and when data input
combinations have old number of 1s then it will be 0 in P column.
Q) What is BCD and its use?
Binary Coded Decimal (BCD) code is a 4-bit code and is used to represent decimal digits 0 to 9
in binary. Only 1st ten binary values are used to represent decimal values from 0 (0000) to 9
(1001). The remaining six 4-bit combinations 1010, 1011, 1100, 1101, 1110 and 1111 are
considered to be invalid and do not exist.
To represent decimal number in BCD, we write BCD codes of individual digits.

Forexample,
BCD code for 216 is 0010 0001 0110
BCD code for 23 is 0010 0011
Q)What is BCD Adder Circuit ?
In Binary Coded Decimal (BCD), the adder is actually working in hex, 0xA shows the
hexadecimal number. If the addition of two BCDdigits results in an invalid result, the result must
be between 0xA (1010) and 0xF (1111).
By adding 6 to this value and generating a carry, you generate the proper BCD values:
0xA + 0x6 = 0x10
(the BCD value 10)
0xB + 0x6 = 0x11 (the BCD value 11) etc.
So by adding 6 we use the hardware BCD adder circuit of the computer which is designed for
counting in binary to skip over the binary values we won't need because we want to represent
digits in BCD.
In table 15.1 shows if the circuit finds the result of the first Adder circuit to be a valid BCD
number (between 0 and 9 and no Carry has been generated), the circuit adds a zero to the valid
BCD result using the second Adder. The output of the second Adder gives the same result.
Q) What is Standard form of Product terms?
The Product terms in the Standard SOP (Sum OF Product) form are known as Minterms and the
Sum terms in the Standard POS (Product OF Sum) form are known as Maxterms.
1 or 0 are placed according to minterm and maxterm term expression.
Please firstly see the table 9.5 then you will understand A represents in minterm is 1 and in
maxterm is 0 and A’ represents in minterm is 0 and in maxterm is 1.e.g
The Standard SOP (Minterm) expression having a Domain of three variables

ABC’ + AB’C’ + A’BC’ is mapped into 3-Variable Karnaugh Map.
A\BC 00 01 11 10
0 0 0 0 1
1 1 0 0 1
You can see ABC’ in binary (110), this number check in table and put 1 in second row and last
column. Same like in second expression AB’C’, put 1 in (100) means second row and first
column. Lastly check third expression A’BC’, put 1 in (010) means first row and last column.

Q) What is GAL and its Use?
GAL is one of type of Programmable Logic Devices and it is also available in a variety of
configurations. Like GAL16V8 firstly you can elaborate these 4 terms in wording for better
understanding.
GALs are identified by a prefix Generic array Logic followed by a 2-digit number indicating the
number of inputs (that is Sixteen Inputs) which is followed by V indicating variable output
configuration followed by a number which indicates the number of outputs(that is Eight
Outputs).
What is Logic Function Generator?
A multiplexer can work as a logic function generator. The purpose it serves is that it can generate
expression of a function, against the values mentioned in the output of a truth table. Actually on
the basis of truth table we connect the different combinations of data select inputs to either 0 or
1. Those combinations at which the output is 1 in the truth table are connected to 1, whereas all
other combinations are connected to 0. We apply all the input combinations of data select inputs,
and final output is generated to 1 or 0 depending on the input combination applied. In this way
we can get the function in SOP form.
Lecture no 1
Digital representing of quantities

Digital quantities unlike Analogue quantities are not continuous but represent quantities
measured at discrete intervals.
Q)What are the differences between digital and analog circuits?
Analog circuits operate on a continuous range of voltages. For example, an audio signal may range anywhere
from 0V to 1000mV, and an infinite number of places between.

Digital circuits operate on only one of two states: "off" or "on", typically represented as 0 and 1. These on and
off states are represented by different voltages in different systems. But any given digital signal will have one
of only two distinct values. For example, a typical digital signal will dictate that anything below 1.0V is
considered "off", and anything above 4.5V is considered "on".

Information in digital circuits is represented as either a consecutive stream of these on and off states ("serial")
(ex: 10010110) or a set of signals together representing a value ("Parallel") where 8 wires represent 8 bits of a
one byte value.
Q) Difference between CMOS and TTL?
TTL stands for Transistor-Transistor Logic. It is a classification of integrated circuits. The name is
derived from the use of two Bipolar Junction Transistors or BJTs in the design of each logic gate.
CMOS (Complementary Metal Oxide Semiconductor) is also another classification of ICs that uses
Field Effect Transistors in the design.
The primary advantage of CMOS chips to TTL chips is in the greater density of logic gates within the
same material. A single logic gate in a CMOS chip can consist of as little as two FETs while a logic
gate in a TTL chip can consist of a substantial number of parts as extra components like resistors are
needed.
TTL chips tend to consume a lot more power compared to CMOS chips especially at rest. The power
consumption of a CMOS chip can vary depending on a few factors.
One major factor in the power consumption of a CMOS circuit is the clock rate, with higher values
resulting to higher power consumption. Typically, a single gate in a CMOS chip can consume around
10nW while an equivalent gate on a TTL chip can consume around 10mW of power. That is such a
huge margin, which is why CMOS is the preferred chip in mobile devices where power is
supplied by a limited source like a battery.
CMOS chips are a bit more delicate compared to TTL chips when it comes to handling as it is quite
susceptible to electrostatic discharge. People often unwittingly damage their CMOS chips from simply
touching the terminals as the amount of static electricity needed to damage CMOS chips are too
minute for people to notice.

The prominence of CMOS chips has pushed TTL chips to the background. Instead of being the
primary IC of choice, it is now used as components that link the whole circuit as ‘glue logic’. CMOS
chips that emulate the TTL logic has also gained prominence and is slowly replacing most TTL chips.
These chips have similar name to their TTL equivalent so that users can easily identify them.
1. TTL circuits utilize BJTs while CMOS circuits utilize FETs.
2. CMOS allows a much higher density of logic functions in a single chip compared to TTL.
3. TTL circuits consumes more power compared to CMOS circuits at rest.
4. CMOS chips are a lot more susceptible to static discharge compared to TTL chips.
5. There are CMOS chips that have TTL logic and are meant as replacements for TTL chips.
Q) What is the use of caveman?
Caveman number system is just a method of representing numbers like some other methods e.g
hexadecimal or octal, it has no connection with our daily life.
Q) what do u meant by Sequential circuits ?
Sequential circuit one type of digital circuits which has memory element in it.
Q) What is difference between digital system and values?

Digital systems are those system which measure are give outputs in only two digits, 1 or 0. where as
digital values are 1 and 0.
Q) What is radix ?
Every number system is represented by a base value, for example decimal number system is base 10
system, hexadecimal system is base 16 system and this base is called radix.
Q) Decimal to binary conversion using sum of weights?
Suppose we want to convert decimal number 392 into its equivalent binary, follow the following steps
Step 1: Draw a 4 column table
Step 2: Write multiples of 2 starting from 1 from bottom to top in “weight” column
Step 3: write decimal number 392 in “Number” column
Step 4: Now see whether 392 is greater or equal to 256? If so, place 1 in “Binary” column and if it is
less place zero in “Binary” column
Step 5: Subtract number from its respective weight and write the result in next row and repeat the
procedure again until weight 1 is reached

Step 6: write the binary digits from top to bottom
So binary number for decimal 392 is 110001000
Lecture no 2
.Q)Sum-of-non-zero terms?
In the Sum-of-Weights method, the Binary bits 0 do not contribute towards the final
sum representing the decimal equivalent. Secondly, the weight of each binary bit increases by
a factor of 2 starting with a weight of 1 for the least significant bit. For example, the Binary
number 101102 has weights 20=1, 21=2, 22=4, 23=8 and 24=16 corresponding to the bits 0, 1,
1, 0 and 1 respectively.
Q)Explain it please how 2 power 0 =1?
A quicker method is to add the weights of non-zero terms. Thus for the numbers
o 100112 = 16 + 2 + 1 = 19
o 1011.1012 = 8 + 2 + 1 + ½ + 1/8 = 11 + 5/8 = 11.625
Q)Signed and Unsigned Binary Numbers
Digital systems not only handle positive numbers but both positive and negative
numbers. In the decimal number system positive numbers are identified by the + sign and
negative numbers are represented by the – sign.

In a digital system which uses the Binary number system, the positive and
negative signs can not be represented as + and -.
As mentioned in the Overview all forms

of numbers, text, punctuation marks etc. are represented in the form of 1s and 0s. Thus
the positive and negative signs are also presented in terms of binary 0 and 1.
To handle positive and negative binary numbers, the digital system sets aside the
most significant digit (bit) to represent the sign
• MSB set to 1 indicates a negative number

• MSB set to 0 indicates a positive number
Thus +13 and -13 are represented as 01101and 11101 respectively. The bits 1101
represent the number 13 and the MSBs 0 and 1 represent positive and negative signs
respectively. Thus binary numbers having the MSB signifying the Sign bit are treated as
Signed Binary Numbers. This representation is known as the Signed-Magnitude
representation.
Digital systems also handle binary numbers which are assumed to be positive and therefore do not
have the most significant sign bit. Such numbers are known as signed and unsigned. Thus 111012 represent -13
in signed binary and 29 in unsigned binary.
A digital system on its own cannot decide how to handle a binary number. The digital system has to
be notified beforehand to deal with a certain
binary representation as signed or unsigned.
Q)Range of Signed and Unsigned Binary numbers?
The maximum range of values that can be represented in any number system depends upon the
number of digits assigned to represent the value. A 5-digit car odometer can only count up to 99,999
and then it rolls back to 00000. Similarly an 8-digit
calculator can only handle integer numbers of the magnitude 99,999,999. A calculator that reserves
the most significant digit to write + or – can only handle a maximum range of integer numbers from -
9,999,999 to +9,999,999.

A 3-bit unsigned binary number can have values ranging between 000 and 111.Adding 100 and 111
unsigned numbers results in 1011, this result is considered to be out of range as 4 bits are required.
Similarly a 4-bit sign magnitude number can handle a
number range between -7 and +7. -8 can not be represented as 5-bits are required 11000.A 4-bit 2’s
complement based signed number range is between -8 to +7.
Q)What is ?
Binary Addition?
Addition between two binary numbers and it is also called asBinary Addition.
Binary numbers are the numeric codes to represent the numbers. The numeric codes are group of bits
0s and 1s 0 and 1 which are weighted by the specific values based on their places. In digital circuits,
binary arithmetic operations are important because the digital circuits do not process decimal
numbers; only works based on the binary numbers. The below binary addition logic is used in this
binary addition calculator to perform the addition between binary numbers. The equivalent decimal
addition also done by this binary adder for verification of the results
Binary Addition Logic
0 + 0 = 0
1 + 0 = 1
0 + 1 = 1
1 + 1 = 10
1 + 1 + 1 = 11

Binary Subtraction:
Key Subtraction Results for Binary Numbers
1 – 0 = 1
10 – 1 = 1
11 – 1 = 10
When you add and subtract binary numbers you will need to be careful when 'carrying' or
'borrowing' as these will take place more often.


Binary Multiplication:

Q)What is the 1's and 2's complement?
A two's-complement system or two's-complement arithmetic is a system in which negative numbers

are represented by the two's complement of the absolute value; this system is the most common
method of representing signed integers on computers.
There are two steps of taking 2’s complement of a number.
i- Take 1’s complement of the number, that is, change 0 to 1 and 1 to 0.

ii- Add 1 into the 1’s complement calculated above.
For example:
The number is 01101

1’s complement 10010
Add 1 + 1
10011
So 10011 is the 2’s complement of 01101.
Q)What are PLD devices?
A programmable logic device or PLD is an electronic component used to build reconfigurable digital
circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time
of manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured.
Q) How PLDs are programmed?

PLD can be programmed using Hardware Descriptive Languages (HDLs) languages like ABEL,
Verilog, VHDL.
Q) what does mean by complement of binary number and what is difference between
complement of 1 and 2?
Complement here means inverting the bits, that is, change 0 to 1 and 1 to 0.
Complement and 1’s complement is the same thing.
For example, we want to take the complement of binary number 10010110
10010110 (original number)

01101001 (1’s complement)
The 2’s complement of a binary number is obtained by adding ‘1’ to its 1’s complement.
10010110 (original number)

+ 1 (Adding 1)
---------------------------------
2’s complement arithmetic is commonly used in computers to handle negative numbers.
For example, we want to represent decimal number -39 in 2's complement form.
First, write the binary of +39

00100111

Now, take its 1's complement (by inverting the bits)

11011000
Finally, the 2's complement (by adding 1 to its 1's complement)

11011001
So, decimal -39 = 11011001 2's complement
Q)Is BCD a positional code?
BCD code is used to represent decimal digits in binary. BCD code is a 4-bit code, each digit is
represented by 4-bits binary code. The first 10 combinations represent the decimal digits 0-9, the
remaining 6 combinations are considered to be invalid BCD code. BCD is a positional number system
where BCD code for each digit has some weights such as BCD code 1001 has weights 8, 4, 2, 1 which
can be converted as 1×8 + 0 ×4 + 0 × 2 + 1 × 1 = 9
The BCD code for 28 will be 00101000. The first four bits represents 4-bit binary code of 2 whereas
remaining 4 bits represents binary code of 8
Q) Can we directly Convert octal numbers into Hexadecimal?
Octal number can be converted into Hexadecimal by first converting into Binary number and then
from Binary to Hexadecimal.

Octal Number: 7564
Each digit of Octal number can be represented by 3 bits. Now replacing each digit with 3 bits
7564 = 111101110100
The above binary number can be converted into Hexadecimal by grouping into small groups of 4 bits
each starting from lease significant bit
1111 0111 0100 = F74 (Hexadecimal)
Q) What is meant by signed nd unsigned Binry Numbers?
Signed Numbers: The numbers which can handle both positive and negative numbers are known as
signed numbers. The MSB (Most Significant Bit) of such numbers is used to represent the sign of
number. If MSB is set to logic 1 then numbers is treated as negative numbers and if MSB is set to
logic 0 then number is treated as positive number.
For example, +10 and -10 can be represented in signed numbers as 01010 (+10 in deciaml) and 11010

(-10 in decimal). 1010 indicates binary representation of decimal 10 whereas 0(MSB) and 1(MSB) in
both numbers indicate the sign of numbers.
Unsigned Numbers: The numbers which can handle only positive numbers and do not have most
significant bit as a sign bit are known as unsigned numbers.
Q) What is troubleshooting?
Troubleshooting is the process of identification or diagnosis of problems in the system. It first

determines the cause of problems in the system and then applies problem solving to repair failed
system. It is needed to keep the system in working condition whenever a problem occurs in the
system.
Q) What does MSB Stnd for?
MSB stands for Most Significant Bit which is left most bit.
101001012
In the above binary number, the highlighted bit is MSB (Most Significant Bit).
Q) Why we use the fixed point technique?
Fixed point representation is used for representing fractional value for the processor that does not
support FPU (Floating Point Unit). It provides a simple way for representing fractional values using
fixed number of bits. In fixed point number representation, there is fixed number of bits to the right of
decimal point and fixed number of bits to the left of decimal point. The bits to the right of decimal
point are called fraction part whereas bits to the left of decimal point are called integer part.

The fixed point can represent limited range of values whereas floating point numbers may increase
the range of values.
Q) What is the precise definition of "weight" in number system?
In positional number system, each digit has some weight according to its postion. The left most digit
has the highest weight whereas right most digit has lowest weight. The weight can be represented as
base raise to power positon of digit. The decimal system is a base 10 number system.
In the decimal value 560, the digit 0 has position 0 and has weight 100, the digit 6 has position 1 and
has weight 101, the digit 5 has position 2 and has weight 102
560 = 5×102 + 6×101 + 0×100 = 560
Q) What is Logic gates?
Logic gates are the basic building block of digital systems. Digital circuits are made from the
combination of logic gates which performs Boolean logic operation such as AND, OR and NOT
operations. AND gate performs logical multiplication operation, OR gate performs addition operation
whereas NOT gate performs inversion operation.
Q) What is PLD ?
PLDs (Programmable logic device): It is used in many applications to replace the logic gates and MSI
chips. The PLDs are used to save the circuit space by reducing logic gates and reduce the cost of
components in logic circuits. It provides general purpose hardware which can be programmed by end
user. The logic gates such as AND, OR and XOR gates provides a pre-defined functions whereas
PLDs do not provide pre-defined function at manufacturer time. It can be programmed using array of
AND gate and array of OR gate. It consists of array of AND and OR gate that can be used to
implement any kind of sequential and combinational circuit. PLDs consist of array of AND gate
followed by array of OR gate.

Q) Negative representation of 2's compliment:?
In two’s complement, positive integers are represented in standard binary, as in signed magnitude.
However, the representation of a negative number is determined as follows: (1) compute a binary
representation of the magnitude of the number, (2) ﬂip all the bits, and (3) add 1. For example,
the 8-bit two’s complement representation of 13 is 00001101 (as before) while −13 is represented
as follows (using the steps given above):
−13
(1)
=⇒ 00001101
(2)
=⇒ 11110010
(3)
=⇒ 11110011
the Process for -5:

Binary number for decimal 5 is :0101
same for 5 and -5 like for +5 its value is 0101
then converting in -5 it will take 1010( all 1s are replaced by 0s and 0s with 1s)
and then in to 1011(1is inserted/added at the end of binary number)
Q)Binary to Decimal Conversion:
Most real world quantities are represented in Decimal Number System. Digital Systems Onon the
other hand are based on the Binary Number System. Therefore, when converting from the Digital

Domain to the real-world, Binary numbers have to be represented in terms of their Decimal
equivalents
The method used to convert from Binary to Decimal is the Sum-of-Weights method.The
Sum-of-Weights method has been used to represent the Caveman numbers some
symbols and the Binary numbers 10011 and 1011.101
Q)What Is Sum Of Weights Method?
Sum-of-Weights Method
Sum-of-weights as the name indicates sums the weights of the Binary Digits (bits) of aBinary Number
which is to be represented in Decimal. The Sum-of-Weights method can beused to convert a Binary
number of any magnitude to its equivalent Decimal representation.
In the Sum-of-Weights method an extended expression is written in terms of the Binary

Base Number 2 and the weights of the Binary number to be converted.
The weights correspond to each of the binary bits which are multiplied by the corresponding binary
value.Binary bits having the value 0 do not contribute any value towards the final sum expression.

Q)How we have to find highest weight?

The Highest weight in decimal fractions can be found in the same way as described for decimal
(integer) to binary conversion.
The only difference is that we check for –ve powers of 2 (2-1, 2-2, 2-3,….) to find the highest weight.
This is because of the reason that powers of 2 become –ve towards right of the decimal point (2-1, 2-2,
2-3…).
For example,
Sum term = Sum

Term – Highest
Sum Term Highest Weight Binary Number Weight
0.625 0.500 0.100 0.125
0.125 0.125 0.101 0
Here, 2-1 = ½ = 0.5 is highest weight which is below 0.625. So, Binary number will be 0.100.
Next 2-3 = 1/8 = 0.125 is highest weight. So, binary number will be 0.101.
•
Q) What are floating point notations in the binary number system?

Basically there are different ways of representing numbers in binary. Floating point notations is one of
them and it is used to help in handling numbers having an integer and a fraction part.
32 Bits of Floating-Point numbers are divided in to this partition. The single Sign (S) bit represents the
sign of the number (0=positive 1=negative),the Exponent (E) 8 bits represent the exponent, the
Mantissa 23 bits represent the magnitude of the number.
For example 15-digit Decimal Floating Point Number
The number 0.69183125 x 104 is represented in decimal floating point notation as

+04691831250000
The Sign (S) 1 digit represents the sign of the number (+/–),the Exponent (E) 2 digits represent the
exponent, the Mantissa 12 digits represent the magnitude of the number.
Q)"2bits normally represents four values in binary number system"Explain the following
statement?
As we have two digits 0 and 1 in binary number system. We can arrange these two digits in four different combinations 00,
01, 10, 11, to represent four different values.
The number of combinations can be calculated by using the formula 2n, where n is the number of bits.
Q)How we will convert number 48.8125 into binary using repeated multiplication by 2?
Answer:
48.8125
Separate the integer part and fraction part first.
Integer part = 48
Fraction Part = 0.8125
Step 1:
Convert the Integer part 48 into its equivalent in binary using any method specified.
2 48
2 24 0
2 12 0
2 6 0
2 3 0
1 1
48 = 110000 in binary
Step 2:
Convert the fractional part 0.8125 into binary using repeated multiplication by 2.
Integer part after Fraction part after
Number multiplication multiplication
0.8125 1 0.625
0.625 1 0.25
0.25 0 0.5
0.5 1 0.0
0.8125 = 0.1101 in binary
Decimal point will always be placed on left of the fractional part.
Step 3:
Now combining integer part and fractional part in binary, we get,
48.8125 = 110000.1101 in binary = (110000.1101) 2
•

Lecture no 3
Hexadecimal Numbers
 The Hexadecimal number system is a base 16 number system and therefore has 16 digits and is used primarily to
represent binary strings in a compact manner.
 Hexadecimal number system is not used by a Digital System.
 The Hexadecimal number system is for our convenience to long binary strings in a short and concise form.
 Each Hexadecimal Number digit can represent a 4-bit Binary Number
•
Hexadecimal to Binary Conversion
Converting from Hexadecimal back to binary is also very simple. Each digit of the Hexadecimal
number is replaced by an equivalent binary string of 4-bits.
FD13 Hexadecimal Number 1111 1101 0001 0011 Replacing each Hexadecimal digit by its 4-bit
binary equivalent.
•
Q) What is weight method?
Suppose we want to convert decimal number 392 into its equivalent binary, follow the following steps
Step 1: Draw a 4 column table
Step 2: Write multiples of 2 starting from 1 from bottom to top in “weight” column
Step 3: write decimal number 392 in “Number” column
Step 4: Now see whether 392 is greater or equal to 256? If so, place 1 in “Binary” column and if it is
less place zero in “Binary” column
Step 5: Subtract number from its respective weight and write the result in next row and repeat the
procedure again until weight 1 is reached
Step 6: write the binary digits from top to bottom
So binary number for decimal 392 is 110001000
Q)What is the 2's compliment of 00000?
Take 1's complement of 00000 first = 11111

add 1 in 1's complement = 11111+1 = 100000
so 2's complement of 00000 is 100000.

Q)What are first and second complement ?
1's complement is calculated by revesing each bit and 2's complement is obtained by adding 1 in 1's
complement. These complements are used just to represent different forms of binary numbers. For
example
(7) 0111 =
1's complement 1000
then Add + 1
----------
1001 = (-7)
Q)What is mantissa?
Mantisa is the magnitude of the number after it has been converted to required format. For example
we want the number 6.9183125 x 103 to represent it into "decimal number floating-point format" the
the number firstly will be written as 0.69183125 x 104. In this, magnitude 691831250000 is called
mantisa.
Q)What is meant by Highest weight in decimal to binary conversion?
Weight of binary bits starts from 1 and increases by multiple of two so highest weight means that the
staring weight should not be greater then the decimal number which is being converted into binary.
Weights go like this
1024 512 256 128 64 32 16 8 4 2 1

Now suppose we want to convert decimal 350 and 615 to their equivalent binaries, the highest weights
for 350 and 615 are 256 and 512 respectively.

Q)What is Range?
Range means that how many numbers can be represented by certain number of bits. For exapmle if we
have 3 bits, total 8 numbers ( 0 to 7) can be represented by these three bits so maximum number is 7
and total numbers are 8. We can say that range of binary number having 3 bits is 8 or 23 or in general
if you have n number of bits the range would be 2n. Similarly in "signed magnitude representation"
both positive and negative numbers can be represented. If we have 'n' number of bits the total positive
numbers that can be represented are (2n-1-1) and total negative numbers that can be represented are
(2n-1-1).
Suppose you have 4 bits then 24-1-1=7 positive numbers and 7 negative numbers can be represented.
So range is from +7 to -7.
-7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7.
•
on November 1, 2013 at 8:50am
Q)What do u meant by MSB/LSB ?
The MSB (most significant bit) is in binary sequence, it is farthest to the left (or first) or greatest
value in contrast LSB (least significant bit) is farthest to the right (or last) or right-most bit.
Let’s see this example, in the binary number 1000, the MSB is 1 and LSB is 0.
Q)How many methods are there to represent Binary to Decimal and Decimal to Binary ?
There are two methods used for decimal to binary and binary to decimal conversion which are
mentioned on page no:14 to 18 of handouts.
For example: By using Repeated Division-by-2 method, it converted into decimal to binary and vice
versa
Decimal number =19

Repeated
Division-by-2 Quotient after Remainder
method Number division after division
2 19 9 1
2 9 4 1
2 4 2 0
2 2 1 0
2 1 0 1
Binary number =10011
10011= 1 x 24 + 0 x23+ 0 x 22 + 1 x 21 + 1 x 20
= 16+0+0+2+1
= 19
Q)What is Flip Flop circuit?
Flip flop is the storage element in sequential circuits. It has two stable states and a feedback
path that allows it to store a bit of information. A flip-flop only changes state when a control
signal goes from high to low or low to high. There are many types of flip-flops like SR Flip-flop,
JK Flip-flop, D Flip-flop, etc.
what is Sequential Logic:

Sequential Logic:
Sequential logic is the form of a logic circuit whose output depends on the present input state(s) as
well as on the previous state(s). It contains the memory element where previous state is stored. Flip-
flop is an example based on sequential logic

Q)How to do calculation using Caveman numbers?
Caveman is a base 5 number system. It consists of five unique symbols ∑, ∆,>, ῼ and ↑ that are used
to represent numbers 0, 1, 2, 3, 4 respectively. To represent larger number a combination of symbols
is used.
For example, to represent the decimal 5, a two number combination of Caveman number system is
used. The most significant digit is ∆ which is equivalent to decimal 1. The least significant digit is ∑
which is equivalent to decimal 0. The five combinations of Caveman numbers having the most
significant digit ∆, represent decimal values 5 to 9 respectively. This is similar to the Decimal Number
system, where a 2-digit combination of numbers is used to represent values greater then 9. The most
significant digit is set to 1 and the least significant digit varies from 0 to 9 to represent the next 10
values after the largest single decimal number digit 9.
The Caveman number ∆↑ can be written in expression from based on the base value 5 and weights
5 0, 51, 52 etc.
= ∆ * 51 + ↑ * 50 = ∆ * 5 + ↑ * 1
Replacing the Caveman numbers ∆ and ↑ with equivalent decimal values in the expression yields;
= ∆ * 51 + ↑ * 50 = ∆ * 5 + ↑ * 1 = 9
The number ∆ ῼ↑∑ in decimal is represented in expression from as;
= ∆ * 53 + ῼ * 52 + ↑ * 51 + ∑ * 50 = ∆ * 125 + ῼ * 25 + ↑ * 5 + ∑ * 1
Replacing the Caveman numbers with equivalent decimal values in the expression yields;
= (1) * 125 + (3) * 25 + (4) * 5 + (0) * 1 = 125 + 75 + 20 + 0 = 220
•
Lecture no 4
Q)What is the concept of hexadecimal subtraction and addition?
Let's tackle subtraction first. Subtraction in hexadecimal works similar to subtraction in decimal.
Suppose we want to subtract 1586 - 243 (in decimal).
We write the subtrahend (the number to be subtracted) underneath the minuend (the number to
subtract from), lining up the place values at the decimal

point - or at the right if there is no decimal point - like this:
1586
- 243
---------
Now, starting from the right, we subtract the digits. (Ones place) 6-3 = 3, (tens place) 8-4 = 4,
(hundreds place) 5-2 = 3,
(thousands place) 1-0 = 1. It looks like this
1586
- 243
---------
1343
We do the same thing in hexadecimal, except that we occasionally have a digit larger than 9. For
example, suppose w
e want to subtract 5CD2 - 2A0 (hexadecimal). As with decimal, we write the subtrahend (the number
to be subtracted) underneath the
minuend (the number to subtract from), lining up the place values at the radix point - or at the right if
there is no radix point - like this:
5CD2 h (The 'h' just indicates a hexadecimal value)
- 2A0 h
-----------
Now, starting from the right, we subtract the digits. 2-0 = 2, D-A = 13-10 = 3, C-2 = 12-2 = 10 = A, 5-
0 = 5. It looks like this:
5CD2 h
- 2A0 h
----------
5A32 h
That's fine - until you get a place value in which there's not enough to subtract from. What do we do in
decimal?
We borrow from the next higher place value. For example, suppose we want to subtract 3145 - 1976
(decimal). We'll align our numbers:
3145
-1976
----------
Now in the ones place, we can't subtract 6 from 5 (5 is less than 6) so we borrow 1 from the tens
place.
This gives us 15 (5 plus the 10 we got from the borrow). We now subtract 15-6 = 9:
3 15
3 1 \ \ (There was a 4 and a 5 under the '\'s)
-1976
-------------
9
Similarly in the tens place, we can't subtract 7 from 3 so we borrow one from the hundreds place. We
now subtract 13-7 = 6:

0 13 15
3\\\
-1976
--------------
69
We do the same for the next, borrowing 1 from the thousands, and then subtract the thousands. We
end up like this:
2 10 13 15
\\\\
-1976
-------------
1169
Q)Why did we get 10 from each borrow? Because each time, the next place value was 10 times as large.
This is because decimal is base-10.
Now let's look at a hexadecimal problem that requires borrowing. For example, suppose we want to
subtract A8D2 - 3EAC (hexadecimal).
We'll align our numbers:
A8D2h
-3EACh
----------------
Now in the ones place, we can't subtract C (12) from 2 so we borrow 1 from the second place. Since
that has a place value (a "weight") of sixteen,
this gives us 18 (2 plus the 16 we got from the borrow). We now subtract 18-12 = 6:
(Note that I use decimal here. Some people
12 18 write these as Ch and 12h.)
A 8 \ \ h (There was a D and a 2 under the '\'s)
-3EACh
-----------------
6h
In second place, we don't need to borrow because we can subtract 10 (A) from 12:
12 18
A8\\h
-3EACh
-------------------
26h
In the third place, we again need to borrow. We'll borrow 1 from the 4rth place which gives us 24 (8
plus the 16 from the borrow).
We then can subtract 24-14 = 10 = A. So we have:
9 24 12 18
\\\\h
-3EACh

-------------
A26h
Finally, we subtract 9-3 = 6 in the 4096's place:
9 24 12 18
\\\\h
-3EACh
-------------
6A26h
Q)Why did we get 16 from each borrow? Because each time, the next place value was 16 times
as large. This is because hexadecimal is base-16.
One final note: If the subtrahend (the bottom number) is larger than the minuend (the top number), flip
the numbers around and make the final answer
negative, just as you would in decimal.All the operations work exactly the same in any base, as long
as you use the right tables and remember to use the base when you carry or borrow.
For example, here's 25 x 3A (37 x 58 base 10):
25
x 3A
--------
32 A x 5 (10 x 5 = 50)
14 A x 2 (10 x 2 = 20)
F 3 x 5 (3 x 5 = 15)
6 3 x 2 (3 x 2 = 6)
----------
862 = 2146 (base 10)
I wrote out each product of a pair of digits here, to save carrying, and to show explicitly the four
numbers you would get from a multiplication table
(though I just multiplied each pair in base 10 and converted to base 16); normally you'd write it as
25
x 3A
---------------
172 = 32 + 140
6F = F + 60
--------------
862

Here, for example, 5 x A = 32, so I put down 2 and carried the 3, which I added to the result of A x 2
= 14 to get 17.
When I added the partial products, I found that 7+F = 16, so I put down the 6 and carried the 1.
Q) What is The Excess Code ?
Excess code is a number representation system like any other system. Excess code of any number is
obtained by adding some number to it. For example in excess- 3 code, the code for 0 is obtained by
adding 3 in 0 as 0000+0011=0011, similarly excess-3 code for 2 is 0010+0011=0101.Similary we can
get excess-5 or excess-8 codes.
Decimal Excess-8
-8 0000 (-8+8 = 0 )
-7 0001 (-7+8 = 1 )
-6 0010 (-6+ 8 = 2)
-5 0011 (-5+8 = 3)
-4 0100 (-4+8 = 4)
-3 0101 (-3+8 = 5)
-2 0110 (-2+8 = 6)
-1 0111 (-1+8 = 7)
0 1000 (0+8 = 8)
1 1001 (1+8 = 9)
2 1010 (2+8 = 10)
3 1011 (3+8 = 11)
4 1100 (4+8 = 12)
5 1101 (5+8 = 13)

6 1110 (6+8 = 14)

7 1111 (7+8 = 15)
Q)What is caveman number system?
In caveman number system caveman used 5 distinct shapes ∑, ∆,>, ῼ and ↑ to represent the numbers
from 0 to 4. If you want to convert 13 into caveman number system divide 13 by 5 to get the number
of carries then represent them into their respective symbols so answer of 13 is 23( and in caveman it
would be as “> ῼ”)
How 0.500 and 0.125 will be converted into binary number 0.100 and 0.101?
In sum of weight method, the highest weight means a value that can be represented in the power of 2
and less than sum term. This method is suitable for only small number. For large number, you can use
another method of repeatedly multiplication by 2.
1) Example: Converting decimal 0.500 into binary
Sum Term Highest Weight Binary value Sum term = Sum term - Highest weight
0.500 0.500 (2-1 = 1/2 = 0.500) 0.100 0.500 - 0.500 = 0
In the above example, highest weight for 0.500 is 2-1, if we will take 20 then it will be larger than
0.500 so we will take highest weight 2-1. Now we will place 1 at the position 1 after decimal point.
The process will stop here as the sum term becomes equal to zero.
2) Example: Converting decimal 0.125 into binary
Sum Term Highest Weight Binary value Sum term = Sum term - Highest weight
0.125 0.125 (2-3 = 1/8 = 0.125) 0.001 0.125 - 0.125 = 0

In the above example, highest weight for 0.125 is 2-3. Now, we will place 1 at the position 3 in the
binary value. The process will stop here as the sum term becomes equal to zero.
Decimal to Octal Conversion

There are two methods to convert from Decimal to Octal. The first method is the
Indirect Method and the second method is the Repeated Division Method.
1. Indirect Method
A decimal number can be converted into its Octal equivalent indirectly by first
converting the decimal number into its binary equivalent and then converting the binary
to Octal.
2. Repeated Division-by-8 Method
The Repeated Division Method has been discussed earlier and used to convert
Decimal Numbers to Binary and Hexadecimal by repeatedly dividing the Decimal
Number by 2 and 16 respectively. A decimal number can be directly converted into Octal
by using repeated division. The decimal number is continuously divided by 8 (base value
of the Octal number system).
Octal Numbers
Octal Number system also provides a convenient way to represent long string of
binary numbers. The Octal number is a base 8 number system with digits ranging from 0
to 7. Octal number system was prevalent in earlier digital systems and is not used in
modern digital systems especially when the Hexadecimal number is available. Each Octal
Number digit can represent a 3-bit Binary Number.

Explain implementing an AND Gate using two NAND gates, How can this process implementing.
What is Excess COde?
Excess code is used to represent numbers in the range +7 to -8. In simple words, we just add 8 (1000)
to all the numbers in the range +7 to -8 to represent in excess code.
For example,
0000 (0) + 1000 (8) = 1000 represents 0 in excess code.
0001 (1) + 1000 (8) = 1001 represents 1 in excess code.
.
.
.
.
.
1110 (-2) + 1000 (8) = 0110 represents -2 in excess code.
1111 (-1) + 1000 (8) = 0111 represents -1 in excess code.
What us Sign-magnitude form?
Sign-Magnitude form:
Actually in sign-magnitude form, Most Significant bit is used to represent the sign (either
+ve or -ve) of a number. If it is 1 then the number is negative, and if it is 0 then the number is positive.
Here we are treating with 4 bit numbers, it means that 1st bit will represent the sign and the remaining
three bits will represent the magnitude of the number.
For example,
1111 means -7 and 0111 means +7.
1110 means -6 and 0110 means +6.
And so on. (Bits in red color represents the sign of a number)
what is 2nd Complement form?
2's Complement form:
It is very simple. In 2's complement form the positive numbers are represented in original
form, whereas to represent the negative numbers 2's complement is taken.
For example,
+7 is represented as 0111 and -7 is represented as 1001 (2's complement of 7).
+6 is represented as 0110 and -6 is represented as 1010 (2's complement of 6).
And so on.

Explain subtraction of Hexadecimal?

Borrowing 1 from hexadecimal numbers means borrowing 16, 10 in decimal numbers and 2 in binary
numbers.
Please carefully check each step of hexadecimal subtraction which is given below
Borrow 111
Number1 92B5
Number 2 2AC6
Difference 6 7 E F
21-6 = 15d (decimal) = Fh (hexadecimal)
26-C = 14d (decimal) = Eh (hexadecimal)
17-A = 7d (decimal) =7h (hexadecimal)
8-2 = 6d (decimal) =6h (hexadecimal)
Lecture no 5
Q)Explain NOT gate timing diagram.
Basically the timing diagram of any gate operation is made according to the value which is given
in truth table and it describes the response of the any gate in a certain period of time with respect
to the changing input. The timing diagram describes the operation of NOT gate for 7 interval of

time (t0 to t6) and this operation is performed with the help of NOT gate table which is given the
input (A) and output (F).Please see the figure 5.11 of handouts which indicates first input A is 0
and F indicates output which is 1.
Q) What is diff in single precision and double precision numbers and their definition?
The difference between the single precision and double precision is that single is of 32 bits and double is
64 bits and so single precision has less capability to represent values while the double precision has 64
bit with higher capability to represent the more and higher values than 32 bit single precision. While the
1st bit ‘S’ is a single bit used to represent sign is always 1 for standard format.
Q)why we use logic gates & what is use of them ?
A logic gate is the basic building block of a digital circuit. A logic gate is used to implement
a Boolean function. It performs a logical operation on one or more logical inputs, and
produces a single logical output. At any given moment, every terminal is in one of the two
binary states: low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can change as the circuit processes data.
There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR. T
Q)what is meant by the implementation of AND gate ?
Let’s take this example for better understanding of AND gate implementation. We can design a
digital electronic circuit to make an instant decision based on some information. Here we
emphasize “instant” in the decision making process i.e. the process has no time delay.
These condition will be applied
X = It is a sunny day? Yes, Y = Is it Sunday or holiday? Yes and Action Z = Go for shopping.
The rule is Z = X and Y. The circuit is a simple AND gate implementation. Logic can also be expressed in Truth Table
which is given below.
X Y Z
0 0 0

0 1 0
1 0 0
1(yes) 1(yes) 1(Go for shopping)
Q)How to find the output of NAND gate?

The output of NAND gate is Low (0) only if both the inputs are High (1). Otherwise the output is High (1).
It can be considered as NOT AND gate. It inverts the output of the AND gate. See the difference in both the tables mentioned below.
AND Gate
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
NAND Gate
A B Output
0 0 1
0 1 1
1 0 1
1 1 0

Q) What is transistor device?
A transistor device composed of semiconductor material that amplifies a signal or opens or

closes a circuit. An integrated circuit (IC) consists of active and passive components as well as
interconnections and these components include transistors, diodes, capacitors and resistors. For
example: The number of transistors used in Intel's current state-of-the-art Pentium 4
microprocessor, which has 42 million transistors and is capable of executing 1.7 billion
instructions a second.
Explain Implementation of Logic Gate?
The practical implementation of the Logic gates is through the Integrated Circuits technologies.
Different types of Integrated Circuit technologies are used to implement the digital circuit’s e.g.
CMOS, TTL, ECL, PMOS, and E2CMOS.CMOS and TTL are the different technologies to
implement the digital circuits.Binary Coded Decimal (BCD) code is a 4-bit code and is used to
represent decimal digits 0 to 9 in binary. Only 1st ten binary values are used to represent decimal
values from 0 (0000) to 9 (1001). The remaining six 4-bit combinations 1010, 1011, 1100, 1101,
1110 and 1111 are considered to be invalid and do not exist.
To represent decimal number in BCD, we write BCD codes of individual digits. For example,
BCD code for 216 is 0010 0001 0110
BCD code for 23 is 0010 0011
In Binary Coded Decimal (BCD), the adder is actually working in hex, 0xA shows the
hexadecimal number and it is not used for multiplication. If the addition of two BCD digits
results in an invalid result, the result must be between 0xA (1010) and 0xF (1111). By adding 6
to this value and generating a carry, you generate the proper BCD values:
0xA + 0x6 = 0x10 (the BCD value 10)
0xB + 0x6 = 0x11 (the BCD value 11) etc.
So by adding 6 we use the hardware of the computer which is designed for counting in binary to
skip over the binary values we won't need because we want to represent digits in BCD.Please
also see the example which is mentioned in page: no: 35 of handout.
Please try to post only one query in a single post.

Q) Explain Gray Code?
Gray code is basically used to refer to a binary sequence in which only a single bit changes value
when transitioning between adjacent states. Exclusive-OR method is used to convert binary code
to gray code.
For example: Firstly Binary number 10101010 is converted into gray code and then it can be
converted into decimal. Please see the table which is given below. Exclusive -OR is applied on
binary bits of column A and B and result is placed on column B of Gray code Section.
Same procedure is applied on all columns.

Binary 27 26 25 24 23 22 21 20
number
system
Gray Column Column Column Column Column Column Column Column
number A B C D E F G H
system
Binary 1 ⊕ 0 1 0 1 0 1 0
section
Gray 1 1 1 1 1 1 1 1
code
section
How can we calculate Hexadecimal addition and subtraction?
We can do hexadecimal addition and subtraction in same way as we do in decimal number

system. Two examples are given on the 30 of the handouts. Here in the example of addition at

left most column the values to be added are 5+6 = B because 11= B, next is B+C = 17 for
understanding (B = 11 of decimal and C= 12 hence 11+ 12 = 23
of decimal cover 23 into hexadecimal by repeated division by 16 you will get 1 as quotient and
7 as remainder so it is 17), 7 will be written and 1 will be taken as carry. () 1+A+2 = D and so
on
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Q)Explain sum of weights?
Here we have the decimal value 411, which is to be converted into binary value.
512 256 128 64 32 16 8 4 2 1
The above values are used according to the position of the binary bit. So, for 411 the maximum
available value is 512 which is greater than 411 obviously we cannot use it. So we take 256
which fall under 411 here now we take 411 – 256 = 155 here, in fact now 155 value remains
there to be represented in binary. Now for 155 the maximum possible value that fall under it is
128 again we repeat and 155 – 128 = 27 and so on. At the end we add the all binary values as
given below and wee the sum as result which is binary equivalent of 411 which is shown below.
256 128 64 32 16 8 4 2 1
256 1 0 0 0 0 0 0 0 0
128 0 1 0 0 0 0 0 0 0
16 0 0 0 0 1 0 0 0 0
8 0 0 0 0 0 1 0 0 0
2 0 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0 0 1
SUM 1 1 0 0 1 1 0 1 1

Q)Hexadecimal to decimal conversion using sum of weight method?
First understand what each hexadecimal digit stands for. The digits 0 through 9 stand for their decimal
counterparts, and A = 10, B = 11, C = 12, D = 13, E = 14, and F = 15.
Now suppose we want to convert hexadecimal number B61F.Follow the foolowing steps now.
Step1
Write each character multiplied by 16 and separated by +.
Bx16 + 6x16 + 1x16 + Fx16
Step2
Write decimal equivalent against each hexa digit
11x16 + 6x16 + 1x16 + 15x16
Step3
Put power on each 16 starting from 0 from left side.
11x163 + 6x162 + 1x161 + 15x160
Step4
Solve powers and solve
= 11x4090 + 6x256 + 1x16 + 15x1

= 45056 + 1536 + 16 + 15
= 46623
So Decimal equivalent to B61F is 46623
Q)Decimal to Hexadecimal using Repeated Division by 16 Method?
Suppose we have decimal number 845 and we want it into hexadecimal number by repeated division by 16
method. Follow the steps given below.
Step1:
Divide 845 by 16: The remainder will be 13 which is equal to ‘D’ in hexadecimal.
Step2:
Now divide quotient 52 by 16: Remainder will be 4 and quotient would be 3 (Which is less then 16 so further
division is not possible)
Step3:
Now write all remainders in from bottom to top direction as 34D. So hexadecimal equivalent to decimal 845 is
34D.
16 845
16 52….........3 (D)
3…………4

Q)What is BJT ?
Bipolar Junction Transistors

BJTs can have two different polarities, NPN and PNP. An NPN BJT is one where a positively-doped (P-type)
semiconductor is sandwiched between two negatively-doped (N-type) semiconductors. A PNP BJT is,
obviously, one where an N-type semiconductor is sandwiched between two P-types. Both types of BJTs have
an exponential dependence between the input voltage and the current output. For the record, I should state that
a semiconductor is basically a material with conductance between that of an insulator and a conductor. Silicon
and germanium are the two most well-known semiconductors. Also, doping just means the addition of
impurities into a semiconducting material in order for it to either: increase its electron acceptance (P-type) or
increase its electron conductance (N-type)
Q) what is the use of an Integrated Circuit ?
Large and complex digital system such as a computer is built using combinations of basic Logic Gates such as
AND, OR, NOT gates. These basic building blocks are available in the form of Integrated Circuit or ICs.
These gates are implemented using standard CMOS and TTL technologies. It saves circuit space and cost.
Digital circuits to perform specific functions are available as Integrated Circuits for use. Implementing a
Digital system in terms of these dedicated functional units makes the system more economical and reliable.
Thus an adder circuit does not have to be implemented by connecting various gates, a standard Adder IC is
available that can be readily used. Other commonly used combinational functional devices are Comparators,

Decoders, Encoders, Multiplexers and Demultiplexers.

Consider the example of Adder circuit which is a combination of AND, OR and XOR gates. It requires 3
chips to implement Adder circuit. We can implement it by using single chip so the circuit space reduces
from 3 chips to 1 chip.
Q)What is an inverter ?
Inverter is a NOT gate. The NOT gate performs logical inverse operation. The NOT gate has single input and a
single output. If input is 0 then output will be logic 1. If input is 1 then output will be logic 1.
Q)What is CMOS?
CMOS: Complementary Metal-Oxide Semiconductor
The most extensively used technology, characterized by low power consumption,switching speed which is
slower but comparable to TTL. Has higher chip density TTL. Due to high input impedance is easily damaged
due to accumulated
static charge.
Lecture no 7
Q)What is Carry?
When we add two binary bits then sum bit and carry bit is generated. The binary addition is identical to
decimal addition. For example, when we add 10 and 6 then result is 16 in which 6 is the sum part whereas 1 is
carry part.
Consider the following example of adding 2 binary numbers

Decimal
Carry 1 1 0 Equivalent
1st Number 1 0 1 0 10
2nd Number 0 1 1 0 6
Result 1 0 0 0 0 16
The binary addition starts from adding least significant bits. In the above example, the least significant bit of
1st number is 0 and least significant bit of 2nd number is 0. When we add these two bits then sum bit is 0 and
carry bit is 0. Now, bits 1 and 1 and carry bit 0 will be added. The result will be 10 in which sum is 0 and carry
is 1. Next, bits 0 and 1 and carry bit 1 will be added. The result will be 10 in which sum is 0 and carry is 1.
Now, bits 1 and 0 and carry bit 1 will be added. The result will be 10.
Q)How can noise effect on CMOS AND circuit?
Let consider a noise signal is induced in the circuit of CMOS AND gate. The acceptable output logic level is
from 0 to 0.33 for logic 0 and 4.4 to 5 for logic 1. Suppose, when the noise is added to circuit then it drops the
output voltage down to 3.4 volts. As the acceptable output voltage for logic 1 is from 4.4 to 5 volts, thus the
circuit will malfunction.
For better understanding of noise, noise margin and logic levels, read the following concepts.
Noise:
Noise is an unwanted voltage that is induced in the circuit due to high frequency electromagnetic radiations.
The TTL and CMOS circuit operating at +5 or 3.3 Volts respectively are designed to accept voltages in a
certain range as logic 1 and 0. These voltage ranges are noise margin. The VIH and VIL indicate the
acceptable voltage ranges for the input logic high and low respectively. Similarly VOH and VOL indicate the
acceptable output voltage range for logic high and low respectively. These voltage ranges determine the
suitability of a gate to work in noisy environments. As long as the input remains in these ranges, the circuit
will work properly in the presence of noise.
Logic levels for TTL: If the input voltage is from 0 to 0.8 volts then it will be treated as logic 0. If the input
voltage is from 2 to 5 volts then it will be treated as logic 1.
If the output voltage is from 0 to 0.4 volts then it will be treated as logic 0. If the input voltage is from 2.4 to 5
volts then it will be treated as logic 1.
Logic levels for CMOS 5 Volts series: If the input voltage is from 0 to 1.5 volts then it will be treated as logic
0. If the input voltage is from 3.5 to 5 volts then it will be treated as logic 1.
If the output voltage is from 0 to 0.33 volts then it will be treated as logic 0. If the input voltage is from 4.4 to
5 volts then it will be treated as logic 1.
Logic levels for CMOS 3.3 Volts series: If the input voltage is from 0 to 0.8 volts then it will be treated as
logic 0. If the input voltage is from 2 to 3.3 volts then it will be treated as logic 1.
If the output voltage is from 0 to 0.4 volts then it will be treated as logic 0. If the input voltage is from 2.4 to
3.3 volts then it will be treated as logic 1.
Noise Margin: Noise margin is a measure of the circuit’s immunity to noise. The high-level and low level
noise margins are represented by VNH and VNL respectively.
VNH = VOH(min) – VIH(min)

VNL = VIL(max) – VOL(max)
TTL 5 volt Noise Margins

VNH = VOH(min) – VIH(min) = 2.4 - 2.0 = 0.4 v
VNL = VIL(max) – VOL(max) = 0.8 – 0.4 = 0.4 v
CMOS 5 volt series Noise Margins

CMOS 3.3 volt series Noise Margins

VNH = VOH(min) – VIH(min) = 2.4 – 2.0 = 0.4 v

Q) What is Logic levels and Noise Margin?
Noise is an unwanted voltage that is induced in the circuit due to high frequency
electromagnetic radiations. The TTL and CMOS circuit operating at +5 or 3.3
Volts respectively are designed to accept voltages in a certain range as logic 1 and 0.
These voltage ranges are noise margin. The VIH and VIL indicate the acceptable voltage
ranges for the input logic high and low respectively. Similarly VOH and VOL indicate
the acceptable output voltage range for logic high and low respectively. These voltage
ranges determine the suitability of a gate to work in noisy environments. As long as the
input remains in these ranges, the circuit will work properly in the presence of noise.
Logic levels for TTL: If the input voltage is from 0 to 0.8 volts then it will be treated as
logic 0. If the input voltage is from 2 to 5 volts then it will be treated as logic 1.
If the output voltage is from 0 to 0.4 volts then it will be treated as logic 0. If the input
voltage is from 2.4 to 5 volts then it will be treated as logic 1.
Logic levels for CMOS 5 Volts series: If the input voltage is from 0 to 1.5 volts then it
will be treated as logic 0. If the input voltage is from 3.5 to 5 volts then it will be treated
as logic 1.
voltage is from 4.4 to 5 volts then it will be treated as logic 1.
Logic levels for CMOS 3.3 Volts series: If the input voltage is from 0 to 0.8 volts then it
will be treated as logic 0. If the input voltage is from 2 to 3.3 volts then it will be treated
as logic 1.
voltage is from 2.4 to 3.3 volts then it will be treated as logic 1.
Noise Margin: Noise margin is a measure of the circuit’s immunity to noise. The high-
level and low level noise margins are represented by VNH and VNL respectively.
VNH = VOH(min) – VIH(min)

VNL = VIL(max) – VOL(max)



VNH = VOH(min) – VIH(min) = 2.4 – 2.0 = 0.4 v
Q)What is Binary Addition and Binary Subtraction ?
Binary Addition
When we add two binary bits then sum bit and carry bit is generated. The binary addition is identical to
decimal addition. For example, when we add 10 and 6 then result is 16 in which 6 is the sum part whereas 1 is
carry part.
Consider the following example of adding 2 binary numbers
Decimal
Carry 1 1 0 Equivalent
1st Number 1 0 1 0 10
Result 1 0 0 0 0 16

The binary addition starts from adding least significant bits. In the above example, the least significant bit of
1st number is 0 and least significant bit of 2nd number is 0. When we add these two bits then sum bit is 0 and
carry bit is 0. Now, bits 1 and 1 and carry bit 0 will be added. The result will be 10 in which sum is 0 and carry
is 1. Next, bits 0 and 1 and carry bit 1 will be added. The result will be 10 in which sum is 0 and carry is 1.
Now, bits 1 and 0 and carry bit 1 will be added. The result will be 10.
Binary Subtraction
In binary number system, when we borrow a number then it is actually 2 (binary 10) just like in decimal
number system the borrow taken is 10.
Consider the following example of subtracting 2 binary numbers
Decimal
Borrow 1 Equivalent
1st Number 1 1 1 0 14
Result 1 0 0 1 9
The subtraction starts from least significant bits. In the above example, the least significant bit of first number
is 0 and least significant bit of second number is 1. The bit 0 is less than 1 and cannot be subtracted therefore a
borrow is taken preceding bit. The borrow taken is 10 (binary number). Now, 10 will be subtracted from 1
which gives the result 10 – 1 = 1. Next, bits 1 and 0 will be subtracted. As a borrow has already been taken
from the preceding bit of first number therefore it is left as 0. Now, bit 0 of first number and bit 0 of second
number will be subtracted which gives the result 0 – 0 = 0. Next, bit 1 of first number and bit 1 of second
number will be subtracted which gives the result 1 – 1 = 0. Next, bit 1 of first number and bit 0 of second
number will be subtracted which gives the result 1 – 0 = 1.
The decimal equivalent of binary number means the decimal number obtained after converting binary number
into decimal number. In the above example, the decimal equivalent of binary number 1110 is 14.
1110 2 = 1×23 + 1×22 + 1×21 + 0×20 = 8 + 4 + 2 + 0 = 14
Noise Margin
Noise margin is a measure of the circuit’s immunity to noise. The high-level and low-level noise margins
are represented by VNH and VNL respectively.
• VNH = VOH(min) – VIH(min)
• VNL = VIL(max) – VOL(max)
• VNH = VOH(min) – VIH(min) = 4.4 - 3.5 = 0.9 v
• VNL = VIL(max) – VOL(max) = 1.5 – 0.33 = 1.17 v

• VNH = VOH(min) – VIH(min) = 2.4 – 2.0 = 0.4 v

• VNH = VOH(min) – VIH(min) = 2.4 - 2.0 = 0.4 v

Q)What is Power Dissipation

Logic Gates and Logic circuits consume varying amount of power during their operation. Ideally, logic gates
and logic circuit should consume minimal power. Advantages of low power consumption are circuits that can
be run from batteries instead of mains power supplies. Thus portable devices that run on batteries use Integrated circuits that have
low power dissipation. Secondly, low power consumption means less heat is dissipated by the logic devices; this means that logic gates
can be tightly packed to reduce the circuit size without having to worry about dissipating the access heat generated by the logic devices.
Microprocessors for example generate considerable heat which has to be dissipated by mounting small fans.
Generally, the Power dissipation of TTL devices remains constant throughout their operation. CMOS device
on the other hand dissipate varying amount power depending upon the frequency of operation
Q)What is (SPP)?
An important parameter is the Speed-Power Product which is used as a measure

of performance of a logic circuit taking into account the propagation delay and the power
dissipation.
The SPP = tPPD expressed in Joules (J), the unit of energy. Lower the SP product better is
the performance.
Q)What is Fan-out ?
The maximum number of gates that can be connected to the output of a single gate is referred to as
Fan-Out.
The fan-out is the number of gates that are connected to the output of the driving gate. Fan-out leads
to increase capacitive load on the driving gate and therefore longer propagation delay and when an
input signal of a logic gate is changed, there is a propagation delay before the output of the logic gate
changes. This is due to capacitive loading at the output.
Q)What is TTL?

The practical implementation of the Logic gate is through the Integrated Circuits technologies and
different types of Integrated Circuit technologies are used to implement the digital circuit’s e.g.
CMOS, TTL, ECL, PMOS, E2CMOS.
TTL stands for transistor–transistor logic. It is a class of digital circuits built from bipolar junction
transistors and resistors and it is used in many applications such as computers, industrial controls, test
equipment and instrumentation etc.
•
Lecture no 8
Q)What is Parity?
Parity is used to detect even number of 1's or odd number of 1's in any binary sequence. Even parity bit is used
to make number of 1's even in any binary sequence and Odd parity bit is used to make number of 1's odd in
any binary sequence. For example in binary sequence 1110001110001.
Number of 1's is 7 which an odd number so odd parity bit will be 0 and even parity bit will be 1( because we
want to make number of 1's even in even parity method.
Q)What is NPN Transistor?
There are two types of transistors NPN(P-Type material is sandwiched in two N-type material) and PNP(N-
Type material is sandwiched in two P-type material). It works just like a switch i.e At some conditions current
flow through it and we call it as ON and on some conditions current don't flow through it this is called OFF
condition.

Q)How can we identify the sop and pos?
An expression which contains minterms or product terms in which minterms are summed together is called
SOP expression whereas an expression which contains maxterms or sum terms in which maxterms are
multiplied together is called POS expression. Minterms are the product terms whereas Maxterms are the sum
terms.
The following is an SOP expression which contains minterms 2, 4 and 6. In the expression given below,
minterms have been summed together.
A’BC’+ AB’C’ + ABC’
The following is a POS expression which contains maxterms 1, 3, 5 and 7. In the expression given below,
maxterms have been multiplied together.
(A+B+C’)(A+B’+C’)(A’+B+C’)(A’+B’+C’)
Q) What is mantissa and biased exponent?

Mantissa represents the magnitude of number. The Biased exponent value is used to represent negative
exponents. In 15 digit floating point representation, the biased value 50 is added to exponent value. The
highest exponent value that can be represented is 49 (49+50 = 99) and the smallest exponent value that can be
represented is -50 (-50+50 = 0). As in 15 digit floating point representation, the exponent fields of 2 digits
therefore the largest value must be 99.
Q)What is parity method and what is even parity and odd parity ?
Parity method is used to detect errors while transmitting information from one end to other end. There are two
methods: even parity bit method and odd parity bit method. An extra bit is appended at the end of binary
information to detect error. We can use both even parity and odd parity method to detect errors.
Even parity method: With even parity bit method, the total number of 1s is counted to make it equal to even
number of 1s. If the number of 1s is even then appended bit is 0 otherwise the appended bit is 1 so that total
number of 1s become even.

For example, 8 bit binary information to be transmitted is 11001011. The total number of 1s in the 8 bit binary
information is odd so we append 1 at the end of information to make it equal to even number of 1s such as
110010111. Similarly, if the 8 bit binary information is 11001010 then we append 0 at the end of information
to make the number of 1s equal to even such as 1100101110.
Odd parity method: With odd bit parity method, the total number of 1s is counted to make it equal to odd
number of 1s. If the number of 1s is odd then appended bit is 0 otherwise the appended bit is 1 so that total
number of 1s becomes odd.
For example, 8 bit binary information to be transmitted is 11001000. The total number of 1s in the information
is odd so we append 0 at the end of binary information to make it equal to odd number of 1s such as
110010000. Similarly, if the 8 bit binary information is 11001001 then we append 1 at the end of binary data to
make the number of 1s equal to odd such as 110010011.
Q) what is the purpose of Boolean Algebra?
Boolean algebra is the mathematics of Digital Systems therefore digital systems work on the basis of Boolean
algebra. Digital circuits are made from the combination of logic gates which performs Boolean logic operation
such as AND, OR and NOT operation. Logic gates are the basic building block of digital systems which
performs Boolean logic operation on one or more logic inputs and produces a single logic output. Digital
circuits are made from the combination of logic gates such as AND, OR, NOT gates.
AND gate performs logical multiplication operation. It gives output 1 when all inputs are logic 1 whereas it
gives output 0 when any of the input is 0.
OR gate performs addition operation. It gives output 1 when any of the input is 1 whereas it gives output 0
when all inputs are 0.
NOT gate performs inversion operation. If input is 1 then output is 0 and if input is 0 then output is logic 1.

Q)Boolean Algebra Definitions

1. Variable
A variable is a symbol usually an uppercase letter used to represent a logicalquantity. A

variable can have a 0 or 1 value.
2. Complement
A complement is the inverse of a variable and is indicated by a bar over the variable.
Complement of variable X is X . If X = 0 then X = 1 and if X = 1 then X= 0.
3. Literal A Literal is a variable or the complement of a variable.
Q)Standard Form of Boolean Expressions?

All Boolean expressions can be converted into and represented in one of the two standard forms.
• Sum-of-Products form
• Product-of-Sums form
1. Sum of Product form
When two or more product terms are summed by Boolean addition, the result is a Sum-of-Product or SOP
expression.
• AB + ABC
• ABC + CDE + BCD
• AB + ABC + AC
The Domain of an SOP expression is the set of variables contained in the expression, both complemented and
un-complemented. A SOP expression can have a single variable term such as A. A SOP expression can not

have a term of more than one

variable having an over bar extending over the entire term, such asAB + C .
2. Product of Sums form
When two or more sum terms are multiplied by Boolean multiplication, the result is a Product-of-Sum or POS
expression.
• (A + B)(A + B + C)
• (A + B + C)(C + D + E)(B + C + D)
• (A + B)(A + B + C)(A + C)
The Domain of a POS expression is the set of variables contained in the expression, both complemented and
un-complemented. A POS expression can have a single variable term such as A. A POS expression can not
have a term of more than one
variable having an over bar extending over the entire term such as (A +B)(A +B + C)
Q)What is range of Signed forms?
Basically 2’s complement form is used to represent signed numbers. E.g. 2’s complement
representation +13 is represented as 01101 and -13 is represented as 10011.All negative numbers are
represented in their 2’s complement form and all positive numbers are represented in their actual
form.
For example:
0111 The actual binary number of 7 (MSB set to 0 indicates a positive number)
1000 Using 1’s complement of 7, all bits are inverted (0 to 1 or 1 to 0)
+1 Adding 1 in inverted binary numbers (2’s complement)
1001 this binary number represents -7 (MSB set to 1 indicates a negative number)

Q)Rule No 11 and 12 of Boolean Algebra ?
Please check it all steps and comments. Hope you can understand better.
11. A + A’.B
= A.1 + A’.B according to Rule 2: (B+1) = 1,So replaced 1 to
(B+1)
= A(B+1) + A’.B
= AB +A + A’.B
= B(A+ A’ ) +A
according to Rule 6 : A’ + A =
1
=B+A
12. (A+B).(A+C)
= AA+AC+AB+BC applying the Distributive Law(multiply
each variable to each variable of next block )
= A(1+C+B) +BC common A and then will be 1 according to
Rule 2: (1+B+C) = 1
= A+BC
Q)How 6918.3125 can be written 6.9183125*10 power 3?
When the decimal point is moved left side of the magnitude of the number so that the positive number
is added and when it is moved right side it is added negative number in exponent part.
For example the magnitude of the number is 6918.3125. It can be written as 6.9183125 x 103.When
this decimal point is moved to the extreme left of the number it can be written as 0.69183125 x 103+1 =
0.69183125 x 104.
Lecture no 9
Q) What is a canonical sum and canonical product forms?

An expanded form of Boolean expression, where each term contains all Boolean
variables in their true or complemented form, is also known as the canonical form of the
expression. Canonical form is also known as standard form.
Q)SOP and Pos conversion? SOP and Pos conversion?
When two or more product terms are summed by Boolean addition, the result is a Sum-
of-Product or SOP expression.
When two or more sum terms are multiplied by Boolean multiplication, the result is a
Product-of-Sum or POS expression.
Any logical expression can be converted into SOP form by applying techniques of
Boolean Algebra.
Q) How we can make borrow column in binary subtraction?
Let's first look at an easy example.
111
- 10
101
Note that the difference is the same if this was decimal subtraction.

Concept of "borrowing" Is similar as it is in decimal number system Watch as

"borrowing" occurs when a larger digit, say 8, is subtracted from a smaller digit, say 5, as
shown below in decimal subtraction.
35
-8
27
1 is borrowed from the "tens" (i.e. 101) column for use in the "ones" column, leaving the
"tens" column with only 2.
The following examples show "borrowing" in binary subtraction.
10
-1
1
In the above example 0 is smaller then 1 so 21 is borrowed now 0 zero become 2, 1 is

subtracted from it.
Now look at another example
100
- 10___
10

Q) What is Standard and non Standard forms?
If every term in the expression contains all the variables (either in complemented or non-
complemented form) used in the expression then it is considered to be in Standard form.
Otherwise it will not be in the Standard form.
For example, consider an expression AB + AC. It is clear that the expression depends on

three variables A, B and C, but first term is missing C and 2nd term is missing B. So it is
in non-standard form.
Consider another expression A'BC + ABC'. It is standard SOP expression, as every term
contains all the three variables used (either in complemented or non-complemented
form).
•
Q) How you have found the binary values of the expressions?
In SOP form, A represents 1 and A’ represents 0. For example,
ABC’ = 110
A’B’C = 001
In POS form, A represents 0 and A’ represents 1. For example,
A+B+C’ = 001
A’+B’+C = 110
Q) How to convert non standard to standard form?
A non standard SOP is converted into a standard SOP by using the rule A + A’ = 1. Consider a
three variable expression, AC + AB’ + A’BC. First term AC is missing the variable B, so

multiply it with (B+B’). The second term AB’ is missing the variable C, so multiply it with
(C+C’). The third term A’BC contains all the three variables so it remains unchanged. We get
then,
AC(B+B’) + AB’(C+C’) + A’BC
= ABC + AB’C + AB’C + AB’C’ + A’BC
= ABC + AB’C + AB’C’ + A’BC
Q) Conversion from POS to SOP?
• The conversion from POS form to SOP and from SOP form to POS becomes simpler, if
the expressions are represented in Standard forms.
• It makes the simplification of Boolean expression quite easy. Normally we use K-map for
simplification of expressions, and it is better to convert the expression in Standard form before
mapping into the K-map. Mapping the Standard expressions in K-map reduces the chances of
error (K-map is discussed in lesson 10).
• In PLD programming, a function represented by an expression in Standard SOP form can
be easily programmed.

Conversion:
A non standard SOP is converted into a standard SOP by using the rule A + A’ = 1. Consider a
three variable expression, AC + AB’ + A’BC. First term AC is missing the variable B, so
multiply it with (B+B’). The second term AB’ is missing the variable C, so multiply it with
(C+C’). The third term A’BC contains all the three variables so it remains unchanged. We get
then,
AC(B+B’) + AB’(C+C’) + A’BC
= ABC + AB’C + AB’C + AB’C’ + A’BC
= ABC + AB’C + AB’C’ + A’BC
A non standard POS is converted into a standard POS by using the rule AA’ = 0.
Lecture no 10
Q)If 66 and 67 are decimal numbers. then we can say that 66 is non positional and 67 is
positional number. if no then why? Give reasons. Also give some examples of positional and
non positional number system.
The positional system is based on exactly where the numbers are in the sequence of numbers and the
decimal number system is a positional number system as the position of a digit represents its true
magnitude as compared to non-positional number systems where the position of the number is not
determining factor.
For Example: 66 and 67 are decimal positional numbers. The left most digit has the highest weight and
the right most digit has the lowest weight. 66 and 67 can be written in the form of an expression in terms
of the base value of the number system and weights.
1. 6 x 101 + 6 x 100 = 60 + 6 = 66

2. 6 x 101 + 7 x 100 = 60 +7 = 67
An example of the non-positional systems is the roman numerals
Q)Why and when we use don't care condition in truth table?
They don't care conditions are the conditions which never occur. In some situation, it may possible
that some input combinations never occur. As these input combinations never occur so the output of
these input combinations will be marked as × which means output can be 0 or 1 as it is not affected by
such input combinations. For example, BCD code is a 4-bit code and may have 16 possible input
combinations. The BCD code represents first 10 decimal digits (0-9). The remaining 6 input
combinations (1010, 1011, 1100, 1101, 1110, 1111) are considered to be invalid and never occur so
these input combinations are don't care conditions. In the k-map, these input combinations will be
marked as × which can have binary value 0 or 1 depending on the expression. It helps to simplify the
Boolean expression using k-map. During grouping process, it can be assigned value 0 or 1.
The figure 10.16 of handouts represents the k-map of Odd-Parity checker which checks the numbers
between 0 and 8. The inputs 9 to 15 never occur therefore these are don’t care conditions. The odd
parity numbers from 0 to 8 are 0001 (decimal 1), 0011 (3), 0101 (5) and 0111 (7). These inputs
conditions will have output 1 in the k-map. Other input conditions 0000 (0), 0010 (2), 0100 (4), 0110
(6) and 1000 (8) will have output 0 in k-map. As the inputs 9 to 15 are don’t care conditions therefore
× will be placed in these cells.
AB\CD 00 01 11 10
00 0 1 1 0
01 0 1 1 0
11 × × × ×
10 0 × × ×

Q) What is the difference between BCD and excess code?
Binary Coded Decimal (BCD) code is used to display decimal digits on 7-Segment Display panels. It
is a 4-bit binary code. As you know, there are total 16 combinations of 4-bits but decimal digits are
from 0 to 9. So, only first 10 combinations of 4-bits are valid BCD codes. The rest of six combinations
1010, 1011, 1100, 1101, 1110 and 1111 are not valid.
Excess code is a biased code which provides a uniform scale for representing positive and negative
numbers. With excess code, a pre-specified value is added to original number. For example in Excess-
8 code, we add 8 to the original number. So, we can also represent negative numbers with it. The
Excess-8 code is a 4-bit code. The binary code 0000 is assigned to -8 (smallest number in the range)
whereas 1111 is assigned to +7 (highest number in the range). The number 8 is added to all digits (+7
to -8) to get the excess code.
Decimal Number Excess Code Decimal Number Excess Code

0 1000 (0+8 = 8) -1 0111 (-1 + 8 = 7)
1 1001 (1+8 = 9) -2 0110 (-2 + 8 = 6)
2 1010 (2 + 8 = 10) -3 0101 (-3 + 8 = 5)
3 1011 (3 + 8 = 11) -4 0100 (-4 + 8 = 4)
4 1100 (4 + 8 = 12) -5 0011 (-5 + 8 = 3)
5 1101 (5 + 8 = 13) -6 0010 (-6 + 8 = 2)
6 1110 (6 + 8 = 14) -7 0001 (-7 + 8 = 1)
7 1111 (7 + 8 = 15) -8 0000 (-8 + 8 = 0)
A number system has unique symbols, like Decimal number system has symbols 0 to 9. Binary
number system has only two symbols, 0 and 1.
Excess, BCD and Gray code all use Binary number system but with some restrictions.
Q)Simplification of SOP expressions using the Karnaugh Map
SOP expressions can be very easily simplified using the K-Map method. In the
first step of the simplification process, the SOP expression is mapped on the K-map. In
the next step, groups of 1s are formed starting with the largest group of 1s. The group
should be of size 2, 4, 8, 16 etc. having adjacent 1s. Multiple (unique) groups of 1s are
formed. All the groups formed can either be separate groups or they could share common

1s each having at least a single 1 that is not common to any other group. A single 1 that is
not adjacent to any other 1 is considered as a group having only a single cell.
Lecture no 11
Q)Segment Display
Segment Display is used to display the decimal numbers 0 to 9. A 7-segment display

digit has 7 segments a, b, c, d, e,
f and g that are turned on/off by a digital circuit depending upon the number that is to
be displayed. Different set of segments have to be turned on to display different digits.
Forexample, to display the digit 3, segments a, b, c, d and g have to be turned on. To
display the digit 7, segments a, b and c have to be turned on.
Q)Functions having multiple outputs

Boolean functions it has been assumed that Logic Circuits have multiple inputs and
single output. Practical Logic circuits however, have multiple inputs and multiple
outputs. Circuits having a single output or multiple outputs are treated in the same
manner.
Circuits having multiple outputs are represented by multiple function tables one
for each output or a single function table having multiple output columns. The example
of a BCD to 7-Segment Decoder circuit which has 4 inputs and 7 outputs is considered to
explain functions having multiple outputs.
Q)What is 7-segment display

A 7-segment display is a group of light emitting diodes (LEDs) arrangement.7-

Segment display is used to display the decimal numbers 0 to 9 and it has 7 segments a, b, c, d, e,
f and g that are turned on or off by a digital circuit depending upon the number that is to be
displayed. It is widely used in digital clocks, electronic meters and other electronic devices for
displaying numerical information.
Lecture no 12
Q)What is Comparator?
A comparator circuit compares two numbers and sets one of its three outputs to 1
indicating the result of the comparison operation. A Comparator circuit has multiple
inputs and three outputs.
A 2-bit Comparator circuit compares two 2-bit numbers A and B. The comparator
circuit has three outputs. It sets the A>B output to 1 if A>B. It sets the A=B output to 1 if
A=B and sets A<B output to 1 if A < B.
• The output A>B is set to 1 when the input combinations are 01 00, 10 00, 10 01, 11
00, 11 01 and 11 10
• The output A=B is set to 1 when the input combinations are 00 00, 01 01, 10 10 and
11 11
• The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01
10, 01 11 and 10 11
•

Q)What is Comparator Circuit?

A 2-bit Comparator circuit that compares two 2-bit numbers A and B and
activates one of its three outputs A>B, A=B and A<B depending upon the magnitudes of
the numbers A and B has been discussed earlier. The function outputs of the three outputs
A>B, A=B and A<B can easily be represented using truth tables which can then be
written in a simplified Boolean expression form after simplifying the three function
expressions using 4-variable Karnaugh maps.
A comparator circuit that compares two 3-bit numbers A and B instead of the 2-
bit numbers has an input of 6-bits, which represents an input combination of 64.
Writing a truth table and simplifying the three expressions using the 6-variable Karnaugh maps
becomes unmanageable. A program based Quine-McCluskey method can easily handle
expression of 6 variables represented in the Canonical form (8,16,17,24,.........) A,B,C,D,E,F Σ
Q)Odd-Prime Number Detector?

A circuit that detects Odd Prime numbers between 0 and 9 has been considered
earlier. The circuit is to be improved to detect Odd Prime numbers for a decimal number
range represented by 5-bit binary numbers or in terms of decimal numbers between the
decimal number range 0 to 31.
Writing out a function table to represent the 32 input

combinations and their corresponding outputs, and then simplifying the function
expression using a 5-varaibale K-map can take up considerable amount of time.
Quine-McCluskey method can be used to easily simplify the 5-variable Boolean
expression represented in Canonical Sum form as (1,3,5,7,11,13,17,19,23,29,31) A,B,C,D,E Σ .
The minterms 1, 3, 5, 7, 11, 13, 17, 19, 23, 29 and 31 represent the 5-bit input
combinations (decimal numbers) which are Odd and Prime numbers

Q)Explain topic Function table of a comparator circuit?
Basically a comparator circuit compares two numbers and it has multiple inputs
and three outputs. There are three rules to set which is given below and it is also mentioned in
handouts.
1. The output A>B is set to 1 when the input combinations are 01 00, 10 00, 10 01, 11 00,
11
01 and 11 10
2. The output A=B is set to 1 when the input combinations are 00 00, 01 01, 10 10 and 11
11
3. The output A<B is set to 1 when the input combinations are 00 01, 00 10, 00 11, 01 10,
01
11 and 10 11
In function table.it is provided 16 different inputs and output is given after comparison; if it is
true according to above given rules then output is set 1 otherwise set 0.

Q) Explanation of kmapping ?
Karnuagh map method becomes difficult to manage when numbers of variables
exceed 4.so quine-mccluskey method is used.
In table 12.4 when comparing minterms the rule is to compare each minterm in one group with
each minterm in the other group.Basically comparison is used to eliminate common
variables.for example Please see table which is given below to compare 1 with 6, in this table
three values are different but we want only to eliminate single variable which is different and
all rest values should be common so ignore this camparison and it will get only those
camparison which has only single value eliminate like terms 1 and 3 forms a single term
eliminating variable C,forming the product term A’B’D. The comparison terms 1 and 3 are
marked as used in table 12.3. Similarly, terms 1 and 9 form a single term eliminating variable
A, forming the product term B’C’D.
Minterm A B C D
1 0 0 0 1
6 0 1 1 0
Explain?
(A>B)=A1B1'+A0B1'B1'+A1A0B0'
(A<B)=A1'B1+A1'A0'B0+A0'B1B0

handouts.
11
01 and 11 10
2. The output A=B is set to 1 when the input combinations are 00 00, 01 01, 10 10 and 11
11
01
11 and 10 11
In function table.it is provided 16 different inputs and output is given after comparison.
In comparison, when it is true according to above given rules then output is set 1
otherwise
set 0.
In table 12.5 there are 6 product terms of two variables each. Therefore the terms B’D,AC’,CD
,BC ,AD and AB are considered to be Prime Implicants. Exhaustive search for finding prime
implicants has not completed. The three variable terms in table 12.4 are compared to eliminate
another single variable. All terms that combine to eliminate a variable are represented in table
12.5.
In table 12.6,circles are marked in cells having x, which represent minterms covered by only a
single Prime Impicant (means single cross represent in column).Thus the minterms 1, 6 and 8
are covered by only the Prime Implicants B’D, AC’ and BC respectively.
Lecture no 13
What is Combinational Logic?

Individual gates AND, OR and NOT, NAND and NOR Universal Gates and XORand XNOR gates perform
unique functions. These gates in their individual capacity can not perform any useful function. The Logic
Gates have to be connected together in different combinations to form Logic Circuits that are able to perform
some useful operation like addition , comparison etc. These combinations of gates which results in a
circuit used to perform some function are known as Combinational Logic.
The function of any Digital Logic circuit is represented by Boolean expressions.In the examples discussed
earlier, Boolean expressions for various functions have been determined. Two forms of representing functions
through Boolean expressions are the SOP and POS expressions. These two types of Boolean expressions are
implementedusing a combination of gates to form Combinational Logic Circuits.
Q) Explain QuinMcCluskey simplification method ?
The Quin McCluskey method is suitable for the simplification of Boolean expression having
more than 4 variables. K-map is not much suitable for Boolean expression having more than 4
variables therefore Quin McCluskey method is used in such situation. This method is based on
exhaustive search. It is a two step method. In the first step prime implicants are found by
exhaustive search. In the second step, minimal prime implicants are found.

Q) How to Adding two BCD numbers?
1.Adding15and17.
0001 0101
0001 0111
0010 1100
1100 is not a valid BCD number. So we will add 0110 in it.
1100
0110
1 0010
1 is the carry. Add carry in 0010 above (left most digit).
0010
0001
0011
So final answer is,
0011 0010 (32)
2. Adding 38 and 43.
0011 1000
0100 0011

0111 1011
1011 is not a valid BCD number. So we will add 0110 in it.
1011
0110
1 0001
1 is the carry. Add carry in 0111 above.
0111
0001
1000
So final answer is,
1000 0001 (81)
Q) Explain operation of Adjacent 1,s Detector circuit?
The Adjacent 1s Detector circuit takes 4-bit input and if two adjacent 1s are
detected then the output is set to high. As input is of 4-bits, therefore 24 (16)
different combinations can be applied at input and output is high only when adjacent 1s
are detected at input. In table 13.6, 16 different possible inputs and their respective

outputsare
For example, 0110 has two adjacent 1s so output is high, whereas 0101
has not adjacent 1s so output
is low.
Lecture no 14
Q)Half Adder and Full Adder?
A single bit binary adder circuit basically adds two bits and a carry bit, generated by the
addition of the least significant bits. The output of the single bit adder circuit generates a
sum bit and a carry bit. A single digit binary adder circuit therefore has three inputs, one
representing single bit number A, the other representing the single bit number B and the
third bit represents the single bit carry. The single bit binary adder has two bit output. One
bit represents the Sum between numbers A and B. The other bit represents the carry bit
generated due to addition.
In Digital logic terminology the adder which has been described is known as a full adder. An
adder circuit that only has two bit input representing the two single bit numbers A and B and
does not have the carry bit input from the least significant digit is regarded as a half-adder.
The block diagrams represent a Half-Adder and a Full-Adder

Block diagrams of Half-Adder and Full-Adder
Q)Carry Propagation?
Parallel Binary Adders can be implemented by connecting the required number of 1-bit full
adders in a configuration represented in figure 14.9. However, there is a practical limitation
to the number of 1-bit Full-Adders that can be connected in parallel. In the 4-bit Parallel
Adder, the Most significant bit adder which adds bits A 3 , B 3 and the Carry bit C 3 , can not
proceed until it receives the Carry from the next least significant 1-bit adder which adds bits
A 2 , B 2 . The A 2 B 2 bit adder can not proceed unless it receives the carry input C 2 from the
A 1 , B 1 adder. The A 1 , B 1 adder in tern depends on A 0 , B 0 adder to provide the carry input.
Thus the carry has to propagate through each Full-adder before it reaches the last or most
significant full adder.
Assume that each gate has a propagation delay of 10 nsec. A 1-bit Full Adder generates a Carry out after 30
nsec. For a 4-bit Parallel Adder Full-adder the Carry out from the most significant adder would be after 120
nsec. The delay can increase to prohibitive levels if 8-bit, 16-bit or 64-bit parallel adders are implemented.
64-bit parallel adders are used by computers
Q)simplifying the expressions using K-Map, we follow three steps procedure.?
In Step 1, we map the terms in K-Map.

In Step 2, we make groups of adjacent 1s. We try to make groups as large as possible. The groups can
comprise of 2, 4, 8, 16,… cells. A single 1 which is not adjacent to any other 1 is considered as a group of
a single cell.
In Step 3, we determine the minimal product terms. Each group forms a unique Minterm. From each
group we write only those variables which remain constant within that group. It means we write only
those variables that exist only in one form in that group, either complemented or non-complemented.
Now considering an example (B.C’ + A.C + B’.C) at page 94. K-Map is given as:
AB\C 0 1
00 0 1
01 1 0
11 1 1
10 0 1
We will make groups now.
The first group will be made of two adjacent 1s in cells 2 and 6, as shown in red color in figure
below.
AB\C 0 1
00 0 1
01 1 0
11 1 1
10 0 1
The product term from this group is BC’. As B and C’ are constant values in this group (exists
only in one form), whereas A is changing values in this group from A’ to A (present in both form
complemented and non-complemented).
The 2nd group will be made of two adjacent 1s in cells 5 and 7, as shown in blue color in figure
below.
AB\C 0 1
00 0 1
01 1 0
11 1 1

10 0 1
The product term from this group is AC. As A and C are constant values in this group (exists
only in one form), whereas B is changing values in this group from B to B’ (present in both form
The 3rd group will be made of two adjacent 1s in cells 1 and 5, as shown in black color in figure
below (Cell 5 is overlapped in two groups).
AB\C 0 1
00 0 1
01 1 0
11 1 1
10 0 1
The product term from this group is B’C. As B’ and C are constant values in this group (exists
only in one form), whereas A is changing values in this group from A’ to A (present in both form

So the final simplified SOP expression from this K-Map is:
B.C’ + A.C + B’.C
Q)what is meant by minimal number of largest groups covering unique cells or adjacent
cells inPOS k- mapping?
This statement means that in a K-Map we always try to make groups of adjacent cells as
large as possible. In SOP K-Map we make group of each and every 1 present in the K-Map.
We can make groups of 2, 4, 8, 16,... cells. A single 1 which is not adjacent to any other 1 is
considered
as a group of a single cell.
Same rules are followed in POS K-Map with just a difference that we make groups of 0s present
in the K-Map, instead of 1s.
Q)what are pos and sop in k map and we can use pos and sop in kmap?
The Product terms in the Standard SOP (Sum OF Product) form are known as Minterms
and the Sum terms in the Standard POS (Product OF Sum) form are known as Maxterms.

1 or 0 are placed according to minterm and maxterm term expression. Please firstly see the
table 9.5 then you will understand A represents in minterm is 1 and in maxterm is 0 and A’
represents in minterm is 0 and in maxterm is 1.e.g
The Standard SOP (Minterm) expression having a Domain of three variables

ABC’ + AB’C’ + A’BC’ is mapped into 3-Variable Karnaugh Map.
A\BC 00 01 11 10
0 0 0 0 1
1 1 0 0 1
You can see ABC’ in binary (110), this number check in table and put 1 in second row and last
column. Same like in second expression AB’C’, put 1 in (100) means second row and first
column. Lastly check third expression A’BC’, put 1 in (010) means first row and last column.
Yes, POS and SOP expression can be used in K-map.
What is X?
Don’t care Conditions are those it cannot occur or mentioned.
For example:
Only the first ten input (0 to 9) states can occur and the last 6 inputs never occur. The function table for the conditions that never occur it is
considered don’t care Conditions and marked as x and x outputs can be considered as 0 or 1.

Lecture no 15
Arithmetic and Logic Unit (ALU)
Microprocessors have Arithmetic and Logic Units, a combinational circuit that can perform any of the
arithmetic operations and logic operations on two input values. The operation to be performed is selected
by set of inputs known as function select inputs.
There are different MSI ALUs available that have two 4-bit inputs a 4-bit output and three to five function
select inputs that allows up to 32 different functions to be performed. Three commercially available 4-bit
ALUS are
 74XX181: The 4-bit ALU has five function select inputs allowing it to perform 32 different
Arithmetic and Logic operations.
 74XX381: The 4-bit ALU only has three function select inputs allowing only 8 different arithmetic
and logic functions. Table 15.6
 74XX382: The 4-bit ALU is similar to the 74XX381, the only difference is that 74XX 381 provides
group-carry look-ahead outputs and 74XX382 provides ripple carry and overflow outputs

Input
S2 S1 S0 Function
0 0 0 F=0000
0 0 1 F=B-A-1+Cin
0 1 0 F=A-B-1+Cin
0 1 1 F=A+B+Cin
1 0 0
1 0 1 F=A+B
1 1 0 F=A.B
1 1 1 F=1111
 Table 15.6 Function Table of 74XX381 4-bit ALU
Q) Explain Binary Division ?
Binary division is similar to the decimal division. The division of 1101 by 101 is shown in the

figure 2.1, at page 19 in the handouts.
Explanation:
Multiply 101 with 1 gives 101 in the first step. Now subtracting 101 from 110, gives the
remainder 01. Putting down the remaining 1 from the original number (1101) gives 011.
Now multiply 101 with 0 gives 000, and final remainder is 11.
As 11 is less that 101, we stop the division process here.
The above quotient (10) is the result of this division.
Lecture no 16
the concept of conversion between POS and SOP using K-map
While converting the POS expression into SOP expression, we follow the following
steps:
1. Map the POS expression into the K-Map by putting 0 for all the Maxterms present.
2. Fill all the remaining empty cells with 1.
3. Grouping of adjacent 0s gives the Maxterms and write them in the form of POS.
4. Grouping of adjacent 1s gives the Minterms and write them in the form of SOP.
As shown in example at page 102 in the handouts. POS expression,
(A+B’+C).(A+B’+D’).(B+C+D’)+(A’+B’+C’+D) is given.
Mapping the Maxterms in the K-Map gives:
AB\CD 00 01 11 10
00 0
01 0 0 0
11 0
10 0
Mark all the empty cells with 1, we get

AB\CD 00 01 11 10
00 1 0 1 1
01 0 0 0 1
11 1 1 1 0
10 1 0 1 1
Grouping all the adjacent 1s (as shown in the handouts) gives the equivalent SOP
expression, B’D’+B’C+ABC’+ABD+A’CD’
Q)how we can evaluating the expression? and how made its truth table?
Evaluating the expression through the gates which are used in output expression and simplification the
expression through the rules of Boolean algebra which is mentioned in page no:73 of handout.In example
1,simplification expression through these rules which are applied, firstly used Demorgan’s second theorem
then first theorem and apply these rules 9 and 8.Lastly this expression A’.B’.C.D put into truth table and only
this case A=0 AND B=0 AND C=1 AND D=1, output will be 1 otherwise in all cases it will be 0.

How carry added?

Carry is added to the next most significant digit;
otherwise the result is not accurate. See the solved example below:
0011 1000
0001 1001
0100 10001
As carry is generated by adding 1000 and 1001, we will add 0110 in 10001.
10001
0110
1 0111
1 is the final carry left. Add carry in 0100 above (next most significant digit).
0100
0101
So final answer is,
0101 0111 (57)

Lecture17
Q)can we say latches and flip flop are same? if they are different then how we can defines both?
A latch is asynchronous device and does not have a clock signal. The outputs changes as soon as the
changes in inputs occur (or at least after a small propagation delay). A latch is the level triggered
device, the output of present state and input of the next state depends on the level that is binary input 1
or 0.
Flip flop works depending on the clock pulses. It is an edge triggered device, the output and the next
state input changes when the change in clock pulse occurs, whether it can be a +ve or –ve clock pulse.
•
Q)when a circle is drawn on the Karnaugh map for grouping purpose, then entries in the map
are vanished. ?
When you draw circle or any AutoShapes then right-click on the image after selecting and follow the
steps mentioned below:
1- From drop down menu after right-click, select Format AutoShape. A new window will be
displayed infront.
2- Then in Wrapping style, select the option Behind text, and then click OK.
Q) In 74XX138 3-to-8 decoder my question is XX stands for?
xx part in 74xx138 identifies the switching speed of the gate. xx is replaced by AS, LS, etc by the
manufacturer depending on the switching speed. You can see the details at page 61 in the
handouts.
Lecture no 18
Q)Demultiplexer as a Serial to Parallel Converter?
de-multiplexer which by name is clear that it is invers of the multiplexer that is, it takes the data
stream as input from serial transmission line and sends the concerned data bits to the (pins shown on
the left side) pin to whom the destination of that data is connected. You can see the three pin input at
the bottom which may be used to select the particular output pin for each bit. In fact there is buffer
memory that is used to distribute the bits of each output pin due to which it look like all the pins are
receiving the data in parallel.

Q)explain the GAL22V10?

The GAL22V10 has 22 inputs and it is organized as 44 lines. The vertical lines in groups of four
represent the inputs and the first group of four vertical lines represents the input from the GAL input
pin and the input from the OLMC. The horizontal lines represent the product terms.
What is Logic Function Generator.?

A multiplexer can work as a logic function generator. The purpose it serves is that it can generate
expression of a function, against the values mentioned in the output of a truth table. Actually on the
basis of truth table we connect the different combinations of data select inputs to either 0 or 1. Those
combinations at which the output is 1 in the truth table are connected to 1, whereas all other
combinations are connected to 0. We apply all the input combinations of data select inputs, and final
output is generated to 1 or 0 depending on the input combination applied. In this way we can get the
function in SOP form.
Lecture no 19
Q)explain the table of (19.15) 4 x 3 PLA device. how we can get output through this PLA. and
also tell me 20.2 4 x 3 PLA Odd-prime number device. ?
Basically PLA has a programmable AND gate and OR gate arrays and it can be programmed to
implement any SOP logic expressions. As you mention table 19.15, basically it is figure 19.15 which
shows the programmed 4 x 3 PLA Device, 4 represents the four number of inputs and 3 represents
three number of outputs and output can be gotten from sum of product terms such as in this diagram
L1,L2,L3,L4 are four inputs and there are six products terms provided by AND gate P1, P2, P3, P4 P5
and P6. The outputs of each of the six AND gates are connected to the input of the OR gate array and
then each OR gate can perform a sum operation on six product terms. The first OR gate sums product
terms P1, P2, P3 and P5, second OR gate sums the product terms P2, P4 and P6. and third OR gate
sums the product terms P1, P3, P4 and P6.
•
Q)Kindly explain the Odd-Prime number of minters.
explain the column_row intersection&explain the figure 20.3 fuses.
and also explain the test vectors?

PLA (Programmable Logic Array) and its functionality then you can easily implement any example
according to it. The Odd-Prime Number generator can be implemented by programming the 4 x 3
PLA and PLA is discussed in MDB of lesson no: 19.
E2CMOS is one of Integrated Circuit Technologies and it is the combination of CMOS and NMOS
technologies.it is mostly used to implement Programmable Logic Devices. (GAL) Generic Array
Logic uses E2CMOS technology which is Electrically Erasable CMOS instead of Bipolar technology
and fusible links. It can be programmed to connect a column with a row. In this logic at each column
and row intersection is known as a cell and the purpose of this cell is that ‘on’ state connects the
column with the row and a
cell in the ‘off’ state disconnects the column and row cell.
Test vectors are used to test and verify the design of the logic circuit before committing it to the PLD.
If any flaws are detected during the testing process the design must be debugged and submitted for
recompilation.
•
Q)why are test vector and and truth table preform the assentialy the shame ?
Because test vectors are used to faster test throughput, lower cost fixtures, more reliable test
measurements, and higher fault coverage.
•
Lecture no 20
What is Look-ahead carry Generator ?
Look-ahead carry basically overcome the carry propagation problem by calculating the carry signals in
advance and based on the input signals. This type of circuit is called as look-ahead carry adder circuit
and it is based on the fact that a carry signal will be generated in two cases: when both bits A and B are
1, or when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

Q) Explain ALU?
Arithmetic and Logic Units circuit
basically performs different logical functions like AND,
OR, NOT, ADD, SUBTRACT etc on two input
Q)What is Comparator Circuit?
handouts.
2.
3. 11 01 and 11 10
2. The output A=B is set to 1 when the input combinations are 00 00, 01 01, 10 10 and
3. 11 11
5. 01
11 and 10 11
Q) 1st Adjacent ?
it is described SOP based Implementation of the Adjacent 1s Detector Circuit,

only adjacent 1s are detected in the 4 input table like 0011, 0110, 0111,1011, 1100, 1101, 1110
and 1111 and output will be 1 only in these given binary numbers. You know in SOP expression
AND, OR and NOT gates are used. Please firstly convert this numbers in to alphabetic form like first
binary number represents 0011 and also represents as A’B’CD and you notice there are 10 zeros
in all series of binary numbers its mean it has 10 NOT gates, 8 AND gates and 1 OR gates after that
put 1 in to table according to rule which is given above then draw the K-maps and then you will
get the expression AB+CD+BC through k-maps. Lastly draw the diagram according to simplified SOP
expression.
Lecture no 21
Q) What is GAL16V8 device?

GAL16V8 device has eight inputs, two special function input pins and eight pins that can
be used as inputs or output. The architecture of the GAL16V8 is similar to that of a PAL
and it is designed to be programmed in one of the three available modes to emulate
most of the existing PALs, thus replacing the PAL. The three modes in which PALs are
programmed are
· Simple
· Complex
· Registered
The simple and complex modes are associated with the Combinational Logic whereas
the Registered mode is associated with Sequential Logic.
The GAL16V8 has eight OLMCs each connected to eight product terms. Each
product term is implemented using a 32-bit input AND gate. The 32 inputs comprise of
the 16 complemented and un-complemented inputs of the 8 input pins and 16
complemented and un-complemented inputs of the 8 input/output pins that can be
configured as input pins.
Q)What is ABEL?
ABEL which is an acronym for Advanced Boolean Expression Language is a

hardware description language used for implementing logic designs using PLDs.
ABEL is a device-independent language and can be used to program any type of PLD.
ABEL is run on a computer connected to a PLD programmerwhich programs the PLD.
ABEL provides three different text-based methods for describing and entering a logic
design.
The three methods are
 Boolean Equations
 Truth Tables
 State Diagrams

The Boolean Equations and the Truth Table method are used for Combinational Logic
Circuits.
The State Diagram is used specifically for Sequential Logic circuits.
The Boolean Equations and the Truth Table method can also be used for describing and
entering Sequential Logic Circuits.
Q)Write the four names of OLMC configurations?
The four OLMC configurations are
· Combination Mode with active-low output
· Combinational Mode with active-high output
· Registered Mode with active-low output
· Registered Mode with active-high output
Lecture no 22
Q)Define Latches and Flip-Flops?
Latches and flip-flops are the basic elements for storing information. One latch or flip-
flop can store one bit of
information. The main difference between latches and flip-flops is that for latches, their
outputs are constantly
affected by their inputs as long as the enable signal is asserted. In other words, when they
are enabled, their content
changes immediately when their inputs change. Flip-flops, on the other hand, have their
content change only either
at the rising or falling edge of the enable signal. This enable signal is usually the
controlling clock signal. After the
rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes.
There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major
differences in these
flip-flop types are the number of inputs they have and how they change state. For each
type, there are also different
variations that enhance their operations. In this chapter, we will look at the operations of
the various latches and flipflops.
Q)Important thing for Sequential Logic Design ?
An important thing to note with sequential circuits is that duration of the activating pulse
should be low enough so that the secdorey inputs do not change state in same activating
pulse. Allowing the clock pulse to be too long would result in incorrect circuit function,
as there will be two different secondary input values for one clock cycle and therefore
lead to potentially two state changes in one clock.
It would be benefical to have our storage elements to be edge triggered, as this would
mean that the clock pulse can be as long as we would like it to be and the circuit would
behave in the same way. This is why flip-flops are used as they are edge triggered storage
devices.

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CS302 Lecture Wise Questions By Virtualians.

Q)How to count Result of binary encoding?

Q) Rule for Octal Addition?

Example: The addition between two octal numbers (8 A 5 C) 16 and (F 3 9 A) 16

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The resulting octal number is (601) 8

Q)How Hexadecimal addition is done?

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The resulting hexadecimal number is (17DF6) 16

The resulting hexadecimal number is (67EF) 16

Q) What is Flip flop?

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Q) What is Parity Generator?

Q) What is BCD and its use?

To represent decimal number in BCD, we write BCD codes of individual digits.

BCD code for 23 is 0010 0011

Q)What is BCD Adder Circuit ?

Q) What is Standard form of Product terms?

The Standard SOP (Minterm) expression having a Domain of three variables

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Q) What is GAL and its Use?

What is Logic Function Generator?

Digital representing of quantities

Q)What are the differences between digital and analog circuits?

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considered "off", and anything above 4.5V is considered "on".

Q) Difference between CMOS and TTL?

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1. TTL circuits utilize BJTs while CMOS circuits utilize FETs.

3. TTL circuits consumes more power compared to CMOS circuits at rest.

Q) What is the use of caveman?

Q) what do u meant by Sequential circuits ?

Q) What is difference between digital system and values?

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Q) Decimal to binary conversion using sum of weights?

procedure again until weight 1 is reached

So binary number for decimal 392 is 110001000

Q)Explain it please how 2 power 0 =1?

Q)Signed and Unsigned Binary Numbers

negative numbers are represented by the – sign.

As mentioned in the Overview all forms

• MSB set to 1 indicates a negative number

Q)Range of Signed and Unsigned Binary numbers?

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Binary Addition Logic

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Key Subtraction Results for Binary Numbers

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Q)What is the 1's and 2's complement?

A two's-complement system or two's-complement arithmetic is a system in which negative numbers

There are two steps of taking 2’s complement of a number.

i- Take 1’s complement of the number, that is, change 0 to 1 and 1 to 0.

The number is 01101

So 10011 is the 2’s complement of 01101.

Q)What are PLD devices?

Q) How PLDs are programmed?

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10010110 (original number)

10010110 (original number)

2’s complement arithmetic is commonly used in computers to handle negative numbers.

First, write the binary of +39

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Now, take its 1's complement (by inverting the bits)

Finally, the 2's complement (by adding 1 to its 1's complement)

So, decimal -39 = 11011001 2's complement

Q)Is BCD a positional code?

Q) Can we directly Convert octal numbers into Hexadecimal?

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Octal Number: 7564

1111 0111 0100 = F74 (Hexadecimal)