Lesson8 CMOS Gates
Lesson8 CMOS Gates
Lesson8 CMOS Gates
Ali El Kateeb
U of M- Dearborn
ECE 514
Overview
NOR and NAND gates
Logic Formation
Layout of complex logic gates
CMOS transmission gates
NAND2
The nFETs provide a path from the output to ground if and only if
both A=1 AND B=1
If any one of nFET is OFF, the output has a strong connection path
to the power supply Vdd through one of the pFETs
NOR2
When either A=1 OR B=1 (or both), then at least one of the
nFET is conducting and the output voltage is 0v
The only time the output is high when both A=0 AND B=0
General CMOS Static Logic Gates
Features of the topology are:
Every input variable is connected to both
nFET and pFET
β pMOS only
B
A
α
C nMOS only
General CMOS Static Logic Gates
Features of the topology are:
Two logic arrays are used to implement the logic
function
One array consists of nFETs with the logic block
connecting the output to ground
The other, pFET, build a logic block connected from the
output to VDD
When the inputs are stable, only one logic block is
closed, i.e., either pFET or nFET
Low DC power dissipation
N-input gate requires 2N transistors (one for nFET
and one for pFET)
CMOS Static Logic Gates
Static logic gate can implement And-Or-Invert (AOI)
and OAI logic functions easily
Correspond to Sum of Products (SOP) and Product
of Sum (POS)
The basic rules of logic formation can be summarized
as following:
Rules apply to group of nFETs that implement
individual functions:
Series-connected nMOSFETs give the NAND operation
Parallel-connected nMOSFETs give the NOR operation
Rules apply to group of pFETs
Series-connected pMOSFETs to implement the NOR
operations
Parallel-connected pMOSFETs to implement the NAND
operation
CMOS Static Logic Gates:AOI example
The structure of the pFET logic array is the dual of
the nFET connections
nFETs is series require that the corresponding
pFETs be in parallel
Example: F = (AB + C)’
CMOS Static Logic Gates:XOR Example
Example: F = A XOR B (i.e., F= A’B + AB’)
Create the AOI form, which leads directly to the gate logic, i.e.,
F = (AB +A’B’)’
-
CMOS Static Logic Gates:XNOR Example
Example: F = AB + A’B’
Layout of complex logic gates
Logic formation rules are based on series and parallel
combinations of MOSFETs
Layout techniques can be divided into these groups
Series-connected MOSFETs
Parallel-connected MOSFETs
Input and output wiring
Wiring to ground and VDD
Layout of complex logic gates
Series-connected MOSFETs
n+ and p+ regions can be shared between two transistors
Since drain and source electrodes are not defined until the
voltage are applied, a common n+ region serves as either a
drain or source as required
As the transistor resistance are in series, the RC time
constant of the group can be a limiting factor in the
switching time
Layout of complex logic gates
Parallel-connected MOSFETs
Parallel connections can be achieved by using n+
and p+ regions in connections with metal
interconnect routing
Layout of NAND2 and NOR2 gates
Series-parallel logic is required for
NAND2 and NOR2 layout
NAND2: Two nFETs in series and two pFETs in
parallel
NOR2: Two nFETS in parallel and two pFETs in
series
Basic Layout Guidelines
Do wire planning before cell layout
Assign preferred direction to each layer
Group p’s and n’s
Determine input/output port locations
Power, ground must be wide
Determine cell pitch
Height of tallest cell
Number of over-the-cell tracks and wire lengths
Use metal for wiring
Use poly for intra-cell wiring only
Use diffusion for connection to transistors only
Do stick diagram first!
Basic Cell Layout Guidelines
P-N spacing is large, so keep pMOS
together and nMOS together
Vdd and ground distribution must be in
wide metal
Vdd runs near pMOS groups
Ground runs near nMOS groups
Layers in alternate directions
M1 and M2 should run in orthogonal
directions.
Transistor Layout
No connection
Connection
connected transistor
Basic Layout Planning
Need to route power and ground (in metal)
Keep nMOS devices near nMOS devices and
pMOS devices near pMOS devices
nMOS near ground and pMOS near Vdd
Run poly vertically and diffusion horizontally
with m1 horizontally
Keep diffusion wires as short as possible
just enough to make transistors
All long wires in m1 and m2
Typical Cell Layout Plan
Inverter
pMOSFETs: near VDD
nMOSFETs: near GND
Vdd
Gnd
B A B C
Vdd
out out
C
Gnd
A
Switches
How to built switches from MOS transistors?
N-type switch
Require one transistor and one gate signal
Transmit 0 well, but when Vdd is applied to the drain, the
voltage at the source is Vdd-Vtn
As Vgs is always equal to Vds, the NMOS transistor is either in
0 saturation or off
When switch logic drives gate logic, n-type switches can cause
electrical problems
When n-type switch driving a complementary gate cause the gate
to run slower when the switch input = 1
Since pulldown current is weaker when a lower gate voltage
is applied
Vdd−Vth The complementary gate’s pulldown will not suck current off
the output capacitance as fast as it should be
Switches
How to built switches from MOS transistors?
P-type switch
When Vin = 0 and Vout = Vdd
Cload will be discharged through P transistor until Vout = Vtp
P-device will stop conducting
Vin Vout
Cload
Review: Voltage Degradation
Both nMOS and pMOS have voltage
degradation problems
nMOS degrades logic ‘1’
pMOS degrades logic ‘0’
Vdd−Vth Vdd
0 |Vth|
CMOS Transmission Gate
To solve voltage degradation problem, use
both nMOS and pMOS
Need both true and complement of control
Bi-directional gate
When S=0, both FETs are in cutoff (TG modeled as open
switch)
Setting S to 1, turns on both FETs (TG modeled as closed
switch) Other symbols used
S
S
A B A B
S’ S’
CMOS Transmission Gate
Electrical model of TG