LAB 5-DIGITAL LOGIC SIMULATION (1112) FFF

POLYTECHNIC of TUANKU SULTANAH BAHIYAH
ELECTRICAL ENGINEERING DEPARTMENT

EC 302 ELECTRONIC COMPUTER AIDED DESIGN
DEE3061 - COMPUTER AIDED DESIGN CLO/GSA MARKS

PRACTICAL WORK 4 - DIGITAL LOGIC SIMULATION
NAME : MUHAMMAD FAIZ FAHMI BIN PILEHAN CLO2

MATRIX NO. : 16DET17F1112 CLO3
CLASS : DET3B TOTAL
OBJECTIVES
At the end of this lab session, the student should be able to:
1. Describe the concept of the logic level simulation

2. Describe and show how to setup digital /logic sources
3. Obtain the digital and analogue output of the circuit
4. Conduct simulation of Full adder circuit
5. Plot the input and output of the digital simulation
6. Compare the simulation results with the theoritical results Look at Simulation output and develop Truth
Table for (AND Gate, OR Gate, XOR, NOT Gate, NAND Gate, NOR Gate, XNOR)
MATERIAL AND APPARATUS
Personal Computer with Orcad Family Release 9.2 Software
THEORY
A logic gate is an elementary building block of a digital circuit . Most logic gates have two inputs and one
output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1),
represented by different voltage levels. The logic state of a terminal can, and generally does, change
often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V),
while the high state is approximately five volts positive (+5 V).
There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the same
way as the logical "and" operator. The following illustration and table show the circuit symbol and logic
combinations for an AND gate. (In the symbol, the input terminals are at left and the output terminal is at
right.) The output is "true" when both inputs are "true." Otherwise, the output is "false."
Figure 5.1: AND gate symbol
Input 1 Input 2 Output

0 0 0
0 1 0
1 0 0
1 1 1 [email protected]
Table 5.1: AND gate truth table
The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive "or."
The output is "true" if either or both of the inputs are "true." If both inputs are "false," then the output is
"false."
0 0 0
0 1 1
1 0 1
Figure 5.2: OR gate symbol 1 1 1
Table 5.2:OR gate truth table
The XOR ( exclusive-OR ) gate acts in the same way as the logical "either/or." The output is "true" if
either, but not both, of the inputs are "true." The output is "false" if both inputs are "false" or if both
inputs are "true." Another way of looking at this circuit is to observe that the output is 1 if the inputs are
different, but 0 if the inputs are the same.

0 0 0
0 1 1
1 0 1
1 1 0

Figure 5.3: XOR gate symbol Table 5.3: XOR gate truth table

A logical inverter , sometimes called a NOT gate to differentiate it from other types of electronic
inverter devices, has only one input. It reverses the logic state.

Input 1 Output
0 1
1 0
Figure 5.4: Inverter or NOT gate symbol Table 5.4: Inverter or NOT gate truth table
The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the logical
operation "and" followed by negation. The output is "false" if both inputs are "true." Otherwise, the
output is "true."
Figure 5.5: NAND gate symbol
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Table 5.5: NAND gate truth table
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both inputs are
"false." Otherwise, the output is "false."
0 0 1
0 1 0
1 0 0
1 1 0
Figure 5.6: NOR gate symbol Table 5.6: NOR gate truth table
The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output is "true"
if the inputs are the same, and"false" if the inputs are different.

0 0 1
0 1 0
1 0 0
1 1 1
Figure 5.7: XNOR gate symbol
Table 5.7: XNOR gate
truth table
Using combinations of logic gates, complex operations can be performed. In theory, there is no limit to
the number of gates that can be arrayed together in a single device. But in practice, there is a limit to the
number of gates that can be packed into a given physical space. Arrays of logic gates are found in digital
integrated circuits (ICs). As IC technology advances, the required physical volume for each individual logic
gate decreases and digital devices of the same or smaller size become capable of performing ever-more-
complicated operations at ever-increasing speeds.
Half Adder
In electronics, an Adder is a device that performs the addition of two numbers.

A Half Adder is a Logic Circuit that performs 1-bit binary addition. Given that P and Q are two 1-bit binary
numbers, S is the 1-bit Sum of P and Q, and CO is the CARRY OUT bit. Mathematically, as shown in Figure
5.8, S and CO form a 2-bit Arithmetic Sum of P and Q, with CO being the Most Significant Bit (MSB). Figure
5.9 shows all possible cases for 1-bit binary addition and Table 5.8 is the Half Adder Truth-Table.
1 ←P
+) 1 ←Q
1 0
↑ ↑
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CO S
Figure 5.8: Addition of two 1-bit binary numbers
0+0=0
0+1=1
1+0=1
1 + 1 = 0 with a Carry of 1
Figure 5.9: All possible cases for 1-bit binary addition
Table 5.8: Half Adder Truth-Table
Inputs Outputs
P Q CO S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
According to the Truth-Table, if we consider the logic relation between the Inputs and Outputs of a Half
Adder, S is the XOR operation of the Inputs and CO is the AND operation of the Inputs. This means that
the Half Adder circuit can be implemented with just two Logic Gates: an XOR Gate and an AND Gate,
Figure 5.10
Figure 5.10: Half Adder
Full Adder
The binary full-adder is very useful because it can add three digits at a time. If you recall from our
binary addition section, there are sometimes carries that need to be added along with the two other
digits. This requires the addition of three bits at a time, which is exactly what the full-adder is used for.
Figure 5.11 show the logic diagram for the more complex full-adder, which employs two HA's (half-
adders) as well as an OR gate.
Figure 5.11 Full Adder
As you can see, there are now three inputs: A, B and C. A and B are usually used for the two bits which
would be normally added, while C is usually used as a carry from a lower place value. As you can see,
inputs A and B go into a half-adder. The sum of the half-adder is sent as one of the inputs (along with
input C) to the second half-adder.
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The sum of the second half-adder is the sum of all three inputs. If there was a carry from either or both
of the half-adders, the Carry output for the full adder is HIGH. There are 8 possible combinations of inputs
for the full-adder, all recorded on the Table 5.9 full-adder truth table:
Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 5.9: Full Adder Truth-Table
This experiment describes how the digital logic simulation can be performed. Table 5.10 shows the
component that used in this experiment.
No. Name Part Component Symbol

1. 3 Input AND Gate 7411 U 8A
1
2 12
13
7411
2. 2 Input OR Gate 7432 U 6A

1
3
2
7432
3. XOR 7486 U 11A

1
3
2
7486
4. Inverter or NOT Gate 7404

U 10A
1 2
7404
5. 2 Input NAND Gate 7410 U 9A

1
2 12
13
7410
6. 2 Input NOR Gate 7402 U 7A

2
1
3
7402
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6. Digital Component Source STIM1 O F F T IM E = .5 u S D S T M 3

O N T IM E = .5 u S C LK
D ELAY =
S TA R TV A L = 0
O PPVAL = 1
PROCEDURE:
A. Simulation of Basic Logic Gates
i) 3-Input AND Gate Schematic
1. Draw the 3-Input AND Gate Schematic in Figure 1
Figure 1: 3-Input AND Gate Schematics
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2. Use the DigClock component as a source and set the value for DSTM1 and DSTM2 acording to Figure 1
3. Create a New Simulation Profile
4. Set up the Simulation, use the Transient Analysis and set the:
Run to Time: 8m
Start saving data after time: 0
Maximum step size: .8m
5. Select Voltage Level Marker from the top toolbar and place the voltage markers at A, B, C and Q.
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6. Run the simulation

7. View the results
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8. Based on the results, fill in Table 1 below
Table 1: Truth table for 3-Input AND Gate Schematic

INPUT OUTPUT
A B C Q
0 0 0 0
0 0 1 0
1 0 0 0
1 0 1 0
0 1 0 0
0 1 1 0
1 1 0 0
1 1 1 1
ii) 2-Input OR Gate Simulation Settings
1. Draw the 2-Input OR Gate Schematic in Figure 2
Figure 2: 2-Input OR Gate Schematic
2. Repeat steps 2 untill steps 7 in section A(i)
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3. Based on the results, fill in table 2 below
Table 2: Truth Table for 2-Input OR Gate
INPUT OUTPUT
A B Q
0 0 0
1 0 1
0 1 1
1 1 1
iii) 2- input XOR Gate
1. Draw the 2-Input XOR Gate Schematic in Figure 3
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Figure 3: 2-Input XOR Gate
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Table 3: Truth Table for 2-Input XOR Gate

INPUT OUTPUT
A B Q
0 0 0
1 0 1
0 1 1
1 1 0
iv) Inverter or NOT Gate
1. Draw the Inverter Gate Schematic in Figure 4
Figure 4: Inverter or NOT Gate
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Table 4: Truth Table for Inverter or NOT Gate

Input Output
A B
0 1
1 0
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v) 3-Input NAND Gate Schematic
1. Draw the 3-Input NAND Gate Schematic in Figure 5
Figure 5: 3-Input NAND Gate Schematic
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Table 5: Truth Table for 3-Input NAND Gate

INPUT OUTPUT
A B C Q
0 0 0 1
0 0 1 1
1 0 0 1
1 0 1 1
0 1 0 1
0 1 1 1
1 1 0 1
1 1 1 0
vi) 2-Input NOR Gate Schematic
1. Draw the 2-Input NOR Gate Schematic in Figure 6
Figure 6: 2-Input NOR Gate Schematic
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Table 6: Truth Table for 2-Input NOR Gate

INPUT OUTPUT
A B QBAR
0 0 1
1 0 0
0 1 0
1 1 0
B. Half Adder Circuit
1. Draw the following schematic of the half adder circuit in Figure 7
Figure 7: Half Adder Circuit
2. Use the DigClock component as a source

4. Set up the Simulation, use the Transient Analysis and set the:
Run to Time: 4us
Start saving data after time: 0
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5. Select Voltage Level Marker from the top toolbar and place the voltage markers at A, B, S and C.
6. Run the simulation

7. View the results
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Table 7: Truth table for Half Adder Circuit
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
QUESTION:
1. Draw the following schematic of the full adder circuit in Figure 8 below
Figure 8: Full Adder Circuit

3. Run the simulation until 4us
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4. Visualize the output at A0, B0, Cin, S1 and Cout
5. View the results
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Table 8: Truth table for Half Adder Circuit
Inputs Outputs
A0 B0 Cin Sum(S1) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
DISCUSSION
In this lab, we need to simulate the digital logic gates in order to gain the
output/performed and hence develop a truth table. They are seven basic logic gates,
AND, OR, XOR, NOT, NAND, NOR, XNOR and Adder circuit. We use computer lab
with Orcad software. In the beginning, we have to build and construct the circuit given
for each gate. The first gate is AND gate. Use and choose the name or part given in the
circuit. For AND gate, it use digital component as source and 3 input AND gate. Adjust
the value and set the simulation by following the information provided. After that, put a
voltage level maker in line of all input. Next, run the simulation and we get the output.
The output of this gate is true only when all the inputs are true. When one or more inputs
of the AND gate’s are false, then only the output of the AND gate is false. Then, build a
truth table for the gate simulation. Next is OR gate. OR gate use 2 input OR gate and we
change the value as given. Build the circuit and repeat the procedure from AND GATE.
The output of the OR gate is true only when one or more inputs are true. Thirdly are
XOR gate. It use 2 input XOR gate component. Build up the circuit, set the value with
simulation and repeat the procedure to get the output. We can see that if any one of the
inputs of this gate is high, then the output of the XOR gate will be high. Next are NOT
gate (inverter). Repeat the previous procedure after done construct the circuit. Output
shows that when the input of the NOT gate is true then the output will be false and vice
versa. After that is NAND gate. It use 3 input NAND gate connected with the digital
component source. Follow the previous procedure and run the simulation. NAND gate is
designed by combining the (AND) and (NOT) gates. If the input of the NAND gate high,
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then the output of the gate will be low. The NOR gate used only 2 inputs in the circuit.
Repeat the step and run the simulator. We get that the when any one of the input of the
NOR gate is true, then the output of the NOR gate will be false. Lastly, the XNOR gate.
Repeat all the previous procedure after build the circuit. Adjust the value in simulation
just like the information given. When both the inputs of this gate are high, then the output
of the XNOR gate will be high. But, if any one of the inputs is high (but not both), then
the output will be low. For the next simulation are Adder circuit. Adder are divided into
two group, half adder and full adder. The first one is half adder. Before that the half adder
circuit has two inputs: A and B, which add two input digits and generate a carry and sum.
. Construct the circuit given. It use two gate (XOR) and (AND) gate connected with two
digital source. Set up the simulation with value given and put the voltage level makers at
the all input line and all output line. Apply and run the simulation to get the output. The
output tells us that The half adder adds two binary digits and produces two outputs as
sum and carry; XOR is applied to both inputs to produce sum and AND gate is applied to
both inputs to produce carry. Lastly, the full adder circuit. Full adder have three inputs
and two outputs. The circuit has 3 different gate and must connected correctly from the
input to the output. Visualize the output and repeat the previous step in half adder circuit
until run the simulator. Full adder are A full adder takes two binary numbers plus a carry
or overflow bit. The output is a sum and another carry bit. Full adders are made from
XOR, AND and OR gates in hardware. A full adder takes two binary numbers plus a
carry or overflow bit. The output is a sum and another carry bit. Full adders are made
.from XOR, AND and OR gates in hardware
CONCLUSION
As we know a logic gate is an elementary building block of a digital circuit. Most logic gates
have two inputs and one output. At any given moment, every terminal is in one of the
two binary conditions low (0) or high (1), represented by different voltage levels. The logic
state of a terminal can, and generally does, change often, as the circuit processes data. In
most logic gates, the low state is approximately zero volts (0 V), while the high state is
approximately five volts positive (+5 V). In other words a logic gate implements a Boolean
function and thus performs a logical operation on one or several logic inputs in order to
produce a single logic output. For this lab there are seven basic logic gates: AND, OR, XOR,
NOT, NAND, NOR, and XNOR circuit that we need to construct and simulate then obtain
each of the gate result with a truth table. A truth table is a mathematical table used to
determine if a compound statement is true or false and it used to show logic gate function
Firstly, we have to understand the concept and how to set up the logic gate simulator. In
addition, there are one more circuit in digital electronics called adder. Adder is a digital
circuit that performs addition of two numbers. It is mainly designed for the addition of
binary number, but they can be used in various other applications like binary code
decimal, address decoding, table index calculation, etc. There are two types of Adder one
is Half Adder, and another one is known as Full Adder. The experiment continue with both
of the circuit. Half adder is an example of a simple, functional digital circuit built from two
logic gates. The half adder adds two one-bit binary numbers (AB). The output is the sum of
the two bits (S) and the carry (C). Secondly, the full adder circuit. This adder is difficult to
implement than a half-adder. The difference between a half-adder and a full-adder is that the
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full-adder has three inputs and two outputs, whereas half adder has only two inputs and two
outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When
a full-adder logic is designed, the string eight of them together to create a byte-wide adder
and cascade the carry bit from one adder to the next. . We successfully obtain the output all
the seven gate and adder circuit result after simulate and need to compare with theoretical
result. All the combination logic gates are made of these three basic gates. Output from one
logic gate can be used as input for another logic gate to form combination logic gate. Lastly,
each basic gate works in unique way, which is proved during this experiment.
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POLYTECHNIC of TUANKU SULTANAH BAHIYAH

ELECTRICAL ENGINEERING DEPARTMENT

DEE3061 - COMPUTER AIDED DESIGN CLO/GSA MARKS

NAME : MUHAMMAD FAIZ FAHMI BIN PILEHAN CLO2

1. Describe the concept of the logic level simulation

MATERIAL AND APPARATUS

Personal Computer with Orcad Family Release 9.2 Software

Figure 5.1: AND gate symbol

Input 1 Input 2 Output

Table 5.1: AND gate truth table

Table 5.2:OR gate truth table

Figure 5.5: NAND gate symbol

Table 5.5: NAND gate truth table

Input 1 Input 2 Output

In electronics, an Adder is a device that performs the addition of two numbers.

Table 5.8: Half Adder Truth-Table

Figure 5.10: Half Adder

Figure 5.11 Full Adder

No. Name Part Component Symbol

2. 2 Input OR Gate 7432 U 6A

3. XOR 7486 U 11A

4. Inverter or NOT Gate 7404

5. 2 Input NAND Gate 7410 U 9A

6. 2 Input NOR Gate 7402 U 7A

6. Digital Component Source STIM1 O F F T IM E = .5 u S D S T M 3

A. Simulation of Basic Logic Gates

i) 3-Input AND Gate Schematic

1. Draw the 3-Input AND Gate Schematic in Figure 1

Figure 1: 3-Input AND Gate Schematics

6. Run the simulation

8. Based on the results, fill in Table 1 below

Table 1: Truth table for 3-Input AND Gate Schematic

ii) 2-Input OR Gate Simulation Settings

1. Draw the 2-Input OR Gate Schematic in Figure 2

Figure 2: 2-Input OR Gate Schematic

2. Repeat steps 2 untill steps 7 in section A(i)

3. Based on the results, fill in table 2 below

Table 2: Truth Table for 2-Input OR Gate

iii) 2- input XOR Gate

1. Draw the 2-Input XOR Gate Schematic in Figure 3

Figure 3: 2-Input XOR Gate

2. Repeat steps 2 untill steps 7 in section A(i)

3. Based on the results, fill in table 3 below

Table 3: Truth Table for 2-Input XOR Gate

iv) Inverter or NOT Gate

1. Draw the Inverter Gate Schematic in Figure 4

Figure 4: Inverter or NOT Gate

2. Repeat steps 2 untill steps 7 in section A(i)

3. Based on the results, fill in table 4 below

Table 4: Truth Table for Inverter or NOT Gate

v) 3-Input NAND Gate Schematic

1. Draw the 3-Input NAND Gate Schematic in Figure 5

Figure 5: 3-Input NAND Gate Schematic

2. Repeat steps 2 untill steps 7 in section A(i)

3. Based on the results, fill in table 5 below

Table 5: Truth Table for 3-Input NAND Gate

vi) 2-Input NOR Gate Schematic

1. Draw the 2-Input NOR Gate Schematic in Figure 6

Figure 6: 2-Input NOR Gate Schematic

2. Repeat steps 2 untill steps 7 in section A(i)

3. Based on the results, fill in table 6 below

Table 6: Truth Table for 2-Input NOR Gate