Single-Phase Energy Meter IC: Data Sheet
Single-Phase Energy Meter IC: Data Sheet
Single-Phase Energy Meter IC: Data Sheet
71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
Voltage reference
precision voltage reference, and 32-bit computation engine (CE) supports a
wide range of single-phase metering applications with very few low cost
external components. A 32kHz crystal time base for the entire system and < 10ppm/°C -- 71M6511H,
internal battery backup support for RAM and RTC further reduce system < 50ppm/°C -- 71M6511
cost. Three sensor inputs - VDD referenced
2
Low jitter Wh/VARh pulse outputs
Pulse count for pulse outputs
Maximum design flexibility is supported with multiple UARTs, I C, a power
Four-quadrant metering
fail comparator, a 5V LCD charge pump, up to 12 DIO pins and an in-
system programmable flash. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction Voltage/current angle
residential/commercial meter applications requiring multiple Line frequency count for RTC
voltage/current inputs and complex LCD or DIO configurations.
Digital temperature compensation
Sag detection
Independent 32-bit compute engine
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards. 40-70Hz line frequency range with
same calibration
Phase compensation (±7°)
CT/SHUNT
7/20/2007
DATA SHEET
NOVEMBER 2010
Table of Contents
GENERAL DESCRIPTION..................................................................................................................................... 1
FEATURES ............................................................................................................................................. 1
HARDWARE DESCRIPTION ................................................................................................................................. 8
Hardware Overview .................................................................................................................................. 8
Analog Front End (AFE) ........................................................................................................................... 8
Multiplexer.................................................................................................................................. 8
ADC ........................................................................................................................................... 9
FIR Filter .................................................................................................................................... 9
Voltage Reference ...................................................................................................................... 9
Temperature Sensor ................................................................................................................... 10
Functional Description ................................................................................................................ 10
Computation Engine (CE) ......................................................................................................................... 11
Meter Equations ......................................................................................................................... 12
Pulse Generator ......................................................................................................................... 12
Real-Time Monitor ...................................................................................................................... 13
CE Functional Overview ............................................................................................................. 13
80515 MPU Core ..................................................................................................................................... 15
80515 Overview ......................................................................................................................... 15
Memory Organization ................................................................................................................. 15
Special Function Registers (SFRs) .............................................................................................. 17
Special Function Registers (Generic 80515 SFRs) ...................................................................... 18
Special Function Registers Specific to the 71M6511 .................................................................... 20
Instruction Set ............................................................................................................................ 21
UART ......................................................................................................................................... 21
Timers and Counters .................................................................................................................. 24
WD Timer (Software Watchdog Timer) ........................................................................................ 26
Interrupts.................................................................................................................................... 29
External Interrupts ...................................................................................................................... 32
Interrupt Priority Level Structure .................................................................................................. 34
Interrupt Sources and Vectors..................................................................................................... 35
On-Chip Resources.................................................................................................................................. 37
DIO Ports ................................................................................................................................... 37
Physical Memory ........................................................................................................................ 38
Oscillator .................................................................................................................................... 39
Real-Time Clock (RTC)............................................................................................................... 40
LCD Drivers ............................................................................................................................... 40
LCD Voltage Boost Circuitry........................................................................................................ 41
UART (UART0) and Optical Port (UART1)................................................................................... 41
Hardware Reset Mechanisms ..................................................................................................... 42
Reset Pin (RESETZ)................................................................................................................... 42
Hardware Watchdog Timer ......................................................................................................... 42
Crystal Frequency Monitor .......................................................................................................... 42
V1 Pin ........................................................................................................................................ 42
I2C Interface (EEPROM) ............................................................................................................ 43
Internal Clocks and Clock Dividers .............................................................................................. 44
Battery ....................................................................................................................................... 44
Internal Voltages (VBIAS, VBAT, V2P5) ...................................................................................... 44
Test Ports .................................................................................................................................. 44
DATA SHEET
NOVEMBER 2010
FUNCTIONAL DESCRIPTION ............................................................................................................................... 47
Theory of Operation ................................................................................................................................. 47
System Timing Summary.......................................................................................................................... 47
Data Flow ................................................................................................................................................ 50
CE/MPU Communication.......................................................................................................................... 50
Fault, Reset, Power-Up ............................................................................................................................ 51
Battery Operation ..................................................................................................................................... 52
Power Save Modes .................................................................................................................................. 52
Temperature Compensation ..................................................................................................................... 53
Chopping Circuitry.................................................................................................................................... 53
Internal/External Pulse Generation and Pulse Counting ............................................................................. 55
Program Security ..................................................................................................................................... 56
FIRMWARE INTERFACE ...................................................................................................................................... 57
I/O RAM MAP – In Numerical Order .......................................................................................................... 57
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ........................................................ 58
I/O RAM (Configuration RAM) – Alphabetical Order................................................................................... 59
CE Program and Environment .................................................................................................................. 65
CE Program ............................................................................................................................... 65
Formats...................................................................................................................................... 65
Constants................................................................................................................................... 65
Environment ............................................................................................................................... 66
CE Calculations.......................................................................................................................... 66
CE RAM Locations ................................................................................................................................... 67
CE Front End Data (Raw Data) ................................................................................................... 67
CE Status Word.......................................................................................................................... 67
CE Transfer Variables ................................................................................................................ 68
TYPICAL PERFORMANCE DATA.......................................................................................................................... 75
Wh Accuracy at Room Temperature ......................................................................................................... 75
VARh Accuracy at Room Temperature ..................................................................................................... 75
Harmonic Performance............................................................................................................................. 76
Meter Accuracy over Temperature (71M6511H) ........................................................................................ 76
APPLICATION INFORMATION .............................................................................................................................. 77
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil) .................................................................... 77
Distinction between 71M6511 and 71M6511H Parts.................................................................................. 77
Temperature Compensation and Mains Frequency Stabilization for the RTC.............................................. 78
External Temperature Compensation........................................................................................................ 79
Temperature Measurement ...................................................................................................................... 79
Connecting LCDs ..................................................................................................................................... 80
Connecting I2C EEPROMs....................................................................................................................... 82
Connecting 5V Devices ............................................................................................................................ 82
Optical Interface ....................................................................................................................................... 83
Connecting V1 and Reset Pins ................................................................................................................. 83
Flash Programming .................................................................................................................................. 84
MPU Firmware Library.............................................................................................................................. 84
SPECIFICATIONS ................................................................................................................................................. 85
Electrical Specifications ............................................................................................................................ 85
LOGIC LEVELS.......................................................................................................................... 86
VREF, VBIAS ............................................................................................................................. 88
CRYSTAL OSCILLATOR............................................................................................................ 88
LCD BOOST .............................................................................................................................. 90
LCD DRIVERS ........................................................................................................................... 90
RTC ........................................................................................................................................... 90
DATA SHEET
NOVEMBER 2010
RESETZ..................................................................................................................................... 90
COMPARATORS ....................................................................................................................... 90
RAM AND FLASH MEMORY ...................................................................................................... 91
FLASH MEMORY TIMING .......................................................................................................... 91
EEPROM INTERFACE ............................................................................................................... 91
Recommended External Components ....................................................................................................... 91
Packaging Information.............................................................................................................................. 92
Pinout (Top View) ....................................................................................................................... 93
Pin Descriptions ......................................................................................................................... 94
I/O Equivalent Circuits: ............................................................................................................... 96
ORDERING INFORMATION .................................................................................................................... 97
Figures
Figure 1: IC Functional Block Diagram .......................................................................................................................... 7
Figure 2: General Topology of a Chopped Amplifier ..................................................................................................... 10
Figure 3: AFE Block Diagram...................................................................................................................................... 11
Figure 4: Samples in Multiplexer Cycle ....................................................................................................................... 13
Figure 5: Accumulation Interval.................................................................................................................................. 13
Figure 6: Memory Map .............................................................................................................................................. 15
Figure 7: Interrupt Structure ...................................................................................................................................... 36
Figure 8: DIO Ports Block Diagram ............................................................................................................................. 37
Figure 9: Oscillator Circuit ......................................................................................................................................... 40
Figure 10: LCD Voltage Boost Circuitry....................................................................................................................... 41
Figure 11: Voltage Range for V1 ................................................................................................................................ 43
Figure 12: Voltage. Current, Momentary and Accumulated Energy................................................................................ 47
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers ................................................................ 48
Figure 14: RTM Output Format .................................................................................................................................. 49
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ............................................................................................ 49
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ................................................................. 49
Figure 17: MPU/CE Data Flow .................................................................................................................................... 50
Figure 18: MPU/CE Communication (Functional)......................................................................................................... 51
Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................................ 51
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up................................................. 52
Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................................ 54
Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................................ 54
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping........................................................... 55
Figure 24: Wh Accuracy, 0.3A - 200A/240V ................................................................................................................ 75
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................................... 75
Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................................ 76
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) ......................................................................... 77
Figure 30: Resistive Shunt (left), Rogowski Coil (right) ............................................................................................... 77
Figure 31: Crystal Frequency over Temperature .......................................................................................................... 78
Figure 32: Crystal Compensation ............................................................................................................................... 79
Figure 33: Connecting LCDs ...................................................................................................................................... 80
Figure 34: LCD Boost Circuit...................................................................................................................................... 81
Figure 35: EEPROM Connection ................................................................................................................................. 82
Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 82
Figure 37: Connection for Optical Components ........................................................................................................... 83
Figure 38: Voltage Divider for V1 ............................................................................................................................... 83
Figure 39: External Components for RESETZ .............................................................................................................. 84
DATA SHEET
NOVEMBER 2010
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles .............................................................................. 8
Table 2: Channel control based on MUX_DIV and FIR_LEN ........................................................................................ 9
Table 3: CE DRAM Locations for ADC Results............................................................................................................. 12
Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation) .................................. 12
Table 5: Stretch Memory Cycle Width......................................................................................................................... 16
Table 6: Internal Data Memory Map ........................................................................................................................... 17
Table 7: Special Function Registers Locations............................................................................................................. 17
Table 8: Special Function Registers Reset Values ........................................................................................................ 18
Table 9: PSW Register Flags ...................................................................................................................................... 19
Table 10: PSW bit functions ...................................................................................................................................... 19
Table 11: Port Registers ............................................................................................................................................ 20
Table 12: Special Function Registers .......................................................................................................................... 21
Table 13: Baud Rate Generation ................................................................................................................................. 22
Table 14: UART Modes.............................................................................................................................................. 22
Table 15: The S0CON Register ................................................................................................................................... 22
Table 16: The S1CON register .................................................................................................................................... 23
Table 17: The S0CON Bit Functions ............................................................................................................................ 23
Table 18: The S1CON Bit Functions ............................................................................................................................ 24
Table 19: The TMOD Register .................................................................................................................................... 24
Table 20: TMOD Register Bit Description .................................................................................................................... 25
Table 21: Timers/Counters Mode Description ............................................................................................................. 25
Table 22: The TCON Register ..................................................................................................................................... 25
Table 23: The TCON Register Bit Functions ................................................................................................................. 26
Table 24: Timer Modes.............................................................................................................................................. 26
Table 25: The PCON Register ..................................................................................................................................... 26
Table 26: The IEN0 Register (see also Table 34) ......................................................................................................... 27
Table 27: The IEN0 Bit Functions (see also Table 34)................................................................................................... 27
Table 28: The IEN1 Register (see also Tables 35/36) ................................................................................................... 27
Table 29: The IEN1 Bit Functions (see also Tables 35/36) ............................................................................................ 27
Table 30: The IP0 Register (see also Table 46)............................................................................................................ 28
Table 31: The IP0 bit Functions (see also Table 46) ..................................................................................................... 28
Table 32: The WDTREL Register ................................................................................................................................ 28
Table 33: The WDTREL Bit Functions ......................................................................................................................... 28
Table 34: The IEN0 Register ...................................................................................................................................... 29
Table 35: The IEN0 Bit Functions ............................................................................................................................... 30
Table 36: The IEN1 Register ...................................................................................................................................... 31
Table 37: The IEN1 Bit Functions ............................................................................................................................... 31
Table 38: The IEN2 Register ...................................................................................................................................... 31
Table 39: The IEN2 Bit Functions ............................................................................................................................... 31
Table 40: The TCON Register ..................................................................................................................................... 32
Table 41: The TCON Bit Functions .............................................................................................................................. 32
Table 42: The IRCON Register.................................................................................................................................... 32
Table 43: The IRCON Bit Functions............................................................................................................................. 32
Table 44: External MPU Interrupts ............................................................................................................................. 33
Table 45: Control Bits for External Interrupts .............................................................................................................. 33
Table 46: Priority Level Groups .................................................................................................................................. 34
Table 47: The IP0 Register:........................................................................................................................................ 34
Table 48: The IP1 Register:........................................................................................................................................ 34
DATA SHEET
NOVEMBER 2010
Table 49: Priority Levels ............................................................................................................................................ 34
Table 50: Interrupt Polling Sequence .......................................................................................................................... 35
Table 51: Interrupt Vectors ........................................................................................................................................ 35
Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups ............................................................. 37
Table 53: DIO_DIR Control Bit.................................................................................................................................. 38
Table 54: Selectable Controls using the DIO_DIR Bits ................................................................................................ 38
Table 55: MPU Data Memory Map.............................................................................................................................. 38
Table 56: Liquid Crystal Display Segment Table (Typical) ............................................................................................ 41
Table 57: EECTRL Status Bits................................................................................................................................... 44
Table 58: TMUX[3:0] Selections ............................................................................................................................... 45
Table 59: SSI Pin Assignment .................................................................................................................................... 46
Table 60: Power Saving Measures ............................................................................................................................. 52
Table 61: CHOP_EN Bits.......................................................................................................................................... 53
Table 62: Frequency over Temperature ....................................................................................................................... 78
DATA SHEET
NOVEMBER 2010
VREF VBIAS V3P3A GNDA GNDA
IA VBIAS ∆Σ ADC
VA CONVERTER
IB MUX
VOLTAGE
BOOST
V3P3A - VDRV
FIR LCD_IBST
+ LCD_BSTEN
FILTER
VREF
CHOP_EN VREF FIR_LEN GNDD
MUX
TEMP VREF_DIS
MUX
CTRL
CK32
EQU VOLT
MUX_ALT REG V3P3D
MUX_DIV
VBAT
XIN RTCLK (32KHz) MCK 0.1V
OSC GNDD
PLL
(32KHz)
XOUT
OSC_DIS
V2P5
V2P5
CK_EN
CKFIR 2.5V to logic
CKTEST 4.9MHz 4.9MHz VLCD
CKOUT_EN
CK_GEN CK_2X CE RAM
SSI
(1KB)
ECK_DIS
CKMPU_2X
MPU_DIV
MUX_SYNC WPULSE
STRT
VARPULSE MUX
CKCE CE RTM
<4.9MHz LCD DISPLAY
32-bit Compute DATA DRIVER
Engine 00-FF COM0..3
TEST MEMORY SHARE
SEG0..SEG2
CE PROG
CONTROL 000-7FF 1000-13FF SEG8..SEG19
LCD_NUM
LCD_MODE
LCD_CLK SEG24/DIO4 ...
LCD_EN SEG31/DIO11
EQU RTM_EN DIGITAL I/O SEG34/DIO14 ...
PRE_SAMPS CE_EN DIO_EEX
SUM_CYCLES
WPULSE SEG37/DIO17
PULSEV/W
VARPULSE
CE_RUN DIO_IN
XFER BUSY
SEG3/SCLK
CE_BUSY
CE PROG DIO_OUT
LCD_NUM
SEG4/SSDATA
RAM
(4KB) DIO_GP SEG5/SFR
3000-3FFF
CE_LOAD SEG6/SRDY
I/O RAM
COMP_STAT
FAULTZ IBIAS 1 TMUXOUT
COMP_INT DGND 0
TMUX
October 5, 2005
RESETZ
DATA SHEET
NOVEMBER 2010
HARDWARE DESCRIPTION
Hardware Overview
The TERIDIAN 71M6511 single chip single-phase meter integrates all primary functional blocks required to implement a solid-
state electricity meter. Included on chip are an analog front end (AFE), an 8051-compatible microprocessor (MPU) which
executes one instruction per clock cycle (80515), an independent 32-bit digital computation engine (CE), a voltage reference,
a temperature sensor, LCD drivers, RAM, flash memory, a real time clock (RTC), and a variety of I/O pins. Various current
sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils.
In addition to advanced measurement functions, the real time clock function allows the 71M6511/6511H to record time of use
(TOU) metering information for multi-rate applications. Measurements can be displayed on either a 3V or a 5V LCD. Flexible
mapping of LCD display segments will facilitate integration with any LCD format. The design trade-off between the number of
LCD segments and DIO pins can be flexibly configured using memory-mapped I/O to accommodate various requirements.
The 71M6511 includes several I/O peripheral functions that improve the functionality of the device and reduce the component
count for most meter applications. The I/O peripherals include two UARTs, digital I/O, comparator inputs, LCD display drivers,
2
I C interface and an optical/IR interface.
One of the two internal UARTs (UART1) is adapted to support an Infrared LED with internal drive output and sense input but it
can also function as a standard UART.
A block diagram of the chip is shown in Figure 1. A detailed description of various hardware blocks follows.
Analog Front End (AFE)
The AFE of the TERIDIAN 71M6511 Power Meter IC is comprised of an input multiplexer, a delta-sigma A/D converter with a
voltage reference, followed by an FIR filter. A block diagram of the AFE is shown in Figure 3.
Multiplexer
The input multiplexer supports four input signals that are applied to the pins IA, VA, and IB plus the output of the internal
temperature sensor. The multiplexer can be operated in two modes:
•
•
During a normal multiplexer cycle, the signals from the pins IA, VA, and IB, are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) is selected, along with the other signal sources
shown in Table 1.
Alternate multiplexer cycles are usually performed infrequently (every second or so). VA is not replaced in the alternate multi-
plexer cycles. Missing samples due to alternate multiplexer cycles are automatically interpolated by the CE.
States 0 → 3 States 0 → 3
Sequence MUX Sequence
0 1 2 3 0 1 2 3
000 IA VA IB - TEMP VA - -
001 IA VA IB - TEMP VA IB -
In a typical application, the IA input is connected to a current transformer that senses the line current. VA is typically connected
to a voltage sensor through resistor dividers. IB may be connected to a second current transformer, e.g. for optional tamper
detection.
The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is
governed by the I/O RAM registers MUX_ALT (0x2005[2]), EQU (0x2000[7:5]), and MUX_DIV (0x2002[7:6]). MUX_DIV controls
the number of samples per cycle. It can request 2, 3, 4, or 6 multiplexer states per cycle.
DATA SHEET
NOVEMBER 2010
The MUX_ALT bit requests an alternate multiplexer cycle. The bit may be asserted on any MPU cycle and may be sub-
sequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the Control Circuit to wait
until the next multiplexer cycle and implement a single alternate cycle.
Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The
Multiplexer Control Circuit is clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE
program.
Table 2 shows the possible settings for MUX_DIV and FIR_LEN and the resulting channels sampled along with sample
frequencies.
DATA SHEET
NOVEMBER 2010
A A
Vinp + Voutp
B B
G
A A
Vinn - Voutn
B B
CROSS
IA ∆Σ ADC
VA CONVERTER
IB MUX VBIAS
V3P3A -
FIR
+
FILTER
VREF
CHOP_EN VREF FIR_LEN
MUX
TEMP VREF_DIS
MUX
CTRL
CK32
EQU
MUX_ALT
MUX_DIV
DATA SHEET
NOVEMBER 2010
Figure 3: AFE Block Diagram
DATA SHEET
NOVEMBER 2010
EQU Formula Channels used from MUX Channels used from alternative
States 0 → 3 States 0 → 3
Sequence MUX Sequence
0 1 2 3 0 1 2 3
VA IA
000 IA VA IB - TEMP VA - -
(1 element, 2W 1φ)
VA(IA-IB)/2
001 IA VA IB - TEMP VA IB -
(1 element, 3W 1φ)
Table 4: Standard Meter Equations (inputs shown gray are scanned but not used for calculation)
Pulse Generator
The CE contains two pulse generators which create low jitter pulses at a rate set by the CE DRAM registers APULSEW*WRATE
and APULSER*WRATE if EXT_PULSE (a CE input variable in CE DRAM) is 15. This mode puts the MPU in control of pulse
generation by placing values into the APULSEW and APULSER registers (“external pulse generation”).
If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. In this mode, the CE
generates pulse based on its internal computation of WSUM_X and VARSUM_X, the signed sums of energy from all three
elements (“internal pulse generation”).
The DIO_PV and DIO_PW bits as described in the Digital I/O section can be programmed to route WPULSE and VARPULSE
to the output pins DIO6 and DIO7 respectively. DIO6 and DIO7 can be configured to generate interrupts (useful for pulse
counting by the MPU – see On-Chip Resources (DIO Section).
DATA SHEET
NOVEMBER 2010
Real-Time Monitor
The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM locations at full
sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the
beginning of each CE code pass (see the Test Ports Section for details)
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the samples taken during one
multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS
(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz] (for MUX_DIV = 1)
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100
and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation
cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
1/32768Hz =
30.518µs
IB
IA
VA
13/32768Hz = 397µs
per mux cycle
Figure 4: Samples in Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle,
status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 5: Accumulation Interval
Figure 5 shows the accumulation interval resulting from MUX_DIV = 1, PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of
2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz signal.
DATA SHEET
NOVEMBER 2010
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when
SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6ms). Furthermore, sampling does not have to
start when the line voltage crosses the zero line.
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be
sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
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NOVEMBER 2010
80515 MPU Core
80515 Overview
The 71M6511/6511H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle.
Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and
implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, there-
fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0].
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are
available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface
library is available to help reduce design cycle.
Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, CE PRAM and I/O RAM, and
internal data memory (Internal RAM). Figure 6 shows the memory map (see also Table 55).
Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6511 IC. Ex-
ternal data memory is only external to the 80515 MPU core.
0xFFFF 0xFFFF
---
0x4000
0x3FFF
CE PRAM
0x3000
0x2FFF
---
0x2100
0x20FF
I/O RAM
0x2000
Flash memory
0x1FFF
---
0x1400
0x13FF
CE DRAM
0x1000
0x0FFF
---
0x0800
0x07FF 0xFF SFRs, RAM,
XRAM
0x0000 0x0000 0x00 reg. banks
Program memory External data memory Internal data memory
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NOVEMBER 2010
when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing
a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low ordered
bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very
slow external RAM or external peripherals.
Table 5 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of
the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table,
performs the MOVX instructions with a stretch value equal to 1.
CKCON register Stretch Value Read signals width Write signal width
CKCON.2 CKCON. CKCON. memaddr memrd memaddr memwr
1 0
0 0 0 0 1 1 2 1
0 0 1 1 2 2 3 1
0 1 0 2 3 3 4 2
0 1 1 3 4 4 5 3
1 0 0 4 5 5 6 4
1 0 1 5 6 6 7 5
1 1 0 6 7 7 8 6
1 1 1 7 8 8 9 7
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Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data
memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function
Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing
accesses the upper 128 bytes of Internal RAM.
The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight
registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a
block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible
through direct or indirect addressing. Table 6 shows the internal data memory map.
Address Direct addressing Indirect addressing
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Special Function Registers (Generic 80515 SFRs)
Table 8 shows the location of the SFRs and the value they assume at reset or power-up.
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NOVEMBER 2010
Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The
mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.
B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold
temporary data.
Program Status Word (PSW):
MSB LSB
CV AC F0 RS1 RS OV - P
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-
byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or
data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented
during the fetching operation code or when operating on data from program memory.
DATA SHEET
NOVEMBER 2010
Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be
observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 11) causes the corresponding pin to
be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction
registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section On-Chip Resources – DIO Ports for
details).
Register SFR R/W Description
Addres
s
P0 0x80 R/W Register for port 0 read and write operations (pins DIO4…DIO7)
DIR0 0xA2 R/W Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
P1 0x90 R/W Register for port 1 read and write operations (pins DIO8…DIO15)
DIR1 0x91 R/W Data direction register for port 1.
P2 0xA0 R/W Register for port 2 read and write operations (pins DIO16-DIO17)
DIR2 0xA1 R/W Data direction register for port 2.
DATA SHEET
NOVEMBER 2010
DATA SHEET
NOVEMBER 2010
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR
0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the
receive buffer. Writing data to the transmit buffer starts the transmission by the associated UART. Received data are
available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data.
WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity
enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps.
Table 13 shows how the baud rates are calculated. Table 14 shows the selectable UART operation modes.
UART 0 UART 1
Mode 0 N/A Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Mode 1 Start bit, 8 data bits, stop bit, Start bit, 8 data bits, stop bit, variable baud rate
variable baud rate (internal baud (internal baud rate generator)
rate generator or timer 1)
Mode 2 Start bit, 8 data bits, parity, stop bit, N/A
fixed baud rate 1/32 or 1/64 of
fCKMPU
Mode 3 Start bit, 8 data bits, parity, stop bit, N/A
variable baud rate (internal baud
rate generator or timer 1)
DATA SHEET
NOVEMBER 2010
Serial Interface 1 Control Register (S1CON).
The function of the serial port depends on the setting of the Serial Port Control Register S1CON.
MSB LSB
SM - SM21 REN1 TB81 RB81 TI1 RI1
DATA SHEET
NOVEMBER 2010
DATA SHEET
NOVEMBER 2010
TMOD.7 Gate If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
TMOD.3 respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a
counter is incremented every falling edge on t0 or t1 input pin
TMOD.6 C/T Selects Timer or Counter operation. When set to 1, a Counter operation is
TMOD.2 performed. When cleared to 0, the corresponding register will function as a Timer.
TMOD.5 M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
TMOD.1 description.
TMOD.4 M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD
TMOD.0 description.
M1 M0 Mode Function
0 0 Mode 0 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0 1 Mode 1 16-bit Counter/Timer.
1 0 Mode2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,
while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows,
a value from TH(x) is copied to TL(x).
1 1 Mode3 If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0
bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.
DATA SHEET
NOVEMBER 2010
Timer 1
Mode 0 Mode 1 Mode 2
Timer 0 - mode 0 YES YES YES
Timer 0 - mode 1 YES YES YES
Timer 0 - mode 2 Not allowed Not allowed YES
DATA SHEET
NOVEMBER 2010
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from
becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction
sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock
cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is
reloaded with the content of the WDTREL register and WDT is automatically reset. Since the WDT requires exact timing,
firmware needs to be designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the
use of the software WDT.
Special Function Registers for the WD Timer
Interrupt Enable 0 Register (IEN0):
MSB LSB
Table 27: The IEN0 Bit Functions (see also Table 34)
Note: The remaining bits in the IEN0 register are not used for watchdog control
Interrupt Enable 1 Register (IEN1):
MSB LSB
Table 29: The IEN1 Bit Functions (see also Tables 35/36)
Note: The remaining bits in the IEN1 register are not used for watchdog control
DATA SHEET
NOVEMBER 2010
Interrupt Priority 0 Register (IP0):
MSB LSB
IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer was started. Can be
read by software.
Table 31: The IP0 bit Functions (see also Table 46)
Note: The remaining bits in the IP0 register are not used for watchdog control
Watchdog Timer Reload Register (WDTREL):
MSB LSB
7 6 5 4 3 2 1 0
Prescaler select bit. When set, the watchdog is clocked through an additional
WDTREL.7 7
divide-by-16 prescaler
WDTREL.6 Seven bit reload value for the high-byte of the watchdog timer. This value is
to 6-0 loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDTREL.0 WDT and SWDT.
DATA SHEET
NOVEMBER 2010
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or
disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the
71M6511/6511H, for example the CE, DIO, RTC EEPROM interface, comparators.
Interrupt Overview: When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 51. Once
interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would
have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled
by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set.
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector
address, if the following conditions are met:
• No interrupt of equal or higher priority is already in progress.
• An instruction is currently being executed and is not completed.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If the
MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the
response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This
includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL.
Special Function Registers for Interrupts:
Interrupt Enable 0 register (IE0)
MSB LSB
DATA SHEET
NOVEMBER 2010
DATA SHEET
NOVEMBER 2010
Interrupt Enable 1 Register (IEN1)
MSB LSB
IEN1.7 -
IEN1.6 SWDT Not used for interrupt control
IEN1.5 EX6 EX6=0 – disable external interrupt 6
IEN1.4 EX5 EX5=0 – disable external interrupt 5
IEN1.3 EX4 EX4=0 – disable external interrupt 4
IEN1.2 EX3 EX3=0 – disable external interrupt 3
IEN1.1 EX2 EX2=0 – disable external interrupt 2
IEN1.0 -
- - - - - - - ES1
DATA SHEET
NOVEMBER 2010
Timer/Counter Control Register (TCON)
MSB LSB
IRCON.7 -
IRCON.6 -
IRCON.5 IEX6 External interrupt 6 edge flag
IRCON.4 IEX5 External interrupt 5 edge flag
IRCON.3 IEX4 External interrupt 4 edge flag
IRCON.2 IEX3 External interrupt 3 edge flag
IRCON.1 IEX2 External interrupt 2 edge flag
IRCON.0 -
DATA SHEET
NOVEMBER 2010
XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6
enable and flag bits (see Table 45), and these interrupts must be cleared by the MPU software.
DATA SHEET
NOVEMBER 2010
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 46:
Group
0 External interrupt 0 Serial channel 1 interrupt
1 Timer 0 interrupt - External interrupt 2
2 External interrupt 1 - External interrupt 3
3 Timer 1 interrupt - External interrupt 4
4 Serial channel 0 interrupt - External interrupt 5
5 - - External interrupt 6
DATA SHEET
NOVEMBER 2010
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
Polling sequence
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
DATA SHEET
NOVEMBER 2010
IP1.0/
IP0.0
RI1 IEN2.0
Polling Se quen ce
UART1
>=1
(optical)
TI1
IEN0.1
Timer 0 TF0
IP1.1/ Interrupt
I2FR IEN1.1 IP0.1 Vector
Compar-
INT2 IRCON.1
ators
IEN0.2
DIO IE1
IP1.2/
I3FR IEN1.2 IP0.2
CE_BUSY INT3 IRCON.2
IEN0.3
Timer 1 TF1
IP1.3/
IEN1.3 IP0.3
Compar-
INT4 IRCON.3
ators
RI0 IEN0.4
UART0 >=1
TI0 IP1.4/
IEN1.4 IP0.4
EEPROM/ IRCON.4
INT5
I2C
IEN1.5
INT6 IRCON.5 IP1.5/
IP0.5
XFER_BUSY
>=1
RTC_1S
DATA SHEET
NOVEMBER 2010
On-Chip Resources
DIO Ports
The 71M6511/6511H includes up to 12 pins of general purpose digital I/O. These pins are dual function and can alternatively
be used as LCD drivers. Figure 8 shows a block diagram of the DIO section.
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and
controlled by the DIO and DIO_DIR registers (SFRs) and by the five bits of the I/O register LCD_NUM (0x2020[4:0]). See the
description for LCD_NUM in the I/O RAM Section for a table listing the available segment pins versus DIO pins, depending on
the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general
purpose pins to be LCD segment pins, starting at the higher pin numbers.
LCD DISPLAY
DRIVER
COM0..3
SEG0..SEG2
LCD_NUM SEG8..SEG19
LCD_MODE
LCD_CLK SEG24/DIO4 ...
LCD_EN SEG31/DIO11
DIGITAL I/O SEG34/DIO14 ...
DIO_EEX SEG37/DIO17
PULSEV/W
DIO_IN SEG3/SCLK
DIO_OUT
LCD_NUM
SEG4/SSDATA
DIO_GP SEG5/SFR
SEG6/SRDY
SEG7/
MUX_SYNC
DIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin number -- -- -- -- 37 38 39 40 41 42 43 44 -- -- 20 21
-- -- -- -- 4 5 6 7 0 1 2 3 -- -- 6 7
Data Register bit
DIO0=P0 (SFR 0x80) DIO1=P1 (SFR 0x90)
Direction Register -- -- -- -- 4 5 6 7 0 1 2 3 -- -- 6 7
bit DIO_DIR0 (SFR 0xA2) DIO_DIR1 (SFR 0x91)
Internal Resources
-- -- -- -- Y Y Y Y Y Y Y Y -- -- N N
Configurable
DIO 16 17 18 19 20 21 22 23
Pin number 22 12 -- -- -- -- -- --
0 1 -- -- -- -- -- --
Data Register bit
DIO2=P2 (SFR 0xA0)
Direction Register 0 1 -- -- -- -- -- --
bit DIO_DIR2 (SFR 0xA1)
Internal Resources
N N -- -- -- -- -- --
Configurable
Table 52: Data/Direction Registers and Internal Resources for DIO Pin Groups
DATA SHEET
NOVEMBER 2010
DIO_DIR bit
0 1
DIO Pin Function input output
Flash Memory: The 71M6511 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
DATA SHEET
NOVEMBER 2010
The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
Writing to flash memory:
The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM
register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. After the write
operation, FLSH_PWE must be cleared.
The original state of a flash byte is 0xFF (all bits are 1). Overwriting programmed flash cells with a different value usually re-
quires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a
page erase. After this, the page can be updated in RAM and then written back to the flash memory.
Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to
0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maintain the integrity of the cells 0x2000…0x2007
as a minimum (where important system settings are stored) during the flash-write operation. This can be achieved by
excluding the critical addresses from the write operation.
MPU RAM: The 71M6511 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256-
bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means of
data communication between the two processors.
CE PRAM: The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the CE
starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.
Oscillator
The oscillator drives a standard 32.768kHz watch crystal (see Figure 9). Crystals of this type are accurate and do not require a
high current oscillator circuit. The oscillator in the TERIDIAN 71M6511 Power Meter IC has been designed specifically to
handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power
dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT pin.
DATA SHEET
NOVEMBER 2010
71M651X
XIN
crystal
XOUT
DATA SHEET
NOVEMBER 2010
VOLTAGE
BOOST
VDRV
LCD_IBST
LCD_BSTEN
GNDD
GNDD
V2P5NV V3P3D
VOLT
REG
V3P3D
VBAT
0.1V
GNDD
GNDD
V2P5
V2P5
VLCD
DATA SHEET
NOVEMBER 2010
Hardware Reset Mechanisms
Several conditions will cause a hardware reset of the 71M6511/6511H:
•
•
Voltage at the RESETZ pin low
•
Voltage at the E_RST pin low
•
Voltage at the V1 pin below reset threshold (VBIAS)
•
The crystal frequency monitor detected a crystal malfunction
Hardware Watchdog timer
Reset Pin (RESETZ)
When the RESETZ pin is pulled low (or when V1 < VBIAS), all digital activity in the chip stops while analog circuits are still
active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared.
Hardware Watchdog Timer
In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware
watchdog timer (WDT) is included in the 71M6511/6511H. This timer will reset the MPU if it is not refreshed periodically, and
can be used to recover the MPU in situations where program control is lost.
The watchdog timer uses the RTC crystal oscillator as its time base and requires a reset under MPU program control at least
every 1.5 seconds. When the WDT overflow occurs, the MPU is momentarily reset as if RESETZ were pulled low for half of a
crystal oscillator cycle. Thus, after 4100 cycles of the CK32 (32768Hz clock), the MPU program will be launched from address
00.
An I/O RAM register status bit, WD_OVF (0x2002[2]), is set when WDT overflow occurs. This bit is powered by the VBAT
pin and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power up. After
reading this bit, MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin.
The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a
system reset will be performed when the crystal oscillator resumes.
There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying
the V1 pin to V3P3 (see Figure 11 and WD Disable Threshold [V1-V3P3A] in the Comparator Section of the Electrical
Specifications). Of course, this also deactivates the power fault detection implemented with V1. Since there is no way in firm-
ware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be
reset to a known state upon watchdog timer overflow.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when
WAKE=0 and, during development, when a 0x14 command is received from the ICE port.
Crystal Frequency Monitor
The hardware watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, the I/O RAM
register WD_OVF is set and a system reset will be performed when the crystal oscillator resumes.
V1 Pin
The comparator at the V1 pin controls the state of the digital circuitry on the chip. When V1 < VBIAS (or when the RESTZ pin
is pulled low), all digital activity in the chip stops while analog circuits including the oscillator and RTC module are still active.
Additionally, when V1 < VBIAS, all I/O RAM bits are cleared. As long as V1 is greater than VBIAS, the internal 2.5V regulator
will continue to provide power to the digital section.
DATA SHEET
NOVEMBER 2010
V1
V3P3 -
400mV
Normal
operation,
WDT
enabled
when
(V1 < VBIAS)
VBIAS
the battery is
enabled
Battery or
reset
mode
0V
DATA SHEET
NOVEMBER 2010
CMD Operation
0 No-op. Applying the no-op command will stop the I2C clock
(SCK, DIO4). Failure to issue the no-op command will keep
the SCK signal toggling.
6 Receive the last byte from EEPROM and do not send ACK.
9 Issue a ‘START’ sequence.
Others No Operation, set the ERROR bit.
DATA SHEET
NOVEMBER 2010
TMUXOUT Pin: One out of 16 digital or 4 analog signals can be selected to be output on the TMUXOUT pin. The function of
the multiplexer is controlled with the I/O RAM register TMUX (0x2000[3:0]), as shown in Table 58.
Emulator Port: The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides control of the MPU through
an external in-circuit emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems.
The signals of the emulator port have weak pull-ups. Adding 1kΩ pull-up resistors on the PCB is recommended.
Real-Time Monitor: The RTM output of the CE is available as one of the digital multiplexer options. RTM data is read from the
CE DRAM locations specified by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. The RTM can
be enabled and disabled with I/O RAM register RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked
out in 35 cycles and contains a leading flag bit. Figure 13 in the System Timing Section illustrates the RTM output format. RTM
is low when not in use.
SSI Interface: A high-speed serial interface with handshake capability is available to send a contiguous block of CE data to an
external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before
each CE code pass begins. If the block of data is big enough that transmission has not completed when the code pass begins,
it will complete during the CE code pass with no timing impact to the CE or the serial data. In this case, care must be taken
that the transmitted data is not modified unexpectedly by the CE. The SSI interface is enabled by the SSI_EN bit and consists
of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit
processors. The operation of each pin is as follows:
SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls
whether SCLK runs continuously or is gated off when no SSI activity is occurring. If SCLK is gated, it will begin 3 cycles before
SFR rises and will persist 3 cycles after the last data bit is output.
The pins used for the SSI are multiplexed with the LCD segment outputs, as shown in Table 59. Thus, the LCD should be
disabled when the SSI is in use.
DATA SHEET
NOVEMBER 2010
DATA SHEET
NOVEMBER 2010
FUNCTIONAL DESCRIPTION
Theory of Operation
E = ∫ V (t ) I (t )dt
The energy delivered by a power source into a load can be expressed as:
0
Assuming phase angles are constant, the following formulae apply:
500
400
300
200
V [V], I [A], P [Ws]
100
0
-100
-200
Current [A]
-300 Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
0 5 10 15 time [ms] 20
DATA SHEET
NOVEMBER 2010
Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV = 1 (four mux states) and FIR_LEN = 1 (3 CK32 cycles). Since FIR filter conversions
require two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1
+ 3 * states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
CK32
150
MUX_SYNC
MUX STATE S 0 1 2 3 S
ADC EXECUTION
ADC0 ADC1 ADC2 ADC3
CE TIMING
0 450 900 1350 1800
CE_EXECUTION
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5) MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM and SSI TIMING 140
RTM
SSI
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
DATA SHEET
NOVEMBER 2010
CK32
MUX_SYNC
CKTEST
TMUXOUT/RTM 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31
N
LSB
LSB
LSB
N
SIG
SIG
SIG
SIG
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output) 31 30 16 15 1 0 31 30 16 15 1 0 31 1 0
SSI_BEG SSI_BEG+1 SSI_END
MUX_SYNC
SFR (Output)
SRDY (Input)
SCLK (Output)
SSDATA (Output) 31 30 29 18 17 16 16 16 16 15 14 13 12
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY)
SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single
field, as multiple 16-bit fields, or as multiple 32-bit fields. The SFR pulse is one SCLK clock cycle wide, changes state on the
rising edge of SCLK and precedes the first bit of each field.
DATA SHEET
NOVEMBER 2010
Data Flow
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, and IB, performing calculations to measure active
2 2
power (Wh), reactive power (VARh), A h, and V h for four-quadrant metering. These measurements are then accessed by the
MPU, processed further and output using the peripheral devices available to the MPU.
Pulses
IRQ
Processed
Samples CE Data MPU Metering
Pre- Post- Data
Processor Processor
60 ⋅ 42
τ= = = = 999.75ms
N ACC 2520
fS 32768Hz 2520.62 Hz
13
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
DATA SHEET
NOVEMBER 2010
PULSES
VAR (DIO7) W (DIO6)
DISPLAY (me-
mory-mapped
VARSUM
WSUM
APULSEW LCD segments)
APULSER SERIAL
EXT_PULSE (UART0/1)
MPU
DATA
EEPROM
ADC SAMPLES (I2C)
CE_BUSY
CE XFER_BUSY DIO
Mux Ctrl. INTERRUPTS
The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional
processing such as energy accumulation.
CE PRAM
FLASH
CE_EN
COMPUTATION
XFER Interrupt ENGINE
CE DRAM
MPU
Figure 19: MPU/CE Communication (Processing Sequence)
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the
input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
sequences from address 00. See the security section for more description of preboot and boot.
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NOVEMBER 2010
Power-Up: After power-up, the 71M6511/6511H is in reset as long as V1 < VBIAS. As soon as V1 exceeds VBIAS, the reset
timer is started which takes the MPU out of reset after 4100 oscillator cycles (see Figure 20). The MPU then initiates its pre-
boot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firmware control, following the steps specified in Battery Operation and Power Save Modes.
V3P3
V2P5 3.3V
V1 1.5V
0V
1ms
125ms
0mA
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up
Battery Operation
When V1 is lower than VBIAS, the external battery will power the following parts of the 71M6511/6511H:
• RTC
• Crystal oscillator circuitry
• MPU XRAM
• WD_OVF bit
Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6511/6511H may be shut down by the
MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.
Table 60 outlines these resources and their typical current consumption (based on initial condition MPU_DIV = 0).
DATA SHEET
NOVEMBER 2010
Temperature Compensation
Internal Compensation: The internal voltage reference is calibrated during device manufacture. Trim data is stored in on-chip
fuses.
For the 71M6511, the temperature coefficients TC1 and TC2 are given as constants that represent typical component
behavior.
For the 71M6511H, the temperature characteristics of the chip are measured during production and then stored in the fuse
registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in the
Electrical Specifications section. TC1 and TC2 can be further processed to generate the coefficients PPMC and PPMC2.
TRIMM[2:0], TRIMBGA and TRIMBGB are read by first writing either 4, 5 or 6 to TRIMSEL (0x20FD) and then reading the value
of TRIM (0x20FF).
When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature
errors by controlling the GAIN_ADJ register (address 0x2E) based on the PPMC, PPMC2, and TEMP_X register values. In the
case of internal compensation, GAIN_ADJ is an output of the CE.
External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is
provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide
temperature correction over the entire system rather than local to the chip. The incorporated thermal coefficients may include
the current sensors, the voltage sensors, and other influences. Since the band gap is chopper stabilized via the CHOP_EN bits,
the most significant long-term drift mechanism in the voltage reference is removed.
When the EXT_TEMP register in CE DRAM is set to 15, the CE ignores the PPMC, PPMC2, and TEMP_X register values and
applies the gain supplied by the MPU in GAIN_ADJ. External compensation enables the MPU to control the CE gain based on
any variable, and when EXT_TEMP = 15, GAIN_ADJ is an input to the CE.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between
multiplexer cycles to achieve the desired elimination of DC offset.
The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When
this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain
but inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The two bits
of the CHOP_EN register have the function specified in Table 61.
DATA SHEET
NOVEMBER 2010
Chop Polarity
Re- Re- Re- Re- Re-
Positive Positive Positive Positive Positive Positive
versed versed versed versed versed
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
alt. MUX MUX MUX MUX alt. MUX MUX alt. MUX
cycle cycle 2 cycle 3 cycle n cycle cycle n cycle
Chop Polarity
Re- Re- Re- Positive Re- Re-
Positive Positive Positive Positive Positive
versed versed versed versed versed
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.
Consequently, DC offset will appear on the temperature measurement, which will decrease the accuracy of this measurement
and thus cause temperature reading and compensation to be less accurate.
The sequence shown in Figure 23 uses the CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each
DATA SHEET
NOVEMBER 2010
XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns to 11 (automatic toggle). The value of CHOP_EN, when
set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.
When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in
accurate temperature measurement.
An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6511 and 6511
Demo Kits. Firmware implementations should closely follow this example.
alt. MUX MUX MUX MUX alt. MUX MUX MUX MUX alt. MUX MUX MUX MUX
cycle cycle 2 cycle 3 cycle n cycle cycle 2 cycle 3 cycle n cycle cycle 2 cycle 3 cycle n
Chop Polarity
re- re- re- re- re-
Positive Positive versed Positive Positive Positive Positive versed Positive
versed versed versed
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
CHOP_EN
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping
Internal/External Pulse Generation and Pulse Counting
The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured
pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE
(address 0x37) equals 0. Alternatively, the CE can be configured to generate pulses based on registers that are controlled by
the MPU (“external pulse generation”), i.e. when the register EXT_PULSE equals 15. In the case of external pulse generation,
the MPU writes values to the CE registers APULSEW (0x26) and APULSER (0x27).
The pulse rate, usually inversely expressed as “Kh” (and measured in Wh per pulse), is determined by the CE RAM registers
WRATE, PULSE_SLOW, PULSE_FAST, In_8, as well as by the sensor scaling VMAX and IMAX per the equation:
where
In_8 is the gain factor (1 or 8) controlled by the CE variable In_SHUNT,
X is the pulse gain factor controlled by the CE variables PULSE_SLOW and PULSE_FAST
NACC is the accumulation count (PRE_SAMPS * SUM_CYCLES)
DATA SHEET
NOVEMBER 2010
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked.
This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a
32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to
perform a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.
The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A read-
only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the
ICE can be enabled and is permitted to take control of the MPU.
SECURE (SFR 0xB2[6]), the security enable bit, is reset whenever the MPU is reset. Hardware associated with the bit permits
only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once
SECURE is set, the preboot code is protected and no external read of program code is possible.
Specifically, when SECURE is set:
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or
ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether
•
SECURE is set or not.
Writes to page zero, whether by MPU or ICE, are inhibited.
The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE
interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE
Interface description).
Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with
the emulator. See the cautionary note in the I/O RAM Register description!
DATA SHEET
NOVEMBER 2010
FIRMWARE INTERFACE
I/O RAM MAP – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed.
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration:
CE0 2000 EQU[2:0] CE_EN TMUX[3:0]
CE1 2001 PRE_SAMPS[1:0] SUM_CYCLES[5:0]
CE2 2002 MUX_DIV[1:0] CHOP_EN[1:0] RTM_EN WD_OVF EX_RTC EX_XFR
COMP0 2003 RESERVED RESERVED COMP_STAT[0]
CONFIG0 2004 VREF_CAL RESERVED CKOUT_DIS VREF_DIS MPU_DIV
CONFIG1 2005 RESERVED ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLASH66Z MUX_E
VERSION 2006 VERSION[7:0]
Digital I/O:
DIO0 2008 OPT_TXDIS DIO_EEX DIO_PW DIO_PV
DIO1 2009 RESERVED RESERVED
DIO2 200A RESERVED RESERVED
DIO3 200B DIO_R5[2:0] DIO_R4[2:0]
DIO4 200C DIO_R7[2:0] DIO_R6[2:0]
DIO5 200D DIO_R9[2:0] DIO_R8[2:0]
DIO6 200E DIO_R11[2:0] DIO_R10[2:0]
Real Time Clock:
RTC0 2015 RTC_SEC[5:0]
RTC1 2016 RTC_MIN[5:0]
RTC2 2017 RTC_HR[4:0]
RTC3 2018 RTC_DAY[2:0]
RTC4 2019 RTC_DATE[4:0]
RTC5 201A RTC_MO[3:0]
RTC6 201B RTC_YR[7:0]
RTC7 201C RTC_DEC_SEC RTC_INC_SEC
LCD Display Interface:
LCDX 2020 LCD_BSTEN LCD_NUM[4:0]
LCDY 2021 LCD_EN LCD_MODE[2:0] LCD_CLK[1:0]
LCDZ 2022 LCD_FS[4:0]
LCD0 2030 LCD_SEG0[3:0]
LCD1 2031 LCD_SEG1[3:0]
… … …
LCD19 2043 LCD_SEG19[3:0]
LCD20 2044 RESERVED
… … …
LCD23 2047 RESERVED
LCD24 2048 LCD_SEG24[3:0]
… … …
LCD31 204F LCD_SEG31[3:0]
LCD32 2050 LCD_SEG32[3:0]
LCD33 2051 LCD_SEG33[3:0]
LCD34 2052 LCD_SEG34[3:0]
LCD35 2053 LCD_SEG35[3:0]
LCD36 2054 LCD_SEG36[3:0]
LCD37 2055 LCD_SEG37[3:0]
DATA SHEET
NOVEMBER 2010
LCD38 2056 RESERVED
LCD39 2057 RESERVED
LCD40 2058 RESERVED
LCD41 2059 RESERVED
RTM Probes:
RTM0 2060 RTM0[7:0]
RTM1 2061 RTM1[7:0]
RTM2 2062 RTM2[7:0]
RTM3 2063 RTM3[7:0]
Synchronous Serial Interface:
SSI 2070 SSI_EN SSI_10M SSI_CKGATE SSI_FSIZE[1:0] SSI_FPOL SSI_RDYEN SSI_RDYPOL
S S I _ B E G 2071 SSI_BEG[7:0]
SSI_END 2072 SSI_END[7:0]
Fuse Selection Registers:
TRIMSEL 20FD TRIMSEL[7:0]
TRIM 20FF TRIM[7:0]
9E EEDATA[7:0]
9F EECTRL[7:0]
DATA SHEET
NOVEMBER 2010
I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its para-
meters from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and
copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory
space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all
bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed.
Name Location Dir Description
[Bit(s)]
ADC_DIS 2005[3] R/W Disables ADC and removes bias current
CE_EN 2000[4] R/W CE enable.
CHOP_EN[1:0] 2002[5:4] R/W Chop enable for the reference band gap circuit.
00: enabled 01: disabled 10: disabled 11: enabled
RESERVED 2004[5] R/W Must be 0.
CKOUT_DIS 2004[4] R/W CKOUT Disable. When zero, CKTEST is an active output.
RESERVED 2003[4:3] R/W Must be 0.
RESERVED 2003[2:0] R Reserved
DIO_R4[2:0] 200B[2:0] R/W Connects dedicated I/O pins 4 to 11 to selectable internal resources. If
DIO_R5[2:0] 200B[6:4] R/W more than one input is connected to the same resource, the ‘Multiple’
DIO_R6[2:0] 200C[2:0] R/W column below specifies how they are combined. See Software User’s
DIO_R7[2:0] 200C[6:4] R/W Guide for details).
DIO_R8[2:0] 200D[2:0] R/W
DIO_R9[2:0] 200D[6:4] R/W DIO_GP Resource Multiple
DIO_R10[2:0] 200E[2:0] R/W 0 NONE --
DIO_R11[2:0] 200E[6:4] R/W 1 Reserved OR
2 T0 (counter0 clock) OR
3 T1 (counter1 clock) OR
4 High priority I/O interrupt (int0 rising) OR
5 Low priority I/O interrupt (int1 rising) OR
6 High priority I/O interrupt (int0 falling) OR
7 Low priority I/O interrupt (int1 falling) OR
DIO_DIR0[7:4] SFR A2 R/W Programs the direction of DIO pins 7 through 4. 1 indicates output.
Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW
for special option for DIO6 and DIO7 outputs. See DIO_EEX for special
option for DIO4 and DIO5.
Note: Bit 0, Bit 1, Bit 2 and Bit 3 must be set to 1.
DATA SHEET
NOVEMBER 2010
DIO_DIR1[7:6] SFR91 R/W Programs the direction of DIO pins 15, 14 and 11 through 8. 1
DIO_DIR1[3:0] indicates output. Ignored if the pin is not configured as I/O.
Note: Bit 4 and Bit 5 must be set to 1.
DIO_DIR2[1:0] SFRA1[5:0] R/W Programs the direction of DIO pins 17 and 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1.
DIO_0[7:4] SFR80 R/W Port 0 The value on the DIO pins. Pins configured as LCD will read
DIO_1[7:6], SFR90 R/W Port 1 zero. When written, changes data on pins configured as
DIO_1[3:0] SFR90 R/W Port 1 outputs. Pins configured as LCD or input will ignore writes.
DIO_2[1:0] SFRA0[1:0] R/W Port 2
DIO_EEX 2008[4] R/W When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA.
LCD_NUM must be less than 18.
DIO_PV 2008[2] R/W Causes VARPULSE to be output on DIO7, if DIO7 is configured as
output. LCD_NUM must be less than 15.
DIO_PW 2008[3] R/W Causes WPULSE to be output on DIO6, if DIO6 is configured as
output. LCD_NUM must be less than 17.
EEDATA[7:0] SFR 9E R/W Serial EEPROM interface data
EECTRL[7:0] SFR 9F R/W Serial EEPROM interface control
ECK_DIS 2005[5] R/W Emulator clock disable. When one, the emulator clock is disabled.
This bit is to be used with caution! Inadvertently setting
this bit will inhibit access to the part with the ICE
interface and thus preclude flash erase and programming
operations. If ECK_DIS is set, it should be done at least 1000ms after
power-up to give emulators and programming devices enough time to
complete an erase operation.
EQU[2:0] 2000[7:5] R/W Specifies the power equation to the CE.
EX_XFR 2002[0] R/W Interrupt enable bits. These bits enable the XFER_BUSY and the
EX_RTC 2002[1] RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
FIR_LEN 2005[4] R/W The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
FLASH66Z 2005[1] R/W Should be set to 1 to minimize supply current.
DATA SHEET
NOVEMBER 2010
DATA SHEET
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DATA SHEET
NOVEMBER 2010
W output.
OPT_TXDIS 2008[5] R/ Tristates the OPT_TX output.
W
PREBOOT SFR R Indicates that the preboot sequence is active.
B2[7]
PRE_SAMPS[1:0] 2001[7:6] R/ Together w/ SUM_CYCLES, this value determines the number of
W samples in one sum cycle between XFER interrupts for the CE.
Number of samples = PRE_SAMPS*SUM_CYCLES.
00-42, 01-50, 10-84, 11-100
RTC_SEC[5:0] 2015 R/W The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’,
RTC_MINI[5:0] 2016 ‘minute’ and ‘second’ parameters for the RTC. The RTC is set by
RTC_HR[4:0] 2017 writing to these registers. Year 00 is defined as a leap year.
RTC_DAY[2:0] 2018 SEC 00 to 59
RTC_DATE[4:0] 2019 MIN 00 to 59
RTC_MO[3:0] 201A
RTC_YR[7:0] 201B HR 00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR 00 to 256
RTC_DEC_SEC 201C[1] W RTC time correction bits. Only one bit may be pulsed at a time. When
RTC_INC_SEC 201C[0] pulsed, causes the RTC time value to be incremented (or
decremented) by an additional second the next time the RTC_SEC
register is clocked. The pulse width may be any value. If an additional
correction is desired, the MPU must wait 2 seconds before pulsing
one of the bits again.
RTM_EN 2002[3] R/W Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0] 2060 R/W Four RTM probes. Before each CE code pass, the values of these
RTM1[7:0] 2061 R/W registers are serially output on the RTM pin. The RTM registers are
RTM2[7:0] 2062 R/W ignored when RTM_EN=0.
RTM3[7:0] 2063 R/W
SECURE SFR R/W Enables security provisions that prevent external reading of flash
B2[6] memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
SSI_EN 2070[7] R/W Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take
on the new functions SCLK, SSDATA, SFR, and SRDY, respectively.
When SSI_EN is high and LCD_EN is low, these pins are converted to
the SSI function, regardless of LCDEN and LCD_NUM. For proper
LCD operation, SSI_EN must not be high when LCD_EN is high.
SSI_10M 2070[6] R/W SSI clock speed: 0: 5MHz, 1: 10MHz
SSI_CKGATE 2070[5] R/W SSI gated clock enable. When low, the SCLK is continuous. When
high, the clock is held low when data is not being transferred.
SSI_FSIZE[1:0] 2070[4:3] R/W SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SSI_FPOL 2070[2] R/W SFR pulse polarity: 0: positive, 1: negative
DATA SHEET
NOVEMBER 2010
SSI_RDYEN 2070[1] R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL 2070[0] R/W SRDY polarity: 0: positive, 1: negative
SSI_BEG[7:0] 2071[7:0] R/W The beginning and ending address of the transfer region of the CE
SSI_END[7:0] 2072[7:0] data memory. If the SSI is enabled, a block of words starting with
SSI_BEG and ending with SSI_END will be sent. SSI_END must be
larger than SSI_BEG. The maximum number of output words is limited
by the number of SSI clocks in a CE code pass—see FIR_LEN,
MUX_DIV, and SSI_10M.
Together w/ PRE_SAMPS, this value determines (for the CE) the
SUM_CYCLES
2001[5:0] R/W number of samples in one sum cycle between XFER interrupts.
[5:0]
Number of samples = PRE_SAMPS*SUM_CYCLES.
TMUX[3:0] 2000[3:0] R/W Selects one of 16 inputs for TMUXOUT.
0 – DGND (analog)
1 – IBIAS (analog)
2 – PLL_2.5V (analog)
3 – VBIAS (analog)
4 – RTM (Real time output from CE)
5 – WDTR_EN (Comparator 1 Output AND V1LT3)
6 – reserved
7 – reserved
8 – RXD (from Optical interface)
9 – MUX_SYNC (from MUX_CTRL)
A – CK_10M
B – CK_MPU
C – reserved for production test
D – RTCLK
E – CE_BUSY
F – XFER_BUSY
RESERVED 2005[7] R/W Must be zero.
TRIMSEL 20FD W Selects the temperature trim fuse to be read with the TRIM register
(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)
TRIM 20FF R Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the
value written to TRIMSEL. If TRIMBGB = 0 then the IC is a 6511 else
the IC is a 6511H.
VERSION[7:0] 2006 R The silicon revision number. This data sheet does not apply to
revisions < 000 0100.
VREF_CAL 2004[7] R/W Brings VREF out to the VREF pin. This feature is disabled when
VREF_DIS=1.
VREF_DIS 2004[3] R/W Disables the internal voltage reference.
WD_RST SFR W Resets the WD timer. The WDT is reset when a 1 is written to this bit.
E8[7] Only byte operations on the whole WDI register should be used.
WD_OVF 2002[2] R/W The WD overflow status bit. This bit is set when the WD timer
overflows. It is powered by the VBAT pin and at boot-up will indicate if
the part is recovering from a WD overflow or a power fault. This bit
should be cleared by the MPU on boot-up. It is also automatically
cleared when RESETZ is low.
DATA SHEET
NOVEMBER 2010
CE Program and Environment
CE Program
The CE program is supplied by TERIDIAN as a data image that can be merged with the MPU operational code for meter
applications. Typically, the CE program covers most applications and does not need to be modified. The description in this
section applies to CE code revision CE11B05.
Formats
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement (-1 = 0xFFFFFFFF). ‘Calibration’
parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before
enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the
behavior of the CE code. ‘Output’ variables are outputs of the CE calculations. The corresponding MPU address for the most
significant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte.
Constants
Constants used in the CE Data Memory tables are:
Sampling frequency: FS = 32768Hz/13 = 2520.62Hz (MUX_DIV = 1) or 32786/10 = 3276.8Hz (MUX_DIV = 2)
F0 is the fundamental signal frequency, typically 50 or 60Hz.
IMAX is the external rms current corresponding to 250mV peak at the inputs IA or IB.
VMAX is the external rms voltage corresponding to 250mV peak at the input VA.
NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. This value resides in
SUM_PRE (CE address 36).
Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS.
In_8 is a gain constant of current channel n. Its value is 8 or 1 and is controlled by In_SHUNT.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW.
-9
Voltage LSB = VMAX * 3.3243*10 V (peak).
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to
external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an
actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interface to external meter input
quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be pro-
grammed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.
The parameters EQU, CE_EN, PRE_SAMPS, and SUM_CYCLES are essential to the function of the CE and are stored in I/O
RAM (see I/O RAM section).
DATA SHEET
NOVEMBER 2010
Environment
Before starting the CE using the CE_EN bit, the MPU has to establish the proper environment for the CE by implementing the
following steps:
• Loading the image for the CE code into CE PRAM.
• Loading the CE data into CE DRAM.
• Establishing the equation to be applied in EQU.
• Establishing the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
• Establishing the number of cycles per ADC mux cycle.
The default configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV = 1 (4 conversions per mux cycle). There
must be thirteen CK32 cycles (see System Timing Diagram, Figure 13). This means that the product of the number of cycles
per ADC conversion and the number of conversions per cycle must be 12 (allowing for one settling cycle).
Alternatively, the 71M6511 can be operated at ten CK32 cycles per ADC mux cycle (MUX_DIV = 2). CE quantities are stated
in this section for MUX_DIV = 2, if they differ from those associated with the default setting.
During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer
sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of CHOP must be altered
for each sample. It must also alternate for each alternate multiplexer reading.
The MPU must program CHOP_EN alternately between 01 and 10 on every CE_BUSY interrupt except for the first CE_BUSY
after an XFER_BUSY interrupt. Note that when XFER_BUSY occurs, it will always be at the same time as a CE_BUSY
interrupt.
Operating CE codes with environment parameters deviating from the values specified by Teridian will lead to
unpredictable results.
CE Calculations
The CE performs the precision computations necessary to accurately measure power. These computations include offset
cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag
detection, peak detection, and voltage phase measurement. All data computed by the CE is dependent on the selected meter
equation as given by EQU (in I/O RAM). As a function of EQU, the element components V0 through I2 take on different
meanings.
DATA SHEET
NOVEMBER 2010
CE RAM Locations
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below.
CE Status Word
Since the CE_BUSY interrupt occurs at 2520.6Hz (or at 3276.8Hz when MUX_DIV = 2), it is desirable to minimize the
computation required in the interrupt handler of the MPU. The MPU can read CESTATUS at every CE_BUSY interrupt.
CE Name Description
Address
0x51 CESTATUS See description of CE status word below
The CE Status Word is useful for generating early warnings to the MPU. It contains sag warnings for phase A, as well as F0,
the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage
and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage.
CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).
Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY
interrupt and remains valid for up to 100µs after the CE_BUSY interrupt occurs. Unsynchronized read operations of
CESTATUS will yield unreliable results.
The significance of the bits in CESTATUS is shown in the table below:
CESTATUS Name Description
[bit]
31-29 Not Used These unused bits will always be zero.
28 F0 F0 is a square wave at the exact fundamental input frequency.
27 RESERVED
26 RESERVED
Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT
25 SAG_A
samples. Will not return to zero until VA rises above SAG_THR.
24-0 Not Used These unused bits will always be zero.
DATA SHEET
NOVEMBER 2010
For generating proper status information, the CE is initialized by the MPU using SAG_THR (default of 80V RMS at the meter
input if VMAX=600V) and SAG_CNT (default 80 samples). Using the default value for SAG_CNT, the peak-to-peak signal has to
be below SAG_THR value for 32 milliseconds to activate the SAG_X status bits.
CE Name Default Description
Address
Meter voltage inputs must be above this threshold to prevent sag alarms.
-9
LSB = VMAX * 3.3243*10 V peak.
+56,722,300 For example, if a sag threshold of 80V RMS is desired,
CE Transfer Variables
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer
variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout
each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X.
Fundamental Power Measurement Variables
The table below describes each transfer variable for fundamental power measurement. All variables are signed 32 bit integers.
Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the
integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow.
CE Name Description
Address
42 RESERVED
43 W0SUM_X The sum of Watt samples from each wattmeter element (In_8 is the gain
44 W1SUM_X configured by IA_SHUNT or IB_SHUNT).
-13
LSB = 6.6952*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 1)
-13
45 RESERVED LSB = 5.1501*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)
46 RESERVED
47 VAR0SUM_X The sum of VAR samples from each wattmeter element (In_8 is the gain
48 VAR1SUM_X configured by IA_SHUNT or IB_SHUNT).
-13
LSB = 6.6952*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 1)
-13
49 RESERVED LSB = 5.1501*10 VMAX IMAX / In_8 Wh (for MUX_DIV = 2)
WxSUM_X is the Wh value accumulated for element ‘X’ in the last accumulation interval and can be computed based on the
specified LSB value.
For example with VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X ) is 0.08356 µWh (MUX_DIV = 1).
DATA SHEET
NOVEMBER 2010
Instantaneous Power Measurement Variables
The FREQSEL Register selects the input phase used for frequency measurement and for the MAIN_EDGE counter. The
frequency measurement is implemented using the frequency locked loop of the CE for the selected phase.
IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval.
INSQSUM_X can be used for computing the neutral current.
CE Name Description
Address
33 RESERVED
Fundamental frequency.
4D RESERVED
4E V0SQSUM_X The sum of squared voltage samples from each element.
4F RESERVED LSB= 6.6952*10-13 VMAX2 V2h (for MUX_DIV = 1)
-13 2 2
50 RESERVED LSB = 5.1501*10 VMAX V h (for MUX_DIV = 2)
The RMS values can be computed by the MPU from the squared current and voltage samples as per the formulae:
CE Name Description
Address
52 RESERVED
53 RESERVED
The number of edge crossings of the selected voltage in the previous
55 MAINEDGE_X accumulation interval. Edge crossings are either direction and are de-
bounced.
DATA SHEET
NOVEMBER 2010
EXT_TEMP allows the MPU to select between direct control of GAIN_ADJ or management of GAIN_ADJ by the CE, based on
TEMP_X and the temperature correction coefficients PPMC and PPMC2.
Output variables: TEMP_X is the temperature measurement from reference temperature of TEMP_NOM. TEMP_X is
computed using TEMP_RAW_X and DEGSCALE. This quantity is positive when the temperature is above the reference and is
negative for cold temperatures.
TEMP_RAW_X is the raw processed value from ADC output and is the fundamental quantity for temperature measurement.
TEMP_RAW_X is less than TEMP_NOM at higher temperatures. TEMP_RAW_X is more than TEMP_NOM for cooler
temperatures than reference temperature.
DATA SHEET
NOVEMBER 2010
GAIN_ADJ is a scaling factor for power measurements based on temperature (when in internal temperature compensation
mode). In general, for higher temperatures it is lower than 16384 and higher than 16384 for lower temperatures. GAIN_ADJ is
mainly dependent on the PPMC, PPMC2 and TEMP_X register values. This parameter is automatically computed by the CE
and is used by the CE for temperature compensation.
CE Name Description
Address
0x40 TEMP_X Deviation from Calibration temperature. LSB = 0.1 0C.
Filtered, unscaled reading from temperature sensor. This
0x54 TEMP_RAW_X value should be written to TEMP_NOM during meter
calibration.
Scales all voltage and current inputs. 16384 provides
0x2E GAIN_ADJ unity gain. Default is 16384. If EXT_TMP = 0, GAIN_ADJ
is updated by the CE.
Pulse Generation
Input variables: The combination of the PULSE_SLOW and PULSE_FAST parameters control the speed of the pulse rate. The
default values of 1 and 1 will maintain the original pulse rate given by the Kh equation.
WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The lower WRATE it is the
slower is the pulse rate for measured power quantity. The metering constant Kh is derived from WRATE as the amount of
energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one
pulse per second. If the load is 240V at 150A, ten pulses per second will be generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE > 0. In this case, the pulse rate is determined by
APULSEW and APULSER. The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses.
Irrespective of the EXT_PULSE, status the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE > 0, the MPU is providing the source for pulse generation. If EXT_PULSE is negative, W0SUM_X
and VAR0SUM_X are the default pulse generation sources. In this case, creep cannot be controlled since it is an MPU function.
The maximum pulse rate is FS /2= 1260.3Hz (MUX_DIV = 1).
PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. When
MUX_DIV = 1, the minimum pulse width possible is 397µs.
The maximum time jitter is 397µs (for MUX_DIV = 1) and is independent of the number of pulses measured. Thus, if the pulse
generator is monitored for 1 second, the peak jitter is 397PPM. After 10 seconds, the peak jitter is 39.7PPM. The average jitter
is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its
maximum rate without exhibiting any roll-over characteristics. The actual pulse rate, using WSUM as an example, is:
X ⋅ WRATE ⋅ WSUM ⋅ FS
RATE = Hz
2 46
Where FS = 2520.6Hz (sampling frequency for MUX_DIV = 1) or 3276.8Hz (sampling frequency for MUX_DIV = 2) and X is the
pulse gain factor derived from CE variables PULSE_SLOW and PULSE_FAST (see table below).
DATA SHEET
NOVEMBER 2010
0x36 SUM_PRE 2520 PRE_SAMPS * SUM_CYCLES. This variable is also called NACC.
Should be 15 or 0. When zero, causes the pulse generators to respond to
0x37 EXT_PULSE 15 WSUM_X and VARSUM_X. Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
The maximum pulse width (low-going pulse) is:
(2 * PULSE_WIDTH + 1) * 397µs (for MUX_DIV = 1)
0x3C PULSE_WIDTH 50
(2 * PULSE_WIDTH + 1) * 305µs (for MUX_DIV = 2)
0 is a legitimate value.
Wh pulse generator input, to be updated by the MPU when using external pulse
generation (see DIO_PW bit). The output pulse rate is:
-32 -14
0x26 APULSEW 0 APULSEW * FS * 2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation in-
terval. The change will take effect at the beginning of the next interval.
VARh pulse generator input to be updated by the MPU when using external
pulse generation (see DIO_PV bit). The output pulse rate is:
-32 -14
0x27 APULSER 0 APULSER * FS*2 * WRATE * 2
This input is buffered and can be updated by the MPU during a computation in-
terval. The change will take effect at the beginning of the next interval.
DATA SHEET
NOVEMBER 2010
Current Shunt Variables
Input variables: IA_SHUNT and IB_SHUNT can configure the current inputs to accept shunt resistor sensors. In this case the
CE provides an additional gain of 8 to the current inputs. This will enable the pulse rate to change by 8 times. In order to
maintain a normal pulse rate WRATE may have to be decreased by 8 times. Whenever IA_SHUNT or IB_SHUNT are set to 1 or
a positive number, In_8 is assigned a value of 8 in the equation for Kh.
CE Name Default Description
Address
When +1, these variables increase the respective current gain by 8. The
2A IA_SHUNT -1 gain factor controlled by In_SHUNT is referred to as In_8 throughout this
document. Allowed values are 1 or –1. For example, if IB_SHUNT=-1, IB_8
= 1, if IB_SHUNT = 1, IB_8 = 8.
2B IB_SHUNT -1
IA_SHUNT corresponds to IA_8, IB_SHUNT corresponds to IB_8.
2C RESERVED
CE Calibration Parameters
The table below lists the parameters that are typically entered to affect calibration of meter accuracy.
angle Φ:
a ⋅ TANΦ
PHADJ _ X = 2 20 F0T =
b − c ⋅ TANΦ
F0
a = 1 + (1 − 2 −9 ) 2 − 2(1 − 2 −9 ) cos(2πF0T )
F 0 FS
b = (1 − 2 −9 ) sin( 2πF0T )
c = 1 − (1 − 2 −9 ) cos(2πF0T )
10 0
DATA SHEET
NOVEMBER 2010
Other CE Parameters
The table below shows CE parameters used for suppression of noise due to scaling and truncation effects as well as scaling
factors.
CE Name Default Description
Address
These parameters are added to the Watt calculation to compensate for input
2F QUANTA 0 noise and truncation.
-10
22 QUANTB 0 LSB=(VMAX*IMAX / IA_8) *7.4162*10 W for phase A, and
-10
LSB=(VMAX*IMAX / IB_8) *7.4162*10 W for phase B
These parameters are added to the VAR calculation to compensate for input
34 QUANT_VARA 0 noise and truncation.
-10
24 QUANT_VARB 0 LSB = (VMAX*IMAX / IA_8) * 7.4162*10 W for phase A, and
-10
LSB = (VMAX*IMAX / IB_8) * 7.4162*10 W for phase B
These parameters are added to compensate for input noise and truncation in
2 2
the squaring calculations for I and V .
35 QUANT_IA 0 2 -10 2
LSB=VMAX *7.4162*10 V ,
23 QUANT_IB 0
LSB= (IMAX2/IA_82)*7.4162*10-10 A2 for phase A and
2 2 -10 2
LSB= (IMAX /IB_8 )*7.4162*10 A for phase B.
Scale factor for the VAR calculation. The default value of KVAR should never
need to be changed.
3B KVAR
6448 for MUX_DIV = 1
12880 for MUX_DIV = 2
DATA SHEET
NOVEMBER 2010
DATA SHEET
NOVEMBER 2010
Harmonic Performance
2
1
0
-1
-2
Error [%]
Test performed at current distortion amplitude of 40% and voltage distortion amplitude of 10% as per IEC 62053, part 22.
DATA SHEET
NOVEMBER 2010
APPLICATION INFORMATION
Connection of Sensors (CT, Resistive Shunt, Rogowski Coil)
Figure 27 and Figure 28 show how resistive dividers, current transformers, restive shunts, and Rogowski coils are connected
to the voltage and current inputs of the 71M6511.
The analog input pins of the 71M6511 are designed for sensors with low source impedance. RC filters with resistance
values higher than those implemented in the Teridian Demo Boards should be avoided.
VA
R
Vout
Iin Vout = dIin /dt
1/N
IA
R
Vout VC
V3P3
The second process applied to the 71M6511H is the characterization of the reference voltage over temperature. The
coefficients for the reference voltage are stored in so-called trim fuses (I/O RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0].
The MPU program can read these trim fuses and calculate the correction coefficients PPM1 and PPM2 per the formulae given
in the Performance Specifications section (VREF, VBIAS). See the Temperature Compensation section for details.
The fuse TRIMBGB is non-zero for the 71M6511H part and zero for the 71M6511 part.
Trim fuse information is not available for non-H parts. Thus, the standard are to be applied. These settings are:
• PPMC = TC1 * 22.46 = –149
• PPMC2 = TC2 * 1150.1 = –392
DATA SHEET
NOVEMBER 2010
Temperature Compensation and Mains Frequency Stabilization for the RTC
The accuracy of the RTC depends on the stability of the external crystal. Crystals vary in terms of initial accuracy as well as in
terms of behavior over temperature. The flexibility provided by the MPU allows for compensation of the RTC using the sub-
strate temperature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL,
Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate temperatures tracks the crystal temperature, the
coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the
RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM.
It is not recommended to measure crystal frequency directly due to the error introduced by the measurement probes. A
practical method to measure the crystal frequency (when installed on the PCB with the 71M6511) is to have a DIO pin toggle
every second, based on the RTC interrupt, with all other interrupts disabled. When this signal is measured with a precision
timer, the crystal frequency can be obtained from the measured time period t (in µs):
f = 32768
10 6 µs
t
Example: Let us assume a crystal characterized by the measurements shown in Table 62. The values show that even at
nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal
frequency is 11.6 PPM, resulting in about one second inaccuracy per day, i.e. more than some standards allow.
Deviation from Measured Deviation from
Nominal Frequency [Hz] Nominal
Temperature [°C] Frequency [PPM]
+50 32767.98 -0.61
+25 32768.28 8.545
0 32768.38 11.597
-25 32768.08 2.441
-50 32767.58 -12.817
Table 62: Frequency over Temperature
As Figure 29 shows, even a constant compensation would not bring much improvement, since the temperature characteristics
of the crystal are a mix of constant, linear, and quadratic effects (in commercially available crystals, the constant and quadratic
effects are dominant).
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8
32767.7
32767.6
32767.5
-50 -25 0 25 50
DATA SHEET
NOVEMBER 2010
When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal
characteristics. The frequencies were calculated using the fit coefficients as follows:
c
f = f nom ⋅ 1 + 6 + T 6 + T 2 6
a b
10 10 10
32768.5
32768.4
32768.3
32768.2
32768.1
32768
32767.9
32767.8 crystal
32767.7 curve fit
32767.6 inverse curve
32767.5
-50 -25 0 25 50
T = TN +
TEMP _ X
10
DATA SHEET
NOVEMBER 2010
Crystal Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these
crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is
very low to maximize the lifetime of any battery backup device attached to VBAT.
Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good layouts will have XIN and
XOUT shielded from each other.
For best rejection of electromagnetic interference, connect the crystal body and the ground terminals of the two
crystal capacitors to GNDD through a ferrite bead. No external resistor should be connected across the crystal,
since the oscillator is self-biasing.
Connecting LCDs
The 71M6511 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 31 shows the basic
connection for a LCD.
71M6511
LCD
segments
commons
DATA SHEET
NOVEMBER 2010
V3P3
LCD_BSTEN 71M6511
VDRV
V3P3
5VDC
VLCD 5V LCD
Contrast LCD_FS
ON/OFF LCD_EN
LCD type LCD_MODE segments
commons
DATA SHEET
NOVEMBER 2010
Connecting I2C EEPROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 33.
Pull-up resistors of roughly 3kΩ to V3P3 should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM
must be set to 1 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.
V3P3
71M6511 3kΩ
3kΩ
EEPROM
DIO4 SCL
DIO5 SDA
V3P3
71M651X
R1 = 100kΩ
RX
VIN
DATA SHEET
NOVEMBER 2010
Optical Interface
The pins OPT_TX and OPT_RX can be used for a regular serial interface, e.g. by connecting a RS_232 transceiver, or they
can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a FLAG interface.
Figure 35 shows the basic connections. The OPT_TX pin becomes active when the I/O RAM register OPT_TXDIS is set to 0.
V3P3
71M6511 R1
100pF 100kΩ
OPT_RX
Phototransistor
V3P3
LED
R2
OPT_TX
R1 R3
10kΩ
Vin C1 V1
R2
100pF
DATA SHEET
NOVEMBER 2010
71M6511
V3P3 V3P3
200Ω
R1
10Ω
RESETZ
R2
C1
Pushbutton 1nF
DGND
DATA SHEET
NOVEMBER 2010
SPECIFICATIONS
Electrical Specifications
ABSOLUTE MAXIMUM RATINGS
DATA SHEET
NOVEMBER 2010
RECOMMENDED OPERATING CONDITIONS
LOGIC LEVELS
1
Guaranteed by design, not subject to test.
DATA SHEET
NOVEMBER 2010
SUPPLY CURRENT
1
Guaranteed by design, not subject to test.
DATA SHEET
NOVEMBER 2010
VREF, VBIAS
Unless otherwise specified, VREF_DIS=0
PARAMETER CONDITION MIN TYP MAX UNIT
VREF output voltage, VNOM(25) Ta = 22ºC 1.193 1.195 1.197 V
VREF chop step 40 mV
VREF_CAL = 1,
VREF output impedance 2.5 kΩ
ILOAD = 10µA, -10µA
A 2
VNOM definition VNOM(T) = VREF(22) + (T–22)TC1 + (T–22) TC2 V
-- If TRIMBGA and TRIMBGB available (6511H) --
VREF temperature coefficients
TC1 (linear) x(33-0.28y) + 0.33y + 7.9
TC2 (quadratic) x(0.02-0.0002y) – 0.46 µV/°C
TRIMBGA, TRIMBGB, TRIMM[2:0]: See where x = 0.1TRIMBGB - 0.14(TRIMM[2:0]+0.5), µV/°C
2
VREF (T ) − VNOM (T )
VREF(T) deviation from VNOM(T)
10 6
max(| T − 22 |,40)
-10 10 ppm/ºC
VNOM
-- If TRIMBGA and TRIMBGB not available (6511) --
VREF temperature coefficients
TC1 (linear) 7.0 µV/ºC
2
TC2 (quadratic) -0.341 µV/°C
VREF (T ) − VNOM (T )
VREF(T) deviation from VNOM(T)
10 6 1 1
max(| T − 22 |,40)
Ta = -40ºC to +85ºC -40 +40 ppm/ºC
VNOM
±25
ppm/
VREF aging Ta = 25ºC
year
Ta = 25ºC (-1%) 1.5 (+1%) V
VBIAS output voltage 1 1 1
Ta = -40ºC to 85ºC (-2%) 1.5 (+2%) V
VBIAS output impedance ILOAD = 1mA, -1mA 240 500 Ω
1
Guaranteed by design, not subject to test.
A
This relationship describes the nominal behavior of VREF at different temperatures.
CRYSTAL OSCILLATOR
Crystal is disconnected. Test load is series 200pF, 100kΩ connected between DGND and XOUT.
PARAMETER CONDITION MIN TYP MAX UNIT
Maximum Output Power to Crystal4 Crystal connected 1 μW
XIN to XOUT Capacitance 3 pF
Capacitance to DGND
XIN 5 pF
XOUT 5 pF
Watchdog RTC_OK threshold 25 kHz
DATA SHEET
NOVEMBER 2010
ADC CONVERTER, VDD REFERENCED
FIR_LEN=0, VREF_DIS=0, VDDREFZ=0
PARAMETER CONDITION MIN TYP MAX UNIT
Recommended Input Range mV
-250 250
(Vin-V3P3A) peak
Voltage to Current Crosstalk: Vin = 200mV peak, 65Hz,
on VA
cos(∠Vin − ∠Vcrosstalk ) Vcrosstalk = largest
10 6 *Vcrosstalk -10
1
101 μV/V
Vin
measurement on IA or IB
THD (First 10 harmonics) Vin=65Hz,
250mV- peak 64kpts FFT, Blackman- -75 dB
20mV- peak Harris window -90 dB
Input Impedance Vin=65Hz 40 90 kΩ
Temperature coefficient of Input
Vin=65Hz 1.7 Ω/°C
Impedance
LSB size FIR_LEN=1 150 nV/LSB
Digital Full Scale ±2097152 LSB
ADC Gain Error versus
OPTICAL INTERFACE
TEMPERATURE SENSOR
( N (T ) − N (25))
Temperature Error
ERR = (T − 25) −
1 1
TA = -40ºC to +85ºC -3 3 ºC
Sn
1
Guaranteed by design, not subject to test.
2
This parameter defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that
use this nominal relationship as a reference.
DATA SHEET
NOVEMBER 2010
LCD BOOST
PARAMETER CONDITION MIN TYP MAX UNIT
VDRV Frequency OSC/2 Hz
VDRV Sink Current Vol=1.5V 1.2 2.75 mA
VDRV Source Current Voh=1.5V 1.2 2.6 mA
VLCD Target Voltage 4.5 5.5 V
VLCD=5.0V, LCD_FS=1F,
VLCD Input Current LCD_MODE=0,1,2,3 450 μA
LCD_BSTEN=1
LCD DRIVERS
Applies to all COM and SEG pins. Unless otherwise stated, VLCD=5.0V, LCD_FS=1F
PARAMETER CONDITION MIN TYP MAX UNIT
VLC0 Max Voltage (LCD_FS =1F) With respect to VLCD -0.2 0 V
VLC0 Min Voltage (LCD_FS =00) With respect to VLCD*0.7 -0.2 0.2 V
VLC1 Voltage,
1/3 bias With respect to 2*VLCD/3 -10 +10 %
½ bias With respect to VLCD/2 -10 +10 %
VLC0 Voltage,
1/3 bias With respect to VLCD/3 -15 +15 %
∆ILOAD=10µA
½ bias With respect to VLCD/2 -10 +10 %
Output Impedance 30 kΩ
RTC
PARAMETER CONDITION MIN TYP MAX UNIT
Range for date 2000 - 2255 year
RESETZ
PARAMETER CONDITION MIN TYP MAX UNIT
Reset pulse width 5 µs
Reset pulse fall time 11 µs
1
Guaranteed by design, not subject to test.
COMPARATORS
PARAMETER CONDITION MIN TYP MAX UNIT
Offset Voltage
V1-VBIAS -20 15 mV
Hysteresis Current
V1 Vin = VBIAS - 100mV 0.8 1.2 μA
Response Time
V1 +100mV overdrive 2 15 μs
WD Disable Threshold (V1-V3P3A) -400 -10 mV
DATA SHEET
NOVEMBER 2010
RAM AND FLASH MEMORY
PARAMETER CONDITION MIN TYP MAX UNIT
CKMPU = 4.9MHz 5 Cycles
CE RAM wait states
CKMPU = 1.25MHz 2 Cycles
Flash write cycles -40°C to +85°C 20,000 Cycles
Flash data retention 85°C 10 Years
Flash data retention 25°C 100 Years
Flash byte writes between page or mass
2 Cycles
erase operations
EEPROM INTERFACE
PARAMETER CONDITION MIN TYP MAX UNIT
CKMPU=4.9MHz, Using
78 kHz
interrupts
Write Clock frequency
CKMPU=4.9MHz, “bit-
150 kHz
banging” DIO4/5
≥0.1±20% µF
NAME FROM TO FUNCTION VALUE UNIT
≥0.1±20% µF
C1 V3P3A AGND Bypass capacitor for 3.3V supply
C2 V3P3D DGND Bypass capacitor for 3.3V supply
32.768kHz crystal. Electrically similar to ECS
XTAL XIN XOUT 32.768 kHz
ECX-3TA series
CXS XIN AGND Load capacitor for crystal (depends on crystal 22±10% pF
specs and board parasitics).
≥1000±20%
CXL XOUT AGND 22±10% pF
CBIAS VBIAS AGND Bypass capacitor for VBIAS pF
≥0.1±20% µF
CBST1 VDRV External Boost charging capacitor 33±20% nF
≥0.22±20% µF
C2P5 V2P5 DGND Bypass capacitor for V2P5
CBST2 VLCD DGND Boost bypass capacitor
DATA SHEET
NOVEMBER 2010
Packaging Information
64-Pin LQFP PACKAGE OUTLINE (Bottom View).
NOTE: Controlling dimensions are in mm.
11.7
12.3
11.7
12.3
+
9.8 0.00
10.2
0.20
1.40
0.50 Typ. 0.14 1.60
0.60 Typ. 0.28
DATA SHEET
NOVEMBER 2010
Pinout (Top View)
OPT_RX
E_TCLK
V3P3A
E_RST
VBIAS
GNDA
GNDA
XOUT
VLCD
VREF
TEST
XIN
VA
V1
IB
IA
61
51
49
64
63
62
60
59
58
57
56
55
54
53
52
50
GNDD 1 48 RESETZ
E_RXTX 2 47 V2P5
OPT_TX 3 46 VBAT
TMUXOUT 4 45 RX
TX 5 44 SEG31/DIO11
SEG3/SCLK
VDRV
CKTEST
6
8
TERIDIAN 43
42
41
SEG30/DIO10
SEG29/DIO9
SEG28/DIO8
V3P3D
SEG4/SSDATA
9
10
71M6511-IGT 40
39
SEG27/DIO7
SEG26/DIO6
SEG5/SFR 11 38 SEG25/DIO5
SEG37/DIO17 12 37 SEG24/DIO4
COM0 13 36 SEG19
COM1 14 35 SEG18
COM2 15 34 SEG17
16
COM3 33 SEG16
20
21
22
23
24
25
26
27
28
29
30
31
32
18
19
17
SEG1
SEG36/DIO16
SEG0
SEG2
SEG11
SEG6/SRDY
SEG7/MUX_SYNC
SEG35/DIO15
SEG8
SEG9
SEG34/DIO14
SEG13
SEG14
SEG12
SEG10
SEG15
DATA SHEET
NOVEMBER 2010
Pin Descriptions
Power/Ground Pins
GNDA 49, 58 P Analog ground: This pin should be connected directly to the ground plane.
GNDD 1 P Digital ground: This pin should be connected directly to the ground plane.
V3P3A 50 P Analog power supply: A 3.3V power supply should be connected to this pin.
V3P3D 9 P Digital power supply: A 3.3V power supply should be connected to this pin.
Battery backup power supply. A battery or super-capacitor should be connected between
VBAT 46 P
VBAT and GNDD. If no battery is used, connect VBAT to V3P3D.
Output of the internal 2.5V regulator. A 0.1µF capacitor to GNDA should be connected to this
V2P5 47 O
pin.
VLCD 62 P LCD power supply. A DC source of 3.3V to 5.0V should be connected to this pin.
Analog Pins
DATA SHEET
NOVEMBER 2010
Digital Pins:
DATA SHEET
NOVEMBER 2010
I/O Equivalent Circuits:
V3P3D
V3P3D
V3P3A
110K
Digital
CMOS
Input LCD SEG from VREF
Input LCD
Pin Output internal Pin
Driver
Pin reference
GNDD
GNDD GNDA
Digital Input Equivalent Circuit LCD Output Equivalent Circuit VREF Equivalent Circuit
Type 1: Type 5: Type 9:
Standard Digital Input or LCD SEG or VREF
pin configured as DIO Input pin configured as LCD SEG
with Internal Pull-Up
V3P3D
V3P3A
V3P3D
Digital
CMOS
Input from
Input Analog V2P5
Pin To
110K Input internal Pin
MUX
Pin reference
GNDD GNDD
GNDA GNDD
V3P3D
V3P3A
Digital CMOS
Input Input Comparator
Pin To VLCD LCD
Input
Comparator Pin Drivers
Pin
GNDD
GNDA GNDD
V3P3D
V3P3D
V3P3D
CMOS Digital
Output Output Oscillator To VBAT Power
Pin Pin Oscillator Pin Down
Circuits
GNDD
GNDD
GNDD GNDD
Digital Output Equivalent Circuit Oscillator Equivalent Circuit VBAT Equivalent Circuit
Type 4: Type 8: Type 12:
Standard Digital Output or Oscillator I/O VBAT Power
pin configured as DIO Output
DATA SHEET
NOVEMBER 2010
ORDERING INFORMATION
ORDERING PACKAGE
PART DESCRIPTION
NUMBER MARKING
71M6511
71M6511-IGT 71M6511-IGT
64-pin LQFP, 0.5% accuracy
71M6511
71M6511-IGT/F 71M6511-IGT
64-pin Lead-Free LQFP, 0.5% accuracy
71M6511
71M6511-IGTR 71M6511-IGT
64-pin LQFP, 0.5% accuracy, T&R
71M6511
71M6511-IGTR/F 71M6511-IGT
64-pin Lead-Free LQFP, 0.5% accuracy, T&R
71M6511H
71M6511H-IGT 71M6511H-IGT
64-pin LQFP, 0.1% accuracy
71M6511H
71M6511H-IGT/F 71M6511H-IGT
64-pin Lead-Free LQFP, 0.1% accuracy
71M6511H
71M6511H-IGTR 71M6511H-IGT
64-pin LQFP, 0.1% accuracy, T&R
71M6511H
71M6511H-IGTR/F 71M6511H-IGT
64-pin Lead-Free LQFP, 0.1% accuracy, T&R
DATA SHEET
NOVEMBER 2010
REVISION HISTORY
Revision Date Description
2.7 11/10 Added guaranteed by design specifications to the electrical specifications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent
licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.
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