a CMOS, 330 MHz

Triple 8-Bit High Speed Video DAC

ADV7125
FEATURES FUNCTIONAL BLOCK DIAGRAM
330 MSPS Throughput Rate
Triple 8-Bit DACs VAA

RS-343A/RS-170 Compatible Output

Complementary Outputs BLANK BLANK AND
SYNC SYNC LOGIC
DAC Output Current Range 2 to 26 mA
TTL Compatible Inputs
DATA IOR
Internal Reference (1.23 V) R7–R0 8
REGISTER
8 DAC
IOR
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package DATA IOG
G7–G0 8 8 DAC
Low Power Dissipation (30 mW Min @ 3 V) REGISTER IOG
Low Power Standby Mode (6 mW Typ @ 3 V)
DATA IOB
Industrial Temperature Range (–40°C to +85°C) B7–B0 8
REGISTER
8 DAC
IOB
APPLICATIONS
POWER-DOWN VOLTAGE
Digital Video Systems PSAVE
MODE REFERENCE VREF
CIRCUIT
High Resolution Color Graphics
CLOCK
Digital Radio Modulation ADV7125
Image Processing GND RSET COMP
Instrumentation
Video Signal Reconstruction

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The ADV®7125 is a triple high speed, digital-to-analog converter 1. 330 MSPS (3.3 V only) throughput
on a single monolithic chip. It consists of three high speed, 8-bit 2. Guaranteed monotonic to eight bits
video DACs with complementary outputs, a standard TTL input 3. Compatible with a wide variety of high resolution color
interface, and a high impedance, analog output current source. graphics systems, including RS-343A and RS-170
The ADV7125 has three separate 8-bit-wide input ports. A single
5 V/3.3 V power supply and clock are all that are required to make
the part functional. The ADV7125 has additional video control
signals, composite SYNC and BLANK, as well as a power-
save mode.
The ADV7125 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7125 is available in a 48-lead
LQFP package.

ADV is a registered trademark of Analog Devices, Inc.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADV7125–SPECIFICATIONS
(VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to
5 V ELECTRICAL CHARACTERISTICS TMAX1, unless otherwise noted, TJ MAX = 110ⴗC.)
Parameter Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) –1 ± 0.4 +1 LSB
Differential Nonlinearity –1 ± 0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN –1 +1 µA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 µA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 100 kΩ
Output Capacitance, COUT 10 pF IOUT = 0 mA
Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V
Gain Error2 –5.0 +5.0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, VREF 1.12 1.235 1.35 V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA fCLK = 50 MHz
Digital Supply Current3 10.5 15 mA fCLK = 140 MHz
Digital Supply Current3 18 25 mA fCLK = 240 MHz
Analog Supply Current 67 72 mA RSET = 530 Ω
Analog Supply Current 8 mA RSET = 4933 Ω
Standby Supply Current4 2.1 5.0 mA PSAVE = Low, Digital, and Control
Inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2
Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V REF/RSET × K × (FFH) × 4 and K = 7.9896.
3
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
4
These max/min specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
Specifications subject to change without notice.

–2– REV. 0
 ADV7125
(VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications
3.3 V ELECTRICAL CHARACTERISTICS1 TMIN to TMAX2, unless otherwise noted, TJ MAX = 110ⴗC.)
Parameter Min Typ Max Unit Test Conditions2
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits RSET = 680 Ω
Integral Nonlinearity (BSL) –1 ± 0.5 +1 LSB RSET = 680 Ω
Differential Nonlinearity –1 ± 0.25 +1 LSB RSET = 680 Ω
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN –1 +1 µA VIN = 0.0 V or VDD
PSAVE Pull-Up Current 20 µA
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA Green DAC, Sync = High
Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, ROUT 70 kΩ
Output Capacitance, COUT 10 pF
Offset Error 0 0 % FSR Tested with DAC Output = 0 V
Gain Error3 0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF 1.12 1.235 1.35 V
VOLTAGE REFERENCE (Int.)
Reference Range, VREF 1.235 V
POWER DISSIPATION
Digital Supply Current4 2.2 5.0 mA fCLK = 50 MHz
Digital Supply Current4 6.5 12.0 mA fCLK = 140 MHz
Digital Supply Current4 11 15 mA fCLK = 240 MHz
Digital Supply Current4 16 mA fCLK = 330 MHz
Analog Supply Current 67 72 mA RSET = 560 Ω
Analog Supply Current 8 mA RSET = 4933 Ω
Standby Supply Current 2.1 5.0 mA PSAVE = Low, Digital, and Control
Inputs at VDD
Power Supply Rejection Ratio 0.1 0.5 %/%
NOTES
1
These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
2
Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3
Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V REF/RSET × K × (FFH) × 4 and K = 7.9896.
4
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
Specifications subject to change without notice.

REV. 0 –3–
ADV7125
(VAA = 5 V ± 5%2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX3,
5 V TIMING SPECIFICATIONS1 unless otherwise noted, TJ MAX = 110ⴗC.)
Parameter Min Typ Max Unit Condition
ANALOG OUTPUTS
Analog Output Delay, t6 5.5 ns
Analog Output Rise/Fall Time, t74 1.0 ns
Analog Output Transition Time, t85 15 ns
Analog Output Skew, t96 1 2 ns
CLOCK CONTROL
fCLK7 0.5 50 MHz 50 MHz Grade
fCLK7 0.5 140 MHz 140 MHz Grade
fCLK7 0.5 240 MHz 240 MHz Grade
Data and Control Setup, t16 0.5 ns
Data and Control Hold, t26 1.5 ns
Clock Period, t3 4.17 ns
Clock Pulsewidth High, t46 1.875 ns fCLK_MAX = 240 MHz
Clock Pulsewidth Low, t56 1.875 ns fCLK_MAX = 240 MHz
Clock Pulsewidth High, t46 2.85 ns fCLK_MAX = 140 MHz
Clock Pulsewidth Low, t56 2.85 ns fCLK_MAX = 140 MHz
Clock Pulsewidth High, t4 8.0 ns fCLK_MAX = 50 MHz
Clock Pulsewidth Low, t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay, tPD6 1.0 1.0 1.0 Clock Cycles
PSAVE Up Time, t106 2 10 ns
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.

–4– REV. 0
 ADV7125
(VAA = 3.0 V to 3.6 V2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN
3.3 V TIMING SPECIFICATIONS1 to TMAX3, unless otherwise noted, TJ MAX = 110ⴗC.)

Parameter Min Typ Max Unit Condition

ANALOG OUTPUTS
Analog Output Delay, t6 7.5 ns
Analog Output Rise/Fall Time, t74 1.0 ns
Analog Output Transition Time, t85 15 ns
Analog Output Skew, t96 1 2 ns
CLOCK CONTROL
fCLK7 50 MHz 50 MHz Grade
fCLK7 140 MHz 140 MHz Grade
fCLK7 240 MHz 240 MHz Grade
fCLK7 330 MHz 330 MHz Grade
Data and Control Setup, t16 0.2 ns
Data and Control Hold, t26 1.5 ns
Clock Period, t3 3 ns
Clock Pulsewidth High, t46 1.4 ns fCLK_MAX = 330 MHz
Clock Pulsewidth Low, t56 1.4 ns fCLK_MAX = 330 MHz
Clock Pulsewidth High, t46 1.875 ns fCLK_MAX = 240 MHz
Clock Pulsewidth Low, t56 1.875 ns fCLK_MAX = 240 MHz
Clock Pulsewidth High, t46 2.85 ns fCLK_MAX = 140 MHz
Clock Pulsewidth Low, t56 2.85 ns fCLK_MAX = 140 MHz
Clock Pulsewidth High, t4 8.0 ns fCLK_MAX = 50 MHz
Clock Pulsewidth Low, t5 8.0 ns fCLK_MAX = 50 MHz
Pipeline Delay, tPD6 1.0 1.0 1.0 Clock Cycles
PSAVE Up Time, t106 4 10 ns
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) for 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.

t3
t4 t5

CLOCK
t2
DIGITAL INPUTS
(R7–R0, G7–G0, B7–B0, DATA
SYNC, BLANK)
t1 t8
t6
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t7
NOTES
1. OUTPUT DELAY (t6 ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.

Figure 1. Timing Diagram

REV. 0 –5–
ADV7125
ABSOLUTE MAXIMUM RATINGS 1 NOTES
1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
Voltage on any Digital Pin . . . . . GND – 0.5 V to VAA + 0.5 V device at these or any other conditions above those listed in the operational
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C sections of this specification is not implied. Exposure to absolute maximum rating
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C conditions for extended periods may affect device reliability.
2
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C Analog output short circuit to any power supply or common can be of an indefinite
duration.
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA

ORDERING GUIDE

Speed Options
1 1
Package 50 MHz 140 MHz 240 MHz2 330 MHz2, 3
Plastic LQFP (ST-48) ADV7125KST50 ADV7125KST140 ADV7125JST240 ADV7125JST330
NOTES
1
Specified for –40°C to +85°C operation.
2
Specified for 0°C to +70°C operation.
3
Available in 3.3 V version only.

PIN CONFIGURATION PSAVE

RSET
GND
GND
R7
R6
R5
R4
R3
R2
R1
R0

48 47 46 45 44 43 42 41 40 39 38 37

GND 1 36 VREF
PIN 1
GND 2 IDENTIFIER 35 COMP
G0 3 34 IOR
G1 4 33 IOR
G2 5 32 IOG
G3 6 ADV7125 31 IOG
TOP VIEW
G4 7 (Not to Scale) 30 VAA
G5 8 29 VAA
G6 9 28 IOB
G7 10 27 IOB
BLANK 11 26 GND
SYNC 12 25 GND

13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
VAA

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7125 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–6– REV. 0
 ADV7125
PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Function

1, 2, 14, 15, 25, GND Ground. All GND pins must be connected.
26, 39, 40
3–10, G0–G7, Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
16–23, B0–B7, of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
41–48 R0–R7 be connected to either the regular PCB power or ground plane.
11 BLANK Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the
analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the
rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.
12 SYNC Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches
off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the SYNC input should be tied to logical zero.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected.
24 CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.
27, 31, 33 IOR, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These
RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75 Ω load. If the complementary outputs are not required, these outputs should be
tied to ground.
28, 32, 34 IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of
directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.
35 COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF
ceramic capacitor must be connected between COMP and VAA.
36 VREF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
37 RSET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC
is connected to IOG) is given by:
RSET (Ω) = 11, 445 × VREF (V ) / IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11, 444.8 × VREF (V ) / RSET (Ω)(SYNC being asserted )
IOR , IOB (mA ) = 7, 989.6 × V REF (V ) / RSET (Ω)
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used,
i.e., SYNC tied permanently low.
38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this
pin is active.

REV. 0 –7–
ADV7125
TERMINOLOGY Raster Scan
Blanking Level The most basic method of sweeping a CRT one line at a time to
The level separating the SYNC portion from the video portion generate and display images.
of the waveform. Usually referred to as the front porch or back Reference Black Level
porch. At 0 IRE units, it is the level that will shut off the picture The maximum negative polarity amplitude of the video signal.
tube, resulting in the blackest possible picture.
Reference White Level
Color Video (RGB) The maximum positive polarity amplitude of the video signal.
This usually refers to the technique of combining the three
primary colors of red, green, and blue to produce color pictures Sync Level
within the usual spectrum. In RGB monitors, three DACs are The peak level of the SYNC signal.
required, one for each color. Video Signal
Sync Signal (SYNC) The portion of the composite video signal that varies in grayscale
The position of the composite video signal that synchronizes the levels between reference white and reference black. Also referred
scanning process. to as the picture signal, this is the portion that may be visually
observed.
Grayscale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.

–8– REV. 0
 ADV7125
CIRCUIT DESCRIPTION AND OPERATION The BLANK and SYNC functions allow for the encoding of
The ADV7125 contains three 8-bit DACs, with three input these video synchronization signals onto the RGB video output.
channels, each containing an 8-bit register. Also integrated on This is done by adding appropriately weighted current sources
board the part is a reference amplifier. CRT control functions to the analog outputs, as determined by the logic levels on the
BLANK and SYNC are integrated on board the ADV7125. BLANK and SYNC digital inputs. Figure 3 shows the analog
Digital Inputs output, RGB video waveform of the ADV7125. The influence of
Twenty-four bits of pixel data (color information) R0–R7, G0–G7, SYNC and BLANK on the analog video waveform is illustrated.
and B0–B7 are latched into the device on the rising edge of Table I details the resultant effect on the analog outputs of
each clock cycle. This data is presented to the three 8-bit DACs BLANK and SYNC.
and then converted to three analog (RGB) output waveforms All these digital inputs are specified to accept TTL logic levels.
(See Figure 2).
Clock Input
The CLOCK input of the ADV7125 is typically the pixel clock
CLOCK
rate of the system. It is also known as the dot rate. The dot rate,
DIGITAL INPUTS and thus the required CLOCK frequency, will be determined by
(R7–R0, G7–G0, B7–B0, DATA the on-screen resolution, according to the following equation:
SYNC, BLANK)
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/(Retrace Factor)
ANALOG OUTPUTS
(IOR, IOR, IOB Horiz Res = Number of Pixels/Line
IOR, IOG, IOB)
Vert Res = Number of Lines/Frame
Figure 2. Video Data Input/Output Refresh Rate = Horizontal Scan Rate. This is the rate at which
The ADV7125 has two additional control signals that are latched the screen must be refreshed, typically 60 Hz for a noninterlaced
to the analog video outputs in a similar fashion. BLANK and system or 30 Hz for an interlaced system.
SYNC are each latched on the rising edge of CLOCK to maintain Retrace Factor = Total Blank Time Factor. This takes into account
synchronization with the pixel data stream. that the display is blanked for a certain fraction of the total
duration of each frame (e.g., 0.8).

RED, BLUE GREEN

mA V mA V
18.62 0.7 26.67 1.000 WHITE LEVEL

100 IRE

0 0 8.62 0.3 BLANK LEVEL

43 IRE

0 0 SYNC LEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75⍀ LOAD.
2. V REF = 1.235V, RSET = 530⍀.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 3. RGB Video Output Waveform

Table I. Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)

Description IOG (mA) IOG (mA) IOR/IOB IOR/IOB SYNC BLANK DAC Input Data
WHITE LEVEL 26.67 0 18.62 0 1 1 FFH
VIDEO Video + 8.05 18.62 – Video Video 18.62 – Video 1 1 Data
VIDEO to BLANK Video 18.62 – Video Video 18.62 – Video 0 1 Data
BLACK LEVEL 8.05 18.62 0 18.62 1 1 00H
BLACK to BLANK 0 18.62 0 18.62 0 1 00H
BLANK LEVEL 8.05 18.62 0 18.62 1 0 xxH
SYNC LEVEL 0 18.62 0 18.62 0 0 xxH

REV. 0 –9–
ADV7125
Therefore, if we have a graphics system with a 1024 × 1024 Analog Outputs
resolution, a noninterlaced 60 Hz refresh rate, and a retrace The ADV7125 has three analog outputs, corresponding to the
factor of 0.8, then: red, green, and blue video signals.
Dot Rate = 1024 × 1024 × 60 / 0.8 The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
= 78.6 MHz
current outputs is capable of directly driving a 37.5 Ω load,
The required CLOCK frequency is thus 78.6 MHz. such as a doubly terminated 75 Ω coaxial cable. Figure 4a
All video data and control inputs are latched into the ADV7125 shows the required configuration for each of the three RGB
on the rising edge of CLOCK, as previously described in the outputs connected into a doubly terminated 75 Ω load. This
Digital Inputs section. It is recommended that the CLOCK arrangement develops RS-343A video output voltage levels
input to the ADV7125 be driven by a TTL buffer (e.g., 74F244). across a 75 Ω monitor.
Video Synchronization and Control A suggested method of driving RS-170 video levels into a 75 Ω
The ADV7125 has a single composite sync (SYNC) input con- monitor is shown in Figure 4b. The output current levels of the
trol. Many graphics processors and CRT controllers have the DACs remain unchanged, but the source termination resistance,
ability to generate horizontal sync (HSYNC), vertical sync ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
(VSYNC), and composite SYNC.
IOR, IOG, IOB
ZO = 75⍀
In a graphics system that does not automatically generate a DACs
composite SYNC signal, the inclusion of some additional logic (CABLE)
circuitry enables the generation of a composite SYNC signal. ZS = 75⍀ ZL = 75⍀
(SOURCE (MONITOR)
TERMINATION)
The sync current is internally connected directly to the IOG 

output, thus encoding video synchronization information onto

TERMINATION REPEATED THREE TIMES
the green video channel. If it is not required to encode sync FOR RED, GREEN, AND BLUE DACs
information onto the ADV7125, the SYNC input should be tied
to logic low. Figure 4a. Analog Output Termination for RS-343A
Reference Input IOR, IOG, IOB
ZO = 75⍀
The ADV7125 contains an on-board voltage reference. The
DACs
VREF pin is normally terminated to VAA through a 0.1 µF capaci- (CABLE)
tor. Alternatively, the part could, if required, be overdriven by ZS = 150⍀ ZL = 75⍀
(SOURCE (MONITOR)
an external 1.23 V reference (AD1580). TERMINATION)


A resistance, RSET, connected between the RSET pin and GND

TERMINATION REPEATED THREE TIMES
determines the amplitude of the output video level according to FOR RED, GREEN, AND BLUE DACs
Equations 1 and 2 for the ADV7125:
Figure 4b. Analog Output Termination for RS-170
IOG * (mA) = 11, 444.8 × VREF (V ) / RSET (Ω) (1)
More detailed information regarding load terminations for various
IOR , IOB (mA) = 7 , 989.6 × VREF (V ) / RSET (Ω)
output configurations, including RS-343A and RS-170, is avail-
(2)
able in an application note entitled, Video Formats and Required
*Applies to the ADV7125 only when SYNC is being used. If SYNC is not being Load Terminations available from Analog Devices,
encoded onto the green channel, Equation 1 will be similar to Equation 2. (www.analog.com/library/applicationNotes/video/AN205.pdf).
Using a variable value of RSET allows for accurate adjustment of Figure 3 shows the video waveforms associated with the three RGB
the analog output video levels. Use of a fixed 560 Ω RSET resistor outputs driving the doubly terminated 75 Ω load of Figure 4a. As
yields the analog output levels quoted in the specification page. well as the gray scale levels (black level to white level), the diagram
These values typically correspond to the RS-343A video wave- also shows the contributions of SYNC and BLANK for the
form values as shown in Figure 3. ADV7125. These control inputs add appropriately weighted cur-
DACs rents to the analog outputs, producing the specific output level
The ADV7125 contains three matched 8-bit DACs. The DACs requirements for video applications. Table I details how the SYNC
are designed using an advanced, high speed, segmented archi- and BLANK inputs modify the output levels.
tecture. The bit currents corresponding to each digital input are Grayscale Operation
routed to either the analog output (bit = “1”) or GND (bit = “0”) The ADV7125 can be used for standalone, grayscale (mono-
by a sophisticated decoding scheme. As all this circuitry is on chrome) or composite video applications (i.e., only one channel
one monolithic device, matching between the three DACs is used for video information). Any one of the three channels, red,
optimized. As well as matching, the use of identical current sources green, or blue, can be used to input the digital video data. The
in a monolithic design guarantees monotonicity and low glitch. two unused video data channels should be tied to logical zero.
The on-board operational amplifier stabilizes the full-scale The unused analog outputs should be terminated with the same
output current against temperature and power supply variations. load as that for the used channel. In other words, if the red

–10– REV. 0
 ADV7125
channel is used and IOR is terminated with a doubly terminated Ground Planes
75 Ω load (37.5 Ω), IOB and IOG should be terminated with The ADV7125 and associated analog circuitry should have a
37.5 Ω resistors (See Figure 5). separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
DOUBLY
plane at a single point through a ferrite bead, as illustrated in
VIDEO R0
INPUT R7
IOR TERMINATED Figure 7. This bead should be located as close as possible
75⍀ LOAD
IOG
(within three inches) to the ADV7125.
ADV7125 37.5⍀
G0 The analog ground plane should encompass all ADV7125
G7 ground pins, voltage reference circuitry, power supply bypass
IOB
37.5⍀ circuitry, the analog output traces, and any output amplifiers.
B0
B7 The regular PCB ground plane area should encompass all the
GND
digital signal traces, excluding the ground pins, leading up to
the ADV7125.
Figure 5. Input and Output Connections for Power Planes
Standalone Grayscale or Composite Video The PC board layout should have two distinct power planes,
Video Output Buffers one for analog circuitry and one for digital circuitry. The analog
The ADV7125 is specified to drive transmission line loads, as power plane should encompass the ADV7125 (VAA) and all
are most monitors rated. The analog output configurations to associated analog circuitry. This power plane should be con-
drive such loads are described in the Analog Outputs section nected to the regular PCB power plane (VCC) at a single point
and are illustrated in Figure 6. However, in some applications, through a ferrite bead, as illustrated in Figure 6. This bead
it may be required to drive long transmission line cable lengths. should be located within three inches of the ADV7125.
Cable lengths greater than 10 meters can attenuate and distort The PCB power plane should provide power to all digital logic
high frequency analog output pulses. The inclusion of output on the PC board, and the analog power plane should provide
buffers will compensate for some cable distortion. Buffers with power to all ADV7125 power pins, voltage reference circuitry,
large full power bandwidths and gains between two and four will and any output amplifiers.
be required. These buffers will also need to be able to supply
sufficient current over the complete output voltage swing. Analog The PCB power and ground planes should not overlay portions
Devices produces a range of suitable op amps for such applica- of the analog power plane. Keeping the PCB power and ground
tions. These include the AD84x series of monolithic op amps. planes from overlaying the analog power plane will contribute to
In very high frequency applications (80 MHz), the AD8061 is a reduction in plane-to-plane noise coupling.
recommended. More information on line driver buffering Supply Decoupling
circuits is given in the relevant op amp data sheets. Noise on the analog power plane can be further reduced by the
Use of buffer amplifiers also allows implementation of other video use of multiple decoupling capacitors (see Figure 7).
standards besides RS-343A and RS-170. Altering the gain com- Optimum performance is achieved by the use of 0.1 µF ceramic
ponents of the buffer circuit will result in any desired video level. capacitors. Each of the two groups of VAA should be individually
decoupled to ground. This should be done by placing the capaci-
Z2 Z1
tors as close as possible to the device with the capacitor leads as
+VS 0.1␮F short as possible, thus minimizing lead inductance.
ZO = 75⍀
It is important to note that while the ADV7125 contains circuitry
IOR, IOG, IOB 75⍀
AD848 to reject power supply noise, this rejection decreases with fre-
DACs 0.1␮F (CABLE) ZL = 75⍀ quency. If a high frequency switching power supply is used, the
(MONITOR)
designer should pay close attention to reducing power supply
ZS = 75⍀
(SOURCE
–VS
GAIN (G) = 1 +
Z1 noise. A dc power supply filter (Murata BNX002) will provide
TERMINATION) Z2 EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
Figure 6. AD848 As an Output Buffer a three-terminal voltage regulator.
PC Board Layout Considerations Digital Signal Interconnect
The ADV7125 is optimally designed for lowest noise performance, The digital signal lines to the ADV7125 should be isolated as
both radiated and conducted noise. To complement the excel- much as possible from the analog outputs and other analog
lent noise performance of the ADV7125, it is imperative that circuitry. Digital signal lines should not overlay the analog
great care be given to the PC board layout. Figure 7 shows a power plane.
recommended connection diagram for the ADV7125.
Due to the high clock rates used, long clock lines to the ADV7125
The layout should be optimized for lowest noise on the ADV7125 should be avoided to minimize noise pickup.
power and ground lines. This can be achieved by shielding the
Any active pull-up termination resistors for the digital inputs
digital inputs and providing good decoupling. The lead length
should be connected to the regular PCB power plane (VCC) and
between groups of VAA and GND pins should by minimized to
not the analog power plane.
minimize inductive ringing.

REV. 0 –11–
ADV7125
Analog Signal Interconnect For optimum performance, the analog outputs should each have
The ADV7125 should be located as close as possible to the a source termination resistance to ground of 75 Ω (doubly termi-
output connectors, thus minimizing noise pickup and reflections nated 75 Ω configuration). This termination resistance should
due to impedance mismatch. be as close as possible to the ADV7125 to minimize reflections.
The video output signals should overlay the ground plane and Additional information on PCB design is available in an application
not the analog power plane, thereby maximizing the high fre- note entitled Design and Layout of a Video Graphics System for
quency power supply rejection. Reduced EMI. This application note is available from Analog

C03097–0–10/02(0)
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).

POWER SUPPLY DECOUPLING (0.1␮F AND 0.01␮F

CAPACITOR FOR EACH VAA GROUP)

L1
13, 29, 0.1␮F 0.01␮F (FERRITE BEAD)
0.1␮F 30 VAA VCC
5V (VAA) COMP VAA
ANALOG GROUND PLANE
10␮F 33␮F
41–48 0.1␮F
VREF 5V (VAA)
R7–R0

RSET
3–10 RSET MONITOR
VIDEO 530⍀ COAXIAL CABLE (CRT)
DATA G7–G0
75⍀
INPUTS
16–23 IOR
75⍀
B7–B0
IOG
75⍀

IOB
75⍀ 75⍀ 75⍀ 75⍀
ADV7125
BNC
SYNC IOR CONNECTORS
BLANK
IOG COMPLEMENTARY
OUTPUTS
CLOCK
IOB
PSAVE
GND
1, 2, 14, 15,
25, 26, 39, 40

Figure 7. Typical Connection Diagram

OUTLINE DIMENSIONS

48-Lead Plastic Quad Flatpack [LQFP]

1.4 mm Thick
(ST-48)
Dimensions shown in millimeters

PRINTED IN U.S.A.
1.60 MAX
PIN 1
0.75 INDICATOR
9.00 BSC
0.60
0.45 48 37
1 36

SEATING
1.45 PLANE
0.20 TOP VIEW 7.00
1.40
0.09 (PINS DOWN) BSC
1.35
7ⴗ VIEW A
3.5ⴗ
0.15 0ⴗ 12 25
0.05 SEATING 0.08 MAX 13 24
PLANE COPLANARITY
0.50 0.27
VIEW A BSC 0.22
ROTATED 90ⴗ CCW 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC

–12– REV. 0
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.