Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A
Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A
Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A
Resolver-to-Digital Converters
AD2S81A/AD2S82A
FEATURES AD2S82A FUNCTIONAL BLOCK DIAGRAM
Monolithic (BiMOS ll) Tracking R/D Converter
Ratiometric Conversion DEMOD DEMOD INTEGRATOR
I/P O/P I/P
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User AD2S82A
PHASE
Velocity Output SIN I/P A1
SENSITIVE
DETECTOR
INTEGRATOR
O/P
ESD Class 2 Protection (2,000 V Min) SIGNAL SEGMENT
GND SWITCHING
COS I/P A2 R-2R A3 AC ERROR
AD2S81A ANALOG
DAC O/P
28-Lead DIP Package GND
RIPPLE
Low Cost CLK 16-BIT VCO DATA
VCO I/P
UP/DOWN COUNTER TRANSFER INHIBIT
+12V
AD2S82A –12V
LOGIC VCO O/P
44-Lead PLCC Package COMP +5V
10-, 12-, 14- and 16-Bit Resolution Set by User DATA OUTPUT DATA LATCH
DIGITAL
LOAD GND
High Max Tracking Rate 1040 RPS (10 Bits)
SC2 BUSY DIR
VCO Output (Inter LSB Output) SC1 ENABLE 16 DATA BITS BYTE
Data Complement Facility SELECT
REV. B
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AD2S81A/AD2S82A–SPECIFICATIONS (@ T = +25ⴗC, unless otherwise noted) A
AD2S81A AD2S82A
Parameter Conditions Min Typ Max Min Typ Max Units
SIGNAL INPUTS
Frequency 400 20,000 50 20,000 Hz
Voltage Level 1.8 2.0 2.2 1.8 2.0 2.2 V rms
Input Bias Current 60 150 60 150 nA
Input Impedance 1.0 1.0 MΩ
Maximum Voltage ±8 ±8 V pk
REFERENCE INPUT
Frequency 400 20,000 50 20,000 Hz
Voltage Level 1.0 8.0 1.0 8.0 V pk
Input Bias Current 60 150 60 150 nA
Input Impedance 1.0 1.0 MΩ
CONTROL DYNAMICS
Repeatability 1 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 –10 +10 Degrees
Tracking Rate 10 Bits 1040 rps
12 Bits 260 260 rps
14 Bits 65 rps
16 Bits 16.25 rps
Bandwidth1 User Selectable
ACCURACY
Angular Accuracy H ⴞ22 + 1 LSB arc min
J ⴞ30 + 1 LSB ⴞ8 + 1 LSB arc min
K ⴞ4 + 1 LSB arc min
L ⴞ2 + 1 LSB arc min
Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) J, K 4 Codes
L 1 Code
VELOCITY SIGNAL
Linearity Over Full Range ±1 ⴞ3 ±1 ⴞ3 % FSD
Reversion Error ±2 ±2 % FSD
DC Zero Offset2 6 6 mV
DC Zero Offset Tempco –22 –22 µV/°C
Gain Scaling Accuracy ⴞ10 ⴞ10 % FSD
Output Voltage 1 mA Load ±8 ±9 ± 10.5 ±8 ±9 ± 10.5 V
Dynamic Ripple Mean Value 1.5 1.5 % rms O/P
Output Load 1.0 1.0 kΩ
INPUT/OUTPUT PROTECTION
Analog Inputs Overvoltage Protection ±8 ±8 V
Analog Outputs Short Circuit O/P Protection ± 5.6 ±8 ± 10.4 ± 5.6 ±8 ± 10.4 mA
DIGITAL POSITION
Resolution 10, 12, 14 and 16
Output Format Bidirectional Natural Binary
Load 3 3 LSTTL
3
INHIBIT
Sense Logic LO to Inhibit
Time to Stable Data 600 600 ns
ENABLE3 Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State
ENABLE/Disable Time 35 110 35 110 ns
BYTE SELECT3
Sense
Logic HI MS Byte DB1–DB8,
(LS Byte DB9–DB16)4
Logic LO LS Byte DB1–DB8,
(LS Byte DB9–DB16)4
Time to Data Available 60 140 60 140 ns
SHORT CYCLE INPUTS4, 5 Internally Pulled High
(100 kΩ) to +VS
SC1 SC2
0 0 10 Bit
0 1 12 Bit
1 0 14 Bit
1 1 16 Bit
DATA LOAD4, 5
Sense Internally Pulled High (100 kΩ) 150 300 ns
to +VS; Logic LO Allows
Data to Be Loaded into the
Counters from the Data Lines
–2– REV. B
AD2S81A/AD2S82A
AD2S81A AD2S82A
Parameter Conditions Min Typ Max Min Typ Max Units
4, 5
COMPLEMENT Internally Pulled High (100 kΩ) to
+VS; Logic LO to Activate; No
Connect for Normal Operation
BUSY3
Sense Logic HI When Position O/P Changing
Width 200 600 200 600 ns
Load Use Additional Pull-Up 1 1 LSTTL
DIRECTION3
Sense Logic HI Counting Up
Logic LO Counting Down
Max Load 3 3 LSTTL
RIPPLE CLOCK3
Sense Logic HI, All 1s to All 0s
All 0s to All 1s
Width Dependent On Input Velocity 300 300
Reset Before Next Busy
Load 3 3 LSTTL
DIGITAL INPUTS
High Voltage, VIH INHIBIT, ENABLE 2.0 2.0 V
DB1–DB16, Byte Select
± VS = ± 10.8 V, VL = 5.0 V
Low Voltage, VIL INHIBIT, ENABLE 0.8 0.8 V
DB1–DB16, Byte Select
± VS = ± 13.2 V, VL = 5.0 V
DIGITAL INPUTS
High Current, IIH INHIBIT, ENABLE ⴞ100 ⴞ100 µA
DB1–DB16
± VS = ± 13.2 V, VL = 5.5 V
Low Current, IIL INHIBIT, ENABLE ⴞ100 ⴞ100 µA
DB1–DB16, Byte Select
± VS = ± 13.2 V, VL = 5.5 V
DIGITAL INPUTS
Low Voltage, VIL ENABLE = HI 1.0 1.0 V
SC1, SC2, Data Load
± VS = ± 12.0 V, VL = 5.0 V
Low Current, IIL ENABLE = HI –400 –400 µA
SC1, SC2, Data Load
± VS = ± 12.0 V, VL = 5.0 V
DIGITAL OUTPUTS
High Voltage, VOH DB1–DB16; RIPPLE CLK, DIR 2.4 2.4 V
± VS = ± 12.0 V, VL = 4.5 V
IOH = 100 µA
Low Voltage, VOL DB1–DB16, RIPPLE CLK, DIR 0.4 0.4 V
± VS = ± 12.0 V, VL = 5.5 V
IOL = 1.2 mA
THREE-STATE LEAKAGE DB1–DB16 Only
Current IL +VS = ± 12.0 V, VL = 5.5 V ± 100 ± 100 µA
VOL = 0 V
+VS = ± 12.0 V, VL = 5.5 V ± 100 ± 100 µA
VOH = 5.0 V
POWER SUPPLIES
Voltage Levels
+VS +10.8 +13.2 +10.8 +13.2 V
–VS –10.8 –13.2 –10.8 –13.2 V
+VL +5 +13.2 +5 +13.2 V
Current
+IS ± VS @ ± 12 V ⴞ12 ⴞ23 ⴞ12 ⴞ23 mA
+IS ± VS @ ± 13.2 V ⴞ19 ⴞ30 ⴞ19 ⴞ30 mA
+IL ± VL @ ± 5.0 V ⴞ0.5 ⴞ1.5 ⴞ0.5 ⴞ1.5 mA
NOTES
1
Refers to small signal bandwidth.
2
Output offset dependent on value for R6.
3
Refer to timing diagram.
4
AD2S82A only.
5
These pins are referenced to +V S (i.e., HI = +12 V, LO = 0 V).
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
REV. B –3–
AD2S81A/AD2S82A–SPECIFICATIONS (typical @ +25ⴗC unless otherwise noted)
AD2S81A AD2S82A
Parameter Conditions Min Typ Max Min Typ Max Units
RATIO MULTIPLIER
AC Error Output Scaling 10 Bit 177.6 mV/Bit
12 Bit 44.4 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit
PHASE SENSITIVE DETECTOR
Output Offset Voltage 12 12 mV
Gain
In Phase w.r.t. REF –0.882 –0.9 –0.918 –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF 0.04 0.04 V rms/V dc
Input Bias Current 60 150 60 150 nA
Input Impedance 1 1 MΩ
Input Voltage ±8 ±8 V
INTEGRATOR
Open-Loop Gain At 10 kHz 57 63 57 63 dB
Dead Zone Current (Hysteresis) 100 100 nA/LSB
Input Offset Voltage 1 5 1 5 mV
Input Bias Current 60 150 60 150 nA
Output Voltage Range ± VS = ± 10.8 V dc ±7 V
VCO ± VS = ± 12 V dc
Maximum Rate 1.0 1.1 1.0 1.1 MHz
VCO Rate Positive DIR 7.1 7.9 8.7 7.1 7.9 8.7 kHz/µA
Negative DIR 7.1 7.9 8.7 7.1 7.9 8.7 kHz/µA
VCO Power Supply Sensitivity
Increase +VS +0.5 +0.5 %/V
–VS –8.0 –8.0 %/V
Decrease +VS –8.0 –8.0 %/V
–VS +2.0 +2.0 %/V
Input Offset Voltage 1 5 1 5 mV
Input Bias Current 70 380 70 380 nA
Input Bias Current Tempco –1.22 –1.22 nA/°C
Input Voltage Range ±8 ±8 V
Linearity of Absolute Rate
Full Range <2 <2 % FSD
Over 0% to 50% of Full Range <1 <1 % FSD
Reversion Error 1.5 1.5 % FSD
Sensitivity of Reversion Error ±8 ±8 %/V of
to Symmetry of Power Supplies Asymmetry
VCO Output1, 2 ± 2.7 ± 3.0 ± 3.3 V/LSB
POWER SUPPLIES
Voltage Levels
+VS +10.8 +13.2 +10.8 +13.2 V
–VS –10.8 –13.2 –10.8 –13.2 V
+VL +5 +13.2 +5 +13.2 V
Current
+IS ± VS @ ± 12 V ⴞ12 ⴞ23 ⴞ12 ⴞ23 mA
+IS ± VS @ ± 13.2 V ⴞ19 ⴞ30 ⴞ19 ⴞ30 mA
+IL ± VL @ ± 5.0 V ⴞ0.5 ⴞ1.5 ⴞ0.5 ⴞ1.5 mA
NOTES
1
The VCO output swings between ±3 V depending on the resolver direction. ORDERING GUIDE
2
AD2S82A only.
Operating
Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice. Temperature Package
Accuracy Ranges Options*
AD2S81AJD 30 arc min 0°C to +70°C D-28
AD2S82AHP 22 arc min –40°C to +85°C P-44A
AD2S82AJP 8 arc min –40°C to +85°C P-44A
AD2S82AKP 4 arc min –40°C to +85°C P-44A
AD2S82ALP 2 arc min –40°C to +85°C P-44A
*D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package.
ESD SENSITIVITY
The AD2S81A and AD2S82A features an input protection circuit consisting of large “distributed”
diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model)
and fast, low energy pulses (Charges Device Model). WARNING!
The AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are
strongly recommended to avoid functional damage or performance degradation. For further informa- ESD SENSITIVE DEVICE
tion on ESD precautions, refer to Analog Devices ESD Prevention Manual.
–4– REV. B
AD2S81A/AD2S82A
RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS 1 (with respect to GND)
Power Supply Voltage (+VS to –VS) . . . . . . . . . ± 12 V dc ± 10% +VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc
Power Supply Voltage VL . . . . . . . . . . . . . . . . . . +5 V dc ± 10% –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10% +VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
Signal and Reference Harmonic Distortion . . . . . . . 10% (max) SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
Phase Shift Between Signal and Reference . ± 10 Degrees (max) COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
Ambient Operating Temperature Range Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc
Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
Industrial (HP, JP, KP, LP) . . . . . . . . . . . . –40°C to +85°C Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –VS
PIN FUNCTION DESCRIPTIONS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW
Mnemonic Description Operating Temperature
REFERENCE I/P Reference Signal Input Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
DEMOD I/P Demodulator Input Industrial (HP, JP, KP, LP) . . . . . . . . . . . . . –40°C to +85°C
AC ERROR O/P Ratio Multiplier Output Storage Temperature (All Grades) . . . . . . . . . –65°C to +150°C
COS I/P Cosine Input
ANALOG GND Power Ground Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
SIGNAL GND Resolver Signal Ground CAUTION
SIN I/P Sine Input 1. Absolute Maximum Ratings are those values beyond which damage to the
+VS Positive Power Supply device may occur.
DB1–DB16 Parallel Output Data 2. Correct polarity voltages must be maintained on the +V S and –V S pins.
+VL Logic Power Supply
ENABLE Logic Hi-Output Data in High Impedance AD2S81A/AD2S82A PIN CONFIGURATIONS
State Logic Lo Present Data to the Output Latches
BYTE SELECT Logic Hi-Most Significant Byte to DB1–DB8
Logic Lo-Most Significant Byte to DB1–DB8 REFERENCE I/P 1 28 DEMOD O/P
INHIBIT Logic Lo Inhibits Data Transfer to Output Latches DEMOD I/P 2 27 INTEGRATOR O/P
DIGITAL GND Digital Ground
AC ERROR O/P 3 26 INTEGRATOR I/P
SC1–SC2* Select Converter Resolution
DATA LOAD* Logic Lo DB1–DB16 Inputs COS I/P 4 25 VCO I/P
Logic Hi DB1–DB16 Outputs ANALOG GND 5 24 –VS
BUSY Converter Busy, Data Not Valid While Busy Hi SIN I/P 6 23 RIPPLE CLK
AD2S81A
DIR Logic State Defines Direction of Input Signal Rotation +VS 7
TOP VIEW 22 DIR
RIPPLE CLK Positive Pulse when Converter Output Changes from
MSB DB1 8 (Not to Scale) 21 BUSY
1s to All 0s or Vice Versa
–VS Negative Power Supply DB2 9 20 DIGITAL GND
*AD2S82A Only.
INTEGRATOR I/P
REFERENCE I/P
AC ERROR O/P
ANALOG GND
DEMOD O/P
DEMOD I/P
VCO I/P
REV. B –5–
AD2S81A/AD2S82A
CONNECTING THE CONVERTER in Figure 7 and described in the Connecting the Resolver
The power supply voltages connected to +VS and –VS pins section.
should be +12 V dc and –12 V dc and must not be reversed. The two signal ground wires from the resolver should be joined
The voltage applied to VL can be +5 V dc to +VS. at the SIGNAL GROUND pin of the resolver to minimize the
It is recommended that the decoupling capacitors are connected coupling between the sine and cosine signals. For this reason it
in parallel between the power lines +VS, –VS and ANALOG GND is also recommended that the resolver is connected using indi-
adjacent to the converter. Recommended values are 100 nF vidually screened twisted pair cables with the sine, cosine and
(ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and reference signals twisted separately.
10 µF should be connected between +VL and DIGITAL GND SIGNAL GND and ANALOG GND are connected internally.
adjacent to the converter. ANALOG GND and DIGITAL GND must be connected
When more than one converter is used on a card, then separate externally.
decoupling capacitors should be used for each converter. The external components required should be connected as
The resolver connections should be made to the SIN and shown in Figures 1a and 1b.
COS inputs, REFERENCE I/P and SIGNAL GND as shown
REFERENCE I/P
OFFSET ADJUST
C3 R9
HP FILTER +12V –12V
R3
R8
C1 R2
BANDWIDTH
C2 SELECTION
R1 R4
C5
AC ERROR DEMOD DEMOD INTEGRATOR C4
O/P I/P O/P I/P R5
RIPPLE CLK
16-BIT UP/DOWN COUNTER VCO TRACKING
+12V VCO I/P RATE
DATA TRANSFER
–12V LOGIC SELECTION
OUTPUT DATA LATCH R7
COMP
C6
DATA SC1 SC2 +5V DIGITAL BUSY VCO DIR INHIBIT
LOAD 16 DATA BITS GND O/P
ENABLE BYTE
SELECT
REFERENCE I/P
OFFSET ADJUST
C3 R9
HP FILTER +12V –12V
R3
R8
C1 R2
BANDWIDTH
C2 SELECTION
R1 R4
C5
AC ERROR DEMOD DEMOD INTEGRATOR C4
O/P I/P O/P I/P R5
PHASE-SENSITIVE INTEGRATOR
SIN I/P A1 DETECTOR O/P
SEGMENT VELOCITY
SIGNAL GND R-2R DAC A3 SIGNAL
SWITCHING
COS I/P A2
AD2S81A R6
–6– REV. B
AD2S81A/AD2S82A
CONVERTER RESOLUTION (AD2S82A ONLY) HARMONIC DISTORTION
Two major areas of the AD2S82A specification can be selected The amount of harmonic distortion allowable on the signal and
by the user to optimize the total system performance. The reso- reference lines is 10%.
lution of the digital output is set by the logic state of the inputs Square waveforms can be used but the input levels should be
SC1 and SC2 to be 10, 12, 14 or 16 bits and the dynamic char- adjusted so that the average value is 1.9 V rms. (For example, a
acteristics of bandwidth and tracking rate are selected by the square wave should be 1.9 V peak). Triangular and sawtooth
choice of external components. waveforms should have a amplitude of 2 V rms.
The choice of the resolution will affect the values of R4 and R6 Note: The figure specified of 10% harmonic distortion is for
which scale the inputs to the integrator and the VCO, respec- calibration convenience only.
tively (see the Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into POSITION OUTPUT
the circuit. The resolver shaft position is represented at the converter out-
Note: When changing resolution under dynamic conditions, do put by a natural binary parallel digital word.
it when the BUSY is low, i.e., when Data is not changing. As the digital position output of the converter passes through
the major carries, i.e., all “1s” to all “0s” or the converse, a
CONVERTER OPERATION RIPPLE CLK logic output is initiated indicating that a revolu-
When connected in a circuit such as shown in Figure 1, the tion or a pitch of the input has been completed.
AD2S81A/AD2S82A operates as a tracking resolver-to-digital
converter and forms a type 2 closed loop system. The output The direction of input rotation is indicated by the DIRECTION
will automatically follow the input for speeds up to the selected (DIR) logic output. This direction data is always valid in ad-
maximum tracking rate. No convert command is necessary as vance of a RIPPLE CLK pulse and, as it is internally latched,
the conversion is automatically initiated by each LSB increment, only changing state (1 LSB min change) with a corresponding
or decrement, of the input. Each LSB change of the converter change in direction.
initiates a BUSY pulse. Both the RIPPLE CLK pulse and the DIR data are unaffected
The AD2S81A/AD2S82A is remarkably tolerant of input ampli- by the application of the INHIBIT.
tude and frequency variation because the conversion depends The static positional accuracy quoted is the worst case error that
only on the ratio of the input signals. Consequently there is no can occur over the full operating temperature excluding the
need for accurate, stable oscillator to produce the reference effects of offset signals at the INTEGRATOR I/P (which can be
signal. The inclusion of the phase sensitive detector in the con- trimmed out–see Figures 1a and 1b), and with the following
version loop ensures a high immunity to signals that are not conditions: input signal amplitudes are within 10% of the
coherent or are in quadrature with the reference signal. nominal; phase shift between signal and reference is less than
10 degrees.
SIGNAL CONDITIONING
These operating conditions are selected primarily to establish a
The amplitude of the SINE and COSINE signal inputs should
repeatable acceptance test procedure which can be traced to
be maintained within 10% of the nominal values if full perfor-
national standards. In practice, the AD2S81A/AD2S82A can be
mance is required from the velocity signal.
used well outside these operating conditions providing the above
The digital position output is relatively insensitive to amplitude points are observed.
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc- VELOCITY SIGNAL
ing levels will result in a steady decline in accuracy. With the The tracking converter technique generates an internal signal at
signal levels at 50% of the correct value, the angular error will the output of the integrator (the INTEGRATOR O/P pin) that
increase to an amount equivalent to 1.3 LSB. At this level the is proportional to the rate of change of the input angle. This is a
repeatability will also degrade to 2 LSB and the dynamic re- dc analog output referred to as the VELOCITY signal.
sponse will also change, since the dynamic characteristics are
In many applications it is possible to use the velocity signal of
proportional to the signal level.
the AD2S81A/AD2S82A to replace a conventional
The AD2S81A/AD2S82A will not be damaged if the signal tachogenerator.
inputs are applied to the converter without the power supplies
and/or the reference. DC ERROR SIGNAL
The signal at the output of the phase-sensitive detector (DEMOD
REFERENCE INPUT O/P) is the signal to be nulled by the tracking loop and is, there-
The amplitude of the reference signal applied to the converter’s fore, proportional to the error between the input angle and the
input is not critical, but care should be taken to ensure it is kept output digital angle. This is the dc error of the converter; and as
within the recommended operating limits. the converter is a type 2 servo loop, it will increase if the output
The AD2S81A/AD2S82A will not be damaged if the reference fails to track the input for any reason. It is an indication that the
is supplied to the converter without the power supplies and/or input has exceeded the maximum tracking rate of the converter
the signal inputs. or, due to some internal malfunction, the converter is unable to
reach a null. By connecting two external comparators, this volt-
age can be used as a “built-in test.”
REV. B –7–
AD2S81A/AD2S82A
COMPONENT SELECTION 4. Maximum Tracking Rate (R6)
The following instructions describe how to select the external The VCO input resistor R6 sets the maximum tracking rate
components for the converter in order to achieve the required of the converter, and hence the velocity scaling as at the max
bandwidth and tracking rate. In all cases the nearest “preferred tracking rate, the velocity output will be 8 V.
value’’ component should be used and a 5% tolerance will not Decide on your maximum tracking rate, “T,” in revolutions
degrade the overall performance of the converter. Care should per second. Note that “T” must not exceed the maximum
be taken that the resistors and capacitors will function over the tracking rate or 1/16 of the reference frequency.
required operating temperature range. The components should
10
be connected as shown in Figure 1. 6. 32 × 10
R6 = Ω
PC compatible software is available to help users select the optimum T ×n
component values for the AD2S81A and AD2S82A, and display the
where n = bits per revolution
transfer gain, phase and small step response.
= 1,024 for 10 bits resolution
For more detailed information and explanation, see the Circuit = 4,096 for 12 bits
Functions and Dynamic Performance section. = 16,384 for 14 bits
1. HF Filter (R1, R2, C1, C2) = 65,536 for 16 bits
The function of the HF filter is to remove any dc offset and 5. Closed-Loop Bandwidth Selection (C4, C5, R5)
to reduce the amount of noise present on the signal inputs a. Choose the closed-loop bandwidth (fBW) required
to the AD2S81A/AD2S82A, reaching the Phase Sensitive ensuring that the ratio of reference frequency to band-
Detector and affecting the outputs. R1 and C2 may be omit- width does exceed the following guidelines:
ted—in which case R2 = R3 and C1 = C3, calculated below—
Resolution Ratio of Reference Frequency/Bandwidth
but their use is particularly recommended if noise from
10 2.5 : 1
switch mode power supplies and brushless motor drive is
12 4 :1
present.
14 6 :1
Values should be chosen so that 16 7.5 : 1
–8– REV. B
AD2S81A/AD2S82A
DATA TRANSFER If the AD2S81A/AD2S82A is being used in a pitch and revolu-
To transfer data the INHIBIT input should be used. The data tion counting application, the ripple and busy will need to be
will be valid 600 ns after the application of a logic “LO” to the gated to prevent false decrement or increment (see Figure 2).
INHIBIT. This is regardless of the time when the INHIBIT is RIPPLE CLK is unaffected by INHIBIT.
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred +5V
by the analog equivalent of one LSB and the internal counter is NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS “LO.”
R5 C5
AC ERROR
C4
CLOCK
R6
DIRECTION VCO VELOCITY
DIGITAL
f
–10– REV. B
AD2S81A/AD2S82A
Ratio Multiplier Phase Sensitive Demodulator
The ratio multiplier is the input section of the AD2S81A/ The phase sensitive demodulator is effectively ideal and devel-
AD2S82A and compares the signal from the resolver input ops a mean dc output at the DEMODULATOR O/P pin of
angle, θ, to the digital angle, φ, held in the counter. Any differ-
ence between these two angles results in an analog voltage at ±2 2
the AC ERROR OUTPUT. This circuit function has histori- π × ( DEMODULATOR I / P rms voltage)
cally been called a “Control Transformer” as it was originally for sinusoidal signals in phase or antiphase with the reference
performed by an electromechanical device known by that name. (for a square wave the DEMODULATOR O/P voltage will
The AC ERROR signal is given by equal the DEMODULATOR I/P). This provides a signal at the
DEMODULATOR O/P which is a dc level proportional to the
A1 sin (θ – φ) sin ωt
positional error of the converter.
where ω = 2 π fREF DC Error Scaling = 160 mV/bit (10-bits resolution)
fREF = reference frequency = 40 mV/bit (12-bits resolution)
A1, the gain of the ratio multiplier stage is 14.5. = 10 mV/bit (14-bits resolution)
So for 2 V rms inputs signals = 2.5 mV/bit (16-bits resolution)
AC ERROR output in volts/(bit of error) When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
360
= 2 × sin n × A1 Integrator
The integrator components (R4, C4, R5, C5) are external to
the AD2S81A/AD2S82A to allow the user to determine the
Where n = bits per rev
optimum dynamic characteristics for any given application. The
= 1,024 for 10-bits resolution
Component Selection section explains how to select compo-
= 4,096 for 12 bits
nents for a chosen bandwidth.
= 16,384 for 14 bits
= 65,536 for 16 bits Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle)
Giving an AC ERROR O/P
and can be scaled by selection of R6, the VCO input resistor.
= 178 mV/bit @ 10-bits resolution
This is explained in the Voltage Controlled Oscillator (VCO)
= 44.5 mV/bit @ 12 bits
section below.
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits To prevent the converter from “flickering” (i.e., continually
toggling by ±1 bit when the quantized digital angle, φ, is not an
The ratio multiplier will work in exactly the same way whether
exact representation of the input angle, θ), feedback is internally
the AD2S81A/AD2S82A is connected as a tracking converter or
applied from the VCO to the integrator input to ensure that the
as a control transformer, where data is preset into the counters
VCO will only update the counter when the error is greater than
using the DATA LOAD pin.
or equal to 1 LSB. In order to ensure that this feedback “hyster-
HF Filter esis” is set to 1 LSB the input current to the integrator must be
The AC ERROR OUTPUT may be fed to the PSD via a simple scaled to be 100 nA/bit. Therefore,
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S81A/AD2S82A DC Error Scaling (mV /bit )
R4 =
is a wideband demodulator and is capable of aliasing HF noise 100 (nA /bit )
down to within the loop bandwidth. This is most likely to hap-
pen where the resolver is situated in particularly noisy environ- Any offset at the input of the integrator will affect the accuracy
ments, and the user is advised to fit a simple HF filter R1, C2 of the conversion as it will be treated as an error signal and
prior to the phase sensitive demodulator. offset the digital output. One LSB of extra error will be
The attenuation and frequency response of a filter will affect the added for each 100 nA of input bias current. The method of
loop gain and must be taken into account in deriving the loop adjusting out this offset is given in the Component Selection
transfer function. The suggested filter (R1, C1, R2, C2) is shown section.
in Figure 1 and gives an attenuation at the reference frequency
(fREF) of 3 times at the input to the phase sensitive demodulator. Voltage Controlled Oscillator (VCO)
The VCO is essentially a simple integrator feeding a pair of dc
Values of components used in the filter must be chosen to en- level comparators. Whenever the integrator output reaches one
sure that the phase shift at fREF is within the allowable signal to of the comparator threshold voltages, a fixed charge is injected
reference phase shift of the converter. into the integrator input to balance the input current. At the
same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
REV. B –11–
AD2S81A/AD2S82A
During the reset period the input continues to be integrated, the Figure 5 illustrates how the VCO output compensates for in-
reset period is constant at 400 ns. stances where, due to hysteresis, there is no change in the digital
count output for 1 LSB change in input angle. The sum of the
The VCO rate is fixed for a given input current by the VCO
digital count output and VCO output equals the actual input
scaling factor:
angle.
= 7.9 kHz / µA
Transfer Function
The tracking rate in rps per µA of VCO input current can be By selecting components using the method outlined in the
found by dividing the VCO scaling factor by the number of LSB Component Selection section, the converter will have a critically
changes per rev (i.e., 4096 for 12-bit resolution). damped time response and maximum phase margin. The
The input resistor R6 determines the scaling between the con- Closed-Loop Transfer Function is given by:
verter velocity signal voltage at the INTEGRATOR O/P pin and θOUT 14 (1+ sN )
the VCO input current. Thus to achieve a 5 V output at 100 rps =
(6000 rpm) and 12-bit resolution the VCO input current must θ IN (sN + 2.4)(sN 2 + 3.4 sN + 5.8)
be: where SN, the normalized frequency variable, is:
(100 × 4096) / (7900) = 51.8 µA
2 s
Thus, R6 would be set to: 5/(51.8 × 10-–6) = 96 kΩ SN =
π f BW
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by and fBW is the closed loop 3 dB bandwidth (selected by the
choice of external components).
Velocity Offset Voltage = R6 × (VCO bias current )
The acceleration constant, KA, is given approximately by
The temperature coefficient of this offset is given by
2 −2
Velocity Offset Tempco = R6 × (VCO bias current tempco) K A = 6 × ( f BW ) sec
where the VCO bias current tempco is typically –1.22 nA/°C. The normalized gain and phase diagrams are given in Figures
6 and 7.
The maximum recommended rate for the VCO is 1.1 MHz
which sets the maximum possible tracking rate.
12
Since the minimum voltage swing available at the integrator
output is ± 8 V, this implies that the minimum value for R6 is 9
57 kΩ. As 6
6
1.1 × 10 3
Max Current = = 139 µA
GAIN PLOT
3
7.9 × 10 0
8 –3
Min Value R6 = = 57 kΩ
139 ×10 −6 –6
VCO OUTPUT –9
In order to overcome the “freeplay” inherent in a servo system
using digitized position feedback, an analog output voltage is –12
0.02 0.04 0.1 0.2 0.4 0 2
available representing the resolver shaft position within the least FREQUENCY – fBW
significant bit of digital angle output.
Figure 6. AD2S81A/AD2S82A Gain Plot
The converter updates the output if the error is an LSB or
greater and the VCO output gives the positional error smaller 180
than 1 LSB.
135
90
INPUT
ANGLE 45
PHASE PLOT
DIGITAL COUNT OUTPUT
+LSB
–45
0
–LSB –90
–135
+3V
VCO –180
OUTPUT 0.02 0.04 0.1 0.2 0.4 0 2
–3V FREQUENCY – fBW
–12– REV. B
AD2S81A/AD2S82A
The small signal step response is shown in Figure 8. The time
Input Acceleration [LSB/sec2 ]
from the step to the first peak is t1 and the t2 is the time from Error in LSBs =
the step until the converter is settled to 1 LSB. The times t1 and K A[sec –2 ]
t2 are given approximately by 100 [rev/sec2 ] × 212
= = 0.15 LSBs or 47.5 seconds of arc
2.7 × 106
1
t1 =
f BW To determine the value of KA based on the passive components
used to define the dynamics of the converter, the following
5 R should be used:
t2 = ×
f BW 12 11
4.04 × 10
where R = resolution, i.e., 10, 12, 14 or 16. KA = n
2 ⋅ R6 ⋅ R4 ⋅ (C4 + C5)
OUTPUT t2
POSITION Where n = resolution of the converter
R4, R6 in ohms
C5, C4 in farads
SOURCES OF ERRORS
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. This error will typically be 1 arc
t1 TIME minute over the operating temperature range.
A description of how to adjust from zero offset is given in the
Figure 8. AD2S81A/AD2S82A Small Step Response
Component Selection section and the circuit required is shown
The large signal step response (for steps greater than 5 degrees) in Figures 1a and 1b.
applies when the error voltage exceeds the linear range of the
Differential Phase Shift
converter.
Phase shift between the sine and cosine signals from the resolver
Typically the converter will take three times longer to reach the is known as differential phase shift and can cause static error.
first peak for a 179 degrees step. Some differential phase shift will be present on all resolvers as a
In response to a velocity step, the velocity output will exhibit result of coupling. A small resolver residual voltage (quadrature
the same time response characteristics as outlined above for the voltage) indicates a small differential phase shift. Additional
position output. phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, differ-
ACCELERATION ERROR ent cable lengths or different loads could cause differential
A tracking converter employing a type 2 servo loop does not phase shift.
suffer any velocity lag, however, there is an additional error due The additional error caused by differential phase shift on the
to acceleration. This additional error can be defined using the input signals approximates to
acceleration constant KA of the converter.
Error = 0.53 a × b arc minutes
Input Acceleration where a = differential phase shift (degrees).
KA = b = signal to reference phase shift (degrees).
Error in Output Angle
This error can be minimized by choosing a resolver with a small
The numerator and denominator must have consistent angular residual voltage, ensuring that the sine and cosine signals are
units. For example, if KA is in sec–2, then the input acceleration handled identically and removing the reference phase shift (see
may be specified in degrees/sec2 and the error output in degrees. Connecting the Resolver section). By taking these precautions
Angular measurement may also be specified using radians, min- the extra error can be made insignificant.
utes of arc, LSBs, etc.
Under static operating conditions phase shift between the refer-
KA does not define maximum input acceleration, only the error due ence and the signal lines alone will not theoretically affect the
to it’s acceleration. The maximum acceleration allowable before converter’s static accuracy.
the converter loses track is dependent on the angular accuracy
However, most resolvers exhibit a phase shift between the signal
requirements of the system.
and the reference. This phase shift will give rise under dynamic
Angular Accuracy × KA = degrees/sec2 conditions to an additional error defined by:
KA can be used to predict the output position error for a given
input acceleration. For example for an acceleration of 100 revs/ Shaft Speed (rps) × Phase Shift (Degrees )
sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution.
Reference Frequency
REV. B –13–
AD2S81A/AD2S82A
For example, for a phase shift of 20 degrees, a shaft rotation of Following the preceding precautions will allow the user to use
22 rps and a reference frequency of 5 kHz, the converter will the velocity signal in very noisy environments for example PWM
exhibit an additional error of: motor drive applications. Resolver/converter error curves may
exhibit apparent acceleration/deceleration at a constant velocity.
22 × 20 This results in ripple on the velocity signal of frequency twice
0.088 degrees
5000 the input rotation.
This effect can be eliminated by putting a phase shift in the
CONNECTING THE RESOLVER
reference to the converter equivalent to the phase shift in the
resolver (see Connecting the Resolver section). The recommended connection circuit is shown in Figure 9.
C3
VELOCITY ERRORS 1 REF I/P
The signal at the INTEGRATOR O/P pin relative to the ANA- R3
LOG GND pin is an analog voltage proportional to the rate of 2 AD2S82A
TWISTED PAIR
change of the input angle. This signal can be used to stabilize SCREENED 3 DIGITAL 31
CABLE GND
servo loops or in the place of a velocity transducer. Although the
4 COS I/P
conversion loop of the AD2S81A/AD2S82A includes a digital
section, there is an additional analog feedback loop around the 5 ANALOG
GND
velocity signal. This ensures against flicker in the digital posi- S2 S4 6 SIGNAL
GND
tional output in both dynamic and static states. R1 S3
7 SIN I/P
A better quality velocity signal will be achieved if the following R2 S1
points are considered:
RESOLVER
1. Protection.
POWER RETURN
The velocity signal should be buffered before use.
2. Reversion error* Figure 9. Connecting the AD2S82A to a Resolver
The reversion error can be nulled by varying one supply rail In cases where the reference phase relative to the input signals
relative to the other. from the resolver requires adjustment, this can be easily
3. Ripple and Noise. achieved by varying the value of the resistor R2 of the HF filter
Noise on the input signals to the converter is the major cause of (see Figures 1a and 1b).
noise on the velocity signal. This can be reduced to a minimum Assuming that R1 = R2 = R and C1 = C2 = C
if the following precautions are taken:
1
The resolver is connected to the converter using separate and Reference Frequency = 2 π RC
twisted pair cable for the sine, cosine and reference signals.
Care is taken to reduce the external noise wherever possible. by altering the value of R2, the phase of the reference relative to
An HF filter is fitted before the Phase-Sensitive Demodulator the input signals will change in an approximately linear manner
(as described in the section HF FILTER). for phase shifts of up to 10 degrees.
A resolver is chosen that has low residual voltage, i.e., a small Increasing R2 by 10% introduces a phase lag of 2 degrees. De-
signal in quadrature with the reference. creasing R2 by 10% introduces a phase lead of 2 degrees.
Components are selected to operate the AD2S81A/AD2S82A 1
with the lowest acceptable bandwidth. PHASE LEAD = ARC TAN
2 p fRC
PHASE LAG = ARC TAN 2 p fRC
C R
Feedthrough of the reference frequency should be removed
by a filter on the velocity signal. R C
*
Reversion error, or side-to-side nonlinearity, is a result of differences in the up and
down rates of the VCO.
–14– REV. B
AD2S81A/AD2S82A
1MV
6 5 4 3 2 1 44 43 42 41 40
SIN HIGH 7 39 –12V
PIN 1
+12V 8 IDENTIFIER 38 RIPPLE CLK
9 37 DIRECTION
MSB 10 36 BUSY
11 AD2S82A 35 DATA LOAD
12 TOP VIEW 34 COMPLEMENT
(Not to scale)
13 33 SC2
DATA
OUTPUT 14 32
0V
15 31
16 30 INHIBIT
17 29
18 19 20 21 22 23 24 25 26 27 28
225
OTHER PRODUCTS
180
The AD2S80A is a monolithic resolver-to-digital converter
135 offering 10–16 bits of resolution and user selectable dynamics.
The AD2S80A is also available in 40-lead ceramic DIP, 44-lead
90 LCC and is qualified to MIL-STD 883B Rev C.
45 The AD2S46 is a highly integrated hybrid resolver/synchro to
digital converter packaged in a 28-lead ceramic DIP. The part
0
0 4 8 12 16 20 24 offers the user 1.3 arc minutes of accuracy over the full military
TIME – ms temperature range.
Figure 12. Large Step Response Curves for Typical Circuit The AD2S34 is a dual channel 14-bit hybrid resolver-to-digital
Shown in Figure 11 converter packaged in a 1 in2 32-lead flatpack.
The 1740/41/42 are hybrid resolver/synchro to digital converters
which incorporate pico-transformer isolated input signal
conditioning.
REV. B –15–
AD2S81A/AD2S82A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1453b–2.5–11/98
0.005 (0.13) MIN 0.100 (2.54) MAX
28 15
0.610 (15.49)
0.500 (12.70)
1 14
0.021 (0.53)
TOP VIEW
(PINS DOWN) 0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
17 29
18 28
0.020 0.040 (1.01)
(0.50) 0.656 (16.66) 0.025 (0.64)
R SQ
0.650 (16.51)
0.110 (2.79)
0.695 (17.65)
SQ 0.085 (2.16)
0.685 (17.40)
PRINTED IN U.S.A.
–16– REV. B