ANALOG CIRCUITS 18EC42 (Module - 5)
ANALOG CIRCUITS 18EC42 (Module - 5)
ANALOG CIRCUITS 18EC42 (Module - 5)
Module – 5
OP-AMP CIRCUITS
Fig: Equivalent circuit when b3 is high and b0, b1, and b2 are low
In the figure shown above, the negative input is at virtual ground; therefore
the current through RTH is 0A.
The Current through 2R connected to +5V is 𝐼 = 5𝑉 20𝑘 Ω = 0.25𝑚𝐴
The same current I flows through RF and in turn produces the output voltage
of
𝑉𝑂 = − 20𝑘Ω 0.25𝑚𝐴 = −5𝑉
Using the same analysis, the output voltage when all the switches are
connected to +5V can be calculated as
𝑏3 𝑏2 𝑏1 𝑏0
𝑉𝑂 = −𝑅𝐹 + + +
2𝑅 4𝑅 8𝑅 16𝑅
Where each of the inputs b3, b2, b1, and b0 may be either high (+5V) or low
(0V).
The below graph shows the analog outputs versus possible combinations of
inputs.
According to the comparator output, the SAR will either keep or reset the Q6
bit.
This process goes on until all the bits are tried.
After Q0 is tried, the SAR makes the conversion complete (CC) signal
HIGH to show that the parallel output lines contain valid data.
The CC signal, in turn, enables the latch, and digital data appear at the output
of the latch.
As the SAR determines each bit, digital data is also available serially.
As shown in the figure above, the CC signal is connected to the start
conversion input to convert the cycle continuously.
ACTIVE FILTERS:
2. Active or Passive:
Depending on the type of elements used in their construction, a filter may be
classified as passive or active elements used in passive filters are Resistors,
capacitors, inductors. Elements used in active filters are transistor or op-amp.
where fH > fL and two, stopbands : 0<f< fL and f > fH between the bandpass filter
(equal to fH - fL).
Fig:First order LPF Butterworth filter circuit Fig: LPF Frequecy response
𝑉𝑂 𝑅𝑓 1
= 1+
𝑉𝑖𝑛 𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
𝑉𝑂 1 Where
= 𝐴𝑓 𝑉𝑂
𝑉𝑖𝑛 1 + 𝑗 𝑓 𝑓𝐻 𝑉 𝑖𝑛
= gain of the filter as a function of frequency
𝑅
𝐴𝑓 = 1 + 𝑅𝑓 = passband of the filter
1
1
𝑓𝐻 = = high cutoff frequency of the filter
2𝜋𝑅𝐶
The operation of the low-pass filter can be verified from the gain magnitude
equation:
1. At very low frequencies, that is, 𝑓 < 𝑓𝐻 ,
𝑉𝑂
≅ 𝐴𝑓
𝑉𝑖𝑛
2. At 𝑓 = 𝑓𝐻 ,
𝑉𝑂 𝐴𝑓
= = 0.707𝐴𝑓
𝑉𝑖𝑛 2
3. At 𝑓 > 𝑓𝐻 ,
𝑉𝑂
< 𝐴𝑓
𝑉𝑖𝑛
Thus the low-pass filter has a constant gain 𝐴𝑓 from 0Hz to the high cutoff
frequency fH.
At fH the gain is 0.707Af, and after fH it decreases at a constant rate with an
increase in frequency as shown in the frequency response.
Fig: Second order LPF Butterworth filter circuit Fig: LPF Frequecy response
The voltage gain magnitude euation for a second order low-pass Butterworth
filter is given by
𝑉𝑂 𝐴𝑓 Where 𝐴𝑓 = 1 +
𝑅𝑓
=passband gain of the filter
= 𝑅1
Filter Design:
1. Choose a value for a high cut off freq (fH ).
2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C
then choose a value of c<=1μf.
1
3. Calculate the value of R using eqn 𝑅 =
2𝜋𝑓𝐻 𝐶
4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3)
values, the pass band volt gain AF = (1 + RF / R1) of the second order LPF
has to be equal to 1.586. That is RF = 0.586 R1. Hence choose a value of
R1≤100kΩ and Calculate the value of RF.
Fig:First order HPF Butterworth filter circuit Fig: HPF Frequecy response
𝑅𝑓
𝑉𝑂 = 1 + 𝑉
𝑅1 1
𝑅𝑓 𝑗2𝜋𝑓𝑅𝐶𝑣𝑖𝑛
∴ 𝑉𝑂 = 1 +
𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
𝑉𝑂 𝑅𝑓 𝑗2𝜋𝑓𝑅𝐶
= 1+
𝑉𝑖𝑛 𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
Where
𝑉𝑂 𝑗 𝑓 𝑓𝐿 𝑉𝑂
= gain of the filter as a function of frequency
= 𝐴𝑓 𝑉 𝑖𝑛
𝑉𝑖𝑛 1 + 𝑗 𝑓 𝑓𝐿 𝑅
𝐴𝑓 = 1 + 𝑅𝑓 = passband of the filter
1
1
𝑓𝐿 = 2𝜋𝑅𝐶
= low cutoff frequency of the filter
The operation of the high-pass filter can be verified from the gain magnitude
equation:
4. At very low frequencies, that is, 𝑓 < 𝑓𝐿 ,
𝑉𝑂
< 𝐴𝑓
𝑉𝑖𝑛
5. At 𝑓 = 𝑓𝐿 ,
𝑉𝑂 𝐴𝑓
= = 0.707𝐴𝑓
𝑉𝑖𝑛 2
6. At 𝑓 > 𝑓𝐿 ,
𝑉𝑂
≅ 𝐴𝑓
𝑉𝑖𝑛
Fig: Second order HPF Butterworth filter circuit Fig: HPF Frequecy response
The voltage gain magnitude euation for a second order low-pass Butterworth
filter is given by
𝑉𝑂 𝐴𝑓 Where 𝐴𝑓 = 1 +
𝑅𝑓
=passband gain of the filter
= 𝑅1
BAND-PASS FILTERS:
The narrow band-pass filter using multiple feedback is shown in the figure.
The unique features of this circuit are:
o It has two feedback paths, and this is the reason that it is called a
multiple-feedback filter.
o The op-amp is used in the inverting mode.
The frequency response is as shown in the figure.
Generally, the narrow band-pass filter is designed for specific values of
centre frequency fC and Q or fC and bandwidth.
The circuit components are determined from the following relationships,
Let 𝐶1 = 𝐶2 = 𝐶
𝑄
𝑅1 =
2𝜋𝑓𝐶 𝐶𝐴𝑓
𝑄
𝑅2 =
2𝜋𝑓𝐶 𝐶 2𝑄2 − 𝐴𝑓
𝑄
𝑅3 =
𝜋𝑓𝐶 𝐶
Where Af is the gain at fC, given by
𝑅3
𝐴𝑓 =
2𝑅1
The gain Af, however, must satisfy the condition
𝐴𝑓 < 2𝑄2
The advantageof the abovenarrow band-pass filter circuit is that its centre
frequency fC can be changed to new centre frequency 𝑓𝐶′ without changing the
gain or bandwidth. This can be accomplished by changing R2 to 𝑅2′ so that
2
′
𝑓𝐶
𝑅2 = 𝑅2 ′
𝑓𝐶
PIN DESCRIPTION:
Pin 1: Ground:
o All voltages are measured with respect to this terminal.
Pin 2: Trigger:
o The o/p of the timer depends on the amplitude of the external trigger pulse applied to
this pin.
Pin 3: Output:
o There are 2 ways a load can be connected to the o/p terminal either between pin3 &
ground or between pin 3 & supply voltage
o (Between Pin 3 & Ground- ON load )
o (Between Pin 3 & + Vcc - OFF load )
o When the input is low: The load current flows through the load connected between Pin
3 & +Vcc in to the output terminal & is called the sink current.
o When the output is high: The current through the load connected between Pin 3 &
+Vcc (i.e. ON load) is zero. However the output terminal supplies current to the
normally OFF load. This current is called the source current.
Pin 4: Reset:
o The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When
the reset function is not in use, the reset terminal should be connected to +Vcc to avoid
any false triggering.
Pin 5: Control voltage:
o An external voltage applied to this terminal changes the threshold as well as trigger
voltage. In other words by connecting a potentiometer between this pin & GND, the
pulse width of the output waveform can be varied. When not used, the control pin
should be bypassed to ground with 0.01µF capacitor to prevent any noise problems.
Pin 6: Threshold:
o This is the non inverting input terminal of upper comparator which monitors the
voltage across the external capacitor.
Pin 7: Discharge:
o This pin is connected internally to the collector of transistor Q1.
o When the output is high Q1 is OFF.
o When the output is low Q is (saturated) ON.
Pin 8: +Vcc:
o The supply voltage of +5V to +18V is applied to this pin with respect to ground.
In the block diagram of 555 timer, three 5k internal resistors act as voltage
divider providing bias voltage of 2/3 Vcc to the upper comparator & 1/3 Vcc
to the lower comparator.
It is possible to vary time electronically by applying a modulation voltage to
the control voltage input terminal 5.
In the Stable state:
o The output of the control FF is high. This means that the output is low
because of power amplifier which is basically an inverter. Q = 1; Output =
0
At the Negative going trigger pulse:
o The trigger passes through (Vcc/3) the output of the lower comparator
goes high & sets the FF. Q = 1; Q = 0
At the Positive going trigger pulse:
o It passes through 2/3Vcc, the output of the upper comparator goes high
and resets the FF. Q = 0; Q = 1
The reset input (pin 4) provides a mechanism to reset the FF in a manner
which overrides the effect of any instruction coming to FF from lower
comparator.
Monostable Operation:
Initially when the output is low, that is, the circuit is in a stable state,
transistor Q1 is on and the capacitor C is shorted out to ground.
When negative trigger pulse is applied to pin 2, the transistor Q1 is turned
off, which releases the short circuit across the external capacitor C and
drives the output high.
The capacitor C now starts charging up towards VCC through RA.
When the voltage across the capacitor equals 2/3VCC, comparator 1’s output
switches from low to high, which inturn drives the output to its low state via
the output of the flip-flop.
At the same time, the output of the flip-flop turns transistor Q1 on, and hence
capacitor C rapidly discharges through the transistor.
The output of the monostable remains low until trigger pulse is again
applied.
The the cycle repeats.
The figure shows the trigger input, output voltage, and the capacitor voltage
waveforms.
𝑇 = 1.1𝑅𝐴 𝐶
𝑡𝑐 = 0.69 𝑅𝐴 + 𝑅𝐵 𝐶
Similarly, the time during which the capacitor discharges from 2/3 VCC to
1/3 VCC is equal to the time the output is low and is given by
𝑡𝑑 = 0.69 𝑅𝐵 𝐶
Thus the total period of the output waveform is
𝑇 = 𝑡𝑐 + 𝑡𝑑
𝑇 = 0.69 𝑅𝐴 + 2𝑅𝐵 𝐶
Thus the frequency of oscillation is s
1 1.45
𝑓𝑜 = =
𝑇 𝑅𝐴 + 2𝑅𝐵 𝐶
The duty cycle is the ratio of the time tC during which the output is high to
the total time period T.
It is generally expressed as percentage is expressed as
𝑡𝑐
% 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
𝑇
0.69 𝑅𝐴 + 𝑅𝐵 𝐶
% 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
0.69 𝑅𝐴 + 2𝑅𝐵 𝐶
𝑅𝐴 + 𝑅𝐵
∴ % 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
𝑅𝐴 + 2𝑅𝐵