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    Ct3-Asic Set B

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    skarthikpriya
    This document contains questions that appear to be from an exam on ASIC design. It includes multiple choice and long answer questions covering topics like encoding techniques, memory synthesis approaches, the ASIC design flow steps like synthesis and optimization, simulator types, and Verilog code templates. The questions ask about mux and FSM designs, Altera interconnect features, SRAM cells, and RAM templates in Verilog.

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    Ct3-Asic Set B

    Uploaded by

    skarthikpriya
    27 views1 page
    This document contains questions that appear to be from an exam on ASIC design. It includes multiple choice and long answer questions covering topics like encoding techniques, memory synthesis approaches, the ASIC design flow steps like synthesis and optimization, simulator types, and Verilog code templates. The questions ask about mux and FSM designs, Altera interconnect features, SRAM cells, and RAM templates in Verilog.

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    CT3-ASIC SET B

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    This document contains questions that appear to be from an exam on ASIC design. It includes multiple choice and long answer questions covering topics like encoding techniques, memory synthesis approaches, the ASIC design flow steps like synthesis and optimization, simulator types, and Verilog code templates. The questions ask about mux and FSM designs, Altera interconnect features, SRAM cells, and RAM templates in Verilog.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    27 views1 page

    Ct3-Asic Set B

    Uploaded by

    skarthikpriya
    This document contains questions that appear to be from an exam on ASIC design. It includes multiple choice and long answer questions covering topics like encoding techniques, memory synthesis approaches, the ASIC design flow steps like synthesis and optimization, simulator types, and Verilog code templates. The questions ask about mux and FSM designs, Altera interconnect features, SRAM cells, and RAM templates in Verilog.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 1

    Reg. No. d.

    Unoptimized technology dependent netlist


    SRM INSTITUTE OF SCIENCE AND TECHNOLOGY
    CYCLE TEST – III April-2019 PART – B (4 X 4 = 16 Marks)
    VI Semester – Electronics& Communication Engineering Answer ANY FOUR questions
    15EC327E – ASIC Design
    Duration: 90 Mins Max. Marks: 50 11. Write a Verilog code template for 4:1 Mux
    PART – A (10 X 1 = 10 Marks)
    1. Which encoding technique uses minimum logic difference in the state 12. Write a Verilog code template for designing Mealy FSM
    transition
    a.Adjacent b.Moore c.One hot d.Random 13. Discuss the features of Altera Interconnects
    2. Which of the following is not the memory synthesis approach 14. What are the various design entry used in design of ICs
    a. RAM Compiler b. RAM Standard Component
    c. Register Cell in Datapath d. Standard Cells Based
    15. Draw a 1bit SRAM cell
    3. Which of the following is the process of transforming design entry of circuit into
    a set of logic equations
    a.Simulation b.optimization c.Synthesis d.Verification PART – C(2 X 12 = 24 Marks)
    Answer ALL questions
    4. EPROM is built using which technology
    a. a.ONO b. MIM c. FAMOS d.SRAM 16 a. Write a Synthesizable RAM template in Verilog
    (OR)
    5. Simulator used to simulate critical transistor and another part of design at
    functional level is b. Write short notes on various types of simulation
    a. Mixed Mode simulator
    b. Behavioural Simulator 17 a. Discuss various I/O cells and its requirements
    c. Functional Simulator OR
    d. Gate level Simulator b. Describe the architecture of XILINX LCA family interconnects
    6. STA means
    a. Static Timing Analysis b. Stipulated Timing Analysis
    c. Static Timing Advancement d. Static Trigger Analysis

    7. Which simulator calculates values at boundaries


    a.Event Driven b.Cycle based c.Compiled d.Interpreted

    8. Which encoding technique uses minimum difference in assigning states?


    a.Adjacent b.Moore c.One hot random

    9. Elaboration step is also known as


    a. Translation b. Logic Mapping c. Optimization d.Timing

    10. Logic mapping step converts RTL to


    a.Optimized technology independent netlist
    b. Optimized technology dependent netlist
    c. Unoptimized technology independent netlist

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