Cpre 288 - Introduction To Embedded Systems: Instructors: Dr. Phillip Jones

CprE 288 – Introduction to Embedded Systems
Instructors:
Dr. Phillip Jones
http://class.ece.iastate.edu/cpre288 1
Announcements
• HW 5: Due Sunday (9/26)

• Quiz 5: Tuesday (9/28) – First 10 minutes of class using
Canvas
– Class lectures
– HW 4 & 5 material
– Notes: Once sheet of notes (1-side)
• Quiz 4: This Thursday
4
BITWISE OPERATIONS
Why Bitwise Operation
Why use bitwise operations in embedded systems
programming?
Each single bit may have its own meaning
– Push button array: Bit n is 0 if push button n is pushed
– LED array: Set bit n to 0 to light LED n
Data from/to I/O ports may be packed
– Two bits for shaft encoder, six bits for push button packed in
PINC
– Keypad input: three bits for row position, three bits for
column position
Data in memory may be packed to save space
– Split one byte into two 4-bit integers
Why Bitwise Operation
Read the input:

GPIO_PORTE_R;
How to have application

determine which button
is being pushed?
SW4 SW3 SW2 SW1
Bit 3 Bit 2 Bit 1 Bit 0
Buttons connected to PORTE, bits 3-0
Bitwise Operations
Common programming tasks:

• Clear/Reset certain bit(s)
• Set certain bit(s)
• Test if certain bit(s) are cleared/reset
• Test if certain bit(s) are set
• Toggle/invert certain bits
• Shift bits around
Bitwise Operators: Clear/Force-to-0 Bits
C bitwise AND: &
ch = ch & 0x3C; What does it do?
1 Preserve
Consider a single bit x & x
x AND 1 = x Preserve x
Force 0
x AND 0 = 0 Clear/Force 0 0
0
&
Truth Table x
Bit x Mask bit Bit x & Mask bit
x 0 0 (Forced to 0)
x 1 x (Value preserved)
Bitwise Operators: Clear/Force-to-0 Bits
ch = ch & 0x3C;
x7 x6 x5 x4 x3 x2 x1 x0
AND 0 0 1 1 1 1 0 0
0 0 x5 x4 x3 x2 0 0
Clear bits 7, 6, 1, 0
Preserve bits 5, 4, 3, 2
Clear bit(s): Bitwise-AND with a mask of 0(s)

Bitwise Operators: Clear/Reset Bits
Another example:
char op1 = 1011 1100; We want to clear bit 4 to 0.

char op2 = 1110 1111; We use op2 as a mask
char op3;
1011 1100
AND 1110 1111
op3 = op1 & op2; 1010 1100
Class Exercise
char ch;
Clear every other bit of ch starting from bit-position 0
Bitwise Operators: Set Bits
C bitwise OR: |
ch = ch | 0xC3; What does it do?
Consider a single bit x

x OR 1 = 1 Set
x OR 0 = x Preserve
Bitwise Operators: Set Bits
ch = ch | 0xC3;
x7 x6 x5 x4 x3 x2 x1 x0
OR 1 1 0 0 0 0 1 1
1 1 x5 x4 x3 x2 1 1
Set bits 7, 6, 1, 0
Set bit(s): Bitwise-OR with a mask of 1(s)

Bitwise Operators: Set Bit
Another example:
char op1 = 1000 0101; We want to set bit 4 to 1.

char op2 = 0001 0000; We use op2 as a mask
char op3;
1000 0101
op3 = op1 | op2; OR 0001 0000
1001 0101
Bitwise Operators: Toggle Bits
C bitwise XOR: ^
ch = ch ^ 0x3C; What does it do?
Consider a single bit x

x XOR 1 = x Toggle
x XOR 0 = x Preserve
Bitwise Operators: Toggle Bits
C bitwise XOR: ^ ch = ch ^ 0x3C;
x7 x6 x5 x4 x3 x2 x1 x0
XOR 0 0 1 1 1 1 0 0
x7 x6 x5 x4 x3 x2 x1 x0
Toggle bits 5, 4, 3, 2
Toggle bit(s): Bitwise-XOR with a mask of 1(s)

Bitwise Operators: Invert Bits
C bitwise invert: ~ ch = ~ch;
INV x7 x6 x5 x4 x3 x2 x1 x0
x7 x6 x5 x4 x3 x2 x1 x0
Example: ch = 0b00001111;
~ch == 0b11110000
Class Exercise
unsiged char ch;
short n;
Force the lower half of ch to 0
Starting from bit 0 of ch, force every other bit to 1
Force bit 15 and bit 0 of n to 0
Toggle bits 7 and 6 of ch
Bitwise Operators: Shift-Left
unsigned char my_reg = 0b00000001;

unsigned char shift_amount = 5;
unsigned char my_result;
my_result = my_reg << shift_amount;

00000001
00100000
<<, shifts “my_reg”, “shift_amount” places to the left

0s are shifted in from the right
Bitwise Operators: Shift-Right Logical
unsigned char my_reg = 0b10000000;

my_result = my_reg >> shift_amount; 10000000

00000100
With unsigned type, >> is shift-to-right logical

0s are shifted in from the left
Bitwise Operators: Shift-Right Arithmetic
signed char my_reg = 0b10000000;
my_result = my_reg >> shfit_amount; 10000000

11111100
my_reg = 0b01111111;
my_result = my_reg >> shfit_amount; 01111111
00000011
With signed type, >> is shift-right arithmetic
Sign bit value are shifted in from the left
Bitwise Operators: Shift and Multiple/Divide
n << k is equivalent to n * 2k
Example: 5 << 2 = 5*4 = 20
0b0000 0101 << 2 = 0b0001 0100
n >> k is equivalent to n / 2k
Example: 20 >> 2 = 5
0b0001 0100 >> 2 = 0b0000 0101
Bitwise Operators: Shift and Multiple/Divide
Shift-Right Arithmetic: Why shift in the sign bit?
Example: (char) 32 >> 2 = 32 / 4 = 8

0b0010 0000 >> 2 = 0b0000 1000
Example: (char) -32 >> 2 = -32/ 4 = -8

0b1110 0000 >> 2 = 0b1111 1000
Bitwise Operators: Shift and Set
What’s the effect of the following state?

#define BIT_POS 4
ch = ch | (1 << BIT_POS);
What is (1 << 4)?

0000 0001 << 4
0001 0000
In general case: (1 << n) yields a mask of a 1 at bit n

The effect of the statement: Set bit 4
Bitwise Operators: Shift and Set
Another example:
unsigned char my_mask = 0000 0001;
unsigned char my_result = 1101 0101; Want to force bit 5
to a 1
my_result = my_result | (my_mask << shift_amount);

1101 0101 | 00100000 1101 0101
OR 0010 0000
1111 0101
Shift the 1(s) of the MASK to the appropriate position, then OR
with my_result to force corresponding bit positions to 1.
Bitwise Operators: Shift and Clear
What’s the effect of the following state?

#define BIT_POS 4
ch = ch & ~(1 << BIT_POS);
What is ~(1 << 4)?

0000 0001 << 4
0001 0000 ~
1110 1111
In general case: ~(1 << n) yields a mask of a 0 at bit n
Note: Compiler does the calculation at compilation time
Bitwise Operators: Shift and Clear
unsigned char my_mask = 0000 0111;
unsigned char my_result = 1011 0101; Want to force bit 7-5
to a 0
my_result = my_result & ~(my_mask << shift_amount);
1011 0101 & ~ 11100000 1011 0101

AND 0001 1111
1011 0101 & 00011111 0001 0101
Shift the 0(s) of the MASK to the appropriate position, then
AND with my_result to force corresponding bit positions to
0.
Exercise
unsigned char ch;

unsigned short n;
Divide n by 32 in an efficient way
Swap the upper half and lower half of ch
Bitwise Testing
Reminder: Conditionals are evaluated on the basis of

zero and non-zero (i.e. Boolean).
The quantity 0x80 is non-zero and therefore TRUE.
if (0x02 | 0x44)
TRUE or FASE?
Bitwise Testing
Example
Find out if bit 7 of variable nVal is set to 1
Bit 7 = 0x80 in hex
if ( nVal & 0x80 )

{ …
}
What happens when we want to test for multiple bits?

if statement looks only for a non-zero value, a non-zero value
means at least one bit is set to TRUE
Bitwise Testing: Any Bit is Set to 1?
Example
See if bit 2 or 3 is set to 1
Bits 2,3 = 0x0C in hex
if (nVal & 0x0C)

{
Some code…
}
What happens for several values of nVal?

nVal = 0x04 bit 2 is set Result = 0x04 TRUE
nVal = 0x0A bits 3,1 are set Result = 0x08 TRUE
nVal = 0x0C bits 2,3 are set Result = 0x0C TRUE
Bitwise Testing: All Bits Are Set to 1?
Why does this present a problem?

What happens if we want to see if both bits 2 and 3 are set, not just to
see if one of the bits is set to true?
Won’t work without some other type of test
Two solutions
Test each bit individually
if ( (nVal & 0x08) && (nVal & 0x04))
Check the result of the bitwise AND
if ((nVal & 0x0C) == 0x0C)
Why do these solutions work?
1. Separate tests – Check for each bit and specify logical condition
2. Equality test – Result will only equal 0x0C if bits 2 and 3 are set
Bitwise Testing
• Testing if any of a set of bits is set to 1
1) Decide which bits you want to test
2) Isolate those bits (i.e. force all other bits to 0)
• Testing if all bits of a set of bits are set to 1
1) Decide which bits you want to test
2) Isolate those bits (i.e. force all other bits to 0)
3) Compare for equality with the Mask
• For the case of testing for bits set to 0. Follow bit(s) set to 1 testing
procedure, but invert the variable that you are testing.
• Generic systematic checking example
if( (x & MASK_ALL1s) == MASK_ALL1 &&
(~x & MASK_ALL0s) == MASK_ALL0s &&
(x & MASK_ANY1s) &&
(~x & MASK_ANY0s) )
Exercise
char ch;
Test if any of bits 7, 6, 5, 4 is set to 1
Test if all of bits 7, 6, 5, 4 are set to 1
Test if all of bits 7 and 6 are set to 1, and if bits 5 and 4 are
cleared to 0
Bitwise operations: Summary
•Forcing bits to 0: & (AND)
•Forcing bits to 1: | (OR)
•Toggle bits: ^ (XOR)
•Testing for bits set to 1
•Testing for bits cleared to 0
•Generic systematic testing approach:
if( (val & MASK_ALL1s) == MASK_ALL1 &&
(~val & MASK_ALL0s) == MASK_ALL0s &&
(val & MASK_ANY1s) &&
(~val & MASK_ANY0s) )
*Where: MASK_XXX is a mask with 1s in the positions being tested
Memory Mapped I/O
Microcontroller / System-on-Chip (SoC)
Microcontroller Outside
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
ADC PCTL
CFG|DATA|STATUS 7
0 6
Port X (8-bits)
5
UART X 4
CFG|DATA|STATUS
NVIC Y AFSEL
3
Timers 0
1 2
CFG|DATA|STATUS
1
GPIO_DATA 0
Memory Mapped I/O
•Package Pins
•Pins with shared (multiplexed) functionality
– General Purpose I/O
– Device I/O
•Memory mapped registers
– Configuration registers
– Data registers
– Status registers
TM4C123 I/O Ports
• 64 package pins
TM4C123 I/O Ports
• 64 package pins
Allows Software to access the
world outside of the chip
TM4C123 I/O Ports
• 64 package pins
• 6 GPIOs Ports(A – F)
–Each 8-bits
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
PORT A
TM4C123 I/O Ports
PORT
• 64 package pins B
–Each 8-bits
PORT
PORT
B
B
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
PORT
C
PORT C
TM4C123 I/O Ports
PORT PORT
• 64 package pins D D
–Each 8-bits
PORT D
PORT
D
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
PORT E
PORT
E
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
PORT F
PORT F
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
• Many GPIOs have
alternate functions
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
• Many GPIOs have
alternate functions
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
• Many GPIOs have
alternate functions
select
U0Tx
MUX
PA1
TM4C123 I/O Ports
• 64 package pins
–Each 8-bits
• Many GPIOs have
alternate functions
select
U0Tx
MUX
PA1
TM4C123 I/O Ports
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
SW writes Configuration Register
HW writes Data Register

select
U0Tx
MUX
PA1
Software writes Data Register

TM4C123 I/O Ports
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
U0Tx
Hardware device logic select
Config Data Status
MUX
PA1
Software writes Data Register

TM4C123 I/O Ports
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
U0Tx
Hardware device logic select
Config Data Status
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Program Address Decode
Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Data
World
CPU 0x20000000
Memory 0x20007FFF Memory
Devices GPIO
Interrupts
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Data
World
CPU 0x20000000
0x40000000 Devices GPIO
Interrupts 0x400FFFFF
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
GPIO_PORTA_DATA
TM4C123 I/O Ports
Data
World
CPU 0x20000000
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
0x400043FC GPIO_PORTA_DATA
TM4C123 I/O Ports
Data
World
CPU 0x20000000
0x4000C000 - 0x4000CFFF
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
CPRE 288 Microntroller: Full Memory Map
70
TM4C123 I/O Ports
Data
World
CPU 0x20000000
0x4000C000 - 0x4000CFFF
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
Memory Mapped General Purpose I/O (GPIO) Ports
TM4C123GH6PM:
• 6 general purpose I/O ports: Port A, B, C, D, E, F
• Processor communicates with them through
memory mapped registers.
• A set of data and control registers associated
with each port.
http://class.ece.iastate.edu/cpre288
72 72
• Processor communicates with arbitrary attachments using ports

• Each GPIO port has several registers, we will focus on 4.
SYSCTL_RCGCGPIO_R – Enables the port’s system clock

GPIO_PORTx_DATA_R – 8bit data register (read/write)
GPIO_PORTx_DIR_R – Data direction register
GPIO_PORTx_DEN_R – Digital enable register
SYSCTL_RCGCGPIO_R (GPIO Run Mode Clock Gating Control)

• A GPIO port’s clock must be enabled to use its registers.
(Your program will crash if you attempt to update an GPIO
port’s registers without enabling its clock)
• bits 5-0 in SYSCTL_RCGCGPIO_R represent ports F-A.
E.g.:
//Enable Port F & B clocks
SYSCTL_RCGCGPIO_R |= 0b100010;
GPIO_PORTx_DEN_R (GPIO Digital Enable Register)

– Writing ‘0’ to a bit disables the digital functionality
for the corresponding pin of the Port.
– Writing ‘1’ to a bit enables the digital functionality
for the corresponding pin of the Port.
Example:
// Enable Digital functionality for pin
// 8 and 0 of Port A, and preserve the others
GPIO_PORTA_DIR_R |= 0b10000001;
75 75
GPIO_PORTx_DIR_R (GPIO Direction Register)

– Writing ‘0’ to a bit programs the corresponding pin
of the Port as input
– Writing ‘1’ to a bit programs the corresponding pin
of the Port as output
Example:
//All bits of port A prog for input except bit0
GPIO_PORTA_DIR_R = 0b00000001;
76 76
GPIO_PORTX_DATA_R Register:
For output configured port: If a bit in in the Port’s DATA register
is written when the corresponding pin is configured as an
output, then the port’s pin will be driven with this value.
Write to a port using its DATA register.

E.g.:
SYSCTL_RCGCGPIO_R |= 0b000001; //enable PORTA clock
GPIO_PORTA_DIR_R = 0xFF; //set port A dir to output
GPIO_PORTA_DEN_R = 0xFF; //Enable pins 0-7
GPIO_PORTA_DATA_R = my_char;//set port A to my_char
Give C code without using the
“magic” varible name.
TM4C123 I/O Ports
Data
World
CPU 0x20000000
GPIO_PORTA_DATA_R = my_char;
0x4000C000 - 0x4000CFFF
UART select
CFG|DATA|STATUS
Give C code without using the
MUX
“magic” variable name. PA1
char *ptr; 7 6 5 4 3 2 1 0
ptr = 0x4000_43FC;
*ptr = my_char; 0x400043FC GPIO_PORTA_DATA
GPIO_PORTX_DATA_R Register:
For output configured port: If a bit in in the Port’s DATA register
is written when the corresponding pin is configured as an
output, then the port’s pin will be driven with this value.
Write to a port using its DATA register.

E.g.:
SYSCTL_RCGCGPIO_R |= 0b000001; //enable PORTA clock
GPIO_PORTA_DIR_R = 0xFF; //set port A dir to output
GPIO_PORTA_DEN_R = 0xFF; //Enable pins 0-7
GPIO_PORTA_DATA_R = my_char;//set port A to my_char
Directly using the definition of GPIO_PORTA_DATA_R

*((char *)0x400043FC) = my_char;
// tm4c123gh6pm.h
//*****************************************************************************
// GPIO registers (PORTA)
//*****************************************************************************
#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528))
#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C))
#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530))
#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534))
TM4C123 I/O Ports
Data
World
CPU 0x20000000
0x4000C000 - 0x4000CFFF
UART select
CFG|DATA|STATUS
MUX
PA1
7 6 5 4 3 2 1 0
TM4C123 I/O Ports
Data
World
CPU 0x20000000
0x4000C000 - 0x4000CFFF
UART select
CFG|DATA|STATUS
MUX
Timers PA1
CFG|DATA|STATUS
7 6 5 4 3 2 1 0
TM4C123 I/O Ports
Data
World
CPU 0x20000000
ADC
CFG|DATA|STATUS
UART select
CFG|DATA|STATUS
?
MUX
Timers PA1
CFG|DATA|STATUS
7 6 5 4 3 2 1 0
TM4C123 I/O Ports
Data
World
CPU 0x20000000
ADC
CFG|DATA|STATUS
UART select
CFG|DATA|STATUS select
MUX
MUX
Timers PA1
CFG|DATA|STATUS
7 6 5 4 3 2 1 0
TM4C123 I/O Ports
Data
World
CPU 0x20000000
ADC
CFG|DATA|STATUS
UART select
CFG|DATA|STATUS select
MUX
MUX
Timers PA1
CFG|DATA|STATUS
7 6 5 4 3 2 1 0
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
ADC PCTL
CFG|DATA|STATUS 7
0 6
Port X (8-bits)
5
UART X 4
CFG|DATA|STATUS
NVIC Y AFSEL
3
Timers 0
1 2
CFG|DATA|STATUS
1
GPIO_DATA 0
Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
ADC PCTL
CFG|DATA|STATUS 7
0 6
Port X (8-bits)
5
UART X 4
CFG|DATA|STATUS
NVIC Y AFSEL
3
Timers 0
1 2
CFG|DATA|STATUS
1
GPIO_DATA 0
GPIO Port: Alternative Function Architecture
Hardware writes
(Alternative Function)
Software writes
(GPIO)
Figure 2.17 Function block diagram of Analog/Digital GPIO control.

Program Data
World
Memory CPU
Memory
Devices GPIO
Interrupts
ADC PCTL
CFG|DATA|STATUS 7
0 6
Port X (8-bits)
5
UART X 4
CFG|DATA|STATUS
NVIC Y AFSEL
3
Timers 0
1 2
CFG|DATA|STATUS
1
GPIO_DATA 0
• GPIOAFSEL: For each wire select GPIO or Alternative Function

• GPIOPCTL: For each wire choose which Alternative Function
31 7 6 5 4 3 2 1 0
GPIOAFSEL …... 1 1
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
GPIOPCTL PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0
Table 2.6 Table 2.6

PMC6 Bit Encoding PMC0 Bit Encoding
(1, 2, 3, … 9, 14) (1, 2, 3, … 9, 14)
0001, 0010, 0011, 0001, 0010, 0011,
… 1001, 1110 … 1001, 1110
Figure 2.19 The illustration for GPIOAFSEL and GPIOPCTL registers.
Table 2.6 GPIO Pins and Alternate Functions
Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
I/O Pin
Function 1 2 3 4 5 6 7 8 9 14
PA0 17 - U0RX - - - - - - CAN1RX - -
PA1 18 - U0TX - - - - - - CAN1TX - -
PA2 19 - - SSI0CLK - - - - - - - -
PA3 20 - - SSI0FSS - - - - - - - -
PA4 21 - - SSI0RX - - - - - - - -
PA5 22 - - SSI0TX - - - - - - - -
PA6 23 - - - I2C1SCL - M1PWM2 - - - - -
PA7 24 - - - I2C1SDC - M1PWM3 - - - - -
PB0 45 USB0ID U1RX - - - - - T2CCP0 - - -
PB1 46 USB0VBUS U1TX - - - - - T2CCP1 - - -
PB2 47 - - - I2C0SCL - - - T3CCP0 - - -
PB3 48 - - - I2C0SDC - - - T3CCP1 - - -
PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX - -
PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX - -
PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 - - -
PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 - - -
TCK
PC0 52 - - - - - - T4CCP0 - - -
SWCLK
TMS
PC1 51 - - - - - - T4CCP1 - - -
SWDIO
PC2 50 - TDI - - - - - T5CCP0 - - -
TDO
PC3 49 - - - - - - T5CCP1 - - -
SWO
PC4 16 C1- U4RX U1RX - M0PWM6 - IDX1 WT0CCP0 U1RTS - -
PC5 15 C1+ U4TX U1TX - M0PWM7 - PHA1 WT0CCP1 U1CTS - -
• What values do GPIOAFSEL and GPIOPCTL need to be given
to configure Port B to use UART1 TX?
• What values do GPIOAFSEL and GPIOPCTL need to be given to
configure Port B to use UART1 TX?
I/O Pin
Function 1 2 3 4 5 6 7 8
PB0 45 USB0ID U1RX - - - - - T2CCP0 -
PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
PB2 47 - - - I2C0SCL - - - T3CCP0 -
PB3 48 - - - I2C0SDC - - - T3CCP1 -
PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -
I/O Pin
Function 1 2 3 4 5 6 7 8
PB0 45 USB0ID U1RX - - - - - T2CCP0 -
PB2 47 - - - I2C0SCL - - - T3CCP0 -
PB3 48 - - - I2C0SDC - - - T3CCP1 -
GPIO_PORTB_AFSEL
7 6 5 4 3 2 1 0
I/O Pin
Function 1 2 3 4 5 6 7 8
PB0 45 USB0ID U1RX - - - - - T2CCP0 -
PB2 47 - - - I2C0SCL - - - T3CCP0 -
PB3 48 - - - I2C0SDC - - - T3CCP1 -
GPIO_PORTB_AFSEL
7 6 5 4 3 2 1 0
PortB
1
Wire 1
0
I/O Pin
Function 1 2 3 4 5 6 7 8
PB0 45 USB0ID U1RX - - - - - T2CCP0 -
PB2 47 - - - I2C0SCL - - - T3CCP0 -
PB3 48 - - - I2C0SDC - - - T3CCP1 -
GPIO_PORTB_PCTL
PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_PORTB_AFSEL
7 6 5 4 3 2 1 0
31 28 27 24 23 21 20 16 15 12 11 87 43 0
PortB
1
Wire 1
0
I/O Pin
Function 1 2 3 4 5 6 7 8
PB0 45 USB0ID U1RX - - - - - T2CCP0 -
PB2 47 - - - I2C0SCL - - - T3CCP0 -
PB3 48 - - - I2C0SDC - - - T3CCP1 -
GPIO_PORTB_PCTL
PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_PORTB_AFSEL
7 6 5 4 3 2 1 0
31 28 27 24 23 21 20 16 15 12 11 87 43 0
15
PortB
1
0
Wire 1
0

Cpre 288 - Introduction To Embedded Systems: Instructors: Dr. Phillip Jones

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CprE 288 – Introduction to Embedded Systems

• HW 5: Due Sunday (9/26)

Read the input:

How to have application

Buttons connected to PORTE, bits 3-0

Common programming tasks:

C bitwise AND: &

ch = ch & 0x3C; What does it do?

Clear bit(s): Bitwise-AND with a mask of 0(s)

char op1 = 1011 1100; We want to clear bit 4 to 0.

Clear every other bit of ch starting from bit-position 0

ch = ch | 0xC3; What does it do?

Consider a single bit x

Set bit(s): Bitwise-OR with a mask of 1(s)

char op1 = 1000 0101; We want to set bit 4 to 1.

ch = ch ^ 0x3C; What does it do?

Consider a single bit x

C bitwise XOR: ^ ch = ch ^ 0x3C;

Toggle bit(s): Bitwise-XOR with a mask of 1(s)

C bitwise invert: ~ ch = ~ch;

Force the lower half of ch to 0

Starting from bit 0 of ch, force every other bit to 1

Force bit 15 and bit 0 of n to 0

Toggle bits 7 and 6 of ch

unsigned char my_reg = 0b00000001;

my_result = my_reg << shift_amount;

<<, shifts “my_reg”, “shift_amount” places to the left

unsigned char my_reg = 0b10000000;

my_result = my_reg >> shift_amount; 10000000

With unsigned type, >> is shift-to-right logical

my_result = my_reg >> shfit_amount; 10000000

Shift-Right Arithmetic: Why shift in the sign bit?

Example: (char) 32 >> 2 = 32 / 4 = 8

Example: (char) -32 >> 2 = -32/ 4 = -8

What’s the effect of the following state?

What is (1 << 4)?

In general case: (1 << n) yields a mask of a 1 at bit n

my_result = my_result | (my_mask << shift_amount);

What’s the effect of the following state?

What is ~(1 << 4)?

my_result = my_result & ~(my_mask << shift_amount);

1011 0101 & ~ 11100000 1011 0101

unsigned char ch;

Divide n by 32 in an efficient way

Swap the upper half and lower half of ch

Reminder: Conditionals are evaluated on the basis of

The quantity 0x80 is non-zero and therefore TRUE.

if ( nVal & 0x80 )

What happens when we want to test for multiple bits?

if (nVal & 0x0C)

What happens for several values of nVal?

Why does this present a problem?

Test if any of bits 7, 6, 5, 4 is set to 1

Test if all of bits 7, 6, 5, 4 are set to 1

HW writes Data Register

Software writes Data Register

Software writes Data Register

• Processor communicates with arbitrary attachments using ports