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    Sri Venkateshwara College of Engineering

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    jaya sree
    1. The document is an internal assessment test question paper for a VLSI Design course covering MOS transistor theory, CMOS fabrication, and physical design aspects like layout diagrams. 2. It contains 6 questions divided into 3 parts covering topics like MOSFET operation, CMOS inverter characteristics, nMOS fabrication steps, CMOS vs bipolar technologies, and CMOS gate layout and design rules. 3. The questions range from understanding to application level knowledge as defined in the course outcomes for the course.

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    Sri Venkateshwara College of Engineering

    Uploaded by

    jaya sree
    38 views1 page
    1. The document is an internal assessment test question paper for a VLSI Design course covering MOS transistor theory, CMOS fabrication, and physical design aspects like layout diagrams. 2. It contains 6 questions divided into 3 parts covering topics like MOSFET operation, CMOS inverter characteristics, nMOS fabrication steps, CMOS vs bipolar technologies, and CMOS gate layout and design rules. 3. The questions range from understanding to application level knowledge as defined in the course outcomes for the course.

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    Original Title

    15ec63 Vlsi Design

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    1. The document is an internal assessment test question paper for a VLSI Design course covering MOS transistor theory, CMOS fabrication, and physical design aspects like layout diagrams. 2. It contains 6 questions divided into 3 parts covering topics like MOSFET operation, CMOS inverter characteristics, nMOS fabrication steps, CMOS vs bipolar technologies, and CMOS gate layout and design rules. 3. The questions range from understanding to application level knowledge as defined in the course outcomes for the course.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    38 views1 page

    Sri Venkateshwara College of Engineering

    Uploaded by

    jaya sree
    1. The document is an internal assessment test question paper for a VLSI Design course covering MOS transistor theory, CMOS fabrication, and physical design aspects like layout diagrams. 2. It contains 6 questions divided into 3 parts covering topics like MOSFET operation, CMOS inverter characteristics, nMOS fabrication steps, CMOS vs bipolar technologies, and CMOS gate layout and design rules. 3. The questions range from understanding to application level knowledge as defined in the course outcomes for the course.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    Format No ACD50

    Date 01/08/2016
    Sri Venkateshwara College of Engineering
    INTERNAL ASSESSMENT TEST QUESTION PAPER Rev No. 01
    Page 1 of 1

    USN:
    CBCS SCHEME 2015
    IA Test- I
    Term: April-2021 to August-2021
    Programme: Electronics & Communication Engineering Semester& Section: 6 - ‘A’ & ‘B’
    Course Title : VLSI Design Date: 25/05/2021
    Course Code: 15EC63 Time: 09.15 AM to 10.40 AM
    Duration: 90 Minutes Maximum Marks: 30

    Instructions: Answer THREE full questions, choosing ONE full question from each part. Use A4
    sheets only.
    SL.NO Kx, COx Question Marks
    PART – I (12 Marks)
    Explain with a neat diagram enhancement mode transistor action of nMOS
    a) K2, CO363.1 6
    transistor.
    1 Derive the expression for drain to source current in active and saturation
    b) K3, CO363.1 region of nMOSFET 6

    OR
    a) K2, CO363.1 Explain the working of tri state inverter with a neat diagram 6
    2
    With a neat circuit and sketch explain CMOS inverter DC characteristics by
    b) K2, CO363.1 6
    mentioning all the operating regions
    PART – II (12 Marks)
    3 K2, CO363.2 Describe the fabrication steps for nMOS transistor using a neat diagram 12
    OR 12
    a) K2, CO363.2 Compare CMOS and bipolar technologies 6
    4
    b) K3, CO363.2 Draw the design rule for pMOS, nMOS and CMOS 6
    PART – III (6 Marks)
    Draw the schematic diagram and layout diagram for two input CMOS 6
    5 K3, CO363.3
    NAND gate
    OR
    With a neat sketch explain the CMOS P-Well Process steps to Fabricate a 6
    6 K3, CO363.3
    CMOS inverter
    COx- course outcome (1to5) Kx- blooms knowledge Level (K1, K2, K3, K4, K5, K6)
    K1 – Remember K2 – Understand K3 – Apply K4 – Analyze K5 – Evaluate K6 – Create
    CO No. Knowledge Max
    COURSE OUTCOMES
    XYZ.I Level Marks
    C363.1 Understand the MOS transistor theory analyse the CMOS fabrication flow and
    technology scaling. K2 24

    C363.2 Understand the stick and layout diagrams with the knowledge of physical design K2 24
    aspects.
    C363.3 Analyze the memory elements along with timing considerations K4 12
    TOTAL 60

    Scrutinizer Signature

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