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CMOS Inverter

The document discusses CMOS inverters including their properties, design, and power dissipation. It explains that CMOS inverters have no static power dissipation and always have one transistor on and one off. The document also covers setting transistor width-to-length ratios to achieve symmetrical voltage transfer characteristics and optimal noise margins.

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مصطفى عادل أصغر حسن العبيدي
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26 views15 pages

CMOS Inverter

The document discusses CMOS inverters including their properties, design, and power dissipation. It explains that CMOS inverters have no static power dissipation and always have one transistor on and one off. The document also covers setting transistor width-to-length ratios to achieve symmetrical voltage transfer characteristics and optimal noise margins.

Uploaded by

مصطفى عادل أصغر حسن العبيدي
Copyright
© © All Rights Reserved
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BY

Mustafa Adel Asqer


June 28, 2020
Overview
 CMOS Inverter
 CMOS Properties
 Design of CMOS
inverter (I)
 Design of CMOS
inverter (II)
 Summary
 power Dissipation
Courtesy Quiller Electronics Limited
CMOS Properties
 Full rail-to-rail swing
 No direct path exists between the supply and ground rails
under steady-state operating conditions
 No static power dissipation
 The steady-state input current is nearly zero
 At every point in time (except during the switching transients)
each gate output is connected to either VDD or GND via a
low-resistive path
 Symmetrical VTC
Inverter as simplest logic gate
CMOS Inverter Technology
Complementary MOS (CMOS)
Logic Design
 Inverter with resistive load ⇒ power dissipation when the
input is high.
 If an NMOS and PMOS transistor is used ⇒ CMOS
 One transistor is always off while the other is on ⇒ no static
power consumption
CMOS voltage transfer
Characteristic
Regions of Operation of Transistors in
a Symmetrical Inverter
Design of CMOS inverter (I)
 NMH = VOH - VIH = VDD - VIH
 NML=VIL-VOL=VIL-0=VIL
 KR = Kp / Kn

 Influence of the symmetry


via W/L of transistors
Design of CMOS inverter (II)
 The ratio (W/L) in CMOS design is used to set the level of Vth
 The ratio required to establish a given inverter threshold
voltage
 To get a symmetrical voltage transfer curve,Vth is set to VDD/2
 If in a process |VTp| = VTn, the device aspect ratios for a
symmetrical inverter are related
 Since µn / µp ≈ 2.5, a minimum area CMOS inverter will have
(W/L)n ≈ 1 and (W/L)p ≈ 2.5. In this case the voltage transfer
function is completely symmetric.
Summary
So what did we accomplish until now?
We know how a CMOS inverter works.
VOL, VOH - do you still know it?
We know how to set the W/L ratios of the transistors to
get optimal noise margins.
So we make every inverter the same, that is to say
minimal -or?
power Dissipation
Two kinds of power dissipation in digital electronics:
 static power dissipation 4.0V (logic gate output is stable)
 dynamic power dissipation (during 2.0V switching of logic gate)
 With CMOS nearly no static power dissipation!
Thank you

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