ST5421

SID-GCI : S/T INTERFACE DEVICE WITH GCI

PRELIMINARY DATA

SINGLE CHIP 4 WIRES 192kb/s TRANS-

CEIVER FULLY COMPLYING WITH CCITT
I.430
ISDN BASIC ACCESS HANDLING 144kb/s
2B + D TRANSMISSION
GCI COMPATIBLE INTERCHIP INTERFACE
ADAPTIVE AND FIXED TIMING OPTIONS
FOR NT DIP20 PLCC28
CLOCK RESYNCHRONIZER AND DATA
BUFFERS FOR NT2 ORDERING NUMBERS:
PROGRAMMABLE S1 AND Q CHANNELS ST5421CP ST5421CFN
HANDLING ACCORDING TO US ANSI
STANDARD FOR LAYER 1 MAINTENANCE
EASILY INTERFACEABLE WITH ST5451 PIN CONNECTIONS (Top views)
HDLC & GCI CONTROLLER AND ANY
OTHER GCI COMPATIBLE DEVICE

DESCRIPTION
The ST5421 (SID-GCI) is a complete monolithic
transceiver for data transmission on twisted pair
subscriber loops. It is buIlt on SGS-THOMSON DIP20
HCMOS 3A double metal advanced process, and
requires only a single + 5V supply. AII functions
specified in CCITT recommendation I.430 for
ISDN basic access at the ’S’ and ’T’ interfaces
are provided, and the device can be configured to
operate either in TE (Terminal Equipment), in
NT1 or NT2 (Network Termination) or in PABX
line-card device.
GCI interchip interface highly enhances device
connection efficiency by multiplexing controls and
LSD-
FSA

LO+
VCC

LO-

LI+

data on the same bus and requiring only 4 pins.

LI-

ST5421 implements all the GCI standard func- 4 3 2 1 28 27 26

tions for Monitor and Control/Indicate channels,
supporting up to 8 GCI peripherals in multiplexed VCC 5 25 GND
mode. N.C. 6 24 GND
As specified in I.430, full-duplex transmission at MCLK/XTAL 7 23 MO
192kb/s is provided on separate transmit and re- XTAL2 8
PLCC28 22 RST
ceive twisted wire pairs using inverted Alternate N.C. 9 21 N.C.
Mark Inversion (AMI) line coding. Various chan-
N.C. 10 20 N.C.
nels are combined to form the 192kb/s aggregate
rate, including 2 ’B’ channels, each of 64kb/s, and BX 11 19 SO/BCL/BUS
1 ’D’ channel at 16kb/s. In addition, multiframe 12 13 14 15 16 17 18
transmission is provided in a switchable process-
ing mode based on United State ANSI standard
PCKO/CLK
S1/FSB
DEN

S2/M1
BCLK
N.C.

BR

for Layer 1 maintenance. 800 bit/s message ori- D94TL093

ented data transmission is supported by S1 and

Q channels.

September 1995 1/29

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST5421

DESCRIPTION (Continued) the standard types of cable pairs commonly found

in premise wiring installations when tested with
All I.430 wiring configurations are supported by the noise sources specified in I.430.
ST5421 including passive bus for TE’s distributed
point-to-point and point-to-multipoint extended. Far-end Clock Resynchronizer automatically se-
Adaptive receive signal processing enables the lected, data buffer and slave-slave mode allow
device to operate with low bit error rate on any of design of NT2 trunk-card connected to several T
interfaces.
BLOCK DIAGRAM

2/29
 ST5421

PIN DESCRIPTION

Name DIP PLCC Description

GND 17 24,25 Ground Reference Voltage: all analog and digital signals are referenced to this
pin.

VCC 4 4,5 Positive Power Supply Input 5V ( ± 5%) relative to GND

MCLK/XTAL 5 7 Master Clock or Crystal Oscillator Input: this pin requires either a 15.36MHz
crystal (parallel resonant with RS < 100 Ω ) to be tied between this pin and
XTAL2 or a logic CMOS level 15.36MHz clock from a stable source. When
using a 20pF crystal, a total of 33pF load capacitance to GND must also be
connected. In NT configurations. MCLK clock input doesn’t need to be
synchronous with the Network Reference Clock (FSa).

XTAL2 6 8 Crystal Oscillator Output. This pin should be connected to one end of the
15.36MHz crystal, otherwise is not connected. (see MCLK/XTAL).

BCLK 9 14 Bit Clock: this signal determines the data shift rate at GCI. Data is shifted-in on
Bx and shifted-out on Br at half the BCLK frequency. When NT/TES mode is
selected, BCLK is an input which does not need to be synchronous with the
Master Clock input (MCLK).
When TEM is selected, BCLK is an output at frequency of 1536kHz. This clock
is phase locked to the receive line signal and synchronous with FSa output.

FSa 3 3 Frame Synchronization Clock: 8kHz clock which defines the start of the frame.
In GCI slave (NT/TES) FSa is an input used as a network reference clock for
S/T line. In GCI master (TEM) is an output applicable as a validation strobe for
the first B channel.

S1/FSb 11 16 S1 if M0 = 1; is GCI channel number selection (input).

FSb if M0 = 0 and M1 = 0 (TEM): is a data strobe indicating the active slot for
the second B channel on the GCI (output).
In NT1 mode, M0 = 0; M1 = 1, this pin is not used and must be left floating.

Bx 7 11 Digital Input for GCI Channels: data to be transmitted to S line is shifted-in at

half the BCLK frequency on the 2nd falling edge.

Br 10 15 Digital Output for GCI Channel (OPENDRAIN): data is shifted-out at half the
BCLK frequency on the transmit rising edges of BCLK.
An external pull-up resistor is needed.

DEN 8 13 In TEM mode DEN is an output, normally low, that pulses high to indicate the
active time slot for D channel data at the Bx input. It is intended to be gated
with BCLK to control the D channel shifting from a layer 2 device (i.e. ST5451)
to ST5421 transmit buffer. Using ST5451 HDCL/GCI controller, no external
circuitry is needed. In NT/TES mode this pin is not used and must be kept
floating.

Not Connected – 6,9,10, Leave open on the board.

12,20,21

PCK0/CLK 12 17 PCK0 IN TEM, LT/NT2, NT1 mode: 32 kHz clock output synchronized to GCI
clocks. It is intended to synchronize DC/DC converter in TEM mode.
CLK in TES mode: is a clock signal open drain output phased-locked to the
receive S line signal and applicable as far-end clock reference. Its frequency is
1536kHz compatible with 768kbit/s GCI data rate. An external pull-up resistor
is needed.

M0 16 23 M0 = 0: GCI mode selection; Time slot Assigner is selected on GCI channel 0.

M0 = 1: GCI in a multiplex mode; S0, S1, S2 pins define the GCI channel
number allocated to ST5421. TES/NT2 selection is done with the configuration
registers (input).

3/29
ST5421

PIN DESCRIPTION (continued)

Name DIP PLCC Description

S2/M1 13 18 S2 if M0 = 1: GCI channel number selection (input).

When M0 = 0 M1 select TEM or NT1 mode: M1 = 0 selects TEM, M1 = 1
selects NT1.

S0/BCL/BUS 14 19 S0 if M0 = 1; GCI channel number selection (input).

BCL in TEM; bit clock output at 768kHz compatible with COMBO families
ETC5054/57.
BUS in NT1; S Bus Configuration Selection: low for fixed timing recovery and
high for adaptive timing recovery (input).

RST 15 22 Reset Pin: must be low at Power On Reset; after, a high pulse on this pin
reset ST5421 in a state depending on the other configuration pins (input).

LSD- 18 26 Line Signal Detect: open drain output, normally high impedance, pulling low
when SID-GCI is powered down and an S line signal is detected.
It is applicable to wake up a microprocessor from a low power idle mode.
-
LSD output goes back to high impedance when ST5421 is powered up.

LO+, LO- 1,2 1,2 Transmit AMI signal differential outputs to the S/T line transformer; when used
with an appropriate 2:1 step down transformer, the line signal conforms to the
output pulse masks in CCITT I.430.

LI-,LI+ 19,20 27,28 Receive AMI signal inputs from the S/T line transformer. They should be
connected to an appropriate 1:2 or 1:1 transformer through a line coupling
circuit to conform I.430 recommendation. LI- pin is also the internal voltage
reference pin.

Table 1: Pin configurations

4/29
 ST5421

NT1, NT2 or TES mode, loss of GCI clocks auto-

FUNCTIONAL DESCRIPTION matically forces the power down state.
POWER ON INITIALIZATION
POWER UP/DOWN STATE
Following initial application of power, SID-GCI en-
ters the power down de-activated state. Following a period of activity in the power up
RST input must be tied low during power-on. state, power down state may be re-entered as
described above. Configuration Registers remain
After Power on reset, all the internal I.430 circuits in their current state. They can be changed by the
including the master oscillator are inactive and in GCI Monitor channel.
a low power state except for the line signal detec-
tion circuit. The power down transition disables analog and
I.430 circuitry, stops the Crystal Oscillator and all
After any period of activity a high pulse on RST the clocks internally generated. Line Signal De-
reset completely SID-GCI. tector Circuit remains active allowing LSD-pin to
Configuration mode programming of SID-GCI is pull low if a receive signal is detected.
done by means of pins polarization and register Power up transition enables all analog and I.430
programming. circuitry, starts the Crystal oscillator and reset the
NT1 and TEM modes are defined only by means state machine to the de-activated state. It also in-
of 2 configuration pins M0, M1 at Power On Re- hibits LSD-output.
set.
For NT2 and TES modes (M0=1), configuration LINE CODING AND FRAME FORMAT
has to be completed by means of a Control In-
struction on Monitor channel prior a Power Up in- For both directions of transmission, Alternate
struction. Mark Inversion (AMI) coding with inverted binary
is used, as illustrated in figure 1.
POWER UP/DOWN CONTROL This coding rule requires that a binary ONE is
represented by a 0 current high impedance out-
When TEM configuration is selected, ST5421 pro- put, whereas a binary ZERO is represented by a
vides GCI Clocks needed for control channel positive or negative-going 100% duty cycle pulse.
transfer. Power Up instruction is directly provided Normally, binary ZEROs alternate in polarity to
by pulling low the Bx data input. SID-GCI then re- maintain a d.c. balanced line signal.
acts sending GCI clocks. LSD- output pin can be
directly connected to Bx data input for providing The frame format used in SID-GCI follows CCITT
an automatic Power up when far-end attempts to reccommendation in I.430 and illustrated in figure
activate. 2. Each complete frame consists of 48 bits, with a
After a period of activity, Power down state is nor- line bit rate of 192kbit/s, giving a frame repetition
mally re-entered by C/I control code DC (1111) rate of 4kHz. A violation of the AMI coding rule is
while ST5421 is sending C/I indication code DP used to indicate a frame boundary, by using a 0+
(0000); then ST5421 send twice C/I indication bit followed by a 0- balance bit to indicate the
code DI(1111) before to power down. start of a frame, and by forcing the first binary
It is possible to force immediately power down zero following the balance bit to be of the same
state by using PDN (0001) C/I control code. polarity as the balance bit.
When NT1 configuration is selected, ST5421 is In the Network Termination (NT) to Terminal
powered up directly by receiving GCI clocks on Equipment (TE) transmission direction, the frame
BCLK and FSa input from the ”U” device. The contains in addition to the 2B+D basic access
only way to power down ST5421 is to stop BCLK data, an echo channel, the E bit, which is used to
or FSa clock signal inputs. retransmit the D bits that are received from the
For example PDN (0001) C/I control code has no TE (s), and three extra channels: FA, M and S bit.
effect. In the TE to NT direction, the frame contains in
When NT2 or TES configuration is selected, SID- addition to the 2B + D data, an extra channel, the
GCI is powered up by the PUP code (0000) on FA bit.
C/I Control Channel. After a period of activity, FA, M and S bits are used to set up a Q multi-
Power down state is normally reentred by C/I con- frame channel in the TE or NT direction, and a S1
trol code DC (1111) while ST5421 is sending C/I multiframe channel from NT to TE. These 800bit/s
indication DI(1111). message oriented channels are structured on the
It is possible to force immediately Power down base of the United States ANSI standard specifi-
state by using PDN (0001) C/I control code. In cation for layer 1 maintenance.

5/29
ST5421

Figure 1: Inverted AMI Line-coding Rule.

Figure 2: Frame Format

LINE TRANSMIT SECTION Overvoltage protection is required externally.

The differential line driver outputs LO+ and LO- Depending on TE or NT selected configuration,
are designed to drive a suitable transformer with 192kbit/s data is transmitted on LO+,LO- by
an external termination resistor. A 2:1 trans- means of clocks respectively locked on the far-
former, results in a signal amplitude of 750mV on end received bit and frame clocks recovered from
the line which meets the I.430 pulse shape for all the line with two bit delay between transmit and
the loads specified. receive frame, or locked with a fixed delay on the
When driving a binary 1 symbol, the output pre- Frame Sync signal received from FSa input.
sents a high impedance in accordance with I.430.
When driving a 0+ or 0- symbol, the voltage lim- LINE RECEIVE SECTION
ited current source is turned on.
The receive input signal should be derived via a
Short protection is included in the output stage. 1:1 a or 1:2 transformer of the same type used for

6/29
 ST5421

the transmit direction. At the front end of the re- In NT2 or PBX line card, GCI interface permits
ceive section is a continuous filter which limits the connection of up to 8 SID-GCI onto a common
noise bandwith. To improve the protection of the serial multiplexed bus. Each SID-GCI is assigned
line interface and to comply with the receive input to one GCI channel selected by hardware con-
impedance specification even if power is lost, it is figuration.
necessary to add 3 external resistors between the
receive transformer and the LI+/LI- pins. Figure 3 shows the Frame structure of a GCI
channel. One GCI channel is structured in four
To correct pulse attenuation and distorsion subchannels:
caused by the transmission line in point-to-point - B1 channel 8 bits
and extended passive bus applications, an adap- - B2 channel 8 bits
tive equalizer enhances the received pulse - Monitor (M) channel 8 bits
shape, thereby restoring a ”flat” channel response - SC channel which is structured as follows:
with maximum eye opening over a wide spread of D channel 2 bits
cable attenuation characteristics. C/I channel 4 bits
This equalizer is always enabled when either TE A bit associated with M channel
or NT mode adaptive sampling is selected, but is E bit associated with M channel
disabled for NT short passive bus applications, B1,B2 and D channels are used to transfer 2B +
when NT mode fixed sampling is selected. D basic access data.
An adaptive threshold circuit maximizes Signal to M channel is used to read and write multiframe
Noise ratio in the eye at the detector for all loop S1 and Q channel messages and to configurate
conditions. SID-GCI. Protocol for byte exchange on the M
A DPLL (Digital Phase-Locked Loop) recovers a channel uses the E and A bits.
low-jitter clock for optimum sampling of the re- C/I (Control/Indicate) channel is used to ex-
ceived symbols. change ”real time” primitives between the SID-
The MCLK input provides the reference clock for GCI and the Controller as Activation/Deactivation
the DPLL at 15.36MHz. codes.
When the device is powered down, a Line Signal
Detect circuit, able to discriminate a valid line sig- Physical Description
nal from noise, is enabled to detect the presence
of incoming data. LSD-output pulls low to wake The interface consists of 4 wires:
up the equipment. Input Data: Bx
Output Data: Br
Bit Clock: BCLK
GCI INTERFACE Frame Synchronization: FSa
General Description Data is synchronized by BCLK and FSa signals.
GCI interface is an European standardized inter- The latter insures reinitialization of a time slot
face to connect ISDN dedicated components in counter at each frame beginning. Its rising edge is
the different configurations of equipment as Ter- the reference for the first bit of the first GCI chan-
minals, Network Terminations, PBX, etc... nel. Data is transmitted in both directions at half
the BCLK frequency, on the rising edge of BCLK
In Terminal Equipments, this interface allows con- and is sampled 1.5 period after the transmit rising
nection between SID-GCI and an associated edge. Unused channels are high impedance.
ST5451 HDLC&GCI Controller used for 16kbit/s
D channel processing and SID-GCI control. In NT2 or PABX equipments, up to 8 GCI chan-
64kbit/s B1 and B2 channels are transferred on nels (32 bits each) may be multiplexed on Bx and
GCI interface providing direct connection for B Br links used as a serial bus for several devices.
channel processing peripherals like Programma- The channel number selection is made by pro-
ble ISDN COMBO ST5080 or extra ST5451 con- gramming pins S0,S1 and S2 according to the fol-
trollers. lowing rules:

S2 S1 S0 Channel Number Timeslots

0 0 0 0 0 -3
0 0 1 1 4-7
0 1 0 2 8 - 11
0 1 1 3 12 - 15
1 0 0 4 16 - 19
1 0 1 5 20 - 23
1 1 0 6 24 - 27
1 1 1 7 28 - 31

7/29
ST5421

Figure 3: GCI Interface Structure

BCLK frequency may be any value between 512 that is recognized by SID-GCI if detected in two
and 6176kHz. consecutive frames.
In TEM and NT1 configurations, the first GCI ST5421 will interpret the new code and send the
channels is automatically selected. corresponding control instructions on the S line or
switch a local function as long as the correspond-
In TEM configuration, due to SID-GCI recovery cir- ing action is required.
cuitry, a low jitter should be provided on FSa and
BCLK clocks. FSa and BCLK are always in phase. An information change received from the S line or
The maximum value of jitter amplitude is a step of a local status change of SID-GCI set a new indi-
65ns at each GCI frame (125µs). The maximum cation code on the C/I channel. The code is sent
high frequency jitter amplitude is 130ns pk-pk. at least in 2 consecutive frames.
For applications such as the network side of an Table 2 gives the C/I codes meaning. C1 bit is first
NT2, eg, a PABX trunk card, TES mode allows transmitted. Here after for each mode a list of rec-
the transmission side of SID-GCI to be a slave to ognized Control and Indicate codes is given.
the received frame timing while GCI is also in
slave mode Elastic buffers which allow any phase
relationship between FSa and I.430 frames and a TEM mode: Control
clock resynchroniser circuit absorb jitter and low
frequency wander up to at least 18µs pk-pk at fre- 0000 (DR) : Deactivation Request
quencies below 10Hz. In the Power Up state, DR instruction can be
used as a Deactivation Request instruction to
force transmission of INFO0 on the S line.
Exchange Protocol on the C/I channel
0001 (PDN) : Power Down Request.
Exchange of information in the C/I channel runs PDN instruction forces the device to the Power
as follows: Down state after that DI (1111) has been sent
Two devices connected on a GCI channel send in two consecutive frames.
each other a permanent four bit command code
in the C/I field. The same code is sent at a 8kHz 0110 (NOP) : No operations.
frequency as long as the content of the internal
C/I register remains unchanged. 1000 (AR8) : Activate Request Class 8.
Note: as for GCI definition, in case that a command AR8 instruction combines an Activation Re-
code has to be executed twice, it is neces- quest, which initiates the Activation Sequence
sary that the device, that is sending the com- on the line, and a request to attempt to access
mands, sends, after the first code, a NOP the transmit D channel in the high priority class
before repeting the command for the second at the S interface after its complete activation.
time. After activation of the S interface, AI8 indication
is sent by ST5421. D channel access attempt is
When a change of C/I the command is initiated
8/29
 ST5421

Table 2: C/I Channel Coding

Code TEM LT/NT2 TES NT1
C1 C2 C3 C4 Ind. Com. Ind. Com. Ind. Com. Ind. Com.
0000 DP DR TIM PUP/DR DP PUP/DR TIM DR
0001 X PDN X PDN X PDN X X
0010 X X X X X X X X
0011 EOM X X X X X X X
0100 EI X EI X EI X EI FI2
0101 X X X X X X X X
0110 X NOP X NOP X NOP X NOP
0111 X X X X X X X X
1000 AP AR8 AP AR AP AR AP AR
1001 CON AR10 X X X X X X
1010 X ARL X ARL X ARL X ARL
1011 X X X X X X X X
1100 AI8 X AI FI4 AI X AI FI4
1101 AI10 X X X X X X X
1110 AIL X AIL X AIL X AIL X
1111 DI DC DI DC DI DC DI DC
(x) codes reserved

automatically processed for each HDLC frame ically the Power Down state if the S line is de-
to be transmitted without need for new Control activated (DP sent by SID-GCI). When S line is
Instruction. not deactivated, DC has no effect.
Except for code EOM, any further indication
change on C/I as CON or EI deactivates D
channel access attempt at the S interface. A TEM mode : Indication
new AR8 instruction is needed to restart the
procedure. 0000 (DP) : Deactivation Pending Indication.
Note : A new AR8 instruction means that if the DP code indicates ST5421 is powered up and
controller was already sending AR8, it has to that no identified signal has been detected on
change first the code sent to ie DC (1111) and the S line. DP indication is sent when one of the
after change again to AR8. following events occur :
- Power Up has been completed and no signal
1001 (AR10) : Activate Request Class 10. is identified on the line,
Same meaning as AR8 command but request- - after a period of activity, INFO0 is detected on
ing access to transmit D channel with low prior- the S line,
ity class. - the device being in status F4, F5, F6, F7 or,
After activation of the S interface has been F8, a DR instruction is issued.
completed, AI10 indication is sent by SID-GCI.
0011 (EOM) : End of Message.
1010 (ARL) : Activate Request Loopback. EOM indicates that the closing flag of a D chan-
ARL instruction operates a loopback of 2B + D nel message has been transmitted on S line in-
channels from Bx input to Br output. It may be dicating successfull completion of a packet
set when the device is either activated, in which sending. EOM is sent continuously until receiv-
case it is transparent (the composite signal is ing of a new AR8 or AR10 command or line
also transmitted to the line), or when it is deacti- status change.
vated in which case it is non transparent. EOM code sending can be disabled via a Moni-
Any change from ARL to another C/I command tor channel instruction EID : (see table 3).
clears the loopback.
When the complete loopback is activated, (AIL) 0100 (EI) : Error Indication.
code is sent by SID-GCI. EI indicates that a frame loss of has been de-
tected on S line ; is sent when one of the follow-
1111 (DC) : Deactivation Control. ing events occur :
DC instruction allows ST5421 to enter automat- - being in the F6 or F7 states, detection of a
loss of frame, (jump to F8).
9/29
ST5421

- being in the F7 state, receiving of INFO2, on the line. It is recommended that an AR be

(jump to F6). delayed at least 2ms after the PUP instruction.
1000 (AP) : Activation Pending. 1010 (ARL) : Activate Request Loopback.
AP indicates that INFO2 (or INFO4) frames Identical to TEM mode.
have been identified on the line.
AP indication is sent when one of the following 1111 (DC) : Deactivation Control.
events occur: DC instruction allows ST5421 to enter automat-
- being in F2 deactivated state, detection of ically the Power Down state if the S line is de-
INFO2 or INFO4. activated (DI sent by SID-GCI). When S line is
- being in the loss framing state F8, detection of not deactivated, DC has no effect.
INFO2

1001 (CON) : Contention Indication TES mode : Indication.

CON is sent when, during transmission of a
packet in the D channel, a received E bit does 0000 (DP) : Deactivation Pending.
not match the last transmitted D bit, indicating a DP code indicates ST5421 has been just pow-
lost collision. ered up and no signal has been identified on
D channel access attempt is deactivated at the the line.
S interface. A new AR8 or AR10 instruction is
needed to restart the procedure. 0100 (EI) : Error Indication.
Identical to TEM mode.
1100 (AI8) : Activation Indication Class 8.
AI8 is sent when, following an AR8 instruction, 1000 (AP) : Activation Pending.
the S line is completely activated (state F7). Identical to TEM mode.
The D channel access procedure is set in the
high priority class 8 (or 9). 1100 (AI) : Activation Indication.
AI is sent when, following an AR instruction, the
1101 (AI10) : Activation Indication Class 10. S line is completely activated in state F7.
AI10 is sent when, following an AR10 instruc-
tion, the S line is completely activated. The D 1110 (AIL) : Activation Indication Loopback.
channel access procedure is set in the low pri- Identical to TEM mode.
ority class 10 (or 11).
1111 (DI) : Deactivation indication.
1110 (AIL) : Activation Indication Loopback. DI indication is sent when one of the following
AIL indicates that the complete loopback re- events occur:
quested by the instruction ARL is completed. - After a period of activity, INFO0 is detected
on the S line,
1111 (DI) : Deactivation Indication. - the device beeing in status F4, F5, F6, F7
DI is sent at least in two consecutive frames when, or F8, DR instructions is issued.
being in the S line deactivated state (DP indication
sent by SID-GCI) DC control instruction is received
on C/I control channel. NT1 mode : Control.
After that, SID-GCI is automatically powered down. 0000 (DR) : Deactivation Request.
DR command forces ST5421 through the ap-
propriate deactivation sequence where INFO0
TES mode : Control. is sent on the line. The device remains in the
0000 (PUP/DR) : Power Up Request/Deactiva- Power Up state. DI indication is sent.
tion Request.
When in Power Down, Power Up instruction 0100 (FI2) : Force Info 2
powers up the device in the configuration pre- Being in the activated state G3, FI2 instruction
viously set. When in Power Up, PUP/DR can be forces the appropriate sequence to send INFO2
used as a Deactivation Request instruction to on the line. If the S line is not completely acti-
force the transmission of INFO0 on the line. vated, FI2 instruction has no effect.

0001 (PDN) : Power Down Request. 0110 (NOP): Some as TEM

PDN instruction forces the device to the Power
Down state. 1000 (AR) : Activation Request.
Being in the inactive Power Up state, sending
0110 (NOP): Some as TEM INFO0, AR instruction forces SID-GCI through
the appropriate sequence to send INFO2 on the
1000 (AR) : Activate Request. line. It is recommended that an AR instruction be
AR instruction initiates the Activation Sequence delayed at least 2ms after setting the GCI clocks.

10/29
 ST5421

recommended that AR instruction is sent after

1010 (ARL): Activate Request Loopback. receiving TIM indication..
Identical to TEM mode. 1010 (ARL) : Activation Request Loopback.
Identical to TEM mode.
1100 (FI4) : Force Info 4.
An activation Request being in progress, FI4 in- 1100 (FI4) : Force Info 4.
struction allows SID-GCI through the appropri- An Activation Request being in progress, FI4 in-
ate sequence to send INFO4 on the line. struction puts ST5421 through the appropriate
sequence to send INFO4 on the line.
1111 (DC) : Deactivation Control.
DC instruction has no effect on SID-GCI. 1111 (DC) : Deactivation Control.
The DC instruction allows to enter the power
down state if the S line is deactivated.
NT1 mode : Indication. DC control has no effect if SID-GCI not sending
0000 (TIM) : Timing Requested. DI indication.
Being in Power down state, the LSD- output is
pulled low to indicate that the far-end is at-
tempting to activate the S interface. The device NT2 mode : Indication.
requests GCI clock signals. Receiving of GCI 0000 (TIM) : Timing Requested.
clocks powers up the SID-GCI, LSD- is freed, Being in Power down state, LSD- output is
and TIM code is sent on the C/I channel. pulled low to indicate that far-end is attempting
to activate the interface. SID-GCI requests GCI
0100 (EI) : Error Indication. clocks followed by a PUP instruction. After re-
EI code indicates that a loss of frame has been ceiving, LSD- is freed and TIM is sent on C/I
detected on the S line, ST5421 being previously channel.
activated.
0100 (EI) : Error Indication.
1000 (AP) : Activation Pending. Identical to NT1 mode.
AP code indicates that INFO1 frames have
been identified of the line. The device is waiting 1000 (AP) : Activation Pending.
for an activate request to send INFO2. Identical to NT1 mode.

1100 (AI) : Activation Indication. 1101 (AI) : Activation Indication.

AI code indicates that the S line is activated. Identical to NT1 mode.
That means it is receiving INFO3.
1110 (AIL) : Activation Indication Loopback.
1111 (DI) : Deactivation Indication. Identical to TEM mode.
DI code indicates S line is completely deacti-
vated: the device can be powered down switch- 1111 (DI) : Deactivation Indication.
ing off GCI clocks. The DI code indicates that the S line is com-
pletely deactivated.
1110 (AIL) : Activation Indication Loopback.
Identical to TEM mode.
EXCHANGE PROTOCOL ON M CHANNEL
Protocol allows a bidirectional transfer of bytes
NT2 mode : Control. between SID-GCI and a Controller (for example
0000 (PUP/DR) Power Up Request/Deactiva- ST5451) with an acknowledgement at each re-
tion Request. ceived byte.
When in Power Down state, PUP code powers
up the device in the NT2 configuration pre- Write cycle.
viously selected. When in Power Up state DR The Controller sends to ST5421 control instruc-
code forces the appropriate deactivation se- tion(s) coded on a single byte. It is possible but
quence where INFO0 is sent on the line. SID- optional to write several control instructions in a
GCI remains in Power Up state. single message. Control instruction bytes are
structured as defined in Table 3.
0001 (PDN) : Power Down Request.
Identical to TES mode. Read cycle.
When a new validated S1 or Q message is re-
0110 (NOP): Some as TEM ceived from the line, the device send a single byte
message as defined in table 4. If a new message
1000 (AR) : Activation Request. is received from the S line before the previous is
After a PUP instruction, AR forces the appropri- acknowledged by the controller end, this new
ate sequence to send INFO2 on the line. It is message is lost.
11/29
ST5421

sender turning E bit from active to inactive state

Exchange protocol. and sending the byte in the same frame. The E bit
The exchange protocol is identical for both direc- is set inactive for one frame only. If it remains in-
tions. active more than one frame, it is an end of mes-
The sender uses E bit to indicate that it is sending sage. The second byte may be transmitted only
a M byte while the receiver uses A bit to acknow- after receiving the pre-acknowledgement of the
ledge the received byte. previous byte (see timing diagram).
When no message is transferred, E bit and A bit The receiver validates the current received byte
are forced to inactive state (i.e. high impedance). as for the first one and then set A bit in the next
two frames first from active to inactive state (pre-
A transmission is initialized by the sender setting acknowledgement) and from inactive to active
E bit in active state and sending the first byte on (acknowledgement). If the receiver cannot vali-
M channel in the same frame. Transmission of a date (the two bytes received are not identical) it
message is allowed only if A bit received has pre-acknowledges normally but let A bit in the in-
been detected inactive in the last two frames. active state in the next frame which indicates an
When the receiver is ready, it validates the re- abort request.
ceived byte internally when it has been detected If a message is aborted, ST5421 sends again the
identical in two consecutive frames. Then, the re- complete message until receiving acknow-
ceiver set first A bit from inactive to active state; it ledgement.
is the pre-acknowledgement, and maintain A bit A received message is acknowledged or aborted
active at least in the following frame, it is the ac- without flow Control.
knowledgement. Figure 4 gives the timing of a write cycle. The
If validation is not possible, the two last bytes re- most significant bit of a Monitor byte is sent first of
ceived not identical, the receiver abort the mes- the M channel. E & A bits are active low and inac-
sage by setting A bit active for one frame only. tive state on Br is high impedance.
A second M byte may be transmitted by the

Figure 4: Monitor messaging

12/29
 ST5421

Table 3: Monitor Channel Instruction

Bit Number
Functions Mnemonic
7 6 5 4 3 2 1 0
Device Mode:
NT Mode Adaptive Sampling (*) NTA 0 0 0 0 0 1 0 0
NT Mode Fixed Sampling NTF 0 0 0 0 0 1 0 1
TE Slave Mode (slave-slave) TES 0 0 0 0 0 1 1 0
Monitoring Mode Activation MMA 0 0 0 1 1 1 1 1
TE Master Mode TEM 0 0 0 0 0 1 1 1
B Channel Configuration:
B Channel Mapped Direct (*) BDIR 0 0 0 0 1 1 0 0
B Channel Exchanged BEX 0 0 0 0 1 1 0 1
B1 Channel Enabled (*) B1E 0 0 0 1 0 1 0 0
B1 Channel Disabled B1D 0 0 0 1 0 1 0 1
B2 Channel Enabled (*) B2E 0 0 0 1 0 1 1 0
B2 Channel Disabled B2D 0 0 0 1 0 1 1 1
End of Messages Indication:
EOM Indication Enabled (*) EIE 0 0 0 1 0 0 0 1
EOM Indication Disabled EID 0 0 0 1 0 0 0 0
Multiframe Processing:
Multiframe Disabled (*) MID 0 0 0 1 0 0 1 1
Multiframe Enabled MIE 0 0 0 1 0 0 1 0
Disable Three Time Checking DIS3X 0 0 1 0 1 0 0 1
Enable Three Time Checking (*) EN3X 0 0 1 0 1 0 0 0
Write Multiframe Message MFT 0 0 1 1 M1 M2 M3 M4
Loopback Test Mode:
Clear All loopbacks (*) CAL 0 0 0 1 1 0 1 1
Loopback B1 on Line Enabled LB1E 0 0 0 1 1 0 0 0
Loopback B2 on Line Enabled LB2E 0 0 0 1 1 0 0 1
Loopback 2B+D Enabled (1) LBS 0 0 0 1 1 0 1 0
Loopback B1 on GCI Enabled LBB1E 0 0 0 1 1 1 0 0
Loopback B2 on GCI Enabled LBB2E 0 0 0 1 1 1 0 1
(1) alternate command instruction to ARL (C/I code); but without any status indication pending.
(*) initial state following Power on initialization

Table 4: Monitor Status Messages

Bit Number
Functions Mnemonic
7 6 5 4 3 2 1 0
Multiframe Receive Register MFR 0 0 1 1 M1 M2 M3 M4

Monitor channel code description: when the device is in a NT equipment connected

Monitor channel code list is given in table 3 and 4. on a passive bus wiring configuration up to ap-
proximately 200 meters in length depending on
Device mode. cable type. In this mode the receiver DPLL is dis-
NTA : NT mode Adaptive sampling. abled and sampling of the received symbols is
In NT mode, adaptive sampling should be se- fixed to enable multiple Terminals (nominally up
lected when the device is an NT equipment con- to 8) to be connected anywhere along the passive
nected on any wiring configuration up to the maxi- bus. Transmit and Receive section is phased
mum specified length for operation. Multiple locked to GCI FSa source.
Terminals, if required, must be grouped within ap- TES : TE mode connected on the T interface.
proximately 50 meters one from each other (de-
pending on cable capacitance as indicated in This mode should be selected when the device is
I.430). Transmit section of SID-GCI is phased used on the T interface side of an NT2 equip-
locked to GCI FSa source. ment. I.430 circuitry operates as in TE mode but
GCI interface is driven by BCLK and FSa sources
providing a slave-slave configuration.
NTF : NT mode fixed sampling.
In NT mode, fixed sampling should be selected Data buffers and a clock resynchronizer enable

13/29
ST5421

the GCI to function with FSa and BCLK jittering

sources. No phase relationship is needed be- Multiframe processing.
tween the line recovered clocks and GCI. MFT/MFR/MIE/MID
A 1536kHz clock signal output phased locked to In the Transmit direction, with the device in TEM
the Recevied line signal is delivered on CLK. or TES mode, data entered in bit positions M1,
CLK output signal is generated only when M2, M3 and M4 of instruction MFT is transmitted
ST5421 if fully activated (state F7) and no clock to the NT in multiframe bit positions Q1, Q2, Q3
signal is detected on that pin by the device during and Q4 respectively. With the device in NT mode,
his own selected GCI channel. data entered in the M bit positions is transmitted
Otherwise CLK output remains high impedance. to the TE in multiframe bit positions S11, S12,
Note: CLK output is activated immediately on the first bit of the B2 S13 and S14 respectively. In the Receive direc-
channel (GCI side) and is deactivated immediately if SID-GCI leaves tion, when the Multiframe receive data buffer re-
F7 state. quires servicing, the MFR (see table 4) status
D channel access Control circuitry is disabled. i.e. message is autonomously sent with M1, M2, M3
D channel data at Bx input is continuously trans- and M4 bits representing Q1, Q2, Q3 and Q4 or
mitted to the line; there is no monitoring of the D S11, S12, S13 and S14 bits received from the
echo channel from the network direction. multiframe respectively.
MMA : Monitoring mode activation. Multiframe Structure and transmission protocol on
When ST5421 is configured in TE mode by the line comply with the ANSI US Standard
means of pins M0, M1, the MMA instruction al- T1.605.1989. ”Basic Access Interface for S and T
lows to receive and activate on INFO3 frames, Reference points - Layer 1 specification”.
while remaining the master of GCI. That configu- Multiframe message exchange can be supported
ration can be used for applications such as moni- by SID-GCI when the line is synchronized : states
toring the outputs of TEs on a passive bus. F6 & F7 in TEM or TES modes and state G3 in
The received 2B+D can then be passively moni- NT modes.
tored (the line transmit LO+,LO- would not be The multiframe channel processing must be en-
connected). abled by an MIE instruction to use these chan-
nels.
TEM : TE Master Mode.
When ST5421 is in TE configuration by means of
pins M0, M1, and in the Monitoring Mode Activa- DIS3X/EN3X
tion by means of the instruction MMA, the TEM When EN3X is set, a new Multiframe message re-
instruction set back SID-GCI in the normal TE ceived from the line is checked and transferred on
Master mode. the M channel when received three times identi-
cal.
When DIS3X is set, Multiframe messages are
transferred tranparently every superframe.
B channels configuration.
BDIR/BEX B1E/B1D B2E/B2D Loopback test modes
BDIR and BEX instructions provide for the ex-
change of data between the B1 and B2 channels. CAL/LBS/LB1E/LB2E/LBB1E/LBB2E
(Note: when enabling a B channel in conjuction LB1E and LB2E instructions turn each individual
with the BEX command, channels is referenced at B channel from the line receive input back to the
the CGI). line transmit output. They may be set separately
When either or both B channels are disabled by or together.
means of the B1D or B2D instruction, binary 1 are LBB1E and LBB2E instructions turn each individ-
transmitted on the line regardless of Bx input ual B channel from GCI input to the GCI output.
while Br output is in high impedance state. When They may be set separately or together.
enabled by means of B1E and B2E instructions, B CAL instruction clears both loopbacks.
channel are transparently transmitted. It is not allowed to set or clear a LB1, LB2, LBB1
or LBB2 loopback while a complete loopback is
set by means of the C/I instruction ARL. LBS can
End of message indication. be used as an alternate command to ARL.
EID/EIE
C/I channel End Of Message code sending can Activation/Deactivation
be enabled with instruction EIE and disabled by In NT configuration :
means of EID.
After Power on initialization, ST5421 can be con-

14/29
 ST5421

figured in NT1 or NT2 mode, by means of pins Activation may be initiated from either end of the
and register programming. In NT1, SID-GCI is loop.
powered up directly by receiving the GCI clocks To operate an activation from the Network,
on BCLK and FSa inputs. In NT2 mode, the de- ST5421 must be first powered up by the appropri-
vice is powered up by means of PUP code on the ate procedure followed at least 2ms later by an
C/I Control channel. AR instruction on the C/I channel. Network timing,
Figure 5: Activation Procedure in GCI mode, NT Selected.

G00 POWER DOWN G01 POWER DOWN

pending far-end activation

IF Line Signal Detected IF Power Up Control SET IF Power Up Control SET

SET LSD- =0 Powers Up Powers Up
JUMP to G01 state SET TIM indicate SET TIM indicate
JUMP to G10 state JUMP to G10 state

G10 POWER UP
de-activated

IF AR Control SET IF INFO0 received & IF INFO0 received IF INFO1 received

SEND INFO2 DC Control SET & DC Control SET & SET AP indicate
JUMP to G2 state NT2 mode selected NT1 mode selected SET INFO0
Powers Down JUMP to G10 JUMP to G11 state
JUMP to G01 state

G11 FAR-END G2 NEAR-END

pending activation pending activation

IF AR Control SET IF DR Control SET IF INFO3 received IF DR Control SET

SEND INFO2 SEND INFO0 SET AI indicate SEND INFO0
JUMP to G2 state SET DI indicate SEND INFO2 SET DI indicate
JUMP to G10 JUMP to G3 JUMP to G10

G3
pending activation

IF INFO3 & IF not INFO3 IF DR Control SET

FI4 Control SET SET EI SEND INFO0
SEND INFO4 SEND INFO2 SET DI indicate
JUMP to G4 JUMP to G2 JUMP to G10

G4 ACTIVATED

IF FI2 Control SET IF loss of frame detected IF DR Control SET

SEND INFO2 or if INFO0 received SEND INFO0
JUMP to G2 SEND INFO2 SET DI indicate
SET EI indicate JUMP to G10
JUMP to G2
D95TL217

15/29
ST5421

FSa, BCLK and MCLK must be present at this U line has lost synchronization and requests
time. When activation is initiated by the far-end, sending of INFO2.
SID-GCI being in the Power Down state, a Line
Signal Detector circuit pulls low LSD- pin, which In TEM or TES configuration :
can be used to wake up the system. A power Up After Power on initialization, ST5421 can be con-
procedure must be then be issued allowing identi- figured in TE or TES power down mode, depend-
fication of received signal ie, INFO1 or INFO2. ing on pins and register configuration setting. In
The appropriate procedure is then followed ac- TEM mode, SID-GCI is powered up by pulling low
cording to I.430. the Bx input. SID-GCI reacts by sending GCI free-
I.430 recommends that 2 Timers should be avail- running clocks. In TES mode, the SID-GCI is
able in an NT. An Activation Request should be powered up by means of the PUP code on the C/I
associated with the start of an external Timer 1 if Control channel.
required. Timer 1 should be stopped when the AI Activation may be initiated from either end of the
indication is generated following successful acti- loop. To operate an activation from the Terminal,
vation. If Timer 1 expires before AI is generated, the device must be first powered up by the appro-
however, Control instruction DR should be written priate procedure followed at least 2ms later by an
to the device to force deactivation. Timer 2 which AR instruction on the C/I channel. When activa-
is specified to prevent unintentional re-activation, tion is initiated by the far-end, SID-GCI being in
is not required since ST5421 can uniquely recog- the Power Down state, a Line Signal Detector Cir-
nize INFO1 frames. cuit pulls low the LSD- pin, which can be used to
Two extra codes are needed for NT1 application: wake up the system. A Power Up procedure must
FI4 indicates to the SID-GCI that the U line is acti- then be issued allowing identification of received
vated and allows completion of activation by signal ie, INFO2. The appropriate procedure is
sending INFO4. FI2 indicates to SID-GCI that the then followed according to I.430.
Figure 6: Activation Procedure in GCI mode, TE Selected

F10 POWER DOWN F11 POWER DOWN

pending far-end activation

IF Bx SET = 0 IF Line Signal Detected IF Bx SET = 0

Powers Up SET LSD- =0 Powers Up
SET DP indicate JUMP to F11 SET DP indicate
JUMP to F2 JUMP to F2

F2 POWER µP
deactivated

IF INFO0 received & IF INFO2 or INFO4 received IF INFO received &

AR(1) Control SET SET AP indicate DC Control SET
SEND INFO1 SEND INFO0 SET DI indicate (TEM only)
JUMP to F4 JUMP to F3 Powers Down
JUMP to F10
F3 FAR-END
pending activation

IF AR(1) Control SET IF INFO2 received & IF INFO4 received &

SEND INFO0 AR(1) Control SET AR(1) Control SET
JUMP to F5 SEND INFO3 SET AI(1) indicate
JUMP to F6 SEND INFO3
JUMP to F7
D95TL218

16/29
 ST5421

Figure 6: Continued

F4 FAR-END
pending activation

IF DR Control SET IF Line Signal Detected

SET DP indicate (TEM only) SEND INFO0
SET DI indicate (TES only) JUMP to F5
SEND INFO0
JUMP to F2

F5 IDENTIFYING
pending activation

IF DR Control SET IF INFO2 received IF INFO4 received

SET DP indicate (TEM only) SEND INFO3 SEND INFO3
SET DI indicate (TES only) JUMP to F6 SET AI(1) indicate
SEND INFO0 JUMP to F7
JUMP to F2
F6 SYNCHRONIZED
pending activation

IF INFO0 received OR IF INFO4 received IF Loss of Frame Detected

DR Control SET SET AI(1) indicate SET EI indicate(*)
SET DP indicate (TEM only)(*) SEND INFO3 SEND INFO0
SET DI indicate (TES only)(*) JUMP to F7 JUMP to F8
SEND INFO0
JUMP to F2

F7 ACTIVATED

IF INFO0 received OR IF INFO2 received IF Loss of Frame Detected

DR Control SET SET AP indicate SET EI indicate(*)
SET DP indicate (TEM only)(*) SEND INFO3 SEND INFO0
SET DI indicate (TES only)(*) JUMP to F6 JUMP to F8
SEND INFO0
JUMP to F2

F8 LOSS FRAMING

IF INFO0 received OR IF INFO2 received IF INFO4 received

DR Control SET SET AP indicate SET AI(1) indicate
SET DP indicate (TEM only)(*) SEND INFO3 SEND INFO3
SET DI indicate (TES only)(*) JUMP to F6 JUMP to F7
SEND INFO0
JUMP to F2
D95TL219
(1) AR means: AR, AR8 or AR10 while AI means: AI, AI8 or AI18
depending on configuration
(*) In these cases, the indications DP, DI and EI are preceded by an AI indication that stays for a period of time ≤1ms

17/29
ST5421

I.430 recommends that a Timer should be avail- must begin as before sending a new AR8 (or
able in a TE. An Activation Request to the SID- AR10) ; it has to change first the code sent (ie DI)
GCI should be associated with the start of an ex- and after change again to AR8. Successful send-
ternal Timer 3 if required.Timer 3 should be ing of a transmit frame is detected when the clos-
stopped when the AI indication is generated fol- ing Flag is transmitted in the D channel. ”1”s are
lowing successful activation. Timer 3 expires be- then transmitted in the following D bit positions.
fore AI, AI8 or AI10 is generated, however, Con- If enabled by the Control Instruction EIE, indica-
trol instruction DR should be written to the device tion EOM is sent to indicate the End of message.
to force de-activation. After sending of a transmit frame successfull, SID
GCI will automatically perform a new D access
D CHANNEL ACCESS IN TEM MODE sequence if it’s still receiving AR8 or AR10 com-
mand on C/I channel, otherwise no D access se-
A controller device requiring to start transmission quence will be done until reception of AR8 or
of a packet on the line should first prepare the AR10 command.
complete message such that the opening Flag is
ready to be shifted accross GCI. A Control In- Any indication change on the C/I channel except
struction AR8 or AR10 will initiate first the Activa- EOM indicates deactivation of the D channel ac-
tion Sequence on the line until activation has cess sequence and a new AR8 (or AR10) is
been completed and then the D channel access needed to restart the procedure.
sequence according to Priority Class 1 (signalling) Note: Users willing to control the D channel ac-
or Priority Class 2 (Data packet) respectively. cess, can use this procedure:
After line activation, AI8 (or AI10) indication is Send AR8 or AR10 until receiving DENx, then re-
sent from SID-GCI. Then, DEN output immedi- move ARx command code and replace it by an
ately enables to prefetch the opening flag from another command (ie DI that is equivalent to a
the controller device into the SID-GCI D channel NOP operation if the device is full_activated). At
buffer. Meanwhile, the Priority Counter checks the end of a D frame EOM Indication is received
that no other TE connected to the S interface is (if EIE is set); when a new D message is pre-
transmitting in the D channel. This is assured by pared an ask for a new D channel access by AR8
counting consecutive ”1”s in the E bit position of or AR10 can be sent.
frames received from the NT and comparing the Users that want to discriminate consecutive D
value with the current priority level as specified by channel access with EOM Indication, are sug-
I.430. If another TE is active in the D channel, gested to remove EOM Indication, between 2 D
DEN pulses are inhibited once the Opening Flag frames, to be able to separate the 2 messages
is in the Transmit buffer to prevent further fetching EOM: With the following method: send AR8
of Transmit data from the Controller until D chan- (AR10) continuously, until receiving EOM Indica-
nel access is achieved. tion, then send ONCE AR8~ [0111] (AR10~
As soon as the required number of consecutive E [0110]) on C/I channel and continue to send the
bit ”1”s has been counted, the leading 0 of the previous code AR8 (AR10); this AR8~ (AR10~) is
opening flag is transmitted in the next D bit posi- a kind of EOM aknowledge: the device detect a
tion to the NT. Then, DEN pulses are re-enabled ’new’ primitive AR8 (AR10), stop EOM Indication
in order to get new D channel bits. No other in- and replace it by AI8 or AI10 if ST5421 is still full
structions are necessary for local flow control be- activated.
tween controller and ST5421. For application with automatic D channel access and
During transmission in the D channel, SID-GCI wanting to change the priority class (8 or 10) for D
continues to compare each E bit with the D bit channel, they can use the following procedure:
previously transmitted before proceeding to send Assuming that the present D frame is priority
the next. In case of mis-match, a contention for class 8 and that the next D frame will be priority
the previous D bit is assumed to have been won class 10, users can change AR8 code to AR10 as
by another TE. Transmission of the current soon as they are sure that the present D frame is
packet therefore ceases and ”1”s are transmitted started, by controlling DENx, anticipating the next
in all following D bit positions. Status indication D messages before the closing flag of the present
CON is sent to the controller on C/I channel. DEN D frame. When the automatic D channel access
output pulses are again inhibited, and D channel will be performed for next D message, the D
access sequence is disabled. channel request will be done with the desired pri-
ority class. (see figure below).
In order to retransmit the lost frame, the controller

18/29
 ST5421

MULTIFRAME MAINTENANCE CHANNELS (S1 should generate an MFR interrupt immediately, or

AND Q WORDS) be stored until 3 consecutive multiframes have
contained the same 4-bit word before a MFR
Each direction of transmission across the S inter- message is generated. Table 5 lists the codes
face includes a low-speed (800 b/s) channel for which are 3-times checked. Note, however, that
loop maintenance accessed via the monitor chan- no other action is taken by the ST5421 in re-
nel of ST5421. A multiframe structure, consisting sponse to received codes (e.g. loop-backs are not
of 20 frames on the S interface, is used to syn- automotically implemented); the external control-
chronize these channels and convey messages ler must take the necessary action. This provides
coded into 4-bit words, see Table 5. One word is the freedom to implement maintenance functions
transmitted downstream (NT-to-TE) in the S1 without constrains from the device, and to utilise
channel, and one word is transmitted upstream the unassigned codes for other functions.
(TE-to-NT) in the Q channel every multiframe. It is possible to disable the checking algorithm by
When the device is in NT mode, the MIE com- setting DIS3X instruction on M channel. There,
mand enables both the transmission of the multi- Multiframe words are transferred transparently on
frame identification algorithm (reversal of the M channel.
FA/N bits every 5th frame and M bit set = 1 every The MID command disables the transmission of
20th frame) and enables the MFR message. The the Multiframe identification algorithm in NT mode
algorithm is present during INFO2 and INFO4 and disables the MFR message in both NT and
frames. In TE modes this command only enables TE modes. Both the MIE and MID commands can
the MFR message since the device will always only be written to the device when it is deacti-
search for and synchronize to the multiframing vated (either powered-up or powered-down). The
identification bits if NT is sending them. In all Multiframe Transmit Register should also be
modes, at the end of each multiframe the re- loaded with the appropriate ”idle” messages, by
ceived 4-bit word is decoded to determine if it means of an MFT instruction, prior to activation.

Table 5: Codes for Q and S1 channel messages

NT to TE TE to NT
Message (1) Received at TE Number of Repetitions Received at NT Number of Repetitions
Before MFR message Before MFR message
S11 S12 S13 S14 (EN3X set) Q1 Q2 Q3 Q4 (EN3X set)
Idle (Normal) 0 0 0 0 3 1 1 1 1 3
Loss-of-Power
1 1 1 1 1 0 0 0 0 1
Indication
STP Pass 0 0 1 0 3 -- -- -- -- --
STF Fail 0 0 0 1 3 -- -- -- -- --
ST Request (3) -- -- -- -- -- 0 0 0 1 3
STI Indication 0 1 1 1 3 -- -- -- -- --
DTSE-IN 1 0 0 0 1 -- -- -- -- --
DTSE-OUT 0 1 0 0 1 -- -- -- -- --
DTSE-IN & OUT 1 1 0 0 1 -- -- -- -- --
LB1 Request -- -- -- -- -- 0 1 1 1 3
LB1/Indication 1 1 0 1 3 -- -- -- -- --
LB2 Request -- -- -- -- -- 1 0 1 1 3
LB2/Indication 1 0 1 1 3 -- -- -- -- --
LB1/2Request (2) -- -- -- -- -- 0 0 1 1 3
LB1/2Indication 1 0 0 1 3 -- -- -- -- --
Loss-of-Received
1 0 1 0 3 -- -- -- -- --
Signal Indication
Unassigned All other codes 1 All other codes 1
Notes:
(1) No autonomous action is taken by ST5421 in response to received messages. Where appropriate, the external controller must respond with
a command or other action.
(2) The code ”0011” will be received by an NT1 when the LB1 and LB2 requests are transmitted by two different TEs (NT2s) on a Passive Bus.
(3) The code ”0001” will be received by an NT1 when ST Request and any other code (except LP) is sent simultaneously by two or more TEs
on a Passive Bus.

19/29
20/29
ST5421

+5V +5V +5V

33pF 15.36MHz 33pF

0.47µF GNDA GND VCC VCCA XTAL XTAL2 GND V CC

MIC1- Rt (*) 2:1
PCKO LO+

MIC1+ FS FSa
0.47µF MCLK BCLK ST5421 Rt (*)
LO-
LS+ DX Bx SID-GCI
+5V
DR Br
LS- DEN
12KΩ 2:1
VFr+ LI+
ST5080
FSC DCL DOUT DIN DEN LSD- M0 M1 LI-
Figure 7: ISDN Telephone Set Application (non isolated)

PIAFE 30pF 12KΩ

VFr-
ST5451
A0 A1 A2 A3 MS
HDLC & GCI CONTROLLER VCC
HOOK
SWITCH
AD0-AD7 CE WR RD ALE INT

DEBOUNCE

KEYPAD MCU NMI

D94TL100B

(*) Rt = 33Ω, Required from ST5421version 5.0

 +5V 15.36MHz

Rt (*) GND VCC

LO+ MCLK OSC
FSa
Rt (*)
LO- ST5421 BCLK
S
LI+ SID-GCI Bx
Br
LI-
M0 S0 S1 S2 LSD-

+5V
+5V

Rt (*) GND VCC FSC DCL DOUT DIN FSC DCL DOUT DIN FSC DCL DOUT DIN FSC DCL DOUT DIN
LO+ MCLK
ST5451 ST5451 ST5451 ST5451
FSa
Rt (*) HDLC CONTROLLER HDLC CONTROLLER HDLC CONTROLLER HDLC CONTROLLER
LO- ST5421 BCLK
S AD0-AD7 CE WR RD ALE INT AD0-AD7 CE WR RD ALE INT AD0-AD7 CE WR RD ALE INT AD0-AD7 CE WR RD ALE INT
LI+ SID-GCI Bx
Figure 8: NT2 Application GCI Compatible

Br
LI-
M0 S0 S1 S2 LSD-

+5V
+5V

Rt (*) GND VCC SWITCHING MATRIX MPU ROM RAM

LO+ MCLK
FSa FSC DCL DOUT DIN
Rt (*)
LO- ST5421 BCLK
T +5V
LI+ SID-GCI Bx
Br 8.192MHz
LI-
M0 S0 S1 S2 CLK LSD-
PDN
+5V DPLL
+5V
FSC DCL

Rt (*) GND VCC

LO+ MCLK
FSa
Rt (*)
LO- ST5421 BCLK
T +5V
LI+ SID-GCI Bx
Br
LI-
M0 S0 S1 S2 CLK LSD-

+5V D94TL101B

(*) Rt = 33Ω, Required from ST5421version 5.0

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ST5421
ST5421

ABSOLUTE MAXIMUM RATINGS

Parameter Value Unit
VCC to GND 7 V
Voltage at Bx, Br VCC + 1 to GND - 1 V
Voltage at any Digital Input (except Bx) VCC + 1 to GND - 1 V
Current at any Digital Input (except Br) ± 50 mA
Current at Lo ± 100 mA
Storage Temperature Range -65 to +150 °C
Lead Temperature (soldering 10s) 300 °C

ELECTRICAL CHARACTERISTICS (unless specified otherwise: VCC = 5V ±5%, TA = 0 °C to 70°C;

typical characteristics are specified at VCC = 5V, TA = 25°C. All signals are referenced to GND).
DIGITAL INTERFACE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL Input Low Voltage All Digital Inputs 0.8 V
VIH Input High Voltage All Digital Inputs 2.2 V
VILX Input Low Voltage MCLK/XTAL input 0.5 V
VIHX Input High Voltage MCLK/XTAL input VCC-0.5 V
VOL Output Low Voltage Br: IL = 3.2 mA
0.4 V
All other Digital Outputs: IL = ±1mA
VOH Output High Voltage Br: IL = 3.2 mA 2.4 V
All other Digital Outputs: IL = ±1mA 2.4 V
IIL Input Low Current Any Digital Input, GND < VIN < VIL -10 +10 µA
IIH Input High Current Any Digital Input, VIH < VIN < VCC -10 +10 µA
IOZ Output Current in HIGH All Digital Tri-state I/Os -10 +10 µA
Impedance (tri-state)

LINE INTERFACE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
R LI Differential Input GND < LI+, LI- < VCC 200 kΩ
Resistance
CLLO Load Capacitance From LO+ to LO- 200 pF
Transmit Pullse Amplitude R1 = 212Ω between LO+ and LO- (1) 1.484 1.585 1.696 Vpk
Transmite Pulse O+ relative to O- 5 %
Unbalance
Input Amplitude Differential Between LI+ and LI- ±175 mV
VOS Differential Offset Voltage Driving Binary 1s, 220Ω between LO+ and -20
20 mV
at LO+, LO- LO-

POWER DISSIPATION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Icc0 Power Down Current All Outputs Open-circuit 900 µA
Iccnt Active Current (2) NT/TES not transmitting 12 13 mA
Iccntt Active Current (3) NT/TES transmitting 21 mA
Iccte Active Current (2) TEM not transmitting 17 18 mA
Icctet Active Current (3) TEM transmitting 26 mA
(1) This specification garanties compliance with CCITT1430 recommendation concerning the pulse templates. Winding resistors for the
transformer is assumed to be represented by an extra 12Ω load added to the 200Ω corresponding to the 50Ω load reflected back through
the 1:2 transformer.
(2) Measured with an external 15.36MHz clock applied on pin XTAL1, XTAL2 being left unconnected.
(3) Same condition as in (2) assuming worst case line current on 50Ω.

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 ST5421

ELECTRICAL CHARACTERISTICS (continued)

MASTERCLOCK
Symbol Parameter Test Conditions Min. Typ. Max. Unit
MCLK Frequency 15.36 MHz
MCLK Frequency -100 100 ppm
Tolerance
MCLK Input Clock Jitter 50 ns
pk-pk
Timing Recovery Jitter BCLK Output Relative to MCLK at TE -130 130 ns
tMH, tML Clock Pulse width High VIH = VCC -0.5V, VIL = 0.5V 20 ns
and Low of MCLK
tMR, tMF Rise Time and Fall Time Used as a logical input 10 ns
of MCLK
TRANSFORMER MODEL (all values are to be measured at 10kHz)
Min. Typ. Max. Unit
1:N Primary to Secondary Turn Ratio 1.98 2 2.02 %
Rp Primary Winding Resistance 2 Ω
Rs Secondary Winding Resistance 4 Ω
R Primary Total Resistance 3 Ω
Lp Primary Inductance 22 30 37.5 mH
Lm Primary Inductance with Secondary Shorted 16 20 mH
Cp Primary Capacitance with Secondary Open 25 pF

Figure 9: Transmit & Receive Transformer Model

Rt (*) 2:1 Lm R

CP LP
Rt (*)
s p
SID LINE
2:1 Lm R

CP LP

s p D94TL139

(*) Rt = 33Ω, Required from ST5421version 5.0

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ST5421

TIMING SPECIFICATIONS
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tDCDE Delay Time BCLK TE Mode only 30 ns
High to DEN
Transition
tHCF Hold Time BCLK 0 ns
Trans. to FSa
Transition
tRC, tFC Rise & Fall Time 15 ns
BCLK
tWCH, BCLK width High & Low 60 ns
tWCL
tSFC Setup Time FSa High to 70 BCLK ns
BCLK Low -50
tDCF Delay Time BCLK TE Mode only 30 ns
High to FSa HIGH
tDCD Delay Time BCLK 20 ns
80
High to DATA Valid
tDFD Delay Time FSa High Load 100pF. Apply only if FSa rises later 80 ns
to Data Valid than BCLK rising edge
tDCZ Delay Time BCLK 50 120 ns
Low Data Invalid
tSDC Setup Time Data 30 ns
Valid to BCLK Low
tHDC Hold Time BCLK Low 20 ns
to Data Invalid
tDCC Delay Time BCLK TE and TES side modes only 0 30 ns
High to CLK High

Figure 10: GCI Mode

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 ST5421

nals on adjacent board layers. Ground traces on

APPLICATIONS INFORMATION either side of the high frequency trace also helps
While the pins of ST5421 SID-GCI device are well isolate the noise pickup.
protected against electrical misuse, it is recom-
mended that the standard CMOS practise of ap-
plying GND to the device before any other con- EXTERNAL OSCILLATOR CONFIGURATION
nections, should always be followed. In An external 5V drive clock sourcxed may be con-
applications where the printed circuit card may be nected to the MCLK (pin 5) input pin of ST5421.
plugged into a hot socket with power and clocks The nominal frequency should be 15.36MHz with
already present, an extra long ground pin on the a tolerance of 1 80ppm. The ST5421 SID pro-
connector should be used. vides a load of about 7pF at the MCLK input pin.
To minimize noise sources, all ground connec-
tions to each device should meet at a common LINE TRANSFORMER REQUIREMENTS
point as close as possible to the GND pin in order
to prevent the interaction of ground return cur- The electrical characteristics of the pulse trans-
rents flowing through a common bus impedance. former for the ISDN ”S” interface are defined to
A power supply decoupling capacitor of 0.15F meet the output and input signal and the line iso-
should be connected from this common point to lation and characteristics as defined in CCITT
VCC as close as possible to the device pins. reccommednation I.430. The transformer pro-
vides isolation for the line card or terminal from
the line it lasi provides a means to transfer power
CRYSTAL OSCILLATOR to the terminalb over the S-loop via the ”phantom”
circuit created by center-tapping the line side
The clock source for ST5421 may be provided windings. A transformer is used both at the trans-
with a commercially available crystal or an exter- mit and the receive end of the loop. These notes
nal clock source meeting the frequency require- specify the tolerances of a transformer that is em-
ments as explained in the following sections. ployed with ST5421 to meet the CCITT recom-
mendation on output pulse mask and impedance
requirements.
CRYSTAL SPECIFICATION
ST5421 SID-GCI clock source may be either a
quartz crystal operating in parallel mode or an ex- LINE TRANSFORMER RATIO
ternal signal source at 15.36MHz. The complete The transmit and th receive transformers can be
oscillator (crystal plus the oscillator circuit) must the same (with a winding ratio of 1:2) or option-
meet a frequency tolerance specification of ally, the receive transformer could have a trans-
±50ppm total to comply with the CCITT I.430 former ratio of 1:1. The primary of the transformer
specification for TE applications.The frequency is connected to the S loop while the secondary is
tolerance limits span the conditions of full operat- connected to the device.
ing temeprature range (commercial or industrial)
and effects due to aging and part parameter vari-
ations. EXTERNAL PROTECTION CIRCUITRY
The crystal is connected between pin 5 Precautions are to be taken to ensure that
(MCLK/XTAL) and pin 6 (XTAL2), with a 33pF to- ST5421 SID-GCI is protected against electrical
tal capacitance from each pin to ground. The ex- surges and other interferences due to electro-
ternal capacitors must be mica or high-Q ceramic magnetic fields, power line faults and lightening
type. The use of NPO (Negative Positive Zero co- discharge that may occur in the transmission me-
efficient) capacitors is highly recommended to en- dium. Protection circuits that are external to the
sure tight tolerance over the operating tempera- device are recommended on both the primary and
ture range. The 33pF capacitance includes the secondary sides of the line transformer.
external capacitor plus any trace and lead capaci-
tance on the board. Nominal frequency of
15.360MHz, frequency tolerance (accuracy, tem- DC BIAS CAPACITORS FOR ANALOG REFER-
perature and aging) less than 1.60ppm, with Rs ENCE
= 150, CL= 20pF, parallel mode, C0 (shunt ca- Two decoupling capacitors (0.1µF mica) and
pacitance) 7pF.An external circuit may be driven 10µF (electrolytic) are connected between pin 19
directly from the pin XTAL2 (pin 6) provided that of the device and its ground connection. These
the load presented is greater than 50K shunted capacitors decouple the midpoint of a two-resistor
by a total of 33pF of capacitance. Crystal oscilla- potential divider (inside the device) and provide
tor board layout is critical and should be designed an internally buffered reference for the analog cir-
with short traces that do not run parallel when in cuitry.
close proximity (to minimize coupling between ad-
jacent pins). On multi-layered boards a ground
layer should be used to prevent coupling from sig-
25/29
ST5421

ST5421 EXCEEDING I.430 TRANSMISSION RE- an adaptive line equalizer to accomodate varying
QUIREMENTS line conditions with superior performance. A con-
tinuously tracking adaptive threshold circuit pro-
This ST5421 is designed with the goal of substan- vides the slicing levels for the detection circuits for
tially exceeding the transmission performance re- correct interpretation of transmission bits even on
quirements as specified in the I.430. This is made long lossy loops. This implementation results in
possible in the ST5421 SID design by employing longer ranges of S interface cables compared to
superior analog front end designs. For example, I.430 requirements.
in the receive path, an analog prefiter removes
<200kHz noise signals, which is then followed by

The version 4.1 of the ST5431 has shown ESD weakness on LO+ and LO- pins: these pins only up to 400V. All other pins are passing
SGS-THOMSON Internal Quality Standards (2k volts; Human body model; mil. std. 883 meth. 3015).

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 ST5421

DIP20 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

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ST5421

PLCC28 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 12.32 12.57 0.485 0.495

B 11.43 11.58 0.450 0.456

D 4.2 4.57 0.165 0.180

D1 2.29 3.04 0.090 0.120

D2 0.51 0.020

E 9.91 10.92 0.390 0.430

e 1.27 0.050

e3 7.62 0.300

F 0.46 0.018

F1 0.71 0.028

G 0.101 0.004

M 1.24 0.049

M1 1.143 0.045

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 ST5421

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.

 1995 SGS-THOMSON Microelectronics - All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

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