LMV111 Operational Amplifier With Bias Network: General Description Features

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LMV111 Operational Amplifier with Bias Network

December 1999

LMV111
Operational Amplifier with Bias Network
General Description Features
The LMV111 integrates a rail-to-rail op amp with a V+/2 bias (For 5V Supply, Typical Unless Otherwise Noted)
circuit into one ultra tiny package, SC70-5 or SOT23-5. The
core op amp of the LMV111 is an LMV321, which provides n Resistor ratio matching 1% (typ)
rail-to-rail output swing, excellent speed-power ratio, 1MHz n Space saving package SC70-5 & SOT23-5
bandwidth, and 1V/µs of slew rate with low supply current. n Industrial temp. range −40˚C to +85˚C
The LMV111 reduces external component count. It is a cost n Low supply current 130µA
effective solution for applications where low voltage opera-
n Gain-bandwidth product 1MHz
tion, low power consumption, space saving, and reliable per-
formance are needed. It enables the design of small portable n Rail-to-Rail output swing
electronic devices, and allows the designer to place the de- n Guaranteed 2.7V and 5V performance
vice closer to the signal source to reduce noise pickup and
increase signal integrity.
Applications
n General purpose portable devices
n Active filters
n Mobile communications
n Battery powered electronics
n Microphone preamplifiers

Connection Diagrams

DS101262-21

© 1999 National Semiconductor Corporation DS101262 www.national.com


LMV111
Connection Diagrams (Continued)

5-Pin SC70-5 5-Pin SOT23-5


(M7) (M5)

DS101262-19

Top View
DS101262-20

Top View

Ordering Information
Package Part Number Marking Transport Media NSC Drawing
LMV111M7 1k Units Tape and Reel
SC70-5 A42 MAA05A
LMV111M7X 3k Units Tape and Reel
LMV111M5 1k Units Tape and Reel
SOT23-5 A37A MA05B
LMV111M5X 3k Units Tape and Reel

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LMV111
Absolute Maximum Ratings (Note 1) Junction Temp. (TJ max) (Note 5) 150˚C
If Military/Aerospace specified devices are required, Mounting Temperature
please contact the National Semiconductor Sales Office/ Infrared or Convection (20 sec) 235˚C
Distributors for availability and specifications.
ESD Tolerance (Note 2) Operating Ratings (Note 1)
Machine Model 200V Supply Voltage 2.7V to 5.0V
Human Body Model 1500V Temperature Range −40˚C ≤ TJ ≤ 85˚C
Supply Voltage (V+–V −) 5.5V Thermal Resistance (θJA)
+
Output Short Circuit to V (Note 3) 5-pin SC70-5 478˚C/W

Output Short Circuit to V (Note 4) 5-pin SOT23-5 265˚C/W
Storage Temp. Range −65˚C to 150˚C

2.7V Electrical Characteristics


Unless otherwise specified, all limits guaranteed for T J = 25˚C, V+ = 2.7V, V− = 0V, VO = V+/2 and RL > 1 MΩ. Boldface lim-
its apply at the temperature extremes.
Typ Limit
Symbol Parameter Conditions Units
(Note 6) (Note 7)
VO Output Swing RL = 10kΩ to 1.35V V+ −0.01 V+ −0.1 V
min
0.06 0.18 V
max
IS Supply Current 80 170 µA
max
Resistor Ratio Matching 1 %
GBWP Gain-Bandwidth Product CL = 200pF 1 MHz
Φm Phase Margin 60 Deg
Gm Gain Margin 10 dB

5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T J = 25˚C, V+ = 5V, V− = 0V, VO = V+/2 and RL > 1 MΩ. Boldface limits
apply at the temperature extremes.
Typ Limit
Symbol Parameter Conditions Units
(Note 6) (Note 7)
+ +
VO Output Swing RL = 2kΩ to 2.5V V −0.04 V −0.3 V
V+ −0.4 min
0.12 0.3 V
0.4 max
RL = 10kΩ to 2.5V V+ −0.01 V+ −0.1 V
V+ −0.2 min
0.065 0.18 V
0.28 max
IO Output Current Sourcing, VO = OV 60 5 mA
min
Sinking, VO = 5V 160 10 mA
min
IS Supply Current 130 250 µA
350 max
Resistor Ratio Matching 1 %
GBWP Gain-Bandwidth Product CL = 200pF 1 MHz
φm Phase Margin 60 Deg
Gm Gain Margin 10 dB
SR Slew Rate (Note 8) 1 V/µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω in series with 100pF.

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LMV111
5V Electrical Characteristics (Continued)
Note 3: Shorting circuit output to V+ will adversely affect reliability.
Note 4: Shorting circuit output to V - will adversely affect reliability.
Note 5: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
P D = (TJ(max)–TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 6: Typical values represent the most likely parametric norm.
Note 7: All limits are guaranteed by testing or statistical analysis.
Note 8: Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.

Typical Performance Characteristics (Unless otherwise specified, VS = +5V, single supply, TA =


25˚C.)

Supply Current vs. Sourcing Current vs. Sourcing Current vs.


Supply Voltage Output Voltage Output Voltage

DS101262-1
DS101262-2 DS101262-3

Sinking Current vs. Sinking Current vs. Open Loop Frequency vs.
Output Voltage Output Voltage Response

DS101262-4 DS101262-5 DS101262-6

Open Loop Frequency vs. Open Loop Frequency Gain and Phase vs.
Response Response vs. Temperature Capacitive Load

DS101262-7 DS101262-8 DS101262-9

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LMV111
Typical Performance Characteristics (Unless otherwise specified, VS = +5V, single supply, TA =
25˚C.) (Continued)

Gain and Phase vs. Slew Rate vs. Non-Inverting Large Signal Pulse
Capacitive Load Supply Voltage Response

DS101262-10 DS101262-11 DS101262-12

Non-Inverting Small Signal Pulse Inverting Large Signal Pulse Inverting Small Signal Pulse
Response Response Response

DS101262-13 DS101262-14 DS101262-15

Open Loop Output Short Circuit Current vs. Short Circuit Current vs.
Impedance vs. Frequency Temperature (Sinking) Temperature (Sourcing)

DS101262-16
DS101262-17 DS101262-18

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LMV111
Typical Performance Characteristics (Unless otherwise specified, VS = +5V, single supply, TA =
25˚C.) (Continued)

Output Voltage Swing vs.


Supply Voltage

DS101262-22

Application Section
The LMV111 integrates a rail-to-rail op amp and a V +/2 bias
circuit into one ultra tiny package. With its small footprint and
reduced component count for bias network, it enables the
design of smaller portable electronic products, such as cellu-
lar phones, pagers, PDAs, PCMCIA cards, etc. In addition,
the integration solution minimizes printed circuit board stray
capacitance, and reduces the complexity of circuit design.
The core op amp of this family is National’s LMV321.
1.0 Supply Bypassing
The application circuits in this datasheet do not show the
power supply connections and the associated bypass ca-
pacitors for simplification. When the circuits are built, it is al-
ways required to have bypass capacitors. Ceramic disc ca-
pacitors (0.1µF) or solid tantalum (1µF) with short leads, and
located close to the IC are usually necessary to prevent in-
terstage coupling through the power supply internal imped- DS101262-23

ance. Inadequate bypassing will manifest itself by a low fre- FIGURE 1. Resistive Isolation of a Heavy Capacitive
quency oscillation or by high frequency instabilities. Load
Sometimes, a 10µF (or larger) capacitor is used to absorb
low frequency variations and a smaller 0.1µF disc is paral- The isolation resistor Riso and the CL form a pole to increase
leled across it to prevent any high frequency feedback stability by adding more phase margin to the overall system.
through the power supply lines. The desired performance depends on the value of Riso. A
2.0 Input Voltage Range 50Ω to 100Ω isolation resistor is recommended for initial
evaluation. The bigger the Riso resistor value, the more
The input voltage should be within the supply rails. The ESD
stable VOUT will be.
protection circuitry at the input of the device includes a diode
between the input pin and the negative supply pin. Driving
the input more than 0.6V (at 25˚C) beyond the negative sup-
ply will turn on the diode and cause signal distortions.
3.0 Capacitive Load Tolerance
The LMV111 can directly drive 200pF capacitive load with
unity gain without oscillation. The unity-gain follower is the
most sensitive configuration to capacitive loading. Direct ca-
pacitive loading reduces the phase margin of amplifiers. The
combination of the amplifier’s output impedance and the ca-
pacitive load induces phase lag. This results in either an un-
derdamped pulse or oscillation. To drive a heavier capacitive
load, a resistive isolation can be used as shown in Figure 1.

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LMV111
Application Section (Continued)

4.0 Phase Inverting AC Amplifier


A single supply phase inverting AC amplifier is shown in Fig-
ure 2. The output voltage is biased at mid-supply, and AC in-
put signal is amplified by (R2/R 1). Capacitor CIN acts as an
input AC coupling capacitor to block DC potentials. A capaci-
tor of 0.1µF or larger can be used. The output of the LMV111
can swing rail-to-rail. To avoid output distortion, the
peak-to-peak amplitude of the input AC signal should be less
than VCC(R1/R2).
It is recommended that a small-valued capacitor is used
across the feedback resistor R2 to eliminate stability prob-
lems, prevent peaking of the response, and limit the band-
width of the circuit. This can also help to reduce high fre-
quency noise and some other interference.

DS101262-25

FIGURE 3. Fixed Current Source

6.0 Difference Amplifier


The difference amplifier allows the subtraction of two volt-
ages or, as a special case, the cancellation of a signal com-
mon to two inputs. It is useful as a computational amplifier, in
making a differential to single-ended conversion or in reject-
ing a common mode signal.

DS101262-24

FIGURE 2. Phase Inverting AC Amplifier

5.0 Fixed Current Source


A multiple fixed current source is show in Figure 3. A refer-
ence voltage (VREF = 2.5V) is established across resistor R3
by the voltage divider (R 3 and R4). Negative feedback is
used to cause the voltage drop across R1 to be equal to
VREF. This controls the emitter current of transistor Q1 and if
we neglect the base current of Q1 and Q2, essentially this
same current is available out of the collector of Q1. A Dar-
lington connection can be used to reduce errors due to the
DS101262-26
bias current of Q1.
FIGURE 4. Difference Amplifier

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LMV111
Physical Dimensions inches (millimeters) unless otherwise noted

5-Pin SC70-5 Tape and Reel


Order Numbers LMV111M7 and LMV111M7X
NS Package Number MAA05A

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LMV111 Operational Amplifier with Bias Network
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

5-Pin SOT23-5 Tape and Reel


Order Numbers LMV111M5 and LMV111M5X
NS Package Number MA05B

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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
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accordance with instructions for use provided in the safety or effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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This file is the datasheet for the following electronic components:

LMV111M7X - http://www.ti.com/product/lmv111m7x?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M7 - http://www.ti.com/product/lmv111m7?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M5X - http://www.ti.com/product/lmv111m5x?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M5 - http://www.ti.com/product/lmv111m5?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M7 - http://www.ti.com/product/lmv111m7?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M7X - http://www.ti.com/product/lmv111m7x?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M5 - http://www.ti.com/product/lmv111m5?HQS=TI-null-null-dscatalog-df-pf-null-wwe

LMV111M5X - http://www.ti.com/product/lmv111m5x?HQS=TI-null-null-dscatalog-df-pf-null-wwe

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