Design of High Gain LNA Using 180nm CMOS For Wearable Devices Network

8 IX September 2020
https://doi.org/10.22214/ijraset.2020.31566
International Journal for Research in Applied Science & Engineering Technology (IJRASET)
ISSN: 2321-9653; IC Value: 45.98; SJ Impact Factor: 7.429
Volume 8 Issue IX Sep 2020- Available at www.ijraset.com
Design of High gain LNA using 180nm CMOS for

Wearable Devices Network
M. Shaieena Bhanu1, S. Suvitha2, J. M. Mathana3
1
PG Scholar, Department of ECE, S.A. Engineering College, Chennai, Tamilnadu
2
Assistant Professor, Department of ECE, S.A. Engineering College, Chennai, Tamilnadu,
3
Professor, Department of ECE, Chennai Institute of Technology, Chennai, Tamilnadu,
Abstract: Low Noise Amplifier is the very importance block in any receiver front end. This paper presents the design of a Low
Noise Amplifier (LNA) operating at 2.4 GHz for wearable devices for Wireless Body Area Network (WBAN) using 0.18 um
CMOS technology. The proposed circuit is a single stage low noise amplifier based on the inductive source degeneration
topology for achieving best impedance matching and stability. The cascade design of CMOS is used to achieve high gain of
22.904 dB and very low noise figure of 0.814 dB. The proposed LNAs is made to operate with supply voltage of 1.8 V. The
designed circuit and results are simulated using Advanced Design System (ADS) software by tuning some library files and LNA
parameters.
Keywords: ADS, CMOS, Inductive source degeneration, Low noise amplifier, WBAN
I. INTRODUCTION
The wearable devices are vital wireless application of a micro-lightweight device to be easily wore. Wearing a device for example
smart watches, tracking devices, VR glasses not only entertain, but check and analyze physical conditions, providing users such as
footprints, burning calories, blood pressure info to improve their life quality. A body area network (BAN), also referred to as
a wireless body area network (WBAN) or a body sensor network (BSN) or a medical body area network (MBAN), is a wireless
network of wearable computing devices. Wearable devices may be embedded inside the body, implants, may be surface-mounted on
the body in a fixed position. The IEEE 802.15.6 standard supports 2.4 GHz band for RF transceiver of wearable sensors.
The existing design of LNA for wearable sensor network is designed using 40nm CMOS technology using current reuse technique
but it has resulted in high noise figure with moderate gain [1] Hence the proposed LNA is designed with the aim of achieving
improved gain and low noise figure with low voltage supply. The description of this paper is depicted as follows. In Section II, the
proposed LNA is explained and analyzed. The simulation results of the LNA are presented in Section III. The conclusion details and
performance comparison between the proposed Low Noise Amplifier and some previously designed Low Noise Amplifiers is
tabulated and analysed in Section IV.
II. DESIGNED LNA
A. Topology Analysis
There are different LNA topologies such as Resistive Termination, Series Shunt Feedback, Common gate termination, Inductor
degeneration, common gate, common source, cascade and current reuse topology etc. The analysis of the advantages and
disadvantages of all the topologies leads to the conclusion that the most preferable topology for LNA design is the common source
topology as it can produce high gain which is the main performance parameter for the LNA. By implementing the inductive source
degeneration, the best performance LNA for narrowband applications can be designed. The main advantages of inductive source
degeneration LNA are low Noise Figure (NF), high stability, linearity and low power consumption. The main disadvantage of this
topology is that the poor isolation than other topologies. It is seen that cascode design can provide good isolation. Hence cascode
inductor source degeneration is chosen for designing the proposed LNA.
B. Conventional LNA
In the inductively source degenerated cascode LNA, Ls adds a real part to the input impedance, while (Lg+Ls) resonates with Cgs
(gate-source capacitance) of M] to provide impedance matching at the operating frequency. Ideally, Ls adds no noise to the system,
making this input matching method highly attractive. In order to increase the gain the Ls value should be lesser than 0.1 nH which is
difficult to be implemented on chip Hence capacitance Cgs is used to increase the Source Degenerated inductor value. The input
impedance of the LNA is well known to be
Zin= (1/(jωCgs)) || (jω (Lg+Ls )) || (gm*Ls/Cgs) (1)
©IJRASET: All Rights are Reserved 695

By using the below formula we can achieve the input impedance matching to 50 Ohms.
gm*Ls/Cgs = 50 (2)
Fig 1: Schematic diagram of proposed Low Noise Amplifier
Fig 2: Input and Output Matching Circuits
C. Proposed LNA Architecture

Based on the above topology analysis and considering our application to be Wearable devices Network. The proposed LNA design
uses the inductively degenerated LNA architecture .The cascode structure also helps to obtain higher input-output isolation and
high gain .The circuit is made to operate with supply 1.8V . Mosfet M1 of the common-source stage and M2 of the cascode stage
are given the proper biasing voltages.
Table 1: Important circuit components of proposed LNA

Circuit Components Values
MOSFET-1 360µm/0.18µm
MOSFET-2 85µm/0.18µm
Lg 2.56nH
Ld 1nH
C7 1pF

D. Impedance Matching circuits

Though minimum noise figure is obtained by the proposed LNA’s common-source cascade topology, the input matching of this
configuration is not suitable. Hence the circuit made up of L1, L2 and C1 has been used at the input stage of the amplifier for input
matching which in turn has reduced the input reflection coefficient (S11-input return loss ). Similarly, in order to ensure the
maximum power is transferred to the load, the input and output impedance matching is required. Hence an output matching circuit
composed of C2 and C3 is used at the output.
Zin=(jωL1) || (jωL2) ||( 1/jωC1) (3)
Zout=(1/jωC2)||(1/jωC3) (4)
III. SIMULATION RESULTS

A. LNA Gain, Return Loss and other S parameters
The designed LNA with cascode design of common source MOSFET helps in achieving high gain of 22.904dB at 2.4GHz
frequency. The amplifier gain of the designed LNA is shown in fig.3. By using the input matching circuit, the input impedance
approximated to 50 Ω is achieved. The cascode topology helps to enhance the power gain and the reverse isolation of the amplifier.
The input reflection coefficient (S11) is -15.393 dB at 2.4 GHz. The output port voltage reflection coefficient (S22) and the reverse
isolation (S12) obtained is -12.168 dB and-36.576 dB
.
Fig 3: Gain of the LNA
Fig 4: Return Loss of the LNA
Fig 5: LNA S-Parameters S22 and S12

B. Noise Figure
Noise figure (NF) gives the measure of reduction of the signal to noise ratio (SNR) during the amplification of the input signal. It is
proposed that a good LNA must have very low noise figure value in the range of 0 to 3dB and the minimum noise figure should be
lesser than 1.The NF curve shows that the noise figure and minimum noise figure achieved is 0.814 dB and 0.611 dB respectively.
The NF plot of the designed LNA is shown in fig 6.
Fig 6: Noise Figure of the LNA

C. Stability factor
For any amplifier the very important property is that it should be stable in its operating range which is defined by the Stability factor
K for the LNA. A stable LNA should have K value greater than 1. The K value of designed LNA is 2.274 which is depicted in fig 7.
The stability factor can be found using the below formula
K = (1+|Δ|2-|S11|2-|S22|2)/(2|S21||S12|) (6)
Δ = S11S22 – S21S12 (7)
Fig 7: Stability Factor of LNA
IV. CONCLUSION
In this paper, a high gain low noise amplifier is designed for the application of wearable devices network operating at 2.4 GHz using
180nm CMOS technology. The proposed high gain LNA is designed using inductive degeneration topology and cascade of
MOSFET. Tuning is also performed in the proposed circuit in order to achieve the high gain. At 2.4 GHz the designed LNA can
provide gain of 22.904 dB along with very low noise figure of 0.814 dB. Thus the designed LNA meets the trade off between gain
and noise figure in such a way that both requirement is met. The input and output matching circuits are added to the circuit to
achieve proper impedance matching. The designed LNA is supplied with supply voltage of 1.8V. The return losses and reverse
isolation meets the LNA specifications for wearable devices network. In summary, the designed LNA provides the high gain with
low noise figure and proves to be an unconditionally stable low noise amplifier. The performance comparison between the proposed
Low Noise Amplifiers and some previously designed Low Noise Amplifiers is tabulated in table 2.

Table 2 : Performance Comparison with Existing Low Noise Amplifie

Reference Frequenc CMOS Supply Voltage Amplifier Noise Figure Return Loss
y (GHz) Technology Vdd (V) Gain S21 (dB) (dB) S11 (dB)
(nm)
[2] 2.4 180nm CMOS 1.8 12.68 3.14 -13.5
[3] 2.4 180nm CMOS 1.8 14.55 1.209 -14.15
[5] 2.4 180nm CMOS 1.8 14.7 4.8 -18
[8] 2.4 180nm CMOS 1.8 4.5 2.77 -15.6
[9] 2.4 180nm CMOS 1.8 16.6 2.14 -15.3
[Proposed 2.4 180nm CMOS 1.8 22.904 0.814 -15.393
Work]
REFERENCES
[1] Ehsan Kargaran, Danilo , Manstretta and RinaldoCastello “Design and Analysis of 2.4 GHz 30 microWatt CMOSLNAs for Wearable WSN Applications”,
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 3, MARCH 2018
[2] Nandini Shrivastava and Rajesh Khatri "Design of a 2.4-GHz Differential Low Noise Amplifier using 180nm technology" Proceeding International conference
on Recent Innovations is Signal Processing and Embedded Systems (RISE -2017) 27-29 October,2017
[3] Santosh B. Patil and Rajendra D. Kanphade“Differential Input Differential Output Low Power High Gain LNA for 2.4 GHz Applications Using TSMC 180nm
CMOS RF Process”,2015 International Conference on Computing Communication Control and Automation.
[4] Aditi and MaltiBansal “High linearity and low noise shunt resistive feedback CMOSLNA in 2.4GHz ISM band” ,2017 Recent Developments in Control,
Automation & Power Engineering (RDCAPE)
[5] Zhiqun Li, Zengqi Wang, Meng Zhang, Liang Chen, Chenjian Wu, and Zhigong Wang “A 2.4 GHz Ultra-Low-Power Current-Reuse CG-LNA With Active
Gm-Boosting Technique”, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 24, NO. 5, MAY 2014
[6] Wang Wen-qi ; Xu Liang ; Tang Xue-feng ; Zhan Fu-chun “A fully integrated 2.4GHz 0.25/spl mu/m CMOS low noise amplifier“ , Asia-Pacific Microwave
Conference Proceedings 2005
[7] Baoyong Chi, Bingxue Shi “A 1.8V 2.4GHZ CMOS ON-CHIP IMPEDANCE MATCHING LOW NOISE AMPLIFIER FOR WLAN
APPLICATIONS”, 2003 IEEE International Symposium on Circuits and Systems (ISCAS)
[8] Yu Shen , Huazhong Yang and RongLuo “A fully integrated 0.18-/spl mu/m CMOS low noise amplifier for 2.4-GHz applications“ , 2005 6th International
Conference on ASIC
[9] S. Radha and Jisha Mathew " Linearization Of Low Noise Amplifier For Wireless Sensor Networks " 2017 International Conference on Inventive Systems and
Control (ICISC),978-1-5090-4715-4/17/$31.00 ©2017 IEEE
[10] Wang Wenqi, et al., "CMOS RFIC for Wireless Communication Applications", Journal of Microwaves vol.17 Supplement,No.5,pp.28-32,Dec. 2001.
[11] J. Masuch and M. Delgado-Restituto, “A 1.1-mW-RX -81.4-dBm sensitivity CMOS transceiver for Bluetooth low energy,” IEEE Trans. Microw.TheoryTechn.,
vol. 61, no. 4, pp. 1660–1673, Apr. 2013
[12] Z. Li, L. Chen, and H. Zhang, “Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application,” Journal of Semiconductors, Vol.
32, N. 10, 2011.
[13] SrinivasJagarapu and R.K. Kavitha,"A 2.4 Ghz Low Noise Amplifier in0.18um CMOS Technology,” International Conference on VLSI,Communication &
Instrumentation (ICVCI) 2011, Proceedingspublished by International Journal of Computer Applications® (IJCA)
[14] Suvitha.S & Mathan JM 2018,”A Novel Automated MOALO Algorithm aided RF Low-Noise Amplifier Design for Wireless Applications”, Concurrency and
Computation: Practice and Experience, Wiley- Blackwell, DOI: 10.1002/cpe.4915 (ANNEXURE I, ISSN: 1532-0626)

Design of High Gain LNA Using 180nm CMOS For Wearable Devices Network

Uploaded by

Copyright:

Available Formats

Design of High Gain LNA Using 180nm CMOS For Wearable Devices Network

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Design of High Gain LNA Using 180nm CMOS For Wearable Devices Network

Uploaded by

Copyright:

Available Formats

8 IX September 2020

Design of High gain LNA using 180nm CMOS for

©IJRASET: All Rights are Reserved 695

Fig 1: Schematic diagram of proposed Low Noise Amplifier

Fig 2: Input and Output Matching Circuits

C. Proposed LNA Architecture

Table 1: Important circuit components of proposed LNA

©IJRASET: All Rights are Reserved 696

D. Impedance Matching circuits

III. SIMULATION RESULTS

Fig 4: Return Loss of the LNA

Fig 5: LNA S-Parameters S22 and S12

©IJRASET: All Rights are Reserved 697

Fig 6: Noise Figure of the LNA

Fig 7: Stability Factor of LNA

©IJRASET: All Rights are Reserved 698

Table 2 : Performance Comparison with Existing Low Noise Amplifie

©IJRASET: All Rights are Reserved 699

You might also like