MOSFET review

and
Short channel effects in FETs
With current channel lengths of
120/45 nm and industry pushing
towards 32 nm, classical approaches
to describe the functioning of the
devices are not good enough.

Outline

Some history

Basic transport equations

MOSFET theory – review

Currents derived from the inversion charge QI

Expression for the threshold voltage

Why downscale the MOSFET?

Short channel effects

Other parameters that influence the behaviour

1
Timeline
1930 1940 1950 1960 1970

1928: Lilienfield – MOSFET patent

1948: Shockley, Bardeen, Brattain – BJT

1960: Kahng, Atalla – Si MOSFET

1962: Wanlass, Sah, Moore – CMOS

1964: Fairchild / RCA – 1st commercial

MOSFETs

1968: Noyce & Moore found Intel

1971: 1st microprocessor,

intel4004

Timeline
1930 1940 1950 1960 1970 2000

1928: Lilienfield – MOSET patent

1948: Shockley, Bardeen, Brattain – BJT

1960: Kahng, Atalla – Si MOSFET

1962: Wanlass, Sah, Moore – CMOS

2000: Nobel Prize for Physics
1964: Fairchild / RCA – 1st commercial
Jack S. Kilby – integrated circuit MOSFETs

Z. I. Alferov, H. Kroemer – 1968: Noyce & Moore found Intel

semiconductor heterostructures
1971: 1st microprocessor,
intel4004

2
Remember definitions:

Drift current Diffusion current

dn( x )
J n ( x ) = eµ n n( x ) E ( x ) + eDn
dx
dp( x)
J p ( x ) = eµ p p( x) E ( x) − eD p
dx
J tot = J n + J p

Relationship between the carrier distribution and the

electric field is given by the Poisson equation. Here
given in 1D.

d
ε ( x ) E ( x ) = qρ ( x )
dx
d
dx
ε ( x)
dV ( x)
dx
(
= e ND +
( x) − N A− ( x) + p( x) − n( x) )

3
 3rd fundamental relationship is:

Carrier neutrality

4rd fundamental relationship is:

Normal component of the electrical displacement is

continuous across an interface. D=εE

When confinement occurs:

Schrödinger equation has to be added and energy levels

can not be regarded as continuous.

Ideal MOSFET review

Source Gate Drain

SiO2
n+ n+
p-Si

pn junction
Bulk (substrate)
np junction

4
 MOSFET control of gate

SiO2
n+ n+
p-Si

Take cross section through gate, oxide,

bulk perpendicular to channel and draw
the energy band diagram for different
gate-source voltages.

Inversion region
φm=φs Depletion region
Inversion
hh+++
VGSV>0
GS M O n h p-Si

ddeplmax
Ecox

Ecs equilibrium
Depleting
V > Vth p-Si
GS =
Inversion
Onset of inversion
E
EF
EFm
Fm
EFm Evs
EFm

Evox
MOSFET control of gate

5
 Field effect
• Channel is NOT created by injection of carriers
via the 3rd contact but is created by the attraction-
repulsion of charges via an electric field
• Control of enhancement and depletion of the
carriers in the channel via capacitive effect
• Current through 3rd contact very very small
IG≈0.

MOSFET control of gate:

enhancement mode n-channel MOSFET

VDS =0 VDS =0 VDS =0

V <V V =V V >V
G GS th G GS th G GS th
S D S D S D
S D S D S D

No channel Channel being formed Channel exists

6
 Currents: apply VDS

MOSFET schematic cross section – low VDS

VGS>VT

Linear region or triode region

for 1 VGS value

MOSFET schematic cross section – VDS<VDsat

Non-linear current region.

Channel gets narrower near drain
Depletion region increases as reverse bias between
drain and bulk increases.

7
MOSFET schematic cross section – VDS=VDsat

Constant current region.

MOSFET schematic cross section – VDS>VDsat

8
 Gradual channel approximation
drift current only
Valid for
low longitudinal electric fields
strong inversion VGS>Vth
dV
I = −eµ n( x) A
dx
e × n( x) = Cox (VGS − Vth − V ( x) )

µCoxW  V2 
I DS =  (VGS − VT )VDS − DS 
L  2 
 
µCoxW
lin
I DS = ((VGS − VT )VDS ) linear region
L
µCoxW
I DS = (VGS − VT )2 saturation region
2L

Charge sheet model

drift & diffusion currents
The general solution of carrier transport through the MOSFET relies on the expression for
the inversion charge. The assumption is that the inversion layer is of infinitesimal thickness.

Vs(x) Vs(x+∆x)
Inversion layer
I(x)

x x+∆x

The inversion charge QI is derived in terms of surface potential Vs

What is the surface potential?

9
 Intrinsic level
For an intrinsic semiconductor the Fermi level is
equal to the intrinsic level.
Or: for EF=Ei, n=ni
Energy

Thus we can write the free carrier density as a

function of intrinsic parameters.

Ec
Ei
e|VGS| EFs
EFm Ev
n = ni e ( E F − Ei ) / kT
Intrinsic level
p = ni e ( Ei − E F ) / kT
y

Applied gate voltage

φm = φs Take the workfunction of metal and semiconductor equal.

eVox Oxide potential Applied gate voltage

Energy

is dropped partly across the oxide and partly

across the semiconductor:
VGS = Vox + Vs
Ec
Ei eVs Surface potential
eVs EFs
e|VGS|
EFm Ev
The surface potential:
Vs = VI + Vdepl ≈ Vdepl
y inversion
depletion

10
 Charges
The inversion layer charge can be determined from charge neutrality:

QG + QI + Qdepl = 0 charge balance equation.

The gate charge:

QG = CoxVox

The potential drop across the oxide:

Vox = VGS − Vs potential balance equation.

Thus the inversion charge:

(
QI = − Cox (VGS − Vs ) + Qdepl )

Depletion charges
The depletion charge can be calculated from the depletion region
width of a one-sided junction.
One-sided n+p-junction
Vbi=0 because no work function difference. φm = φs

2εVdepl
Wdep = & Vdepl ≈ Vs
eN A

Number of fixed ionised charges in the

depletion region

Qdepl = −eN AWdep = − 2eN AεVs

Charges per area A

11
Using
Qdepl = − 2eε s N A Vs = −γ Cox Vs

Body factor

Gives

(
QI = −Cox VG − Vs − γ Vs )
Current are then expressed as:

I tot = I diff + I drift

dVs
I drift = µW (− QI ) Definition drift current
dx
kT dQI
I diff =µ W Definition diffusion current
q dx

Currents visualised

SOURCE DRAIN

More inverted carriers Less inverted carriers

There will also be a diffusion term

Gradient in carrier concentration

Diffusion current, IDS1

Applied electric field

Drift current, IDS2

IDS = IDS1 + IDS2

12
 Threshold voltage
Remember
In an ideal MOSFET the charge in the substrate is only important
for calculating the threshold voltage:
Vth=VGS where #inverted charges = #charges in the bulk

Threshold voltage
From gate to bulk VGS=Vth
Energy

EC − EF @ SiO2 / Si
= EF − EV in bulk

Ec

e|VGS| EFs  − (EC − EF ) 

n ∝ exp 
EFm  kT 
Ev
 − (E F − EV ) 
p ∝ exp 
 kT 

The smaller the distance between

y the band and the Fermi level,
the more free carriers

13
 Definition of φF
Energy

The difference between the Fermi level

and the intrinsic level at any point in
Ec
the semiconductor is defined as eφF
Ei
e|VGS|
eφ F = E i − E F
EFs
EFm Ev φF is an electrostatic potential

Surface potential at threshold

From gate to bulk VGS=Vth
Energy

Condition for onset of inversion

@ Vth
Ec
Ei Vs = 2φ F
e|VGS| EFs
EFm Ev

14
 Expression of Vth as a function of
material parameters
From gate to bulk VGS=Vth

Energy
Start with sketching energy Vox
Vs
band diagram and define
+ ---
parameters: Ec
+ -- Ei
e|VGS| EFs
EFm + Ev
+
+
Then write charge balance equation y

QG + QI + Qdepl = 0
Add potential balance equation
VGS = Vox + Vs (everywhere where the bands are bended)

Expression of Vth as a function of

material parameters
− QI − Qdepl
QG + QI + Qdepl = 0 → CoxVox + QI + Qdepl = 0 → Vox =
Cox
VGS = Vox + Vs → Vox = VGS − Vs
@VGS = Vth → Vs = 2φ F Specific for threshold – definition of threshold
→ Vox = Vth − 2φ F & QI << Qdepl Specific for threshold - approximation
− Qdepl (Vs = 2φ F )
→ Vth − 2φ F =
Cox
− Qdepl (Vs = 2φ F )
Vth = + 2φ F
Cox
2 N 
Vs = × Ei − E F = 2 × kT ln A  = 2φ F
e  ni 
2εVs 4εφ F
Wdep = ⇒ Wdep
max
=
eN A eN A

15
 Expression of Vth as a function of
material parameters

 N  
 eN AεkT ln A  
2 eN Aεφ F   ni   N A 
Vth = + 2φ F = 2 + kT ln 
Cox  Cox  ni 
 
 

Oxide thickness
Substrate doping density

If φm ≠ φs
− Qdepl
Vth = (φm − φs ) + + 2φF
Cox
If there is a workfunction difference between metal and semiconductor, then this
difference needs to be removed before the previous analysis can be done →
introduction of first term.

SPICE:
Vth = (φm − φs ) − γ 2φF + 2φF
2eεN A
γ= Body effect factor
Cox

Influence of the bulk doping on Vth

16
 Threshold voltage
is thus influenced by the
depletion region via bulk charges.
Qdepl=QB

These bulk charges QB however will lead to a depletion width

and thus capacitance that will change from source to drain.
This will influence the threshold voltage and will change
the shape of the I-V characteristics → body effect

m ox inv QB p-Si

Threshold voltage – review (interpretation)

MOS junction
a) Initial band bending due to workfunction
difference between gate and semiconductor.
EC Thus apply VG=φG-φs=VFB for flat band.
Ei
b) For threshold voltage apply gate voltage
EFG φF EFs to flat band condition such that channel is as
EV much n-type as substrate is p-type.
VT1=VFB-2φF (with this sign φF = EF-Ei)
oxide

But fixed negative charges QB in the depletion layer will “screen”

the electrons that need to be attracted from the substrate, so an
extra gate voltage needs to be applied
Amount of charge in depletion region: QB
Thus changes threshold voltage:
VT2=VFB-2φF -QB/Cox

17
 I-V shape – influence of Vth on current
Long channel MOSFET
The depletion charge QB is taken constant along the whole channel
length. The potential in the channel from source to drain is a linear
function of VGS-VT1-Vx(x)

I = Cox (VGS –Vx(x) – VT1) W µe dVx/dx

VT1=VFB-2φF
Or VT1=VFB-2φF -QB/Cox

Approximation: depletion
width constant

But: depletion width along the channel

length not constant (VDS)

NA- NA-

Thus QB in the depletion layer is not constant along the channel

I = Cox (VGS –Vx(x) – VT2 (x) ) W µe dVx/dx
VT2=VFB-2φF –QB(x)/Cox

QB ( x) = 2qN Aε Si (2φ F + Vx ( x))

L − ∆L ( 2φ F ,Vx ( x ))
QB = − ∫ 2qN Aε Si ( 2φ F + Vx ( x))
0+

18
 Influence of substrate on depletion
region and thus on the threshold voltage

Influences depletion/enhancement effects from “substrate”

Space charge region controlled not only by the gate but
also by the drain-substrate reverse bias.

QB = − 2qN Aε Si ( 2φ F + Vx ( x) − Vbulk )

Influence of gate oxide charges

Charges in oxide Assuming we can represent the
charges in the oxide and the charges
at the interface of oxide and
semiconductor (interface charge
density) as an effective positive
charge Qi, then this charge inside
the oxide will cause bandbending
which will need to be taken into
account in the threshold voltage.
VT=VFB-2φF -QB/Cox -Qi/Cox
Sign convention

http://www.ece.ucsb.edu/courses/ECE124/124A_F05Banerjee/Lectures/Lecture5.pdf

19
 Why scale?
Decrease the gate length

• Increase speed
• Increase packing density
• Decrease costs?

Analog performance parameters

∂I DS W
gm = ∝ µ Transconductance, control
∂VGS V L
DS = constant

dVGS
S=
dLog ( I DS ) Sub-threshold slope

gm µ 1
fT ∝ ∝ and f max ∝ Maximum operation frequency
2π CGS L Rg

20
 Digital performance parameters

1) SPEED: intrinsic speed CV/I versus L

2) SWITCHING ENERGY: energy-delay product CV2 × CV/I
versus L
3) SCALABILITY: subthreshold slope S versus L
4) OFF-state energy: CV/I versus Ion/Ioff ratio.

Speed Packing density

Transistor/die (microprocessor)

100

109
Gate delay (ps)

10
106
1
103

0.1
10 100 1000 1970 1980 1990 2000 2010
Gate length (nm)

Price per transistor Factory costs

105
Factory costs (M USD)

1
Price (USdollar)

10-7
1970 2002 10
1975 2005

21
 Short channel effects
Long ago, MOSFETs were big and could be described via drift
currents and carrier control via the gate capacitance
Now MOSFETs are small in order to increase their operation speed.
Pushing the dimensions of the gate length down influences the
electrostatics of the devices.
In order to preserve the electrostatic integrity of the MOSFET
scaling has proceeded in a controlled way:
Lg ↓ has to go together with tox ↓, NA ↑, tj ↓, VDD ↓ and W ↓
But reducing these geometrical parameters not only increases
fabrication complexity but also change the physical processes in
the device

short channel effects

Aim
To understand what short channel effects are and where they come
from.
To investigate ways in which to minimise short channel effects

22
 Gate length modulation

Due to pinch off, the effective gate length reduces

L
∆L

∆L

1 1
I DS ∝ → I DS ∝
L L − ∆L
λ channel length modulation coefficient

Source and drain depletion regions

formed by pn-junctions
Draw the energy band diagram between the source and the drain for different
gate voltages.
L

n n
Leff
p

depletion depletion

23
 Relative importance of source and drain
depletion regions
Due to depletion widths from source and drain area extending towards the centre
of the channel. The extend of the depletion width becomes comparable to the
original gate length in short channel FETs.
L L

Leff Leff

I VT Charge sharing
0.25µm
0.75µm

Increased current V Threshold voltage roll-off L

Looking for an analytical approach for

calculating the threshold voltage shift.
Charges sharing

Ideally QB bulk charge

determined by bulk doping and
gate potential.
inv
QB = − 2qN Aε VGS
L
Depleted bulk charges shared by the drain
tj
LB ∆QB
QB depleted by source ∆VT =
Cox

24
 Assumptions made in order to derive an
analytical model for the Vth roll-off.

• VDS=0V
• S & D implanted regions are circular near the channel
• The implant depth of the S & D ohmic contacts, tj are the
same
• The depletion layers WSB, WDB and Wdepl are all the same
width.
• The charges at the S & D are equally shared with the gate.

L WDepl
From geometrical considerations
S G D
ws = (t j + WSB )
2 2
− WSB −tj

n+ t j n+ = (t j + WDepl )
2 2
− WDepl −tj
WSB LB WDB  2WDepl 
ws ws = t j  1 + − 1
ws  tj 
tj+WSB p  

Q’ is remaining share still controlled by gate

Charge controlled by S & G
L
Half shared with S L + LB
Q’ Q ' = e N A WDepl
Half shared with G 2L
LB = L − 2 ws
Similar for drain side. Encroachment LB

25
 QB: bulk charge due to gate only (no S&D depletion)

Q’: “bulk” charge remaining associated to gate only

(S&D depletion taken into account)
∆Q B Q B − Q '
Threshold voltage roll-off: ∆VT = =
Cox Cox

QDepl t j  2WDepl 
∆VT = 1+ − 1
Cox L  tj 

eN AWDepl t ox t j  2WDepl 
= 1+ − 1
ε oxε 0 L  tj 
 

To limit threshold voltage roll-off:

1. Reduce junction depth tj.
2. Increase Cox thus reduce oxide thickness tox
3. Increase NA

Drain Induced Barrier Lowering (DIBL)

Gate controls source barrier: Simple principle: when the gate voltage is low, an
energy barrier prevents electrons from flowing
from source to drain.
A higher gate voltage lowers the energy barrier,
allowing more current to flow.

S D Drain controls source barrier:

Ideally only gate controls the barrier height. For
small MOSFETs, the drain voltage lowers the barrier
between source and channel. Loss of gate control

DIBL

26
 Drain Induced Barrier Lowering (DIBL)
VDS small
G Short channel
Long channel
S D

n+ n+

Electron potential
energy DIBL

VS

VDS VDS

Position along surface of channel

Reduction of source-channel barrier

height at small VDS for short gate
DIBL

Carrier injection across barrier: exponential

27
 Drain voltage breakdown mechanisms,
VDS large
Avalanche breakdown

Large field

Impact ionisation → multiplication of the amount of

carriers that contribute to the current

Avalanche breakdown

breakdown

28
 Drain voltage breakdown mechanisms,
VDS large
Punch through
I

V
DG depletion reaches SG depletion
Space charge limiting currents appear → carriers hopping through an
insulating layer + thermionic currents across the potential barriers in
the channel.

Strategies to control short-channel

effects
• LDD: lightly doped drain region

Changes n+p regions into np regions → changes

depletion into channel.
Reduces electric field at drain side and limits
drain voltage breakdown mechanisms.

29
 Strategies to control short-channel
effects
• Pocket or halo implants

Remember that depletion width extends in the

lowest doped region → introduction of implant
gradients (halo) or highly doped pockets control
the depletion width extending underneath the
channel

Strategies to control short-channel

effects
• Supersteep retrograde body doping

Controls the extension of the depletion width and controls

the influence of the bulk on the threshold voltage without
influencing the mobility in the channel via high impurity
scattering.

30
 Other parameters
Other parameters that influence the current-
voltage characteristics that we have not yet
taken into account.

Mobility variations
+
ED

S + D

n+ n+ S D
EG
EGD
Due to scattering (function
of resulting field), there is a
Field on the carriers in variation of the mobility in
the channel is composed the channel
of 2 components
Variation of resulting
field along the channel

31
 Velocity saturation
qτ 2nd law of motion
At low fields: v = µE = E
m dv mn
mn + v = qE
Drift velocity increases with increasing
dt τfield

But when E high enough,

τ(E) other scattering processes take over and energy is transferred to
the lattice rather than to the speed of the carriers
and limit the velocity increase

v
Region of varying mobility
vsat I = WC (Vgs − VT )vsat
vsat
fT =
2πL
E

Velocity saturation
influence on I-V characteristics

With velocity saturation If velocity saturation is not considered

32
 Velocity saturation
Influence on transfer characteristics

From: http://www.ece.ucsb.edu/courses/ECE124/124A_F05Banerjee/Lectures/Lecture6.pdf

Velocity saturation-special case

GaAs, InP, InGaAs
n = ND total amount of electrons
n = nΓ + nL
v nL
vsat F=
n
fraction of electrons in upper valley

nΓ n
v eff = vΓ + L vL
n n
E v eff = (1 − F )vΓ + FvL
dv eff dv dF dF dv
µeff = = (1 − F ) Γ − vΓ + vL +F L
E dE dE dE dE dE
under the assumption that the electrons in the upper valley
are moving at saturation velocity
mL>mΓ
dF dF
µeff = (1 − F ) µΓ − µΓ E + vL
dE dE
µeff < 0 if
dF 1− F
k >
L Γ dE E − vL
µΓ

33
 Sub-threshold conduction VGS<VT
Channel region is “weakly” inverted
0 + +

n n
p E

E field mainly across

G-D depletion width
none along channel

More electrons here than here

Sub-threshold conduction

More electrons at higher energy here than here

Weak inversion

Diffusion currents
by electrons in the Fermi-tail
thus will be exponentially dependent on gate voltage

34
 Sub-threshold conduction
Weak inversion
S G D Small voltage drop across channel
-> potential ~constant
Ec
e-
VDS Potential barrier between S & G
Energy

n+ p junction -> diffusion of carriers

with sufficient energy (Fermi-tail see next slide)

e- np-diode potential barrier is decreasing →

current exponential function of VGS-VT

e-

Sub-threshold conduction

ID
ideal

Weak inversion

Diffusion currents VT VG
by electrons in the Fermi-tail Exponential sub-threshold current

35
 Sub-threshold slope

IDS Log(IDS )
Exponential curve
ideal
∆ΙD

∆VG

S small

VT VGS VGS
VT
Sub-threshold current dVGS
S= Subthreshold slope
dLog ( I DS )

Sub-threshold conduction
MOS-bipolar equivalent in weak inversion

MOS in weak inversion = Parasitic BJT

Gate Cox
with “base” controlled via capacitive divider.
Source Drain

Cdepl
Bulk (p)

The S-B-D = npn sandwich with mobile minority carriers in the p-type
bulk region. This is equivalent to a BJT, except that the base potential is
controlled through a capacitive divider Cox and Cdepl, and not directly by
carrier injection via the third electrode.

36
 Sub-threshold conduction
MOS-bipolar equivalent in weak inversion
Consequence for current

 qVBE 
 
In BJT: IC ≅ I S e kT 

 q (VGS −VT ) 
 
Thus by analogy in weakly inverted MOS: I D ≅ I 0e 
nkT

Cox + Cdepl  Cdepl 

With n given by the capacitive divider: n = = 1 +  
Cox  Cox 
The expression for subthreshold slope becomes then:
kT kT  C depl 
S= ln(10)n = ln(10)1 + 

q q  C ox 

→ Subthreshold slope is controlled by oxide thickness and bulk doping

Gate leakage current

From: http://www.ece.ucsb.edu/courses/ECE124/124A_F05Banerjee/Lectures/Lecture6.pdf

37
 Influence of statistical variations in
doping atoms in bulk underneath channel

When this volume is very small, due to the statistical

distribution of the doping atoms, the bulk doping might be
different from device to device.

Dopants in a small transistor.

3D simulation of a 30 nm by 30 nm field-effect
transistor domain that contains random discrete
dopants in the source, drain, and substrate
(bulk).The electrostatic potential is color-mapped
from red (1 V) through the rainbow to blue (0 V).
Potential fluctuations in the channel associated
with the random distribution of dopants result in
differing characteristics for each device.
(Top inset) Schematic diagram of the basic
interconnect wiring structure of a field-effect
transistor.
(Bottom inset) Circuit diagram symbol for a
field-effect transistor.
CREDIT:A. BROWN/UNIVERSITY OF
GLASGOW
Ref. Roy, Asenov, Where do dopants go? Science
magazine.

38
 Conclusion
• Different short channel effects contribute to a
deviation of the current-voltage characteristics
based on the “simple” MOSFET model: DIBL and
leakage currents are the main culprits.
• Present day devices need more ingenious models.
– 2-D and 3-D device simulators are commercially
available
• MEDICI, TAURUS
• ATLAS
• We need novel device geometries or material
systems to deal with these problems.

39