JSPM’s

Rajarshi Shahu College of Engineering Tathawade Pune

E&TC Dept

Academic Year 2023-24 SEM-II

Third Year B. Tech Engineering

Subject Name: CMOD Design and Verification

Subject Incharge: Dr. S. C. Wagaj

 Unit- II MOS Transistor

1) The Metal Oxide Semiconductor Structure,

2) structure and operation of MOS Transistor,
3) Threshold voltage of MOSFET,
4) Body effect,
5) MOSFET Current-Voltage characteristics,
6) MOSFET scaling and small-Geometry effects,
7) MOSFET Capacitances,
8) Channel length modulation,
9) Hot electron effect,
10)Velocity saturation,
11)Drain induced barrier lowering,
12)Subthreshold slope,
13)Drain punch through.
 History of MOSFET

1) 1925- Julius Lilinfield design first transistor and filled patent in Canada.
2) 1947- John Bardeen, Walter Brattain and William Shockley built firt Bipolar
junction transistor
(Nobel Prize in physics in 1956)
3) 1958- Jacks Kilby built first integrated circuit flip flop at Texas instrument
(Nobel prize in physics in 2000)
4) 1960- Built first MOSFET kahang and Atala.
5) 1963- Frank Wanless at Fairchild describes the first CMOS logic gate.
MOSFET Structure
 Structure and operation of NMOS Transistor

Source Gate Drain

Polysilicon
SiO2

1) Two n+ regions will be current

n+ n+
Body conducting terminal of this device.
p 2) Symmetric source and drain
bulk Si
3) Control the current conduction
between source and drain, using the
Four terminals: gate, source, drain, body
electric field generated by gate
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
voltage as a control variable.
SiO2 (oxide) is a very good insulator 4) Current flow in the channel is also
Called metal – oxide – semiconductor (MOS) capacitor control by the drain to source
Even though gate is no longer made of metal voltage & substrate voltage
 Structure and operation of PMOS Transistor

Similar, but doping and voltages reversed

Source Gate Drain Body tied to high voltage (VDD)
Polysilicon Gate low: transistor ON
SiO2 Gate high: transistor OFF
Bubble indicates inverted behavior

p+ p+

n bulk Si
 Transistors as Switches

 We can view MOS transistors as electrically controlled switches

 Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
 Signal Strength

 Strength of signal
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
 But degraded or weak 1
 pMOS pass strong 1
 But degraded or weak 0
 Thus nMOS are best for pull-down network
 Pass Transistors

 Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1
 NMOS and PMOS

Sr.No. level Symbol Switch condition

1 Strong 1 1 P switch gate=0 source=VDD
2 Weak 1 1 N switch gate=1 source=VDD
3 Strong 0 0 N switch gate=1 source=VSS
4 Weak 0 0 P switch gate=0, source=VSS
5 High Z N switch gate=0 or P switch gate=1
impedance
 Threshold Voltage of MOSFET

Energy band diagram of NMOS Structure of NMOS Transistor

Source Gate Drain
Polysilicon
SiO2

n+ n+
Body
p bulk Si
 Threshold Voltage of MOSFET
VFB1   MS
a) Energy band diagram of NMOS

a) The band diagram of a MOS structure having a difference between the metal
and semiconductor work function (metal workfunction (ɸm > ɸs)
b) Positive voltage VFB1 at the gate makes all the bands flat everywhere in the
system
 Threshold Voltage of MOSFET

a) Due to the presence of the oxide b) positive voltage VFB1 at the

charges at the Si-SiO2 interface, bands gate makes all the bands flat
in p-Si bend down, thus creating layer everywhere in the system
near the surface.
 Threshold Voltage of MOSFET
VTH  VFB  Surface _ potential  Voltage _ drop _ against _ depletion _ layer
Qb
VTH  VFB   2F   QB  2qN A si 2F
COX
Qb
VTH  VFB  2F 
COX
 Threshold Voltage
VTH  VFB  Surface _ potential  Voltage _ drop _ against _ depletion _ layer
Qb
VTH  VFB   2F  
COX
Qb
VTH  VFB  2F 
COX

KT  NA 
F   log e  
q  ni 

QB  2qN A si 2F
 Threshold Voltage

1) The substrate Fermi potential ɸf is negative in NMOS and positive in PMOS

2) The depletion region charge densities QB are negative in NMOS and positive in PMOS
Threshold voltage for NMOS
QB 0
VT 0  VFB  2F 
COX

Threshold voltage for PMOS

QB 0
VT 0  VFB  2F 
COX
 Threshold Voltage

Calculate the threshold voltage VT0 at VSB=0, for a polysilicon gate n-channel MOS transistor, with the following
parameters: substrate doping density NA =1016 cm-3 , polysilicon gate doping density ND= 2x1020 cm-3, gate oxide
thickness tox=500A0, and oxide thickness fixed charge density NOX=4 X 1010 cm-2.

QB
VTH  VFB  2F 
COX
KT N
Fermi potential p type substrate F Gate   log e D
q ni
2  1020
F  Substrate  
KT N
log e A F Gate   0.026 log e
q ni 1.45  1010
 2  1020 
1016 M  4.05  0.56   0.026 log e 10 
F  Substrate   0.026 log e  1.45  10 
1.45  1010
F  Substrate   0.35V S  4.05  0.56  0.35
MS  4.0029   4.05  0.56  0.35) 
MS  0.9566V
 Threshold Voltage

QB  2qN A si 2F
QB  2  1.6  1019  1016 11.7  8.85 10 14  0.7
QB  4.8160 108 C / cm 2
 OX 3.97  8.85 10 14 F / cm
COX  
tOX 500 108 cm
COX  7.03 108 F / cm 2

QB
VTH  VFB  2F 
COX
VTH  0.9566  0.7  0.68
VTH  0.42V
 Threshold Voltage

QB 0
VT 0  VFB  2F 
COX
2qN A SI 2F
QB 0 
COX
QB  QB 0 QB 0
VT  VFB  2F  
COX COX
2qN A SI 2qN A SI 2F
VT  VFB  2F 
COX
 2F  VSB  
2F 
COX
2qN A SI
VT  VT 0 
COX
 2F  VSB  2F 
VT  VT 0    2F  VSB  2F 
2qN A SI
 
COX

VSB increases then threshold voltage of N-channel MOSFET increases

Threshold Voltage
 Threshold Voltage

1. The substrate Fermi potential Φf is negative in NMOS and

positive in PMOS
2. The depletion region charge densities QB0 and QB are
negative in NMOS, positive in PMOS.
3. The substrate bias coefficient γ is positive in NMOS and
negative in PMOS.
4. The substrate bias voltage VSB is positive in NMOS, negative
in PMOS.
VSB increases then threshold voltage of N-channel MOSFET increases
MOSFET in different region
MOSFET current and voltage characteristics

1) Choose voltage with respect to the source will be

denoted by Vc(y)
2) In reality the threshold voltage changes along the
channel since the channel voltage is not constant.
3) Electric field Ey along y co-ordinate is dominant
boundary conditions for channel voltage VC are
VC(y=0) = VS = 0 VC(y=L)= VDS
VGS>=VT0, VGD=VGS-VDS >= VT0
4) Let QI(y) be the total mobile electron charges in the
surface inversion layer. This charge can be expressed as
a function of gate to source voltage VGS.
QI(y) = -COX [VGS-VC(y) –VT0)
Incremental resistance dR of the diffential channel
segment shown. Assuming that mobile electron in the
inversion layer have a constant surface mobility μn.
MOSFET current and voltage characteristics (linear region)

dy
dR  
W . n QI  y 
dVC  I D .dR
ID
dVC   dy
W . n .QI  y 
L VDS

I D .dy  W . n  QI  y  .dVC
0 0
VDS

I D L  W . n .COX 
0
(VGS  VC  VT 0 ).dVC
W  n COX W
   n .COX . ID  . .[2.(VGS  VT 0 )VDS  VDS
2
]
L 2 L
2
VDS
I D   [(VGS  VT 0 )VDS  ] W 2
VDS
2 ID   n .COX . .[(VGS  VT 0 )VDS  ]
L 2
MOSFET current and voltage characteristics (saturation region)

VDS  VGS  VT 0
W  (VGS  VT 0 ) 2 
I D  n .COX .  
L 2 
 (VGS  VT 0 ) 2 
ID    
 2 

W μ=Mobility of electron
   n .COX . W=width of MOSFET
L
L=length of MOSFET
εox=permittivity of oxide
tox=thickness of sion2 layer
Current Voltage characteristics
Current Voltage Characteristics
Current Voltage Characteristics
Current Voltage Characteristics
Current Voltage Characteristics
 Current equation


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
μ=Mobility of electron
W=width of MOSFET
W
    COX  L=length of MOSFET
L εox=permittivity of oxide
tox=thickness of sion2 layer
34 Example

 We will be using a 0.6 mm process for your project

 From AMI Semiconductor 2.5
Vgs = 5
 tox = 100 Å
2
 m = 350 cm /V*s
2

1.5 Vgs = 4

Ids (mA)
 Vt = 0.7 V
1
 Plot Ids vs. Vds Vgs = 3

 Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
Vgs = 1
 Use W/L = 4/2 l 0
0 1 2 3 4 5
W  3.9  8.85 1014   W  W Vds
   Cox  350   8    120 μA/V 2
L  100 10  L  L

3: CMOS Transistor Theory

 PMOS I/V Characteristics
35
0
Vgs = -1
 All dopings and voltages are inverted for pMOS Vgs = -2

-0.2
 Source is the more positive terminal Vgs = -3

 Mobility mp is determined by holes

Ids (mA)
-0.4
Vgs = -4
 Typically 2x lower than that of electrons mn
-0.6
 Thus pMOS must be wider to
Vgs = -5
-0.8
provide same current -5 -4 -3 -2 -1 0
Vds
 In this class, assume
μn / μp = 2

 Current flow from source to drain then IDS

current is negative.
• VT0 is negative

3: CMOS Transistor Theory

Characteristics of PMOS
 Problem on current equation
The parameters of an n channel MOSFET are μn =650 cm2/V.S, tox=200A0, W/L=50 and
VTH=0.40V. If the transistor is biased in saturation region find the drain current for
VGS=1,2 and 3V.

VGS = 1V
W  (VGS  VT 0 ) 2 
ID   n .COX .  
L  2 
W/L = 50, μn = 650 cm2/V.S, tox = 200x10-8 cm VT0= 0.4V
 OX
COX 
tOX
3.97  8.85 1014 F / cm
COX 
200 108 cm
cm 2 F 0.36
ID  650  17.56  10 8  50 
v.s cm 2 2
ID  1.027 mA
 Problem on current equation
The parameters of an n channel MOSFET are μn =650 cm2/V.S, tox=200A0, W/L=50 and
VTH=0.40V. If the transistor is biased in saturation region find the drain current for
VGS=1,2 and 3V.

VGS = 2V
W  (VGS  VT 0 ) 2 
ID   n .COX .  
L  2 
W/L = 50, μn = 650 cm2/V.S, tox = 200x10-8 cm VT0= 0.4V
cm 2 F 1.6
ID  650  17.56  10 8  50 
v.s cm 2 2
ID  4.56mA

VGS=3V
cm 2 F 2.6
ID  650  17.56  10 8  50 
v.s cm 2 2
ID  7.41mA
 Problem on current equation
For an ideal n channel MOSFET with parameters L=1.25 μm, μn=650 cm2/VS,
Cox=6.9x10-8 F/cm2, VTHn =0.65V. Design the channel width W such that IDSAT = 4mA with
VGS=5V.

W  (VGS  VT 0 ) 2 
ID   n .COX .  
L  2 
L= 1.25 x 10-4 cm, ID =4 mA, VTHn =0.65V

   
2
cm 2
F W 5  0.65
4  103 A  650  6.9  10 8  4  
v.s cm 1.25  10 cm 
2
2 

W  0.513 m
 Operation region of MOSFET
For NMOS and PMOS transistors determine the mode of operation (saturation, Linear or cut-off ) and current for
each of the biasing configurations. (VTHn= 0.7V, VTHp=-0.7V)
1) NMOS VGS=2.5V, VDS=2.5V
2) NMOS VGS=3.3V, VDS=2.2V
3) NMOS VGS=0.6V, VDS=0.1V
4) PMOS VGS=-0.5V, VDS=-1.25V
5) PMOS VGS=-2.5V, VDS=-1.9V
4) PMOS 1) NMOS
VGS=-0.5V and VTHp = -0.7V VGS-VTHn = 2.5V – 0.7V =1.8V, VDS = 2.5V
VGS > VTHp MOSFET work in saturation region.
2) NMOS
MOSFET work in cut off region
VGS-VTHn = 3.3V – 0.7V =2.6V, VDS=2.2V
5) PMOS
VGS = -2.5V VDS = -1.9V MOSFET work in Non saturation region.
3) NMOS
VGS-VTHp = -2.5V + 0.7V = -1.8V, VDS = -1.9V
VGS=0.6V, VGS < VTHn
MOSFET work in Non saturation region
MOSFET work in cut off region
 Detailed MOS Gate Capacitance Model
1) Cutt off
Surface is not inverted . Consequently, there is no conducting channel. Gate to source and gate to
drain
CGS=CGD=0
2) Linear operation mode
The conducting inversion layer on the surface effectively shields the substrate from the gate
dielectric CGB=0
Distributed gate-to-channel capacitance may be viewed as being shared equally.

1
CGS  CGD  COX WL
2
3) Saturation mode
MOSFET is operating in saturation mode, the inversion layer on the surface does not extend the
drain. The gate to drain capacitance component is therefore equal to zero (CGD=0). Since the source
is linked to the conducting channel. Distributed gate to channel capacitance.

2
CGS  COX WL
3
 Detailed MOS Gate Capacitance Model

The MOS gate sits above the channel and may partially overlap the source and diffusion area. Therefore
the gate capacitance has two component the intrinsic capacitance and overlap capacitance.

The intrinsic capacitance was approximated as a simple parallel plate. Let us call this capacitance C O=
WLCox, however bottom plate of the capacitor depends on the mode of operation of transistor.

Approximation of intrinsic MOS gate capacitance

Parameter Cutoff Linear Saturation
Cgb COXWL 0 0
Cgs COXWLD ½ COXWL + COXWLD 2/3 C0XWL + COXWLD
Cgd COXWLD ½ COXWL + COXWLD COXWLD
C-V Characteristics
 Oxide related capacitances
Gate electrode overlaps both the source region and the drain region at the edges. Two overlap capacitance
that arise as a result of this structural arrangement are called C GD and CGS

CGS  COX WLD

CGD  COX WLD
 OX
COX 
tOX
Overlap capacitances don't depend on the bias conditions, they are voltage independent. Channel region is connected
to the source, the drain, and the substrate, we can identify three capacitances between the gate and three regions C GS,
CGD, CGB
MOS Capacitances
MOS Capacitances
 Gate Capacitance

 Approximate channel as connected to source

 Cgs = eoxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body
3: CMOS Transistor Theory
 Problem

Consider an n-channel MOSFET, having tox=10nm, L=1um, W=10 um and LD=0.1um is

biased in the saturation region. Determine its total gate to source and gate to drain
capacitance by finding intrinsic and technological component.

2
C gs  COX WL  COX WLD W  10  m  10 106 102 cm  10 3 cm
3
C gd  0  COX WLD L  1 m  10 6  10 2 cm  10 4 cm
 OX
COX 
tOX
14 F
3.97  8.85  10
COX  cm
10  10 7 cm
8 F
COX  35.13  10
cm 2
 MOSFET Current calculation

 n COX  200  A / V 2
1) Consider an NMOS transistor of size 4/2 and
 p COX  100  A / V 2
calculate drain current ID in microampere for
Wmin  4  0.36  M
VGS=VDD, VDS=0V, VSB=0V
Lmin  2  0.18 M
2) Consider on NMOS transistor of size 4/2 and
VDsatn  0.4V
calculate the drain current ID in microampere for
VDsatp  0.6V
VGS=1V, VDS=0.2V Assume VSB=0V.
VDD  2V
3) Consider an NMOS Transistor of size 4/2 and
VTn  0.4V
calculate the drain current ID in microampere for
VTp  0.4V
VGS=0.6V VDS=1V assume VSB=0V
n  0.07V 1
4) Consider an NMOS transistor of size 4/2 and
 p  0.11V 1
calculate the drain current ID in microampere for
 n  0.4V 0.5
VGS=VDD, VDS=VDD, Assume VSB=0V.
 Sn  0.3V
 Non ideal effects of MOSFETs

1) Sub threshold slope

2) Drain induced barrier lowering
3) Hot electron effects
4) Velocity Saturation
5) Body effect problem
6) Channel length Modulation
7) Drain punch through effect
8) Gate oxide leakage
 Sub Threshold slope
Subthreshold slope is defined as the variation in gate voltage required to have a decade variation
in current
Lower my gate voltage slightly below threshold
voltage, I want to drop current significantly, but
this not achieve due to nonideality.

VGS  VT
log10 I D  log10 I 0  log10 e
nt
d log10 e
log10 I D 
dVGS nt
1
S  nt log e 10
d
log10 I D
dVGS
 n  nonideality _ factor  1
S  60 mV decade
Sub Threshold slope
 Drain Induced Barrier Lowering
The DIBL is defined as difference in threshold voltage when drain voltage increased from V DS =
0.05 V and 1 V (DIBL = VTH (VDS = 0.05 V) – VTH (VDS = 1 V).
In long channel MOSFETs voltage applied to gate acts as a controller to drain current (ID) flow as we
reduce the channel length, ID is not only controlled by the gate voltage (VGS) but also controlled by the
drain voltage (VDS) this behavior of the transistor is called DIBL. To reduce DIBL effects several methods
are proposed as follows
· Increase the gate control by decreasing the oxide thickness.
· By increasing the substrate doping.
· By using a different material which has a lower dielectric constant than Si.
DIBL
 Hot Electron Effect

Hot carrier effect leads in short channel device where electric field is higher. Electron's kinetic energy is higher than the
band gap energy of silicon. These electrons collide with atom at Drain side and electron-hole pair is generated due to
impact ionization. Holes flow at substrate and electrons flow towards Drain side. High energy electron damages silicon-
gate dielectric and degrades Drain current and threshold voltage.
 Velocity Saturation

Vd  drift _ velocity  105 m / s

VDD starting dropping with technology, fix VDD at drift
velocity of electron is 10^5 m/s.
Maximum drift velocity to maximum voltage
permissible
VDS
Vd   E E
L

VdSAT L
VDSAT 
n

VdSAT  105 m s
 Velocity Saturation

1) Velocity of the carriers is known as to saturate due

to mobility saturation of higher electric field
2) In a nanoscale MOSFET, this is observed at lower
drain voltage itself, resulting increased ON
(saturation earlier), we can easily identify weather
the saturation is due to velocity saturation or V DS.

VGS-VTH > VDSAT, then current decreases due to velocity

saturation
Channel length modulation

L’ decreases with increasing VDS saturation current ID will

also increase with VDS. By approximating effective
channel length L’ =L-∆L
 Channel length modulation

n COX W
VGS  VT 0 
2
I D ( Sat ) 
2 L'
 
 1   n COX W VGS  VT 0 
2

I D ( Sat )  
L  L 2
 1 
 L 
L
1  1  VDS
L

n COX W
VGS  VT 0  (1  VDS )
2
I D ( Sat ) 
2 L
 Body effect
Positive value of VSB imply that the source body junction is reverse biased.
Threshold voltage of MOSFET 2 is greater than MOSFET 1.
QB 0
VT 0  VFB  2F 
COX
2qN A SI 2F
QB 0 
COX
QB  QB 0 QB 0
VT  VFB  2F  
COX COX
2qN A SI 2qN A SI 2F
VT  VFB  2F 
COX
 2F  VSB  
2F 
COX
2qN A SI
VT  VT 0 
COX
 2F  VSB  2F 
VT  VT 0   ( 2F  VSB  2F )
2qN A SI
 
COX
 Drain punch through

In order to eliminate the change of

this breakdown happening in a
device is to dope substrate heavily
then reduction of width source
body and drain body
1) Source and drain get connected directly through a very low resistance
2) The result is very huge current flow through the device, since almost entire VDS
gets dropped in source and drain region
 Gate oxide leakage

1) SiO2 is a good insulator to be used in the MOS structure.

2) But, when gate oxide thickness is reduced less than 3nm or 2nm, tunnelling probability increases and
result in an increase of the oxide leakage current .
3) Using a high-k dielectric is used to solve this problem to some extent, as a high-k dielectric can
provide a similar gate electric field even with a physically thick
high-k gate dielectric.
4) This can reduce the direct tunnelling leakage.
 Technology scaling

Parameter Constant field Constant voltage lateral

Length (L) 1/α 1/α 1/α
Width (W) 1/α 1/α 1
Supply voltage 1/α 1 1
Gate oxide thickness tox 1/α 1/α 1
Current 1/α α α
Transconductance 1 α α
Load capacitance 1/α 1/α 1/α
Gate delay 1/α 1/α2 1/α2

W 2
VDS 
Gate delay = VC/I
I DS  nCOX V  V  V  W  (VGS  VT 0 ) 2 
 I D  n .COX . 
2  
GS TH DS
L L 2   ox W
g m  n VGS  VTH 
tox L
Load capacitance = WL/tox
 Result Influence

Parameter Constant field Constant voltage lateral

DC power dissipation 1/α2 α α
Dynamic power dissipation 1/α2 α α
Power delay product 1/α3 1/α 1/α
A= W X L 1/α2 1/α2 1/α
Power density (VI/A) 1 α3 α2
Current density (I/A) α α3 α2