CMOS Design & Verification - 2 - 1706634700206
CMOS Design & Verification - 2 - 1706634700206
CMOS Design & Verification - 2 - 1706634700206
E&TC Dept
1) 1925- Julius Lilinfield design first transistor and filled patent in Canada.
2) 1947- John Bardeen, Walter Brattain and William Shockley built firt Bipolar
junction transistor
(Nobel Prize in physics in 1956)
3) 1958- Jacks Kilby built first integrated circuit flip flop at Texas instrument
(Nobel prize in physics in 2000)
4) 1960- Built first MOSFET kahang and Atala.
5) 1963- Frank Wanless at Fairchild describes the first CMOS logic gate.
MOSFET Structure
Structure and operation of NMOS Transistor
p+ p+
n bulk Si
Transistors as Switches
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
Pass Transistors
s d g=1
g=0
s d 1 strong 1
NMOS and PMOS
n+ n+
Body
p bulk Si
Threshold Voltage of MOSFET
VFB1 MS
a) Energy band diagram of NMOS
a) The band diagram of a MOS structure having a difference between the metal
and semiconductor work function (metal workfunction (ɸm > ɸs)
b) Positive voltage VFB1 at the gate makes all the bands flat everywhere in the
system
Threshold Voltage of MOSFET
KT NA
F log e
q ni
QB 2qN A si 2F
Threshold Voltage
Calculate the threshold voltage VT0 at VSB=0, for a polysilicon gate n-channel MOS transistor, with the following
parameters: substrate doping density NA =1016 cm-3 , polysilicon gate doping density ND= 2x1020 cm-3, gate oxide
thickness tox=500A0, and oxide thickness fixed charge density NOX=4 X 1010 cm-2.
QB
VTH VFB 2F
COX
KT N
Fermi potential p type substrate F Gate log e D
q ni
2 1020
F Substrate
KT N
log e A F Gate 0.026 log e
q ni 1.45 1010
2 1020
1016 M 4.05 0.56 0.026 log e 10
F Substrate 0.026 log e 1.45 10
1.45 1010
F Substrate 0.35V S 4.05 0.56 0.35
MS 4.0029 4.05 0.56 0.35)
MS 0.9566V
Threshold Voltage
QB 2qN A si 2F
QB 2 1.6 1019 1016 11.7 8.85 10 14 0.7
QB 4.8160 108 C / cm 2
OX 3.97 8.85 10 14 F / cm
COX
tOX 500 108 cm
COX 7.03 108 F / cm 2
QB
VTH VFB 2F
COX
VTH 0.9566 0.7 0.68
VTH 0.42V
Threshold Voltage
QB 0
VT 0 VFB 2F
COX
2qN A SI 2F
QB 0
COX
QB QB 0 QB 0
VT VFB 2F
COX COX
2qN A SI 2qN A SI 2F
VT VFB 2F
COX
2F VSB
2F
COX
2qN A SI
VT VT 0
COX
2F VSB 2F
VT VT 0 2F VSB 2F
2qN A SI
COX
dy
dR
W . n QI y
dVC I D .dR
ID
dVC dy
W . n .QI y
L VDS
I D .dy W . n QI y .dVC
0 0
VDS
I D L W . n .COX
0
(VGS VC VT 0 ).dVC
W n COX W
n .COX . ID . .[2.(VGS VT 0 )VDS VDS
2
]
L 2 L
2
VDS
I D [(VGS VT 0 )VDS ] W 2
VDS
2 ID n .COX . .[(VGS VT 0 )VDS ]
L 2
MOSFET current and voltage characteristics (saturation region)
VDS VGS VT 0
W (VGS VT 0 ) 2
I D n .COX .
L 2
(VGS VT 0 ) 2
ID
2
W μ=Mobility of electron
n .COX . W=width of MOSFET
L
L=length of MOSFET
εox=permittivity of oxide
tox=thickness of sion2 layer
Current Voltage characteristics
Current Voltage Characteristics
Current Voltage Characteristics
Current Voltage Characteristics
Current Voltage Characteristics
Current equation
0 Vgs Vt cutoff
Vds V V V
I ds Vgs Vt ds linear
2
ds dsat
Vgs Vt
2
Vds Vdsat saturation
2
μ=Mobility of electron
W=width of MOSFET
W
COX L=length of MOSFET
L εox=permittivity of oxide
tox=thickness of sion2 layer
34 Example
1.5 Vgs = 4
Ids (mA)
Vt = 0.7 V
1
Plot Ids vs. Vds Vgs = 3
Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
Vgs = 1
Use W/L = 4/2 l 0
0 1 2 3 4 5
W 3.9 8.85 1014 W W Vds
Cox 350 8 120 μA/V 2
L 100 10 L L
-0.2
Source is the more positive terminal Vgs = -3
Ids (mA)
-0.4
Vgs = -4
Typically 2x lower than that of electrons mn
-0.6
Thus pMOS must be wider to
Vgs = -5
-0.8
provide same current -5 -4 -3 -2 -1 0
Vds
In this class, assume
μn / μp = 2
VGS = 1V
W (VGS VT 0 ) 2
ID n .COX .
L 2
W/L = 50, μn = 650 cm2/V.S, tox = 200x10-8 cm VT0= 0.4V
OX
COX
tOX
3.97 8.85 1014 F / cm
COX
200 108 cm
cm 2 F 0.36
ID 650 17.56 10 8 50
v.s cm 2 2
ID 1.027 mA
Problem on current equation
The parameters of an n channel MOSFET are μn =650 cm2/V.S, tox=200A0, W/L=50 and
VTH=0.40V. If the transistor is biased in saturation region find the drain current for
VGS=1,2 and 3V.
VGS = 2V
W (VGS VT 0 ) 2
ID n .COX .
L 2
W/L = 50, μn = 650 cm2/V.S, tox = 200x10-8 cm VT0= 0.4V
cm 2 F 1.6
ID 650 17.56 10 8 50
v.s cm 2 2
ID 4.56mA
VGS=3V
cm 2 F 2.6
ID 650 17.56 10 8 50
v.s cm 2 2
ID 7.41mA
Problem on current equation
For an ideal n channel MOSFET with parameters L=1.25 μm, μn=650 cm2/VS,
Cox=6.9x10-8 F/cm2, VTHn =0.65V. Design the channel width W such that IDSAT = 4mA with
VGS=5V.
W (VGS VT 0 ) 2
ID n .COX .
L 2
L= 1.25 x 10-4 cm, ID =4 mA, VTHn =0.65V
2
cm 2
F W 5 0.65
4 103 A 650 6.9 10 8 4
v.s cm 1.25 10 cm
2
2
W 0.513 m
Operation region of MOSFET
For NMOS and PMOS transistors determine the mode of operation (saturation, Linear or cut-off ) and current for
each of the biasing configurations. (VTHn= 0.7V, VTHp=-0.7V)
1) NMOS VGS=2.5V, VDS=2.5V
2) NMOS VGS=3.3V, VDS=2.2V
3) NMOS VGS=0.6V, VDS=0.1V
4) PMOS VGS=-0.5V, VDS=-1.25V
5) PMOS VGS=-2.5V, VDS=-1.9V
4) PMOS 1) NMOS
VGS=-0.5V and VTHp = -0.7V VGS-VTHn = 2.5V – 0.7V =1.8V, VDS = 2.5V
VGS > VTHp MOSFET work in saturation region.
2) NMOS
MOSFET work in cut off region
VGS-VTHn = 3.3V – 0.7V =2.6V, VDS=2.2V
5) PMOS
VGS = -2.5V VDS = -1.9V MOSFET work in Non saturation region.
3) NMOS
VGS-VTHp = -2.5V + 0.7V = -1.8V, VDS = -1.9V
VGS=0.6V, VGS < VTHn
MOSFET work in Non saturation region
MOSFET work in cut off region
Detailed MOS Gate Capacitance Model
1) Cutt off
Surface is not inverted . Consequently, there is no conducting channel. Gate to source and gate to
drain
CGS=CGD=0
2) Linear operation mode
The conducting inversion layer on the surface effectively shields the substrate from the gate
dielectric CGB=0
Distributed gate-to-channel capacitance may be viewed as being shared equally.
1
CGS CGD COX WL
2
3) Saturation mode
MOSFET is operating in saturation mode, the inversion layer on the surface does not extend the
drain. The gate to drain capacitance component is therefore equal to zero (CGD=0). Since the source
is linked to the conducting channel. Distributed gate to channel capacitance.
2
CGS COX WL
3
Detailed MOS Gate Capacitance Model
The MOS gate sits above the channel and may partially overlap the source and diffusion area. Therefore
the gate capacitance has two component the intrinsic capacitance and overlap capacitance.
The intrinsic capacitance was approximated as a simple parallel plate. Let us call this capacitance C O=
WLCox, however bottom plate of the capacitor depends on the mode of operation of transistor.
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body
3: CMOS Transistor Theory
Problem
2
C gs COX WL COX WLD W 10 m 10 106 102 cm 10 3 cm
3
C gd 0 COX WLD L 1 m 10 6 10 2 cm 10 4 cm
OX
COX
tOX
14 F
3.97 8.85 10
COX cm
10 10 7 cm
8 F
COX 35.13 10
cm 2
MOSFET Current calculation
n COX 200 A / V 2
1) Consider an NMOS transistor of size 4/2 and
p COX 100 A / V 2
calculate drain current ID in microampere for
Wmin 4 0.36 M
VGS=VDD, VDS=0V, VSB=0V
Lmin 2 0.18 M
2) Consider on NMOS transistor of size 4/2 and
VDsatn 0.4V
calculate the drain current ID in microampere for
VDsatp 0.6V
VGS=1V, VDS=0.2V Assume VSB=0V.
VDD 2V
3) Consider an NMOS Transistor of size 4/2 and
VTn 0.4V
calculate the drain current ID in microampere for
VTp 0.4V
VGS=0.6V VDS=1V assume VSB=0V
n 0.07V 1
4) Consider an NMOS transistor of size 4/2 and
p 0.11V 1
calculate the drain current ID in microampere for
n 0.4V 0.5
VGS=VDD, VDS=VDD, Assume VSB=0V.
Sn 0.3V
Non ideal effects of MOSFETs
VGS VT
log10 I D log10 I 0 log10 e
nt
d log10 e
log10 I D
dVGS nt
1
S nt log e 10
d
log10 I D
dVGS
n nonideality _ factor 1
S 60 mV decade
Sub Threshold slope
Drain Induced Barrier Lowering
The DIBL is defined as difference in threshold voltage when drain voltage increased from V DS =
0.05 V and 1 V (DIBL = VTH (VDS = 0.05 V) – VTH (VDS = 1 V).
In long channel MOSFETs voltage applied to gate acts as a controller to drain current (ID) flow as we
reduce the channel length, ID is not only controlled by the gate voltage (VGS) but also controlled by the
drain voltage (VDS) this behavior of the transistor is called DIBL. To reduce DIBL effects several methods
are proposed as follows
· Increase the gate control by decreasing the oxide thickness.
· By increasing the substrate doping.
· By using a different material which has a lower dielectric constant than Si.
DIBL
Hot Electron Effect
Hot carrier effect leads in short channel device where electric field is higher. Electron's kinetic energy is higher than the
band gap energy of silicon. These electrons collide with atom at Drain side and electron-hole pair is generated due to
impact ionization. Holes flow at substrate and electrons flow towards Drain side. High energy electron damages silicon-
gate dielectric and degrades Drain current and threshold voltage.
Velocity Saturation
VdSAT L
VDSAT
n
VdSAT 105 m s
Velocity Saturation
n COX W
VGS VT 0
2
I D ( Sat )
2 L'
1 n COX W VGS VT 0
2
I D ( Sat )
L L 2
1
L
L
1 1 VDS
L
n COX W
VGS VT 0 (1 VDS )
2
I D ( Sat )
2 L
Body effect
Positive value of VSB imply that the source body junction is reverse biased.
Threshold voltage of MOSFET 2 is greater than MOSFET 1.
QB 0
VT 0 VFB 2F
COX
2qN A SI 2F
QB 0
COX
QB QB 0 QB 0
VT VFB 2F
COX COX
2qN A SI 2qN A SI 2F
VT VFB 2F
COX
2F VSB
2F
COX
2qN A SI
VT VT 0
COX
2F VSB 2F
VT VT 0 ( 2F VSB 2F )
2qN A SI
COX
Drain punch through
W 2
VDS
Gate delay = VC/I
I DS nCOX V V V W (VGS VT 0 ) 2
I D n .COX .
2
GS TH DS
L L 2 ox W
g m n VGS VTH
tox L
Load capacitance = WL/tox
Result Influence