Journal of Power Electronics

https://doi.org/10.1007/s43236-020-00037-3

ORIGINAL ARTICLE

DC–DC converter implementation with wide output voltage operation

Bor‑Ren Lin1

Received: 28 June 2019 / Revised: 3 September 2019 / Accepted: 11 October 2019

© The Korean Institute of Power Electronics 2020

Abstract
A direct current (DC) to DC converter with soft switching and high efficiency is developed for industry power units with a
wide range of output voltage applications. A series resonant converter is the main circuit on the primary side to accomplish
the soft switching characteristics for the active devices and rectifier diodes without switching loss or reverse recovery cur-
rent loss. To overcome the drawback of the limited operation input or output voltage range in conventional LLC converters,
a hybrid resonant converter including a half-bridge circuit and a full-bridge circuit with auxiliary windings is developed to
achieve 8:1 (Vo,max = 8Vo,min) output voltage characteristics for a wide range of output voltage applications. To achieve this
function, two AC power switches are used in the developed circuit. Since a single-stage hybrid resonant converter is presented
instead of a two-stage converter to realize wide voltage range operation, the developed circuit has better efficiency when
compared to conventional LLC converters and two-stage DC–DC converters. To confirm the circuit analysis and effective-
ness, a prototype with a 400 W rated power was built and tested.

Keywords  Wide output voltage operation · Hybrid resonant circuit · Soft switching

1 Introduction the output inductor is used to achieve soft switching for the
switches at the leading-leg with a wide load range. However,
High-efficiency switching power supplies are demanded for the major disadvantages are hard switching operation at the
industry power units with a variable output voltage such as lagging-leg switches for light load cases and high circulat-
outdoor LED lighting systems. Active clamped flyback con- ing current loss. LLC resonant converters [7–9] have the
verters with a synchronous rectifier [1, 2] have been devel- advantages of zero voltage switching for all of the active
oped for computer adaptors with a high circuit efficiency. devices and zero current switching for the rectifier diodes.
However, the power rating of the active clamped flyback is Therefore, the circuit efficiency is attractive for modern
limited in low power applications. Asymmetric pulse-width power electronic products with high efficiency. However,
modulation (APWM) half-bridge converters [3, 4] were pre- the main problem with resonant converters is the narrow
sented to reduce switching losses and to improve converter voltage operation range.
efficiency. The drawbacks of the APWM half-bridge con- Wide output voltage converters [10–18] have been attrac-
verter are: (1) the DC voltage value on the primary side, (2) tive for the battery chargers in electric vehicle (EV) systems
the unbalance current rating on the active devices, and (3) and power units in LED outdoor lighting systems with varia-
the unbalance current rating on the rectifier diodes. Phase- ble series or parallel combinations of LED strings. The front
shift full-bridge converters [5, 6] were developed for high stage of such power units is normally a power factor correc-
power applications with a high circuit efficiency. According tor (PFC) to accomplish harmonic elimination and power
to phase-shift pulse-width modulation (PSPWM), the gating factor correction. The output voltage of the PFC is usually
signals at the lagging-leg switches are phase shifted to the controlled at 380–400 V for a single-phase AC voltage input.
signals at the leading-leg switches. Therefore, the energy on The secondary stage is a DC–DC converter with wide output
voltage operation. For a battery charger in an EV system,
the output voltage range is variable from Vo,min = 200 V to
* Bor‑Ren Lin Vo,max = 450 V. Conventional pulse-width modulation was
[email protected]
used to realize wide voltage operation. However, the power
1
Department of Electrical Engineering, National Yunlin conduction losses on the active devices are increased under
University of Science and Technology, Yunlin, Taiwan

13
Vol.:(0123456789)
 B.-R. Lin

high voltage input or low voltage output conditions in the Vo

low effective duty cycle case. Cascade series DC–DC con- S1 S3 +
T D1 Lo Ro
verters with a wide voltage gain are another solution to +
Co
accomplish wide voltage operation. However, the circuit Vin a Lm
b
efficiency is reduced due to the series connection of multi- S2 S4 D2
T
ple DC–DC circuits. A hybrid resonant converter [18] with a
(a)
combination of full-bridge and half-bridge circuits has been
presented to have 4:1 (Vin,max = 4Vin,min) input voltage range. Vdc
The limitation of this topology is that the maximum voltage Vo
gain is less than four. Full Buck/
A new wide voltage operation soft switching hybrid reso- +
Bridge Boost +
nant converter is developed and implemented to accomplish Vin Converter Converter Co
the advantages of wide soft switching and wide output volt-
age operation (8:1 output voltage range, Vo,max = 8Vo,min).
A resonant circuit is employed to accomplish the wide soft
(b)
switching characteristics without turn-on switching loss on
the active devices and turn-off switching loss on the rectifier
Fig. 1  DC–DC converters with a wide range of output voltage: a full-
diodes. A half-bridge circuit (with a low effective primary- bridge converter; b cascade DC–DC converter
side voltage) and a full-bridge circuit (with a high effective
primary-side voltage) can be selected on the primary side,
and auxiliary secondary windings (with a high effective T
C1 + DS1 DS3 NS2 D3 S5 V o Io
secondary-side voltage) can be selected on the output side VC1 S1 CS1 S3
to achieve 8:1 wide output voltage operation capability. + Lr Cr T NS1D1 Co
a b
CS3
Ro
This paper in organized as follows. The circuit structure is Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2
presented and discussed in section II. The circuit operations CS2 S4
C2 VC2 DS2 DS4 NS2 D4
with wide output voltage ranges are provided in section III.
The system analysis and circuit characteristics are discussed
in section IV. The design considerations and measured wave- Fig. 2  Hybrid DC–DC resonant converter with a wide range of out-
forms are demonstrated in section V. The conclusion is pre- put voltage
sented is section VI.
semiconductors. However, the main negatives are a wide
frequency operation range and a limited voltage operation
2 Circuit structure range. To improve these drawbacks, a two-stage DC–DC
converter is shown in Fig. 1b. The front stage is a full-bridge
Figure 1a illustrates a circuit diagram of a conventional full- converter and the rear stage is a buck-boost converter to
bridge converter with a 380 V input and a variable output achiever a wide range of output voltage. The advantage of
voltage for industry power supplies. The 380 V input voltage this circuit topology is that it is easy to accomplish a wide
is generated from a power factor corrector with line har- output voltage range. However, the converter efficiency is
monic current elimination and reactive power compensation. reduced due to two-stage circuit operation.
The phase-shift full-bridge converter can accomplish zero Figure 2 illustrates the circuit structure of the devel-
voltage switching and a wide voltage output. However, the oped LLC converter with the ability of a wide range of
maximum effective duty cycle on the primary side is limited output voltage. In the presented circuit configuration,
to 0.5 under the maximum output voltage case. If a lower S1 ~ S5 are active switches, and Q1 is an AC active switch.
voltage output is required, the minimum effective duty cycle, C r is a resonant capacitor. L r is a resonant inductor. T
dmin = dmaxVo,min/Vo,max, is decreased and the root-mean- is an isolation transformer with a magnetizing induct-
square current on the primary side is increased. Therefore, ance Lm. The transformer T has two sets of center-tapped
the conduction losses on the full-bridge converter in the low windings N s1 and N s2. In addition, D 1 ~ D 4 are rectifier
output voltage case are increased and the circuit efficiency diodes on the secondary side. C 1 and C 2 are input split
is reduced. Thus, the converter efficiency under a higher capacitors, C o is an output capacitor, and R o is a load
output voltage is greater than that under the lower output resistor. On the primary side, the proposed converter
voltage condition. Resonant converters were presented with can be operated as a half-bridge resonant converter (Q 1
the benefits of a high circuit efficiency and a wide range of on) as shown in Fig. 3a, b, or as a full-bridge converter
soft switching operation for all of the active and passive (Q1 off) as shown in Fig. 3c to achieve different voltage

13
DC–DC converter implementation with wide output voltage operation

T 3 Operation principle
C1 + DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co The developed converter is based on frequency control to
a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2 regulate the output voltage. Based on different output volt-
+ Q 1 S2 CS2 S4 age ranges, the AC switch Q1 and the auxiliary switch S5
C2 VC2 DS2 DS4 NS2 D4
are turned on or off. For system analysis, the capacitances
(a) are assumed to be CS1 = ··· = CS4 = Coss, C1 = C2 = Cin. The
secondary turns of T are Ns1 = Ns2. There are the three out-
T
C1 + DS1 DS3 NS2 D3 S5 Vo Io
put voltage ranges, Vo,min ~ 2Vo,min, 2Vo,min ~ 4Vo,min and
VC1 S1 CS1 S3 4Vo,min ~ 8Vo,min, in the proposed circuit. Pulse-width modu-
+ Lr Cr T NS1D1 Co
a b
CS3
Ro lation waveforms and the equivalent step circuits for these
Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2 CS2 S4 three output voltage ranges are demonstrated in Figs. 4,
C2 VC2 DS2 DS4 NS2 D4 5 and 6. In relation to the on/off states of Q1, S1 ~ S5 and
D1 ~ D4, the proposed converter has six operating steps for
(b) every switching cycle under fsw (switching frequency) < fr
T
(resonant frequency).
C1 + DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co 3.1 Low output voltage range ­(S1, ­S2, ­S5 off)
a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2
+ Q 1 S2 CS2 S4 For the low output voltage range shown in Fig.  3a, Q1
C2 VC2 DS2 DS4 NS2 D4
turns on and S ­ 1, ­S2 and S­ 5 turn off. The half-bridge reso-
nant converter and the center-tapped rectifier are adopted
(c) on the primary side and the secondary side, respectively.
The turn ratio of the transformer under this operation range
Fig. 3  Equivalent circuits at different output voltage ranges: a low is n1 = Np/Ns1. The DC voltage gain under this condition is
output voltage operation; b medium output voltage operation; c high
output voltage operation
GL = 2n1Vo/Vin. Figure 4 demonstrates pulse-width modula-
tion waveforms and the equivalent step circuits for the low
output voltage range.
Step 1 [t0 ≤ t < t1]: At t = t0, vCS4 = 0. Since iLr(t0) < 0, DS4
conducts. After t > t0, S4 is turned on under zero voltage
gains. The normal secondary windings shown in Fig. 3a switching. The capacitor voltage VC2 = Vin/2 connects to the
or the auxiliary secondary windings shown in Fig. 3b, c components Lr, Cr and Lm. Since D1 conducts, the magnet-
are used on the secondary side to extend the voltage gain izing voltage vLm = n1Vo and iLm increases in this step. In step
and output voltage range. Therefore, a wide voltage range 1, iLr and vCr can be estimated as:
DC–DC soft switching circuit is realized in the proposed
converter. When the load voltage is under the low volt- Vin ∕2 − n1 Vo − vCr (t0 )
iLr (t) = sin 2𝜋fr (t − t0 )
age range V o,min ~ 2V o,min, the active switches S 1, S 2 and Zr (1)
S5 are off as shown in Fig. 3a. The half-bridge resonant + iLr (t0 ) cos 2𝜋fr (t − t0 )
converter is operated on the primary side and the center-
tapped rectifier is used on the secondary side. Thus, the vCr (t) = Vin ∕2 − n1 Vo − [Vin ∕2 − n1 Vo − vCr (t0 )] cos 2𝜋fr (t − t0 )
proposed converter has a low voltage gain. If the output
+ iLr (t0 )Zr sin 2𝜋fr (t − t0 )
voltage is in the medium voltage level 2V o,min ~ 4V o,min, (2)
the active switches S1 and S2 are turned off (Fig. 3b). The √ √
auxiliary switch S5 conducts so that D1 and D2 are reverse where fr = 1∕2𝜋 Lr Cr and Zr = Lr ∕Cr .
biased. The voltage gain shown in Fig. 3b is greater than Step 2 [t1 ≤ t < t2]: Due to fr > fsw, iLm is equal to iLr at t = t1.
the voltage gain shown in Fig. 3a, since more secondary Then, D1 is reverse biased, and Lm, Cr and Lr are resonant in
windings are connected to the output capacitor. When the step 2. iLr and vCr are estimated in (3) and (4).
output voltage is in the high voltage level 4Vo,min ~ 8Vo,min, Vin ∕2 − vCr (t1 )
the active switch Q1 is off as shown in Fig. 3c. The full- iLr (t) = sin 2𝜋fp (t − t1 ) + iLr (t1 ) cos 2𝜋fp (t − t1 )
Zp
bridge LLC converter is worked on the primary side and (3)
the center-tapped rectifier with Ns1 + Ns2 secondary wind-
ing turns is used on the secondary side to obtain a high
voltage gain in the presented circuit.

13
 B.-R. Lin

Fig. 4  Proposed converter for the low output voltage range: a pulse- ▸ vS4,g vS3,g
width modulation waveforms; b step 1 equivalent circuit; c step 2 vS3,d vS4,d
equivalent circuit; d step 3 equivalent circuit; e step 4 equivalent cir- Vin
cuit; f step 5 equivalent circuit; g step 6 equivalent circuit vS1,g, vS2,g
vQ1,g

vS5,g
vCr (t) = Vin ∕2 − [Vin ∕2 − vCr (t1 )] cos 2𝜋fp (t − t1 ) iLr iLm
(4)
+ iLr (t1 )Zp sin 2𝜋fp (t − t1 ) iS4
√ √ iS3
where fp = 1∕2𝜋 (Lm + Lr )Cr and Zp = (Lm + Lr )∕Cr .
iD1
Step 3 [t2 ≤ t < t3]: At t = t2, S4 turns off. Since iLr(t2) > 0, CS3
iD2
is discharged and CS4 is charged. After t > t2, iLr < iLm so that
iD3
D2 conducts and vLm = − n1Vo. vCS3 and vCS4 are estimated as: iD4
t
t0 t 1t 2t 3 t4t5 Tsw+t0
i (t ) Δi
vCS3 (t) = Vin − Lr 2 (t − t2 ) ≈ Vin − Lm (t − t2 ) (5) (a)
2Coss 4Coss T
C1 + DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co
iLr (t2 ) Δi a b
CS3
Ro
vCS4 (t) = (t − t2 ) ≈ Lm (t − t2 ) (6) Vin iLr vCr Lm CS4 NS1D2
2Coss 4Coss + Q1 S2 CS2 S4
C2 VC2 DS2 DS4 NS2 D4

where ΔiLm is the peak-to-peak current on Lm.

(b)
Step 4 [t3 ≤ t < t4]: At t = t3, vCS3(t3) = 0. Since iLr(t3) > 0, DS3
T
conducts and S3 is turned on after t3 to realize soft switch- C1 +
VC1
DS1 DS3 NS2 D3 S5 V o Io
S1 CS1 S3
ing operation. In this step, iLr < iLm so that D2 conducts and +
a
Lr Cr T
CS3 NS1D1 Co
b Ro
vLm = − n1Vo. In addition, Lr and Cr are resonant, and iLr and Vin
+
iLr vCr Lm CS4 NS1D2
Q 1 S2 CS2 S4
vCr are estimated as: C2 VC2 DS2 DS4 NS2 D4

n1 Vo − Vin ∕2 − vCr (t3 ) (c)

iLr (t) = sin 2𝜋fr (t − t3 )
Zr (7) C1
T
NS2 D3 V o Io
+ DS1 DS3 S5
VC1 S1 CS1 S3
+ iLr (t3 ) cos 2𝜋fr (t − t3 ) + Lr Cr T NS1D1 Co
a CS3
b Ro
Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2 CS2 S4
vCr (t) = n1 Vo − Vin ∕2 − [n1 Vo − Vin ∕2 − vCr (t3 )] C2 VC2 DS2 DS4 NS2 D4
(8)
× cos 2𝜋fr (t − t3 ) + iLr (t3 )Zr sin 2𝜋fr (t − t3 ) (d)
T
Step 5 [t4 ≤ t < t5]: Since fsw < fr, iLm is equal to iLr at t = t4. C1 + DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
As a result, D2 is off. Lm, Lr and Cr are resonant in step 5, and + Lr Cr T NS1D1 Co
a CS3
b Ro
iLr and vCr are estimated as: Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2 CS2 S4
V ∕2 + vCr (t4 ) C2 VC2 DS2 DS4 NS2 D4

iLr (t) = − in sin 2𝜋fp (t − t4 )

Zp (9) (e)
T
+ iLr (t4 ) cos 2𝜋fp (t − t4 ) C1 NS2 D3 V o Io
+ DS1 DS3 S5
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co
a CS3
b Ro
vCr (t) = −Vin ∕2 + [Vin ∕2 + vCr (t4 )] cos 2𝜋fp (t − t4 ) Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2 CS2 S4
(10) C2 VC2 DS2 DS4 NS2 D4
+ iLr (t4 )Zp sin 2𝜋fp (t − t4 )
(f)
Step 6 [t5 ≤ t < Tsw + t0]: At t = t5, S3 turns off. Since T
iLr > iLm and iLr(t5) < 0, D1 conducts, CS3 is charged and CS4 C1 +
VC1 S1
DS1
CS1 S3
DS3 NS2 D3 S5 V o Io
is discharged. +
a
Lr Cr T
CS3 NS1D1 Co
Ro
b
Vin iLr vCr Lm CS4 NS1D2
+ Q1 S2
ΔiLm CS2 S4
vCS3 (t) ≈ (t − t5 ) (11) C2 VC2 DS2 DS4 NS2 D4
4Coss
(g)

13
DC–DC converter implementation with wide output voltage operation

Fig. 5  Proposed converter for the medium output voltage range: a ▸ vS4,g vS3,g
pulse-width modulation waveforms; b step 1 equivalent circuit; c step vS3,d vS4,d
2 equivalent circuit; d step 3 equivalent circuit; e step 4 equivalent Vin
circuit; f step 5 equivalent circuit; g step 6 equivalent circuit vS1,g, vS2,g
vQ1,g
vS5,g
Δi
vCS4 (t) ≈ Vin − Lm (t − t5 ) (12) iLr iLm
4Coss
iS4
CS4 is discharged to zero voltage at t = Tsw + t0, and DS4 iS3
becomes forward biased. Then, the circuit operation goes to iD1
the next switching cycle.
iD2
iD3
iD4
3.2 Medium output voltage range ­(S1, ­S2 off) t0 t 1 t 2t 3
t
t4t5 Tsw+t0
(a)
Under the medium output voltage range (Fig. 3b), Q1 and S5 T
C1 + NS2 D3 V o Io
are in the on state, and S­ 1 and S
­ 2 are in the off state. Only S3 VC1 S1
DS1
CS1 S3
DS3 S5
Lr Cr T NS1D1 Co
and S4 are controlled to regulate the load voltage. Basically, +
a CS3
b Ro
Vin iLr vCr Lm CS4 NS1D2
a half-bridge resonant converter by S3, S4, Lr, Cr, T, C1 and + Q 1 S2 CS2 S4
C2 VC2 NS2 D4
C2 is used on the primary side to accomplish soft switching DS2 DS4

operation and a center-tapped rectifier with Ns1 + Ns2 sec- (b)

ondary turns is used on secondary side to obtain a much T
C1 + DS1 NS2 D3 S5 V o Io
higher output voltage. The turn ratio of the transformer in VC1 S1 CS1 S3
DS3

+ Lr Cr T NS1D1 Co
this circuit topology is n2 = Np/(Ns1 + Ns2). The DC voltage Vin
a CS3
b Ro
iLr vCr Lm CS4 NS1D2
gain for the medium output voltage range is expressed as + Q1 S2 CS2 S4
C2 VC2 NS2 D4
GM = 2n2Vo/Vin. Based on the given parameters n1 = Np/Ns1, DS2 DS4

n2 = Np/(Ns1 + Ns2), GL = 2n1Vo/Vin and GM = 2n2Vo/Vin, it can (c)

be observed that the output voltage under medium voltage
operation is greater than that under low voltage operation C1
T
NS2 D3 V o Io
+ DS1 DS3 S5
VC1 S3
due to the conditions of n1 > n2 and GL = GM. Figure 5 illus- +
S1 CS1
Lr Cr T NS1D1 Co
a CS3
Ro
trates pulse-width modulation waveforms and the equivalent Vin iLr vCr Lm
b
CS4 NS1D2
+ Q 1 S2
step circuits for medium output voltage operation. C2 VC2 DS2
CS2 S4
DS4 NS2 D4

Step 1 [t0 ≤ t < t1]: CS4 is discharged to zero voltage at

time t0, and iLr(t0) < 0. Therefore, DS4 is forward biased. The (d)
active device S4 turns on after t0 to achieve zero voltage C1 + DS1 DS3
T
NS2 D3 S5 V o Io
VC1 S1 CS1 S3
operation. In step 1, Cr and Lr are resonant, and vLm = n2Vo. + Lr Cr T NS1D1 Co
a b
CS3
Ro
In addition, iLr and vCr are calculated as: Vin
+
iLr vCr Lm CS4 NS1D2
Q 1 S2 CS2 S4
C2 VC2 DS2 DS4 NS2 D4
V ∕2 − n2 Vo − vCr (t0 )
iLr (t) = in sin 2𝜋fr (t − t0 )
Zr (13) (e)
T
+ iLr (t0 ) cos 2𝜋fr (t − t0 ) C1 + DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co
a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2
vCr (t) = Vin ∕2 − n2 Vo − [Vin ∕2 − n2 Vo − vCr (t0 )] + Q1 S2 CS2 S4
(14) C2 VC2 DS2 DS4 NS2 D4
÷ cos 2𝜋fr (t − t0 ) + iLr (t0 )Zr sin 2𝜋fr (t − t0 )
(f)
Step 2 [t1 ≤ t < t2]: At t = t1, D3 is reverse biased since T
C1 NS2 D3 V o Io
iLr = iLm. Then, the components Lm, Cr and Lr on the pri- +
VC1 S1
DS1
CS1 S3
DS3 S5
NS1D1 Co
mary side are resonant. iLr and vCr in step 2 are the same as +
a
Lr Cr T
b
CS3
Ro
Vin iLr vCr Lm
(3) and (4). + Q1 S2 CS2 S4
CS4 NS1D2

Step 3 [t2 ≤ t < t3]: The active device S4 turns off at time C2 VC2 DS2 DS4 NS2 D4

t2. Since iLr(t2) > 0 and iLr(t2) < iLm(t2), CS3 is discharged and (g)

D4 is forward biased. The capacitor voltages vCS3 and vCS4
are the same as (5) and (6).

13
 B.-R. Lin

Fig. 6  Proposed converter for the high output voltage range: a pulse- ▸ vS1,g, vS4,g vS2,g, vS3,g
width modulation waveforms; b step 1 equivalent circuit; c step 2
equivalent circuit; d step 3 equivalent circuit; e step 4 equivalent cir- vS2,d, vS3,d vS1,d, vS4,d
Vin
cuit; f step 5 equivalent circuit; g step 6 equivalent circuit vQ1,g
vS5,g

Step 4 [t3 ≤ t < t4]: CS3 is discharged to zero voltage at iLr iLm

time t3, and iLr(t3) > 0. Thus, DS3 is forward biased, and S3 iS1, iS4
turns on after t3 to achieve zero voltage operation. In step iS2, iS3
4, D4 conducts and vLm = − n2Vo. In addition, Lr and Cr are
resonant, and iLr and vCr are given as: iD1
iD2
n2 Vo − Vin ∕2 − vCr (t3 )
iLr (t) = sin 2𝜋fr (t − t3 ) iD3
Zr (15) iD4
t
+ iLr (t3 ) cos 2𝜋fr (t − t3 ) t0 t 1t 2t 3 t4t5 Tsw+t0
(a)
T
vCr (t) = n2 Vo − Vin ∕2 − [n2 Vo − Vin ∕2 − vCr (t3 )] C1 NS2 D3 V o Io
+ DS1 DS3 S5
(16) VC1 S1 CS1 S3
× cos 2𝜋fr (t − t3 ) + iLr (t3 )Zr sin 2𝜋fr (t − t3 ) + Lr Cr T NS1D1 Co
a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2
+
Step 5 [t4 ≤ t < t5]: At t = t4, iLm = iLr so that D4 is off. In Q1 S2 CS2 S4
C2 VC2 DS2 DS4 NS2 D4
this step, ­Lm, ­Lr and ­Cr are resonant, and the circuit equa-
tions are the same as (8) and (9). (b)
Step 6 [t5 ≤ t < Tsw + t0]: The active device S3 turns off C1
T
NS2 D3 V o Io
+ DS1 DS3 S5
at t = t5. Since iLr > iLm and iLr(t5) < 0, the diode D3 con- +
VC1 S1 CS1
Lr Cr T
S3
NS1D1 Co
a CS3
ducts and CS4 is discharged. When CS4 is discharged to zero Vin iLr vCr Lm
b
CS4 NS1D2
Ro

voltage at t = Tsw + t0, the circuit operation goes to the next + Q 1 S2 CS2 S4

C2 VC2 DS2 DS4 NS2 D4
switching cycle.
(c)
3.3 High output voltage range ­(Q1 off) C1
T
+ DS1 DS3 NS2 D3 S5 V o Io
VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co
Figure 3c illustrates a circuit diagram for high output range a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2
operation. Q1 is off and S5 is on. S1 ~ S4 are controlled to + Q1 S2 CS2 S4
C2 VC2 NS2 D4
perform a full-bridge resonant converter and to achieve soft DS2 DS4

switching operation. The turn ratio of the transformer in (d)

this circuit topology is n3 = Np/(Ns1 + Ns2). The DC volt- T
C1 + DS1 DS3 NS2 D3 S5 V o Io
age gain for the high output voltage range is expressed VC1 S1 CS1 S3
+ Lr Cr T NS1D1 Co
as G H = n 3V o/V in. Based on the parameters n 1 = N p/N s1 Vin
a b
CS3
Ro
iLr vCr Lm CS4 NS1D2
and n2 = n3 = Np/(Ns1 + Ns2) and the same DC voltage gain + Q1 S2 CS2 S4
C2 VC2 NS2 D4
GL = GM = GH, the output voltage under high output voltage DS2 DS4

range operation is greater than that of the other two opera- (e)
tion ranges (low and medium voltage ranges). Pulse-width T
C1 + DS1 NS2 D3 S5 V o Io
modulation waveforms and the equivalent step circuits for VC1 S1 CS1 S3
DS3

+ Lr Cr T NS1D1 Co
medium output voltage operation are given in Fig. 6. a b
CS3
Ro
Vin iLr vCr Lm CS4 NS1D2
Step 1 [t0 ≤ t < t1]: At t0, CS1 and CS4 are both discharged + Q1 S2 CS2 S4
C2 VC2 NS2 D4
to zero voltage. Since iLr(t0) < 0, DS1 and DS4 conduct. Thus, DS2 DS4

the active devices S1 and S4 turn on at this instant to realize (f)

zero voltage operation. On the primary side, Cr and Lr are T
C1 + NS2 D3 S5 V o Io
resonant and vLm = n3Vo. VC1 S1
DS1
CS1 S3
DS3

+ Lr Cr T NS1D1 Co
a b
CS3
Ro
Vin − n3 Vo − vCr (t0 ) Vin iLr vCr Lm CS4 NS1D2
iLr (t) = sin 2𝜋fr (t − t0 ) + Q1 S2 CS2 S4
Zr (17) C2 VC2 DS2 DS4 NS2 D4

+ iLr (t0 ) cos 2𝜋fr (t − t0 ) (g)

13
DC–DC converter implementation with wide output voltage operation

vCr (t) = Vin − n3 Vo − [Vin − n3 Vo − vCr (t0 )] 4 Circuit analysis

(18)
× cos 2𝜋fr (t − t0 ) + iLr (t0 )Zr sin 2𝜋fr (t − t0 )
To analyze the circuit characteristics of an LLC resonant con-
Step 2 [t1 ≤ t < t2]: ­D3 is off since iLr = iLm at t = t1. The input verter, the frequency control approach is a popular scheme to
voltage Vin, Lm, Cr and Lr are resonant on the primary side. iLr derive the relationship between the switching frequency and
and vCr in step 2 are expressed as: the voltage gain. Fundamental frequency analysis is widely
used to estimate the voltage gain of an LLC converter. To
Vin − vCr (t1 )
iLr (t) = sin 2𝜋fp (t − t1 ) + iLr (t1 ) cos 2𝜋fp (t − t1 ) accomplish wide voltage operation, three operation ranges
Zp
(low, medium and high voltages) are selected according to the
(19) status of the AC switch Q1 on the primary side, and the aux-
vCr (t) = Vin − [Vin − vCr (t1 )] cos 2𝜋fp (t − t1 ) iliary switch S5 on the secondary side. The fundamental root-
(20) mean-square magnetizing inductor voltage is calculated as:
+ iLr (t1 )Zp sin 2𝜋fp (t − t1 )
� √
Step 3 [t2 ≤ t < t3]: At time t = t2, the active devices S1 and S4 2 2n1 Vo ∕𝜋, S5 off
√
VLm,rms = (25)
turn off. Since iLr(t2) > 0 and iLr(t2) < iLm(t2), CS2 and CS3 are 2 2n2 Vo ∕𝜋, S5 on
discharged, and D4 is forward biased. The discharge time of
CS2 and CS3 is soon enough so that iLr and vCr are constant in The fundamental root-mean-square voltage on the input
this time duration. side of the resonant converter Vab,rms is calculated as:
Step 4 [t3 ≤ t < t4]: At t3, CS2 and CS3 are both discharged � √
to zero voltage. Since iLr(t3) > 0, DS2 and DS3 are conducting. 2 2Vin ∕𝜋, Q1 off
√
Vab,rms = (26)
The active devices S2 and S3 turn on at this instant to achiever 2Vin ∕𝜋, Q1 on
soft switching operation. On the primary side, Cr and Lr are
resonant and vLm = − n3Vo. The fundamental resistance on the primary side is approxi-
mately derived as:
n3 Vo − Vin − vCr (t3 )
iLr (t) = sin 2𝜋fr (t − t3 ) { 8n2 R
Zr (21) 1 o
, S5 off
+ iLr (t3 ) cos 2𝜋fr (t − t3 )
Rac = 𝜋2
8n22 Ro (27)
𝜋2
, S5 on

vCr (t) = n3 Vo − Vin − [n3 Vo − Vin − vCr (t3 )] cos 2𝜋fr (t − t3 ) The equivalent AC circuit of the resonant tank of the pro-
+ iLr (t3 )Zr sin 2𝜋fr (t − t3 ) posed converter is given in Fig. 7a. The transfer function of
(22) the resonant tank is calculated in (28) and the voltage gain is
shown in Fig. 7b.
Step 5 [t4 ≤ t < t5]: D4 is reverse biased since iLr = iLm at t = t4.
The input voltage Vin, Lm, Cr and Lr are resonant, and iLr and VLm,rms 1
vCr are given as: �G� = =�
Vab,rms � � ��2 � �2
1 + L1 1 − 1
+ Q2 F − F1
Vin + vCr (t4 ) n F2
iLr (t) = − sin 2𝜋fp (t − t4 ) + iLr (t4 ) cos 2𝜋fp (t − t4 ) 2n1 Vo
Zp ⎧ Vin
, Q1 on & S5 off
(23) ⎪ 2n2 Vo
=⎨ Vin
, Q1 & S5 on
vCr (t) = −Vin + [Vin + vCr (t4 )] cos 2𝜋fp (t − t4 ) ⎪ n3 Vo
(24) ⎩ Vin
, Q1 off & S5 on
+ iLr (t4 )Zp sin 2𝜋fp (t − t4 )
(28)
√
Step 6 [t5 ≤ t < Tsw + t0]: At time t = t5, S2 and S3 turn off. where Q = Lr ∕Cr ∕Rac is the quality factor, Ln = Lm/Lr is the
Since iLr > iLm and iLr(t5) < 0, D3 is forward biased, and CS1 inductor ratio, and F = fsw/fr is the frequency ratio. According
and CS4 are discharged. When CS1 and CS4 are discharged to to (28), the output voltage is re-written as:
zero voltage at t = Tsw + t0, the circuit operation in this cycle Ns1 Vin
is finished. Vo,low = √[ ( )]2 ( )2 (29)
1
2Np 1+ Ln
1 − F12 + Q2 F − F1

13
 B.-R. Lin

Cr Lr to the switching states of Q1 and S5, and the turn ratios

n1 ~ n3 (or secondary winding turns Ns1 and Ns2). From the
vCr iLr gain curve in Fig. 7b, the circuit works at the negative slope
of each gain curve. Then, the input impedance of the LLC
Vab,rms Lm Rac VLm,rms resonant tank is an inductive load, and the active devices are
operated at zero voltage switching to lessen the switching
loss. Based on different output voltage values, the voltage
(a) gain is changed and the switching frequency is increased
or decreased to regulate the load voltage. A higher (lower)
switching frequency increases (decreases) the core loss of
G=VLm,rms/Vab,rms the magnetic core and decreases (increases) the circulating
0.1
current loss on the primary side of the converter. The lower
0.22 Gmin output voltage needs a lower voltage gain G and a higher
2 switching frequency. If a higher load voltage is required,
the switching frequency must be decreased to obtain a high
0.3 voltage gain.

0.5 Gmax
1
5 Experimental results
1 Q=2
The developed converter was constructed and experimented
on in a laboratory prototype with Vin = 400 V, Vo = 320–40 V
0 (8:1 ratio), a resonant frequency of fr = 100 kHz and a load
0.5 1 1.5
power of Po = 400 W. To accomplish the 8:1 wide output volt-
F=fs/fr
age demand for constant power operation, a low inductor ratio
(b) (Ln = 4) and a low quality factor (Q = 0.2) at the rated power
are selected in the proposed converter. When Vo = 80–40 V
Fig. 7  Resonant tank: a AC equivalent circuit; b voltage gain curve (2:1 ratio) range, S1, S2 and S5 are off (Fig. 3a). The output
voltage Vo is obtained in (29). When Vo = 160–80 V (2:1 ratio)
(Ns1 + Ns2 )Vin range, Q1 is on and S1 and S2 are off (Fig. 3b). The output
Vo,medium = √[ ( )]2 ( )2 (30) voltage Vo is obtained in (30) with Ns2 = Ns1. Similarly, when
2Np 1+ 1
L
1 − F
1
2
+ Q2 F− 1
F
Vo = 320–160 V (2:1 ratio) range, Q1 is off (Fig. 3c) and Vo
is obtained from (31). Voltage curves of the developed 8:1
n

resonant converter are given in Fig. 8. The transition voltage

(Ns1 + Ns2 )Vin between the low and medium output voltage ranges is designed
Vo,high = √[ ( )]2 ( )2
1 1 (31) to 80 V, with a ± 5 V voltage tolerance with a Schmitt trigger
Np 1+ 1 − + Q2 F− 1
L n F2 F circuit. Likewise, the transient voltage between the medium
and high output voltage ranges is designed to be 160  V.
From (28) to (30), the proposed converter can have three Schmitt comparators and logic gates can be used to generate
output voltage ranges (Vo,low, Vo,medium, and Vo,high) according proper PWM signals for each of the output voltage ranges. For

Vo.low S1, S2, S5 off Vo.medium S1, S2 off Vo.high Q1 off

0.1 Ln=Lm/Lr=4 0.1 0.1
0.2 0.2 0.2
80 160 320
Vo=80V Vo=160V Vo=320V
0.3 2:1 voltage ratio 0.3 2:1 voltage ratio 0.3 2:1 voltage ratio
0.5 Vo=40V 0.5 Vo=80V 160 0.5 Vo=160V
40 80
1 Q=2 1 Q=2 1 Q=2

0 0 0
0.5 1 1.5 0.5 1 1.5 0.5 1 1.5
F=fs/fr F=fs/fr F=fs/fr

Fig. 8  Output voltage curves of the proposed 8:1 (Vo = 40–320 V) resonant converter with three different operation ranges

13
DC–DC converter implementation with wide output voltage operation

each output voltage range, the transfer function of the voltage Table 1  Circuit components and parameters of the adopted prototype
gain G in (28) is identical to the minimum voltage gain at unity circuit
and the maximum voltage gain at two. Therefore, the design Components Parameters
procedure for the three voltage ranges are the same. For the
Transformer, Np:Ns1:Ns2 50:10:10
low output voltage range, the active devices S1, S2 and S5 are
Inductor ratio, Ln = Lm/Lr 4
off, the half-bridge circuit topology is used on the primary
Quality factor, Q 0.2
side and low winding turns Ns1 are used on the secondary side.
Resonant inductor, Lr 103 μH
The minimum voltage is Vo,min = 40 V and the maximum
Resonant capacitance, Cr 24.6 nF
load voltage is Vo,max = 80 V. The minimum voltage gain Gmin
Magnetizing inductance, Lm 412 μH
is expected at unity in the 40 V output case. From (28), the
Input split capacitances, C1, C2 300 μF/400 V
theoretical turn ratio n1 is obtained as:
Output capacitance, Co 660 μF/400 V
Gmin Vin 1 × 400 MOSFETs, S1 ~ S5, Q1 FMW60N099S2H
n1 = = =5 (32) (600 V/24 A)
2Vomin 2 × 40
Diodes, D1 ~ D4 STTH810FP (1000 V/8 A)
A transformer T with primary turns Np = 50 and secondary
turns Ns1 = 10 and Ns2 = 10 is implemented by a TDK EER 42
core. The rated resistance on the load side under Vo = 80 V is
S3
derived as:
S4
AND Gate
Vo2 802 Gate Driver
S2
Ro = = = 16𝛺 (33) Voltage Controller
(TL431+PC817) UCC25600
Po 400
AND Gate
S1
Gate Driver
From (27), the fundamental resistance on the primary side Gate
Vo S5
of the transformer for low output voltage operation is obtained 80 V Driver

as: Voltage Follower Schmitt Trigger

Optocoupler
Driver
NOT
Gate
Gate
8n21 Ro Driver
Q1
Rac = ≈ 324𝛺 (34) 160 V
Optocoupler
𝜋2 Schmitt Trigger
Driver

From the voltage curves in Fig. 8, the load voltage can be

well regulated under Q = 0.2. Due to the given resonant fre- Fig. 9  Control block of the proposed converter
quency at 100 kHz, the inductor ratio Ln = 4 and the quality
factor Q = 0.2, the resonant components are obtained as:
VD1,stress = VD2,stress = Vo,max + Vo,max Ns1 ∕(Ns1 + Ns2 ) = 480 V
QRac 0.2 × 324 (41)
Lr = = ≈ 103 μH (35)
2𝜋fr 2𝜋 × 100, 000
VD3,stress = VD4,stress = 2Vo,max = 640 V (42)

1 1 FMW60N099S2H MOSFETs (600 V/24 A) are used for

Cr = = ≈ 24.6 nF
4𝜋 2 Lr fr2 4𝜋 2 × 103 × 10−6 × (100, 000)2 S1 ~ S5 and Q1, and STTH810FP diodes (1000 V/8 A) are
(36) adopted for D1 ~ D4. The input and output capacitances are
C1 = C2 = 300 μF/400 V and Co = 660 μF/400 V. Table 1
Lm = Lr Ln = 103 × 4 = 412 μH (37)
shows the calculated circuit parameters in the adopted pro-
Since the half-bridge leg and center-tapped rectifier are totype circuit. A control block diagram of the proposed con-
used on the primary side and secondary side, the voltage verter is given in Fig. 9. PWM waveforms are generated
stresses of the power semiconductors are expressed as: by a frequency modulation controller using a UCC25600.
Schmitt comparators and logic gates are used to select the
VS1,stress = ⋯ = VS4,stress = Vin = 400 V (38) half-bridge or full-bridge resonant circuit.
Constant power control is adopted to regulate the load
VQ1,stress = Vin ∕2 = 200 V (39) voltage. If the load voltage is increased, the load current
and switching frequency are decreased to keep the 400 W
output condition. Figure 10 gives measured waveforms at
VS5,stress = Vo,low (Ns1 + Ns2 )∕(Ns1 ) − Vo,low = 80 V (40)
a 40 V output voltage under the rated power. In this low
output voltage range, only the active devices S3 and S4 are

13
 B.-R. Lin

vS3,g vS3,g

10V
10V
iD1 iD3

10A
vS4,g vS4,g

5A
10V

10V
iD2 iD4

10A

5A
vCr vCr Io

500V
Io

500V
Vo

50V 10A
Vo

100V 5A
iLr iLr

5A

5A
4 µs 4 µs 4 µs 4 µs

(a) (b) (a) (b)

Fig. 10  Measured results at Vo = 40  V and 400  W: a vS3,g, vS4,g, vCr, Fig. 13  Measured results at Vo = 85  V and 400  W: a vS3,g, vS4,g, vCr,
iLr; b iD1, iD2, Io, Vo iLr; b iD3, iD4, Io, Vo

vS4,g vS3,g

10V
vS3,g iD3
vS4,g

10V
10V

5A
vS3,d vS4,d

10V
iD4

200V
200V

5A 5A
vCr

500V
Io
iS3 iS4 Vo

200V
5A
iLr

5A
5A

ZVS 2 µs ZVS 2 µs 4 µs 4 µs

(a) (b) (a) (b)

Fig. 11  Measured results of S3 and S4 at Vo = 40 V and 400 W: a vS3,g, Fig. 14  Measured results at Vo = 155 V and 400 W: a vS3,g, vS4,g, vCr,
vS3,d,iS3; b vS4,g, vS4,d, iS4 iLr; b iD3, iD4, Io, Vo

vS1,g vab

500V
10V
vS3,g vS2,g
10V

iD1

10V
vS4,g
10A

500V
vS3,g vCr
10V

iD2
10A 10A

vCr vS4,g 10V iLr

500V

5A
Io
10V

Vo
100V

iLr 4 µs 4 µs
5A

4 µs 4 µs (a) (b)
(a) (b) iD3
5A
Fig. 12  Measured results at Vo = 75  V and 400  W: a vS3,g, vS4,g, vCr,
iD4 5A

iLr; b iD1, iD2, Io, Vo Io

5A

Vo
200V

controlled to regulate the output voltage, and the diodes

4 µs
D3 and D4 are reverse biased. The voltage gain is close to
unity at the 40 V output condition so that the switching fre- (c)
quency is near the series resonant frequency, and iLr and
vCr are almost sinusoidal waveforms. No reverse recovery Fig. 15  Measured results at Vo = 165  V and 400  W: a vS1,g ~ vS4,g; b
vab, vCr, iLr; c iD3, iD4, Io, Vo
loss is observed on D1 and D2. Figure 11 gives experimental
waveforms of S3 and S4 at the 40 V output condition. It is
clear that both of the switches have the zero voltage turn-on is required under medium output voltage range operation
switching characteristic. Figures 12 and 13 show test results (Fig. 3b). Likewise, measured waveforms at output volt-
at 75 V and 85 V for the low output voltage range (S1, S2 ages of 155 V (medium output voltage range) and 165 V
and S5 are off) and medium output voltage range (S1 and S2 (high output voltage range) are illustrated in Figs. 14 and
are off), respectively. It can be observed that the measured 15, respectively. The diodes D1 and D2 are both off, and D3
waveforms at Vo = 75 V have a low switching frequency and D4 are conducting. Figure 16 shows experimental wave-
since a high voltage gain is needed under low output volt- forms of the major voltages and currents at Vo = 320 V. Fig-
age range operation (Fig. 3a). Test waveforms at Vo = 85 V ure 17a shows test results between the voltage variations of
have a high switching frequency since a low voltage gain 240 V and 320 V at Io = 1.25 A. Measured efficiencies of the

13
DC–DC converter implementation with wide output voltage operation

vS1,g vab rectifier diodes and transformer windings, and the converter

10V

500V
vS2,g efficiency is decreased. Figure 17b shows measured efficien-

10V
cies under various loads and output voltages.
vS3,g vCr

500V
10V
vS4,g iLr

10A
10V
6 Conclusions
4 µs 4 µs

(a) (b)
A new wide output voltage range soft switching DC–DC
iD3
converter is studied and implemented. To satisfy wide output

5A
iD4 voltage requirements, a hybrid resonant converter includ-

5A
ing a half-bridge and a full-bridge converter is adopted on
Io the primary side. Since the fundamental root-mean-square
5A
Vo voltage of the full-bridge converter is two times of the volt-
200V
4 µs age of the half-bridge converter and additional doubler sec-
(c) ondary winding turns are used on the output side, an 8:1
(vo,max = 8vo,min) DC–DC resonant converter is accomplished
Fig. 16  Measured results at Vo = 320  V and 400  W: a vS1,g ~ vS4,g; b in the developed circuit. To achieve wide voltage operation,
vab, vCr, iLr; c iD3, iD4, Io, Vo the proposed converter has three output voltage operation
ranges: low voltage, medium voltage and high voltage,
which are selected by an AC switch on the primary side
Vo (to select half-bridge or full-bridge operation) and a power
100V

switch on the secondary side (to select low winding turns or

doubler winding turns). Since an LLC resonant converter is
constructed in the developed circuit, soft switching turn-on
operation of all the power switches is achieved and the zero
Io current turn-off switching of the rectifier diodes is realized.
Experiments are presented to validate the system analysis
1A

1ms and to demonstrate the performance of the proposed soft

(a) switching hybrid converter.

96 Acknowledgement  This research is supported by the Ministry of Sci-

94 ence and Technology, Taiwan, under contract MOST 108-2221-E-224-
022-MY2. The author would like to thank Mr. Yue Lin for his help to
Efficiency (%)

92 measure the circuit waveforms in the experiment.

90
88
86 References
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16. Wu, H., Zhan, X., Xing, Y.: Interleaved LLC resonant converter and 2018 from the College of Engineering, National Yunlin University
with hybrid rectifier and variable-frequency plus phase-shift con- of Science and Technology. He received Best Paper Awards from the
trol for wide output voltage range applications. IEEE Trans. Power 2007 and 2011 IEEE-International Conference on Industrial Electron-
Electron. 32(6), 4246–4257 (2017) ics and Applications (ICIEA), the 2007 Taiwan Power Electronics
17. Qian, T., Qian, C.: A combined topology with coupled LLC reso- Conference, the 2009 IEEE-Power Electronics and Drive Systems Con-
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