Fpga Implementation of Neural Networks: Main Contents
Fpga Implementation of Neural Networks: Main Contents
Fpga Implementation of Neural Networks: Main Contents
FPGA
•
Implementation of
Neural Networks: A Brief Introduction
• Practical Example: Character Recognition using MATLAB
• VHDL: An Instant Approach
Neural Networks •
•
A Neuron Implementation
Activation Function Implementation
• Overview of the Implemented Network
Presented by Nariman Dorafshan
Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
Computational Intelligence
Neural Networks • A branch of AI, which implements the nature inspired algorithms is called
computational intelligence.
• Introduction to Neural Networks • Its goal is to find ways for System Modeling, Pattern Recognition, Series
o Computational Intelligence Prediction, Optimization, etc.
o Artificial Neuron • Understanding the performance of brain inspired the creation of artificial neural
o Network Structures networks (ANNs) as an information processing system to generate human
• MLP & Back-propagation recognition models based on biological nervous systems.
o Regulation
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
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Biological Neuron Artificial Neural Networks (ANNs)
• A single biological neuron is composed of three major parts including the cell • An artificial neuron network (ANN) is an information-processing system that has
body (called soma), the axon, and the dendrite. certain performance characteristics in common with biological neural networks.
• The cell body of a neuron is connected to the dendrite of a neighbouring neuron.
• Based on examples, together with some feedback from a “teacher,” we learn easily
• Signal communications between neurons are continuously generated which is
delivered from one neuron to the others by firing an electrical signal generated to recognize the letter A or distinguish a cat from a bird.
through a chemical reaction.
• More experience allows us to refine our responses and improve our performance.
• The other neurons receive the signal through the interfaces with the neighbouring
neurons, referred to as a synapse. • Although eventually, we may be able to describe rules by which we can make such
• This system is capable of learning, recalling, and
decisions, these do not necessarily reflect the actual process we use.
generating output corresponding to external signals.
• Even without a teacher, we can group similar patterns together.
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
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Artificial Neuron Characteristics & Applications
• Each neuron is connected to other neurons by means of directed communication • A neural network is characterized by:
links, each with an associated weight, o Its pattern connections between the neurons (called architecture)
• The weights represent information being used by the net to solve a problem. o Its method of determining the weights on the connections (called training, or
learning algorithms)
o Its activation function
• Those above also depends on training data spaces.
• Neural nets can be applied to a wide variety of problems, such as storing and
recalling data or patterns, classifying patterns, performing general mappings
from input patterns to output patterns, grouping similar patterns (clustering), or
finding solutions to constrained optimization problems.
• Most common applications lies in “Fitting a Function”, “Recognizing Patterns”,
“Clustering Data”, and “Time Series Prediction”.
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
• Unsupervised training:
A sequence of input vectors is provided, but no target vectors are specified. 1 n 0
a f ( n)
The net modifies the weights so that the most similar input vectors are 0 n 0
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Activation Functions Network Structures: Connections
• Multiple neurons are interconnected to form a network to facilitate distributed
computing.
• This configuration can be described with a directed graph.
1
a f (n) n a f ( n)
1 e n • Based on the applications, we use appropriate structure with regards to training
data spaces, learning algorithms, etc.
• As is the case with most neural networks, the aim is to train the net to achieve a
balance between the ability to respond correctly to the input patterns that are
used for training (memorization) and the ability to give reasonable responses to
1 en
a f ( n) e n
2
a f ( n)
1 e n input that is similar, but not identical, to that used in training (generalization).
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MLP & Back-propagation MLP & Back-propagation
• For problems that involve mapping a given set of inputs to a specified set of target
outputs (which is supervised learning), using a multi-layer perceptron is very
common.
• The goal is to achieve a balance between:
o respond correctly to the input patterns that are used for training (memorization)
o give reasonable responses to input that is similar, but not identical, to that used in
training (generalization)
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Universal Approximators Universal Approximators
• One use of neural network is to approximate a continuous mapping f. • Kolmogorov Mapping Neural Network Existence Theorem:
A powerful tool for modelling the issues in which the relations between A feedforward neural network with two layers of neurons (input units, a sigmoid
different variables present no clearly defined forms. layer and a linear output layer) can represent any function with a finite number
of discontinuities.
Very important in modelling the laboratory samples.
• The question is, how well a multilayer net can perform this task?
o How many layer?
o How many units?
o What about precision?
o Which structure? This network can be used as a general function approximator.
It can approximate any function with a finite number of discontinuities arbitrarily well,
given sufficient neurons in the hidden layer.
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
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NN Location in process Input Vectors
• In pre-processing unit, input forms has been converted into binary strings.
0011000
0001000
0001000
0010100
0010100
0111110
0100010
0100010
• Pre-processing units such as image processing units, databases, , filters, and etc., 0100010
provide usable data for NN unit. It may be even a manual process. 1110111
They extract input vectors from raw data.
• Post-processing units may be used for inference & decision making, optimization,
Input String:
data compression, etc.
0011000000100000010000010100001010001111100100010010001001000101110111
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Other Input Vectors Neural Networks: Any Questions?
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VHDL Basics: Library VHDL Basics: Entity
• A collection of commonly used pieces of code. Placing such pieces inside a library
• A list with specifications of all input and output pins (PORTS) of the circuit.
allows them to be reused or shared by other designs.
• Signal Modes:
• Entity: something which exists apart from other things, having its own
independent existence.
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VHDL Basics: Arrays VHDL Basics: Port Array
• To specify a new array type: • There are no pre-defined data types of more than one dimension.
• We might need to specify the ports as arrays of vectors, in the specification of the
• 1D×1D array example: The leftmost bit is MSB
input or output pins (PORTS).
• The solution is to declare user-defined data types in a PACKAGE. It will be visible
to the whole design (the TYPE declarations are not allowed in an ENTITY).
• 2D array example: The topmost row is row 0
• Array initialization:
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VHDL Basics: Operations VHDL Design Styles (Architecture)
VHDL Design
Styles
(BEHAVIORAL)
NON-
DATAFLOW STRUCTURAL SYTHESIZABLE
SYNTHESIZABLE
“concurrent” components and “sequential” statements
statements interconnects • State machines
• Gates • Registers
• The constructs that are not synthesizable (or have little synthesis support) are • Simple Comb. Logic • Complex Comb. Logic
marked with the “ ” symbol.
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VHDL Behavior Models Concurrent Mechanism
Concurrent Sequential • Basic granularity of concurrency is the process
o Processes are executed concurrently
o Concurrent signal assignment statements are one-line processes.
• Mechanism for achieving concurrency:
o Processes communicate with each other via signals.
o Signal assignments require delay before new value is assumed.
o Simulation time advances only when all active processes complete.
o Effect is concurrent processing.
VHDL provides concurrent statements using • So, the order in which processes are actually executed by simulator does
`structural’ statements and serial operations using not affect behaviour.
`behavioral statements’.
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Data Values Data Values: Generics
• VHDL provides objects for dealing with values: • A generic parameter is a static parameter that can be easily modified and adapted
o For established (static) values: CONSTANT and GENERIC to different applications. The purpose is more flexibility and reusability.
o For non-static data values: SIGNAL and VARIABLE • A GENERIC statement must be declared in the ENTITY.
• The specified parameter will be truly global (visible to the whole design).
• CONSTANT
o Serves to establish default values.
• Example:
o Can be global (seen by the whole code)
o Can be declared in a PACKAGE, ENTITY, or ARCHITECTURE.
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Data Values: Signals Data Values: Variables
• When used inside a section of sequential code (e.g. PROCESS) • Represents only local information.
Its update is not immediate. o Can only be used inside a sequential code.
Its new value should not be expected to be ready before the corresponding o Its declaration can only be done in the declarative part of a sequential code.
PROCESS, FUNCTION or PROCEDURE. o Its values can not be passed out directly. It must be assigned to a SIGNAL first.
• Its update is immediate.
o The new value can be promptly used in the next line of code.
FPGA Implementation of Neural Networks Semnan University – Spring 2012 FPGA Implementation of Neural Networks Semnan University – Spring 2012
Data Values: Signals vs. Variables Examples: DFF plus NAND gate
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Examples: Sine Wave Generation Examples: ALU
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Memory Design: ROM VHDL: Any Questions?
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A Layer Structure: Description Small Scale Approach
• This approach is appropriate for general purpose NNs (that is, with
programmable weights). • Has the advantage of being simple, easily understandable, and self contained in
• It employs only one input to load all weights (thus saving on chip pins). the main code.
• The weights are shifted in sequentially until each register is loaded with its • Its limitation is that the inputs (x) and outputs (y) are specified one by one.
respective weight.
• The weights are then multiplied by the inputs and accumulated to produce the
desired outputs.
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Small Scale Approach: Architecture Large Scale Approach
• We use a more generic approach which is appropriate for large scale networks.
• The idea is to use arrays for representing inputs, outputs, and weights.
• Since type declaration is not permitted in the entity, we use a package for it.
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Large Scale Approach: Architecture Neuron Implementation:Any Questions?
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Implementation Problem
Activation Function Implementation • The sigmoid and hyperbolic tangent functions are usually used as the activations
in ANNs.
• Straightforward implementation of these functions in hardware is not practical
due to their exponential nature.
• Implementation Problem
• Several different approaches exist for this hardware approximation, including
• Look-Up Tables (LUT) lookup tables (LUT), piecewise linear approximation, piecewise non-linear
approximation, and hybrid methods.
• Linear Approximation Methods
• Range Addressable LUTs (RALUT)
• Hybrid Methods
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Lookup Tables (LUT) Piecewise Linear Approximation
• Generally, LUT implementations are the fastest, while they consume a large area of • Piecewise linear approximations are slow, but consume less area; they are also the
silicon. most common way of implementing the activation functions.
• They are based on ROM design. Get an input range or input address.
LUT RALUT
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Activation Function: Any Questions?
The Entire Design
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Any Questions?
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