Lecture2 PDF
Lecture2 PDF
Lecture2 PDF
Spring 2018
Digital Design and Integrated
Circuits
Instructors:
N. Weaver & J. Wawrzynek
Lecture 2
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Class Schedule - UPDATE
❑ Discussions: Friday 11am-12, 106 Moffit Library
❑ LAB A (ASIC):
▪ W 5-8pm (125 Cory) - Taehwan
❑ LAB B (FPGA):
▪ W 2-5pm (125 Cory) - Arya
▪ Th 2-5pm (125 Cory) - Arya
❑ Office Hours:
▪ Nick : Mo 1-3pm - 329 Soda
▪ John : Tu, Th 2:30pm-3:30pm - 631 Soda
▪ Taehwan: TBD
▪ Arya: TBD
❑ Homework out today, due: next Friday at 11:59PM
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Schedule for this week
❑ First discussion this Friday
❑ Labs starting this week
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Outline
❑ Methodology Basics
❑ Digital Logic – Basic Concepts
❑ Early Design
❑ Design Implementation
Alternatives
❑ Design Flows
❑ ASICs
❑ FPGAs
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Methodology Basics
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Basic Design Tradeoffs
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Design Space & Optimality
“Pareto Optimal” Frontier
Performance
(tasks/sec)
high-performance at high-cost
Cost (# of components)
low-performance at low-cost
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Design Methodologies
❑ Top-Down Design
▪ Starts at the top (root) and works down
by successive refinement.
❑ Bottom-up Design
▪ Starts at the leaves & puts pieces
together to build up the design.
❑ Which is better?
▪ In practice both are needed & used
▪ Top-down to handle the complexity
(divide and conquer)
▪ Bottom-up since structure influenced by
available primitives
(in a well designed system)
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Digital Logic
Basic Concepts
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Digital Integrated Circuit Example
• (Old) PowerPC microprocessor micro-
photograph
– Superscalar (3 instructions/cycle)
– 6 execution units (2 integer and 1 double
precision IEEE floating point)
– 32 KByte Instruction and Data L1 caches
– Dual Memory Management Units (MMU)
– External L2 Cache interface with integrated
controller and cache tags.
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Clock Signal
Τ represents the
time of one clock
“cycle”.
❑ Waveform diagram shows evolution of signal value (in voltage) over time.
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Data Signals Random adder circuit at a
random point in time:
Observations:
• Most of the time, signals are in
either low- or high-voltage position.
• When the signals are at the high-
or low-voltage positions, they are
not all the way to the voltage
extremes (or they are past).
• Changes in the signals correspond
to changes in clock signal (but don’t
change every cycle).
The facts:
1. Low-voltage represents binary 0 and high-voltage, binary 1.
2. Circuits are designed and built to be tolerant of noise and “restoring”.
Deviations from ideal voltages are ignored. Outputs close to ideal.
3. In synchronous systems, all changes follow clock edges.
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Circuit Delay
Digital circuits cannot produce
outputs instantaneously.
❑ In general, the delay through a
circuit is called the propagation
delay. It measures the time
from when inputs arrive until the
outputs change.
❑ The delay amount is a function
of many things. Some out of
the control of the circuit
designer:
▪ Processing technology, the
particular input values.
❑ And others under her control:
▪ Circuit structure, physical
layout parameters.
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Combinational Logic Blocks
abcd y
Example four-input function: 0000 F(0,0,0,0)
0001 F(0,0,0,1)
0010 F(0,0,1,0)
0011 F(0,0,1,1)
0100 F(0,1,0,0)
0101 F(0,1,0,1)
0110 F(0,1,1,0)
1111 F(0,1,1,1)
1000 F(1,0,0,0)
1001 F(1,0,0,1)
❑ Output a function only of the 1010 F(1,0,1,0)
1011 F(1,0,1,1)
current inputs (no history). 1100 F(1,1,0,0)
❑ Truth-table representation of 1101 F(1,1,0,1)
function. Output is explicitly 1110 F(1,1,1,0)
1111 F(1,1,1,1)
specified for each input
combination.
❑ In general, CL blocks have more Truth Table
than one output signal, in which
case, the truth-table will have
multiple output columns.
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Example CL Block
a1 a0 b1 b0 c2 c1 c0
❑ 2-bit adder. Takes two 2-bit 00 00 000
integers and produces 3-bit 00 01 001
result. 00 10 010
00 11 011
01 00 001
01 01 010
01 10 011
01 11 100
10 00 010
10 01 011
10 10 100
10 11 101
11 00 011
❑ Think about truth table for 32-bit 11 01 100
adder. It’s possible to write out, 11 10 101
but it might take a while! 11 11 110
❑ Logic gates are often the primitive elements out of which combinational
logic circuits are constructed.
▪ In some technologies, there is a one-to-one correspondence between logic
gate representations and actual circuits (ASIC standard cells have gate
implementations).
▪ Other times, we use them just as another abstraction layer (FPGAs have no
real logic gates).
❑ How about these gates with more than 2 inputs?
❑ Do we need all these types?
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Example Logic Circuit
abc y
000 0
001 0
a
010 0
b y 011 1
100 0
c
101 1
110 1
111 1
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Logic Gate Implementation
❑ Logic circuits have been built out of many different
technologies. If we have a basic logic gate (AND or OR)
and inversion we can build a complete logic family.
DTL
Hydraulic
CMOS Gate
Mechanical LEGO logic gates.
A clockwise rotation
represents a binary “one” while
a counter-clockwise rotation
represents a binary “zero.”
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Restoration/Regeneration
❑ A necessary property of any suitable technology for logic
circuits is "Restoration” or “Regeneration”
❑ Circuits need:
▪ to ignore noise and other non-idealities at the their inputs, and
▪ generate "cleaned-up" signals at their output.
❑ Otherwise, each stage propagates input noise to their
output and eventually noise and other non-idealities would
accumulate and signal content would be lost.
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Inverter Example of Restoration
Example (look at 1-input gate, to keep it simple):
Actual Inverter
Idealize Inverter
VIN VOUT
clock
Address
• Sometimes used in
Register file large groups by
Input Data or themselves for
Write Control Memory Block “long-term” data
Output Data storage.
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Early Design
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IC Design in the 70’s and early 80’s
❑ Circuit design, layout, and processing tightly linked.
❑ Logic design and layout was all done by-hand in an ad-hoc way
❑ Chip design was the domain of industry (Fairchild, Intel, Texas Instruments, …). These
were IC processing companies. Those who controlled the physics controlled the
creative agenda!
Federico Faggin,
Ted Hoff,
Stan Mazor
Introduced to
help sell memory
chips!
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Geometric Design Rules
❑ Early on, to generate the mask information for fabrication, the designer
needed intimate knowledge of the manufacturing process. Even once
this knowledge was distilled to a set of “Geometric Design Rules”, this
set of rules was voluminous with many special cases.
❑ Academics (C. Mead and others) came up with a much simplified set of
design rules (single page description). A sort of “API” or abstraction of
the process (back-end processing could automatically convert this
information into masks).
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Early ’80’s Design Methodology and Flow
Specification
Schematic + Full-
Custom Layout Transistor Schematics
▪ SPICE for timing,
▪ switch-level simulation for switch
overall functionality, SPICE
simulator
▪ hand layout,
▪ no power analysis, hand
▪ layout verified with geometric layout
Design Rule Checker (DRC)
and later also Layout versus CIF file
Schematic (LVS) Checkers
layout
vs. geometric
schematic design rule
checker
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Computer Aided Design (2)
❑ For some time after CIF was invented: Layout was generated
by hand, then typed in as a CIF file with a text editor.
❑ Layout compilers
– Soon some designers started embedding CIF primitives in
conventional programming languages: LISP, pascal, fortran, C.
– This allows designers to write programs that generated layout.
Such programs could be parameterized:
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Implementation Alternative Summary
All circuits/transistors layouts optimized for
Full-custom:
application.
Arrays of small function blocks (gates, FFs)
Standard-cell:
automatically placed and routed.
A. DeHon
• General Principles
Earlier the decision is bound, the less area, delay/energy
required for the implementation.
Later the decision is bound, the more flexible the device. 34
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Full-Custom
❑ Circuit styles and transistors are custom
sized and drawn to optimize die, size, power,
performance.
❑ High NRE (non-recurring engineering) costs
▪ Time-consuming and error prone layout
❑ Hand-optimizing the layout can result in
small die for low per unit costs, extreme-low-
power, or extreme-high-performance.
❑ Common today for analog design.
❑ Requires full set of custom masks.
❑ High NRE usually restricts use to high-
volume applications/markets or highly-
constrained and cost insensitive markets.
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Standard-Cell*
❑ Based around a set of pre-designed (and verified) cells
▪ Ex: NANDs, NORs, Flip-Flops, counters slices, buffers, …
❑ Each cell comes complete with:
▪ layout (perhaps for different technology nodes and processes),
▪ Simulation, delay, & power models.
❑ Chip layout is automatic, reducing NREs (usually no hand-layout).
❑ Less optimal use of area and power, leading to higher per die costs than
full-custom.
❑ Commonly used with other design implementation strategies (large
blocks for memory, I/O blocks, etc.)
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Gate Array
❑ Prefabricated wafers of “active” & gate layers & local
interconnect, comprising, primarily, rows of transistors. Customize
as needed with “back-end” metal processing (contact cuts, metal
wires). Could use a different factory.
❑ CAD software understands how to make gates and registers.
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Gate Array
• Shifts large portion of design and mask NRE to vendor.
• Shorter design and processing times, reduced time to market for
user.
• Highly structured layout with fixed size transistors leads to large
sub-circuits (ex: Flip-flops) and higher per die costs.
• Memory arrays are particularly inefficient, so often prefabricated,
also:
Sea-of-gates,
structured ASIC,
master-slice.
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Field Programmable Gate Arrays (FPGA)
■ Two-dimensional
array of simple logic-
and interconnection-
blocks.
■ Typical architecture:
Look-up-tables (LUTs)
implement any
function of n-inputs
(n=3 in this case).
■ Optional connected
Flip-flop with each
LUT.
❑ Fuses, EPROM, or Static RAM cells are used to store the “configuration”.
▪ Here, it determines function implemented by LUT, selection of Flip-flop, and
interconnection points.
❑ Many FPGAs include special circuits to accelerate adder carry-chain and
many special cores: RAMs, MAC, Enet, PCI, SERDES, CPUs, ... 39
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FPGA versus ASIC
FPGA
total
cost ASIC
ASICs cost
FPGAs cost effective
effective
volume
• ASIC: Higher NRE costs (10’s of $M). Relatively Low cost per
die (10’s of $ or less).
• FPGAs: Low NRE costs. Relatively low silicon efficiency ⇒
high cost per part (> 10’s of $ to 1000’s of $).
• Cross-over volume from cost effective FPGA design to ASIC
was often in the 100K range.
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Microprocessors
❑ Where relatively low performance and/or
high flexibility is needed, a viable
implementation alternative:
▪ Software implements desired function
▪ “Microcontroller”, often with built in nonvolatile
program memory and used as single function.
❑ Furthermore, instruction set processors are
an “abstraction” level. Two ways:
▪ Instruction Set Architecture (ISA)
▪ “Synthesizable” RTL model (“soft core”, available
in HDL)
❑ Their implementation hosted on a variety of
implementation platforms: standard-cell,
gate-array, FPGA, other processors?
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System-on-chip (SOC)
• Brings together: standard cell blocks,
custom analog blocks, processor cores,
memory blocks, embedded FPGAs, …
• Standardized on-chip buses (or
hierarchical interconnect) permit “easy”
integration of many blocks.
– Ex: AXI, AMBA, Sonics, …
• “IP Block” business model: Hard- or soft-
cores available from third party designers.
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FPGA: Xilinx Virtex-5 XC5VLX110T
Virtex-5 “die photo”
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FPGA Overview
❑ Basic idea: two-dimensional array of logic blocks and flip-flops with a
means for the user to configure (program):
1. the interconnection between the logic blocks,
2. the function of each block.
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Why are FPGAs Interesting?
❑ Staggering logic capacity growth (10000x):
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Why are FPGAs Interesting?
▪ Logic capacity now only part of the story: on-chip
RAM, high-speed I/Os, “hard” function blocks, ...
▪ Modern FPGAs are “reconfigurable systems”
10GBps Serdes
Ethernet MACs
64 ALUs
148 36Kb SRAM Blocks
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FPGAs are in widespread use
Far more designs are implemented
in FPGA than in custom chips.
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User Programmability
• Latch-based (Xilinx, Altera, …) ❑ Latches are used to:
1. control a switch to make or
break cross-point
connections in the
interconnect
2. define the function of the
logic blocks
3. set user options:
+ reconfigurable
– within the logic blocks
– volatile
– in the input/output blocks
– relatively large.
– global reset/clock
❑ “Configuration bit stream” is
loaded under user control
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Background (review) for upcoming
❑ A MUX or multiplexor is a combinational logic circuit
that chooses between 2N inputs under the control of N
control signals.
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Idealized FPGA Logic Block
Function defined by
configuration bit-stream
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4-LUT Implementation
❑ n-bit LUT is implemented as a 2n x 1
memory:
▪ inputs choose one of 2n memory
locations.
▪ memory locations (latches) are
normally loaded with values from
user’s configuration bit stream.
▪ Inputs to mux control are the CLB
inputs.
❑ Result is a general purpose “logic
gate”.
▪ n-LUT can implement any function of
n inputs!
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LUT as general logic gate
Example: 4-lut
❑ An n-lut as a direct implementation of a
function truth-table.
❑ Each latch location holds the value of
the function corresponding to one input
combination.
Example: 2-lut
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FPGA Generic Design Flow
• Design Entry:
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Example Partition, Placement, and Route
• Idealized FPGA structure: ❑ Example Circuit:
▪ collection of gates and flip-flops
A B
Two partitions. Each has single output, no more than 4 inputs, and
no more than 1 flip-flop. In this case, inverter goes in both partitions.
Note: the partition can be arbitrarily large as long as it has not more
than 4 inputs and 1 output, and no more than 1 flip-flop.
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Xilinx FPGAs (interconnect detail)
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