0% found this document useful (0 votes)

489 views

Maintenance Manual: MANUAL NUMBER 006-15563-0001 Revision 1 May, 2003

CMM

Uploaded by

ALEXANDER ROBLES

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

489 views

Maintenance Manual: MANUAL NUMBER 006-15563-0001 Revision 1 May, 2003

CMM

Uploaded by

ALEXANDER ROBLES

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 288

MAINTENANCE MANUAL

KT 73
MODE S
TRANSPONDER

MANUAL NUMBER 006-15563-0001

REVISION 1 MAY, 2003
WARNING
The enclosed technical data is eligible for export under License Designation NLR and is to be
used solely by the individual/organization to whom it is addressed. Diversion contrary to U.S. law
is prohibited.

©2003 Honeywell International Inc.

Reproduction of this publication or any portion thereof by any means without the express written
permission of Honeywell is prohibited. For further information contact the manager, Technical
Publications, Honeywell, One Technology Center, 23500 West 105th Street Olathe KS 66061
telephone: (913) 712-0400.
B KT 73

REVISION HISTORY
KT 73 Maintenance Manual

Part Number: 006-15563-XXXX

For each revision, add, delete, or replace pages as indicated.

REVISION: Rev. 0, April/2003

ITEM ACTION
New manual No previous manual revision exists.

REVISION: Rev. 1, May/2003

ITEM ACTION
Full Reprint Replaces revision 0.

Rev. 1, May/2003 15563M01.JA Page RH-1

B KT 73

THIS PAGE IS RESERVED

Rev. 1, May/2003 15563M01.JA Page RH-2

4-1 MODE S TRANSPONDER SYSTEM, SIMPLIFIED BLOCK DIAGRAM 4-2

4-2 ATCRBS INTERROGATION PULSES FORMAT 4-4
4-3 ATCRBS/MODE S ALL-CALL FORMAT 4-4
4-4 SIDE LOBE SUPPRESSION CHARACTERISTICS 4-5
4-5 MODE S INTERROGATION, UPLINK FORMAT 4-6
4-6 UPLINK FORMATS 4-7
4-7 ATCRBS AND MODE S REPLY FORMAT 4-11
4-8 DOWNLINK FORMATS 4-13
4-9 1090 MHz ADS-B SYSTEM 4-24
4-10 KT 73 BLOCK DIAGRAM 4-25
4-11 KT 73 INTERNAL INTERCONNECTION DIAGRAM 4-27
4-12 RECEIVER BOARD BLOCK DIAGRAM 4-30
4-13 MODULATOR BOARD BLOCK DIAGRAM 4-32
4-14 POWER SUPPLY BLOCK DIAGRAM 4-35
4-15 U2843D INTERNAL BLOCK DIAGRAM 4-37
4-16 TRANSMITTER BOARD BLOCK DIAGRAM 4-39
4-17 KT 73 MAIN BOARD BLOCK DIAGRAM 4-53
4-18 KT 73 FPGA BLOCK DIAGRAM 4-55

Rev. 1, May/2003 15563M01.JA Page TC-3

B KT 73

FIGURES (cont).
FIGURE PAGE

FIGURE 4-4 SIDE LOBE SUPPRESSION CHARACTERISTICS

The KT 73 responds to these ATCRBS interrogations with standard ATCRBS reply

format (explained in the paragraph titled, "Reply Formats" later in this manual).
B. ATCRBS/Mode S All-Call
An ATCRBS/Mode S All-Call interrogation, Figure 4-3, contains formats identical
to ATCRBS Mode A and Mode C Pressure Altitude pulses, but with an added P4
pulse. The P4 pulse width is 1.6 microsec. (There is also an ATCRBS Only All-
Call interrogation identical to the ATCRBS/Mode S All-Call interrogation identical
to the ATCRBS/Mode S All-Call interrogation except that the P4 pulse width is 0.8
microsec. A Mode S transponder, although it replies to standard ATCRBS interro-
gations, will not reply to the short P4 interrogation). The Mode S transponder re-
plies to the interrogation with a Mode S reply if the amplitude of P4 is equal to or
greater than the amplitude of P3 - 1dB, or with an ATCRBS reply if the amplitude
of P4 is less than or equal to the amplitude of P3 - 6dB.
C. Mode S
Figure 4-5 illustrates the Mode S interrogation using Uplink Format (UF). The
waveforms used in conjunction with Mode S interrogations are significantly differ-
ent from the simple ATCRBS interrogations. The Mode S interrogation makes use
of Differential Phase-Shift Keying (DPSK) modulation for the purpose of transmit-
ting the 4 Million Bits Per Second (4Mbps), data burst.
The Mode S interrogation uses one of two general formats; the short format with
56 bits of DPSK data or the long format with 112 bits of DPSK data. The signal is
comprised of a P1, P2 preamble followed by a long pulse called P6.

Rev. 1, May/2003 15563M01.JA Page 4-5

B KT 73

FIGURE 4-5 MODE S INTERROGATION, UPLINK FORMAT

The P1-P2 pair preceding P6, suppresses replies from ATCRBS transponders to avoid synchro-
nous garble caused by random triggering of ATCRBS transponders by the Mode S interrogation.
A series of "chips" containing the information within P6 starts 0.5 microseconds after the sync
phase reversal. A chip is an un-modulated interval of 0.25 microsecond duration preceded by pos-
sible phase reversals. If preceded by a phase reversal, a chip represents a ONE. If preceded by
no phase reversal, a chip represents a ZERO. There are either 56 or 112 chips. The last chip is
followed by a 0.5 microsecond guard interval which prevents the trailing edge of P6 from interfer-
ing with the demodulation process.

The Uplink Format (UF) consists of 25 Mode S interrogation formats (UF=0 through UF=24), as
defined by RTCA/DO-181C. The term UF=4 means uplink format 4. The UF data is DPSK mod-
ulated and contained only in pulse P6 of Mode S interrogations. Presently, KT 73 units are ca-
pable of processing six uplink formats (UF = 0,4,5,11,20, and 21). Refer to Figure 4-6 for a de-
scription of those formats.

Rev. 1, May/2003 15563M01.JA Page 4-6

B KT 73

UPLINK BINARY DATA FIELDS AND NUMBER OF BITS FUNCTIONS

FORMAT FORMAT
NUMBER U #

0 0 0000 P:3 RL:1 P:4 AQ:1 BD:8 P:10 AP:24 Short Air-Air Surveil-
lance (ACAS)

4 0 0100 PC:3 RR:5 DI:3 SD:16 AP:24 Surveillance, Altitude

Request
Surveillance Identity Re-
5 0 0101 PC:3 RR:5 DI:3 SD:16 AP:24 quest
11 0 1011 PR:4 IC:4 CL:3 P:16 AP:24 Mode S-Only All-Call

20 1 0100 PC:3 RR:5 DI:3 SD:16 MA:56 AP:24 Surveillance, Altitude

Request
21 1 0101 PC:3 RR:5 DI:3 SD:16 MA:56 AP:24 Mode S-Only All-Call

Additional content and description of the uplink reply formats are described below.

Notes:
1. RL (Reply Length); commands a reply in DF=0 if zero, and a reply in DF=16 if one.
2. AQ (Acquisition Special); identifies UF=0 and 16 as acquisition transmissions and
is repeated as received by the transponder in DF=0 and DF=16.

FIGURE 4-6 UPLINK FORMATS

(Sheet 1 of 3)

Rev. 1, May/2003 15563M01.JA Page 4-7

B KT 73

Notes
1. PC (Protocol): contains operating commands to the transponder and is part of the
surveillance and Comm-A interrogations. The codes are:
0 = No changes in transponder state.
1 = Non-selective All-Call lockout.
2 = Not assigned.
3 = Not assigned.
4 = Cancel B. (Closeout Comm-B)
5 = Cancel C. (Closeout Comm-C)
6 = Cancel D. (Closeout Comm-D)
7 = Not assigned.
2. RR (Reply Request): contains length and content of the reply requested by the in-
terrogations.
RR Code Reply Length MB Content
0-15 Short No MB Field
16 Long Air Initiated COMM-B
17 Long Extended Capability
18 Long Flight ID
19 Long TCAS RA Report
20-31 Long Least Significant 4 Bits interpreted as BDS1

3. DI (Designator Identification): identifies the coding contained in the SD field (ex-

plained below). The codes are:
0 = SD contains IIS, bits 21-32 are not assigned.
1 = SD contains multi-site II lockout and multisite datalink proto-
col.
2 = SD contains extended squitter control information.
3 = SD contains multisite SI lockout information and extended
data readout.
4-6 = Not assigned.
7 = SD contains extended data readout request.
FIGURE 4-6 UPLINK FORMATS
(Sheet 2 of 3)

Rev. 1, May/2003 15563M01.JA Page 4-8

B KT 73

4. SD (Special Designator): contains control codes affecting transponder protocol.

The content of this field is specified by the DI field (see note 3).
IIS (Interrogator Identifier): 4-bit subfield appears in all SD fields if DI code is 0, 1,
or 7.
5. MA (Message Comm-A): contains messages directed to the aircraft.

Notes
1. PR (probability of Reply): contains commands to the transponder that specify the
reply probability to the Mode S-only All-Call interrogation (UF=11) that contains the
PR. A command to disregard any lockout state can also be given. The assigned
codes are as follows:
0 = Reply with probability = 1.
1 = Reply with probability = 1/2.
2 = Reply with probability = 1/4.
3 = Reply with probability = 1/8.
4 = Reply with probability = 1/16.
5, 6, 7 = Do not reply.
8 = Disregard lockout, reply with probability = 1.
9 = Disregard lockout, reply with probability = 1/2.
10 = Disregard lockout, reply with probability = 1/4.
11 = Disregard lockout, reply with probability = 1/8.
12 = Disregard lockout, reply with probability = 1/16.
13, 14, 15 = Do not reply.
2. IC (Interrogator Code)
3. CL (Code Label)
0 = IC field contains the II code.
1 = IC filed contains SI codes 1 to 15.
2 = IC filed contains SI codes 16 to 31.
3 = IC filed contains SI codes 32 to 47.
4 = IC filed contains SI codes 47 to 63.
5-7 = Not assigned.
FIGURE 4-6 UPLINK FORMATS
(Sheet 3 of 3)

Rev. 1, May/2003 15563M01.JA Page 4-9

B KT 73

4.1.3 MODE S TRANSMISSION CONTENT

All discrete Mode S interrogations (56-bit or 112-bit) and replies (except the All-Call reply) contain
the 24-bit discrete address of the Mode S transponder upon which 24 error-detecting parity check
bits are overlaid. In the All-Call reply, the 24 parity check bits are overlaid on the Mode S interro-
gator’s identity code and the transponder’s discrete address included in the text of the reply.
NOTE:
Blocks of Mode S address codes will be allocated to
state aircraft registration authorities by the Interna-
tional Civil Aviation Organization (ICAO). Individual
states will set their own arrangements for code as-
signments, however, it is expected that users will ap-
ply to their state regulatory authorities for the code
assignments for their aircraft.

The primary function of Mode S is surveillance. For the Mode S transponder this function can be
accomplished by the use of "short" (56-bit) replies and interrogations. In the replies, the aircraft
reports its altitude as well as its flight status (airborne, on the ground, alert).
The "squitter" transmission is unsolicited and is transmitted by a transponder approximately once
every second. The squitter signal is observed by aircraft equipped with airborne collision avoid-
ance systems.
Air-to-air interrogations from airborne collision avoidance systems are addressed to Mode S-
equipped aircraft based upon the address extracted from squitter signals. These interrogations
are used for Mode S target tracking and collision threat assessment.
The discrete addressing and digital encoding of Mode S transmissions permit their use as a digital
data link. Certain interrogation and reply formats of the Mode S system contain coding space for
the transmission of data. Such data may be used for air traffic control purposes or air-to air data
interchange for collision avoidance.
Mode S data link transmissions are handled as one 56-bit message included as part of "long" 112-
bit interrogations or replies. These transmissions include the message, in addition to surveillance
data.
4.1.4 REPLY FORMATS
A. ATCRBS Replies
The ATCRBS reply format is illustrated in Figure 4-7. The KT 73 uses 13 serial
pulses to convey aircraft identification in response to Mode A interrogations or air-
craft altitude reporting in response to Mode C interrogations. The coded pulses are
arranged between two framing pulses located at the beginning and end of the data.
The framing pulses, identified as F1 and F2 are spaced 20.3 microseconds apart
for both Mode A and Mode C replies. The transponder receives the aircraft code
from switch settings on the control panel and altitude data from sensors in the air-
craft.
When no altitude data is available during Mode C interrogations, the transponder
replies with only F1 and F2 framing pulses. The framing pulses are transmitted
even if the altitude reporting switches on the control panel are turned off.
In addition to information pulses and framing pulses, a Special Position Identifica-
tion (SPI) pulse may be included in the reply when requested by the radar control-
ler. The pulse is initiated when the IDENT pushbutton switch is pushed at the con-
trol panel.

Rev. 1, May/2003 15563M01.JA Page 4-10

B KT 73

The SPI pulse follows the last framing pulse by 4.35 microseconds and is transmit-
ted with each response that occurs during the 15- to 30- second period after the
IDENT switch is actuated. The SPI pulse causes an enhanced pattern on the air
traffic controller’s scope thus enabling more positive aircraft identification.
B. Mode S Replies
The Mode S reply is a PPM scheme, much like that used with ATCRBS. The exact
format differs, however, in that a four (4) pulse preamble is followed by the reply
data pulses. See figure 4-7. The reply data pulses are either 56 pulses (bits) if the
reply is short format or 112 pulses (bits) if the reply is long format.
In PPM coding of the reply, 0.5mSec pulses are placed within 1.0 mSec windows
of time relative to the preamble. If the positive pulse lies within the first half of the
1 mSec window, the bit is understood to be a "1". If the positive pulse lies within
the last half of the window, the bit is understood to be a "0". The downlink reply
provides for 25 format possibilities. The 25 Mode S transponder transmission
downlink formats DF=0 through DF=24 are defined in RTCA/DO-181 and DO-
181C. The term DF=4 means downlink format 4.
The short reply format (56-bit) is used exclusively for the purpose of surveillance,
squitter, and TCAS acquisition.
The long format Mode S interrogations and replies are 112 bits of data within P6.
The long format interrogations provide the same surveillance data as their short
format counterparts but include provisions for 56 bits of non-surveillance type mes-
sages.

FIGURE 4-7 ATCRBS AND MODE S REPLY FORMAT

Rev. 1, May/2003 15563M01.JA Page 4-11

B KT 73

Only nine downlink formats (DF=0, 4, 5, 11, 16, 17, 18, 20, 21) are defined and pro-
cessed by the KT 73 transponder. Refer to figure 4-8 for a description of these for-
mats.
The first field (D # ) in all downlink formats is the format number. It is coded in bi-
nary form e.g., the first five bits of DF=20 are 10100.
The last 24 bits (AP) of each downlink format except DF=11 (33 thru 56, short or
89 thru 112, long) or DF=17/18, represents the unique 24-bit Mode S transponder
address plus parity bits overlaid on the address.

Rev. 1, May/2003 15563M01.JA Page 4-12

B KT 73

DOWNLINK BINARY DATA FIELDS AND

FORMAT FORMAT NUMBER OF BITS FUNCTION
NUMBER D #
0 0 0000 VS:1 CC:1 P:1 SL:3 P:2 RI:4 P:2 AC:13 Short Air-Air Surveil-
AP:24 lance (ACAS)
4 0 0100 FS:3 DR:5 UM:6 AC:13 AP:24 Surveillance, Altitude
5 0 0101 FS:3 DR:5 UM:6 ID:13 AP:24 Surveillance, Identity
11 0 1011 CA:3 AA:24 PI:24 All-Call Reply
16 1 0000 VS:1 P:2 SL:3 P:2 RI:4 P:2 AC:13 MV:56 Long Air-Air Surveillance
AP:24
17 1 0001 CA:3 AA:24 ME:56 PI:24 Extended Squitter
18 1 0010 CA:3 AA:24 ME:56 PI:24 Extended Squitter (Non-
Transponder)
20 1 0100 FS:3 DR:5 UM:6 AC:13 MB:56 AP:24 Comm-B, Altitude
21 1 0101 FS:3 DR:5 UM:6 ID:13 MB:56 AP:24 Comm-B, Identity

NOTE: Downlink format 16 is required only with TCAS operation.

Additional content and description of the downlink reply formats are described below.

Notes
1. VS (Vertical Status):
0 = airborne, 1 = on the ground
2. CC (Crosslink Capability) DF=0 only
0 = not supported, 1 = supported
3. SL (Sensitivity Level): TCAS operating levels that determine the area of protected
volume around a TCAS-equipped aircraft. See DO-185 for additional information.
The coding is as follows:
0 = No TCAS sensitivity level reported.
1 = TCAS is operating at sensitivity level 1.
2 = TCAS is operating at sensitivity level 2.
3 = TCAS is operating at sensitivity level 3.
4 = TCAS is operating at sensitivity level 4.
5 = TCAS is operating at sensitivity level 5.
6 = TCAS is operating at sensitivity level 6.
7 = TCAS is operating at sensitivity level 7.
FIGURE 4-8 DOWNLINK FORMATS
(Sheet 1 of 6)

Rev. 1, May/2003 15563M01.JA Page 4-13

B KT 73

4. RI (Reply Information): reports airspeed capability and type of reply to the interro-
gating aircraft. The coding is as follows:
0-7 = Codes indicate that this is the reply to an air-to-air non-acquisition interro-
gation.
0 = No on-board TCAS.
8-15 = Codes indicate that this is an acquisition reply.
8 = No maximum airspeed data available.
9 = Airspeed is less than or equal to 75 knots.
10 = Airspeed is greater than 75 and less than 150 knots.
11 = Airspeed is greater than 150 and less than 300 knots.
12 = Airspeed is greater than 300 and less than 600 knots.
13 = Airspeed is greater than 600 and less than 1200 knots.
14 = Airspeed is greater than 1200 knots.
15 = Not assigned.
5. AC (Altitude Code): contains altitude code. Zero is transmitted in each of the 13
bits if altitude information is not available. Metric altitude is contained in this field if
bit 26 is set to "1".
6. MV (Message, Comm-V): contains information used in air-to-ground exchanges.

FIGURE 4-8 DOWNLINK FORMATS

(Sheet 2 of 6)

Rev. 1, May/2003 15563M01.JA Page 4-14

B KT 73

Notes:
1. FS (Flight Status): reports the flight status of the aircraft. The codes are:
Code Alert SPI Airborne On the Ground
0 no no yes no
1 no no no yes
2 yes no yes no
3 yes no no yes
4 yes yes either
5 no yes either
6,7 not assigned

2. DR (Downlink Request): used to request extraction of downlink messages from

transponder by the interrogator. The codes are:
0 = No downlink request.
1 = Request to send Comm-B message (B bit set).
2 = TCAS information available.
3 = TCAS information available and request to send Comm-B message.
4 = Comm-B broadcast #1 available.
5 = Comm-B broadcast #2 available.
6 = TCAS information available and Comm-B broadcast #1 available.
7 = TCAS information available and Comm-B broadcast #2 available.
FIGURE 4-8 DOWNLINK FORMATS
(Sheet 3 of 6)

Rev. 1, May/2003 15563M01.JA Page 4-15

B KT 73

B KT 73

4.1.5 KT 73 REPLY PULSE CHARACTERISTICS

ATCRBS Replies:

ATCRBS Reply Pulse Positions:

The reply function will consist of two framing pulses (nominally spaced 20.3 µsec apart) and 13
information pulses. The pulse spacing tolerance for each pulse (including the last framing pulse)
with respect to the first framing pulse of the reply group will be ±.10 µsec. The pulse spacing tol-
erance of any pulse in the reply group with respect to any other pulse (except the first framing
pulse) will be no more than ±.15 µsec.
Pulse position from the first framing pulse are as follows:
PULSE POSITION (µsec)
F1 ...................0.00 (Reference)
C1 ...................1.45
A1 ...................2.90
C2 ...................4.35
A2 ...................5.80
C4 ...................7.25
A4 ...................8.70
B1 ...................11.60
D1 ...................13.05
B2 ...................14.50
D2 ...................15.95
B4 ...................17.40
D4 ...................18.85
F2 ................... 20.30
SPI .................. 24.65

ATCRBS-SPI Reply Pulse:

Upon activation of the IDENT switch, the SPI pulse will be transmitted when replying to ATCRBS
Mode A interrogations for a period of 18 ±1 seconds. The pulse spacing tolerance of the SPI pulse
with respect to the last framing pulse will be ±0.10 µsec. The SPI pulse will not be transmitted
when replying to Mode C interrogations.

ATCRBS Reply Pulse Shape:

NOTE:
All reply pulses and SPI pulses will be 0.45 µsec
±.10 µsec duration and have rise times of 0.05 µsec
through 0.1 µsec and decay times of 0.05 µsec
through 0.2 µsec.

The Mode S reply spectrum requirement is an acceptable specification for meeting ATCRBS min-
imum rise and fall time requirement.

Rev. 1, May/2003 15563M01.JA Page 4-19

B KT 73

ATCRBS Reply Delay and Jitter:

A. At all RF input levels from MTL to -21 dBm, the time delay from the leading edge
of P3 to the leading edge of F1 (the first pulse of the reply) will be 3.0 ±.5 µsec.
B. At all RF levels from MTL +3 to -21 dBm the time delay variations between AT-
CRBS modes will not exceed 0.2 µsec.
C. At all RF input levels from MTL +3 to -21 dBm the jitter at the leading edge of the
first pulse of the reply with respect to P3 will not exceed ±0.10 µsec.

Mode S Replies:
The reply data block is formed by PPM encoding of the reply data. A pulse transmitted in the first
half of the interval represents a ONE while a pulse transmitted in the second half represents a ZE-
RO. An example of a Mode S reply waveform is shown in Figure 2-3, paragraph 2.2.4.2, of DO-
181C.

Mode S Preamble:
The preamble will consist of four 0.5, ±.05 µsec pulses. The second, third, and fourth pulses will
be spaced 1.0, 3.5, and 4.5 µsec, respectively, from the first transmitted pulse. The spacing toler-
ance of the second, third, and fourth pulse with respect to the first pulse will be ±0.05 µsec.

Mode S Reply Pulse Width:

The block of reply data pulses will begin 8.0 µsec after the first transmitted pulse. A pulse width
of 0.5 µsec ±0.05 µsec will be transmitted either in the first or in the second half of each interval.
If a pulse in the second half of one interval is followed by another pulse transmitted in the first half
of the next interval, the two pulses will merge and a 1.0 µsec ±0.05 µsec pulse will be transmitted.

Mode S Reply Pulse Shape:

A. The pulse rise time will not exceed 0.1 µsec.
B. The pulse decay time will not exceed 0.2 µsec.
C. The pulse amplitude variation between one pulse and any other pulse in a reply
shall not exceed 2 dB.

Transmitter Spectrum:
The spectrum of a Mode S reply will not exceed the following bounds:

Frequency Difference Maximum Relative Response

(MHz From Carrier) (dB Down From Peak)

Greater than 1.3 and less than 7 3

Greater than 7 and less than 23 20

Greater than 23 and less than 78 40

Greater than 78 60

Rev. 1, May/2003 15563M01.JA Page 4-20

B KT 73

Mode S Reply Delay and Jitter:

A. At all RF input levels from MTL to -21 dBm the first preamble pulse of the reply will
occur 128 µsec ±0.25 µsec after the sync phase reversal of the Mode S interroga-
tion.
B. At all RF input levels from MTL to -2 1dBm the jitter of the reply delay will not ex-
ceed ±0.08 µsec.

4.1.6 KT 73 ATCRBS/MODE S ALL-CALL REPLIES

ATCRBS/Mode S All-Call Reply Delay and Jitter:
A. At all RF input levels from MTL to -21 dBm the first preamble pulse of the reply will
occur 128 µsec ±0.5 µsec after the P4 pulse of the ATCRBS/Mode S All-Call inter-
rogation.
B. At all RF input levels from MTL+3 dB to -21dBm the jitter of the reply delay will not
exceed ±0.1µsec, peak.

Suppression I/O:
This pin is both an input and an output. The transponder will be suppressed if the input is +18 V
dc to +70 V dc. While the transponder is transmitting it will drive this pin above 18 V dc. (See
ARINC 718A Attachment 6).

Suppression In:
The transponder will be suppressed if the voltage applied to this pin is +5V dc to +9V dc. If the
voltage is <3.5V dc, the transponder will not be suppressed. This follows a Honeywell standard.
Side Lobe Suppression Characteristics:
Side lobe suppression is accomplished separately for ATCRBS, ATCRBS-Only All-Call, ATCRBS/
Mode S All-Call and for Mode S interrogations.

4.1.7 KT 73 ATCRBS, ATCRBS-ONLY ALL-CALL AND ATCRBS/MODE S ALL-CALL

SLS Decoding and Dynamic Range:

A. The transponder will reply to no more than 10% of the interrogations when the RF
input signal is varied from +3 dB above the MTL to -21 dBM and the level of P2
equals or exceeds the level of P1 and the pulse interval between P1 and P2 is var-
ied over the range from 1.85 to 2.15 µsec.
B. The transponder will reply to at least 90% of the interrogations when the RF input
signal is varied from +3 dB above the MTL to -21 dBM and the level of P1 exceeds
the level of P2 by 9 dB or more and that no pulse is received at the position 2 ±0.7
µsec following P1.

P2 Duration For 90% Replies:

The transponder will reply to at least 90% of the interrogations when the duration of P2 is less than
0.3 µsec. This is applicable for signal levels from MTL +3 dB thru -21 dBm.

Rev. 1, May/2003 15563M01.JA Page 4-21

B KT 73

Mode S Side Lobe Suppression:

Side lobe suppression for Mode S formats is characterized by the reception of P5, overlaying the
location of the sync phase reversal of P6.
A. At all RF input levels from MTL +3 dB to -21 dBm the reply ratio will be less than
10% if the received amplitude of P5 exceeds the received amplitude of P6 by 3 dB
or more.
B. At all RF input levels from MTL +3 dB to -21 dBm the reply ratio will be at least 99%
if the received amplitude of P6 exceeds the received amplitude of P5 by 12 dB or
more.

Pulse Decoder Characteristics:

Unless otherwise specified, the following pulse decoder characteristics will apply for an RF input
signal levels of MTL +1 dB to -21 dBm and nominal interrogation signal characteristics. Applicable
"valid" interrogations will result in at least 90% replies, and interrogations which are "invalid" will
result in less than 10% replies.
Pulse Level Tolerances:
A. The transponder will accept an ATCRBS/Mode S All-Call as a valid Mode S if the
received amplitude of P4 is above the amplitude of P3 -1 dB.
B. The transponder will not accept the interrogation of an ATCRBS-Only All-Call if the
received amplitude of P4 is above the amplitude of P3 -1 dB.
C. The transponder will accept an ATCRBS/Mode S All-Call as a valid ATCRBS inter-
rogation if the received amplitude of P4 is below the amplitude of P3 -6 dB.
D. The transponder will accept an ATCRBS-Only All-Call as a valid ATCRBS interro-
gation if the received amplitude of P4 is below the amplitude of P3 -6 dB.
NOTE:
Mode S transponders do not accept the ATCRBS-
Only All-Call.

Pulse Position Tolerances:

A. The transponder will accept the pulse position of ATCRBS interrogations as valid
if the spacing between P1 and P3 is within ±0.2 µsec of the nominal spacing.
B. The transponder will accept the pulse position of ATCRBS/Mode S All-Call’s as val-
id if the spacing between P1 and P3 is within ±0.2 µsec of the nominal spacing and
if the spacing between P3 and P4 is within ±0.05 µsec of nominal.
C. The transponder will not accept the pulse position of ATCRBS, ATCRBS-Only All-
Call’s or ATCRBS/Mode S All-Call’s as valid if the spacing between P1 and P3 dif-
fers from the nominal spacing by 1.0 µsec or more.
D. The transponder will not accept the pulse position of ATCRBS/Mode S All-Call’s if
the leading edge of P4 is not detected within the interval from 1.7 to 2.3 µsec fol-
lowing the leading edge of P3.

Rev. 1, May/2003 15563M01.JA Page 4-22

B KT 73

Pulse Duration Tolerances:

A. The transponder will accept the pulses of an ATCRBS interrogation as valid if the
duration of both P1 and P3 is between 0.7 and 0.9 µsec.
B. The transponder will accept an ATCRBS/Mode S All-Call interrogation as valid if
the duration of both P1 and P3 is between 0.7 and 0.9 µsec and if the duration of
P4 is between 1.5 and 1.7 µsec.
C. The transponder will not accept an ATCRBS/Mode S All-Call as valid if the duration
of the P4 pulse is outside of the range between 1.2 and 2.5 µsec.
D. The transponder will accept no more than 10% of ATCRBS or ATCRBS/Mode S
All-Call interrogations as valid if the duration of either the P1 pulse or the P3 pulse
is less than 0.3 µsec, for all signal levels from MTL to -45 dBm.

Simultaneous Interrogation of Mode A and Mode C:

When the transponder receives two valid ATCRBS pulse patterns simultaneously, the transpon-
der will enter the ATCRBS suppression state if one of the received pulse patterns is a P1-P2 sup-
pression pair, or generate a valid Mode C reply if the two received pulse patterns are Mode A and
Mode C.

Sync Phase Reversal Position Tolerance:

Valid SPR Position: At signal levels of MTL +1 dB thru -21 dBm the transponder will accept the
sync phase reversal, of a standard Mode S-Only All-Call, if it is received within the interval from
1.2 to 1.3 µsec following the leading edge of P6.
Invalid SPR Position: At signal levels of MTL +1 dB thru -21 dBm the transponder will not accept
the sync phase reversal, of a Mode S-Only All-Call, if it is received outside of the interval from 1.05
to 1.45 µsec following the leading edge of P6.
NOTE:
In the gray zones, in the zones from 1.05 to 1.2 µsec
and from 1.3 to 1.45 µsec, the transponder may or
may not accept the sync phase reversal.

Squitter: Random Intervals Uniformly Distributed over the range from .8 thru 1.2 seconds, full self
verification of every squitter’s data and occurrence.

4.1.8 TRAFFIC INFORMATION SERVICE DATA LINK

The Traffic Information Service (TIS) data link function is intended to improve the safety and effi-
ciency of “see and avoid” flight by providing automatic display to the pilot of nearby traffic and
warnings of any potentially threatening conditions. The source of TIS information is the file of air-
craft tracks maintained by the ground Mode S sensor providing coverage for a region of airspace.
While TIS can provide traffic information alerts to only those Mode S equipped aircraft under sur-
veillance track, TIS has knowledge of all ATCRBS aircraft in coverage (and, potentially, of non-
transponder-equipped aircraft when a primary radar’s coverage is integrated with the Mode S sen-
sor). TIS generates alerts for any traffic aircraft in Mode S coverage that carry a transponder (AT-
CRBS or Mode S). TIS provides traffic advisories similar to those of TCAS-I but does not provide
resolution advisories. By utilizing the surveillance database maintained by Mode S ground inter-
rogators and the data link, TIS can provide airborne traffic alerting with modest airborne equipage.
The TIS service is provided without ground controller involvement.

Rev. 1, May/2003 15563M01.JA Page 4-23

B KT 73

4.1.8.1 Differences between TIS and TCAS

The major functional difference between TIS and TCAS is the source of surveillance data. TCAS
uses an airborne interrogator with a one second update rate. TIS, on the other hand, uses the
terminal Mode S ground interrogator and its data link to provide about a five second update rate.
The range accuracy of TIS and TCAS are similar. TCAS angular accuracy is limited to a few de-
grees of azimuth measured with respect to the aircraft while TIS angular accuracy is that of Mode
S (about 1 milliradian) measured with respect to the ground interrogator. These differences in sur-
veillance accuracy, coordinate system, and update rate impact the design of TIS. The algorithms
and parameters of TIS have been developed to offset the differences in surveillance performance
in order to yield equivalent alerting service to TCAS-I. TCAS practice may also be used in the
design of TIS display symbology.
4.1.9 DEFINITION OF AUTOMATIC DEPENDENT SURVEILLANCE - BROADCAST
ADS-B is a system for aircraft or surface vehicles operating within the airport surface movement
area that periodically transmits its state vector (horizontal and vertical position, horizontal and ver-
tical velocity) and other information. ADS-B is automatic as no external stimulus is required. It is
dependent as it relies on on-board navigation sources and on-board broadcast transmission sys-
tems to provide surveillance information to other users. The aircraft or vehicle originating the
broadcast may or may not have knowledge of which users are receiving its broadcast. Any user,
either aircraft or ground based within the range of this broadcast, may choose to receive and pro-
cess the ADS-B surveillance information. ADS-B supports the improved use of airspace, reduced
ceiling/visibility restrictions, improved surface surveillance, and enhanced safety such as conflict
management.
Figure 4-9 shows the extent of the 1090 MHz ADS-B system and its major components. As indi-
cated in the figure, the ADS-B system includes the following components: message generation/
transmission by the source A/V, propagation medium, and message reception/report assembling
by the user. The ADS-B system does not include the sources of the data to be sent by the source
subsystem on board the transmitting aircraft. Neither does it include the client applications, which
use the information received by the ADS-B user subsystem on board the receiving aircraft. Some
ADS-B participants may be able to transmit by not receive. In addition, some ground based users
may be able to receive but not to transmit.

FIGURE 4-9 1090 MHZ ADS-B SYSTEM

Rev. 1, May/2003 15563M01.JA Page 4-24

B KT 73

FIGURE 4-10 KT 73 BLOCK DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 4-25

B KT 73

FIGURE 4-11 KT 73 INTERNAL INTERCONNECTION DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 4-27

B KT 73

4.2 GENERAL CIRCUIT THEORY

Refer to Figure 4-10 for a block diagram and Figure 4-11 for an internal interconnect diagram.
The older ATCRBS interrogation signals, Mode A and Mode C, are a combination of pulse ampli-
tude modulated (PAM) and pulse position modulated (PPM) type of signals. The new Mode S in-
terrogation signals are a combination of PAM, PPM, and differential phase shift keying (DPSK)
type of signals. Interrogation signals at 1030 MHz are coupled into the unit via the antenna con-
nector. The signal passes through a 1300 MHz low pass filter and is routed through a 1030 MHz
bandpass filter. After passing through the bandpass filter signal is mixed with a 970 MHz local
oscillator (LO) signal to generate an intermediate frequency (IF) signal at 60 MHz. The output
from the mixer is processed by a bandpass filter to reject undesired mixing frequencies. The de-
sired IF signal is amplified logarithmically, then demodulated by the video processor and DPSK
module to obtain the PAM/PPM and DPSK base-band interrogation pulses. The demodulated sig-
nals are then routed into the FPGA (Field Programmable Gate Array) for further processing. The
operation of KT 73 can be better understood if it is broken into blocks as shown in Figure 4-10.
A brief description of each block is presented. Detailed circuit theory information is presented in
Section 4.3.
The KT 73 has an AMD 80C186, 16 bit Micro-controller that controls the FPGA and performs sev-
eral other functions:
• Reads the front panel rotary switches and pushbutton selections.
• Generates appropriate characters for the front panel display and controls the display bright-
ness.
• Programs and reads the internal and external (if installed) EEPROM.
• Reads the Gillham code lines, EXT STBY_NOT, EXT IDT_NOT, EXT GND_NOT, and AUDIO
INHB_NOT through a parallel to serial converter.
• Checks operational status of unit by monitoring the TX_SENSE line from the transmitter power
amplifier.
• For ATCRBS interrogations, the FPGA validates the video signal and generates the appropri-
ate reply (MOD_TRIG) signal.
• For Mode S interrogations, the FPGA validates the video signal and transfers the received
data to the AMD 80C186 Micro-controller.
The AMD 80C186 will decipher the data and send the appropriate reply data back to the FPGA.
On receipt of data, the FPGA generates proper MOD_TRIG signal. The MOD_TRIG signal from
the FPGA is used by the modulator to generate the appropriate drive signals to turn on/off the pow-
er oscillator and power amplifier. The power oscillator outputs 100W typical at 1090 MHz every
time it is turned on by the modulator. This pulsed RF output is further amplified by the power am-
plifier to 300W. The amplified output goes through the transmit/receive switch, low pass filter and
is coupled out to the antenna. The input power to the KT 73 can vary from 11 to 33Vdc. The power
supply converts the dc-input voltage into the following fixed voltages: +3.3V, +5V, +65V, ±12V,
±95V and +6V that are needed by the circuitry in the KT 73.

Rev. 1, May/2003 15563M01.JA Page 4-29

B KT 73

4.3 DETAILED CIRCUIT THEORY

4.3.1 RECEIVER BOARD
The receiver of the KT73 consists of a 1030 MHz bandpass filter, low noise amplifier (LNA), local
oscillator (LO), Mixer, 60 MHz IF bandpass filter & amplifier, log amplifier/detector, 60 MHz phase
reference, and phase detector. The reference schematic is 002-08273-0020. A block diagram is
shown in figure 4-12.

FIGURE 4-12 RECEIVER BOARD BLOCK DIAGRAM

4.3.1.1 Receiver Front End

The receiver front end consists of a ceramic bandpass filter and low noise amplifier. The ceramic
bandpass filter, FL1, which has a center frequency of 1030 MHz and a bandwidth of 30 MHz, pro-
cesses the input RF signal. The signal is amplified by Q7, a low noise amplifier (LNA). Q6 pro-
vides a regulated bias for the LNA.
4.3.1.2 Local Oscillator (LO)
The local oscillator (LO) consists of several stages. A crystal oscillator (Q1, Y1, and etc.) gener-
ates a fundamental frequency of 161.667 MHz. This signal is multiplied by three (Q2), amplified
by Q3, and multiplied by 2 (Q4), to obtain a LO frequency of 970 MHz. A microstrip bandpass
filter (Z16, C18, C19, and Z17) is used to select out the desired 970 MHz LO signal. The LO signal
is buffered and amplified by Q5 before injection into the mixer.

Rev. 1, May/2003 15563M01.JA Page 4-30

B KT 73

4.3.1.3 Amplified Input Signal

The amplified input signal is multiplied with the LO signal by the Q8 mixer, a low noise dual gate
MOSFET, to obtain the 60 MHz difference frequency used in the IF. Bias adjustment for the input
and LO injection to the mixer is provided by R2156 and R2157 respectively.
4.3.1.4 IF Filter and Amplifier
The IF filter and amplifier then process the signal. A network with T1 and T2, which extracts the
60MHz IF, filters the signal from the mixer output. The IF is subsequently amplified by Q9 and
further processed by a bandpass filter consisting of T3, T4, and T5. Before proceeding to the Log
Amp, the IF is filtered and balanced through T8 and C188. The signal enters the T8 primary, is
coupled to its center tapped secondary, and is shunted to ground through C188 . Each secondary
output feeds one of the balanced inputs to the U1 Log Amp.
4.3.1.5 Log Amp
The U1 Log Amp takes the 60 MHz balanced IF input signal and converts it from a logarithmic
scaling to linear. It is then detected, producing video for both the video and DPSK signal require-
ments on the Main Board. The Log Amp provides a log linear output from -65dBm to 0dBm at its
input. With gain of the LNA, insertion loss from filtering, and conversion gain of the mixer and IF
amplification, an input signal from the RF input has a down converted gain of 18 dB. A -74 dBm
input signal would produce a -56 dBm IF at the input to the Log Amp, which is easily within the
range of linear Log Amp output. Two Log Amp outputs are used to provide video and DPSK sig-
nals.
U1 outputs a video signal with a gain of 20 mV/dB. U4, a video amplifier, inverts and has a voltage
gain of unity. The output passes to a buffer consisting of Q15, Q16, Q19, and Q20. The buffer
inverts the video signal and boosts the gain to 60 mV/dB. The buffer is configured to provide a
DC level near ground for the video signal. The output is passed to the main board through TP6.
A limited IF output of 60 MHz is amplified by U2 and U3 and then split into two paths for DPSK
signal processing.
4.3.1.6 60 MHz Phase Reference
The 60 MHz Phase Reference is created by first generating a 120 MHz signal using a non-linear
amplifying process. Q13 is a tuned 120 MHz amplifier that selectively amplifies this second har-
monic. The 120 MHz output is processed by a high Q bandpass filter (C101-C104, L24, L25) and
amplified by Q14 to obtain a constant phase 120 MHz signal. The 120 MHz signal is divided by
two creating a constant phase 60 MHz reference. This “division by two” process is done by the
feedback arrangement of mixer U12 and Q21, a 60 MHz tuned amplifier. Capacitor C151 provides
phase adjustment of the 60 MHz reference.
4.3.1.7 Active Phase Detector
The active phase detector, U14, receives the 60 MHz phase reference together with Limited IF
from U3 to extract the DPSK data from the Limited IF signal. The positive/negative pulses of I14,
corresponding to DPSK transitions, are low pass filtered and level translated by U15 to TTL signal
level. This TTL level signal is the demodulated DPSK signal that goes to the RLSI for further pro-
cessing.

Rev. 1, May/2003 15563M01.JA Page 4-31

B KT 73

4.3.2 MODULATOR BOARD

The modulator board drives the transmitter according to the signals received from the RLSI chip
on the main board. The KT 73 modulator can be divided into the five major blocks: TX_SENSE
module, 50V regulator, collector modulator, emitter modulator, and TX/RX switch as shown in fig-
ure 4-13. The modulator schematic is P/N 002-08274-0020.

FIGURE 4-13 MODULATOR BOARD BLOCK DIAGRAM

4.3.2.1 TX_SENSE Module

Transistor Q5 provides compensation for the 2 diode voltage drops inside the controller chip over
temperature.
Soft start, i.e. limiting the in-rush current during start up, is provided by C56 which slowly charges
up on power up through R14. It takes approximately 12 ms after turn on for switcher #1 outputs
to reach steady state values.
4.3.3.6 Switcher #2
The operation and control of switcher #2 is essentially the same as switcher #1. Frequency com-
pensation is provided by C22, R48, R49, and R50. The nominal loop bandwidth of switcher #2 is
about 1 kHz. The current through R54 is limited to about 23 A by R46 and R47.
4.3.3.7 RESET
Comparator U5-A is used to check on two conditions that govern the output state of the RESET
line. The reference voltage used in the comparison (+4 V) is provided by linear regulator U1. The
first comparator in U5-A checks the +6.0 volt line output and is configured as an inverting compar-
ator with hysteresis and trip points set at +5.9 V and +5.6 V.
The second comparator in U5-B checks the power input to the switching controllers and is also
configured as an inverting comparator with hysteresis and trip points at +9.3 V and +8.3 V.
The output of the two comparators are logically ORed by CR11 and drives an emitter follower, Q9.
The RESET signal is taken off from the emitter of Q9 and is used on the KT 73 Main Board to reset
the Microprocessor. As configured, the RESET line will reset the KT 73 during power up.
Diodes CR2 and CR3 are used to feedback +12 V from switcher #2 so that operation down to an
abnormal low of +8 V at the input is possible. Diode CR10 is used to harness the residual energy
of the +12 V output after turn-off to hold the RESET line LOW until the +5 V decays to zero.

Rev. 1, May/2003 15563M01.JA Page 4-38

B KT 73

4.3.4 TRANSMITTER BOARD

The transmitter board has three RF devices. The TX/RX switch, the power oscillator, and the pow-
er amplifier. The TX/RX switch routes RF signals received and transmitted through the antenna
by way of the RF input/output port to the receiver and transmitter. Q1 is a power amplifier used
in an oscillator configuration. Q2 is a class C power amplifier providing 6 dB of gain. A block di-
agram of the KT 73 transmitter is shown below in Figure 4-16. Reference schematic for the trans-
mitter is P/N 002-08275-0040.

FIGURE 4-16 TRANSMITTER BOARD BLOCK DIAGRAM

4.3.4.1 Power Oscillator

In order for an amplifier to oscillate, it must have some of its output power fed back to its input at
360 degrees of phase shift. A classic oscillator definition is that an active device must have a loop
gain of one and total phase shift of zero degrees. (360 degrees).

(1) The active device is Q1. The loop includes the output microstrip matching network,
C6, FL1 in series with the entire Q1 output, a 6 dB coupler, the 50 ohm phase match-
ing network (serpentine line), C2, and the input matching network. The transistor
has some un-quantified insertion phase as well.

(2) When the emitter modulator pulls low with the Q1 collector at 50 volts, the circuit be-
gins to oscillate.

(3) The total length of the feedback path determines the frequency of the oscillation.
The reason for the adjustable length 50 ohm line is to compensate for the variance
in insertion phase between different transistors populating the Q1 part inventory.
Even though C3 is used to adjust the frequency when the oscillator is close to 1090
MHz., decreasing the length of the 50 ohm line can raise the frequency higher, while
lengthening the line makes oscillations lower in frequency. Smaller length loops can
be added or removed for smaller frequency change and larger loops will change the
frequency in greater increments.

Rev. 1, May/2003 15563M01.JA Page 4-39

B KT 73

4.3.4.2 Bandpass Filter

Bandpass Filter FL1 is centered at 1090 MHz. with a 3 dB bandwidth of 10 MHz. The purpose of
the filter is to keep the oscillator on frequency over temperature. As the temperature varies, so
does the insertion phase through the transistor. This causes a change in oscillation frequency.
Bandpass filter FL1 has a temperature coefficient of 15 PPM/degree. The variable capacitors
change at 10 PPM/degree. The combined effect of the capacitors and the filter keep the frequency
of oscillation within the +/-1 MHz. limits.
4.3.4.3 6 dB Coupler
The 6 dB Coupler, W1, is used to couple 25% of the FL1 RF output energy back to the input of the
Q1 oscillator to maintain oscillations. The oscillator outputs 130 Watts and is filtered by FL1. The
insertion loss of FL1 is 1.45 dB leaving its output at 93 Watts. The coupled output being fed back
is 23 Watts or 17% of the oscillator output. Therefore, the output is reduced 25% to 70 Watts.
Loss in phase matching network is negligible.
4.3.4.4 Zero dB Attenuator
The Zero dB Attenuator follows W1 but is currently shorted across R2, the series member of the
network. Two shunt members, R3 and R4, make this a PI type design. The purpose is to reduce
the output from W1 to the Power Amp to a level not exceeding the 1 dB compression point. At
higher power inputs, the power amplifier becomes saturated and the output pulse shape of the
power amplifier becomes distorted.
4.3.4.5 Power Amplifier
The final amplifier is a class C RF amplifier with a gain of 6 dB. C4 and C7 are variable capacitors
used to tune the matching networks to power transistor Q2. Tuning C7 may also effect the fre-
quency of the power oscillator due to loading of the power oscillator output. With 70 Watts driving
the input, nominal power amp output is 280 Watts with 180 Watts reaching the antenna. 2 dB of
insertion loss is dissipated in the coaxial cable connecting the output port of the unit to the anten-
na.
4.3.4.6 TX/RX Switch
The TX/RX switch works by biasing two surface mount diodes, CR1 and CR2, to route RF signals
from the antenna to the receiver or to the antenna from the transmitter. The RLSI generates the
RX_EN_NOT signal, which controls the TX/RX switch.

(1) During the transmit cycle, the RX_EN_NOT line is set low by the RLSI. Integrated
circuit I1 inverts the signal that turns on Q7 and connects +5 V to E5. Applying +5
V to E5 turns on both CR1 and CR3. A low impedance path is now formed that di-
rects all the energy from the transmitter output to the antenna while isolating the re-
ceiver with a high impedance path. CR3 is in series with the transmitter output.
While forward biased, it passes the output power to the antenna. CR1 is effectively
shunted to RF ground a quarter wave length away at the receiver input. A shorted
quarter wave length stub is effectively an open circuit path to the transmitter high
power RF. The open circuit isolates the receiver path protecting the receiver.

(2) During the receive cycle, the RX_EN_NOT line is set low by the RLSI. Integrated
circuit I1 inverts the signal that turns on Q8 and connects -12 V to E5. With -12 V
on E5, a low impedance path is now formed which directs all energy from the anten-
na to the receiver input. R22 on the modulator board set the current through the di-
odes at 60 ma.

Rev. 1, May/2003 15563M01.JA Page 4-40

B KT 73

4.3.4.7 Low Pass Filter

The Low Pass Filter is designed to reduce the level of the conducted harmonics of the 1090 MHz
transmitter carrier. The filter is a seven-pole Chebyshev response with a 0.1 dB ripple. The 3 dB
corner frequency is 1.3 GHz. The inductors are implemented using 26 AWG wire and the capac-
itors are ATC 500 volt chip capacitors. The silver plated housing with the wire in the center creates
an air dielectric coax whose characteristic impedance is 130 ohms. The coaxial cavity was creat-
ed to have a high impedance line that would, in turn, create high Q inductors. The filter has 55 dB
of attenuation at the second and third harmonics.

4.3.5 DISPLAY BOARD

The Display Board provides the following:
• A custom gas discharge display.
• Cathode/anode display drivers
• The photocell used to detect the ambient lighting conditions.
• Panel back lighting
• The mode selection switch.
• The push button switches for the IDT and VFR functions.
• The rotary switches for the 4096 code entry.
• The light bulb to light the IDT button.
• A Main board interface for each of these functions.
4.3.5.1 Gas Discharge Display (GDD)
The lighting of the Gas Discharge Display (GDD) requires an initial high voltage of 150 ± 7 volts
to ionize the gas between the anode and cathode of the display. Once the gas is ionized, the re-
sistance of the inter-electrode gap drops and the voltage required to sustain the illumination de-
creases. Thus, the ideal driver would be a current source rather than a voltage source.
The driving circuitry is capable of placing up to 195 volts (divided between the cathode and anode
display drivers) across the display to induce ionization and also limit and control the current level.
To stop ionization or to extinguish the Gas Discharge Display, a voltage of 140 ± 7 volts is required
between the anode and cathode.
4.3.5.2 Cathode Display Drivers
The cathode display drivers are located on the Main board. Each cathode driver is buffered by
the FPGA then demultiplexed and controlled by the Micro Processor. Each cathode has a current
limiting resistor in series with each segment of the display which provides constant current during
the time the display segments are illuminated.
4.3.5.3 Anode Display Drivers
The Message Anode driver is demultiplexed by the FPGA on the Main board. All other anodes
are demultiplexed by U1 which comes from the FPGA. Then it goes to the Micro Processor which
controls all the anodes drivers. Both the anode and cathode drivers act as a voltage level trans-
lator between the FPGA and the display (from +3.3 volts to ±95 volts).

Rev. 1, May/2003 15563M01.JA Page 4-41

B KT 73

4.3.5.4 Photocell
External light variation is detected by the photocell, R77. The resistance of R77 varies with differ-
ent intensities of light. The photocell plus R77 and R214 on the Main board are part of a voltage
divider. This difference in voltage is feed into a A/D converter (U44 on Main board). From the A/
D converter, digital information goes to the Micro Processor.
Using the information from the A/D, the Micro Processor acts as a PWM (Pulse Width Modulator)
to control the dimming and brightness of the display.
4.3.5.5 +14, +28 Volt Back Panel Lighting:
The Back panel lighting consist of eight lamps connected in a series parallel circuit. They are con-
nected to P1 pins 20, 21 and 40. When the panel lighting is set to the +14 volt mode, all the lamps
are in parallel with the +14 volt lighting. When the panel lighting is set to the +28 volt mode, all
the lamps are in series parallel with the +28 volt lighting.
4.3.5.6 Mode Select Switch:
The mode select switch has 7-positions: OFF, FLT_ID, SBY, TST, GND, ON and ALT. The “OFF”
position provides a ground to the gate of Q19 and to the base of Q4 located on the power supply
board. This, in turn, prevents Q19 and Q4 from being turn on by the pull up resistor, R540, located
on the Main board. When the mode select switch is turned to any other position, the ground is
removed from the gate of Q19 and the base of Q4. With the absence of ground on the gate of
Q19, Q19 is allowed to turn on and pull its drain low. The drain of Q19 is connected to the anode
of CR4 on the power supply board which turns on the power supply +12 volt regulator. The base
of Q4 is connected to a resistor, R6, on the power supply board which is connected to the regu-
lated +12 volt supply. This causes Q4 to turn on and latch the power supply on.
4.3.5.7 VFR, IDT Switches:
The “VFR”, “IDT” and the remaining Mode switch positions are connected to a multiplexer (U2).
The output of the multiplexer (U2) goes to the FPGA on the Main board. Here, the information is
read, decoded and processed by the microprocessor.
4.3.5.8 Code Select Switches:
The information from the four Code Select switches go through a level translator (U8) on the Main
board. Then, the information goes to the FPGA and microprocessor where the information is read,
decoded and processed.
4.3.5.9 Fail Indicator Light:
The fail indicator light is controlled by the microprocessor on the Main board. The fail light DS19
(LED) is connected in series with a resistor R111and to +5 volts. The anode of DS19 is connected
to the drain of Q22. When the FPGA applies a high (+3.3 volts) to the gate of Q22, the source to
drain voltage drops from +5 volts to about 0.0 volts. This provides a current path to ground for the
fail light DS19 which drops about 2.4 volts and illuminates.

Rev. 1, May/2003 15563M01.JA Page 4-42

B KT 73

4.3.6 MAIN BOARD AND EEPROM BOARD

Refer to the KT 73 main board schematic, P/N 002-09321-0000, and Figure 4-17, the Main board
block diagram, as required.
The Main Board performs or provides the following:
• Data processing for the received interrogation signals.
• The rear connector interface with the outside world.
• The switching scheme that provides dual functions of the rear connector pins.
• The video processing circuit.
• The front panel gas discharge display drivers.
• Suppression pulse input/output.
• Serial ports including RS232 and ARINC429 receive/transmit logic.
• Temperature sensor.
• The voice synthesis circuit.
Most of the digital IC’s are 3.3V except the A429 LSI and the voice synthesis IC which are 5V.
There are several 5 volt logic gates e.g., U63 through U68 which are used as 3.3V to 5V level
shifters.
The external EEPROM Board is installed on the back of the KT73 mounting rack and interfaces
with the Main Board via the small rear connector J1. The purpose of the external EEPROM Board
is to allow specific, exclusive aircraft information to remain with the host aircraft in case the tran-
sponder is removed. This allows units to be swapped without the need for reprogramming the
unit.
The following paragraphs will give a brief description of operation on each of the blocks shown in
Main board block diagram.
4.3.6.1 System Clock
A 40MHz crystal (Y1) in conjunction with the bypass capacitors form the 40MHz system oscillator.
The generated 40MHz signal feeds the clock inputs of both the microprocessor, U1, and the Field
Programmable Gate Array (FPGA) U5, and UART U19. This clock is divided inside the FPGA to
generate different clocks for ARINC 429 LSI, U18, and voice synthesis IC, U70.
4.3.6.2 Microprocessor
U1 AMD 186ER, is a 3.3V integrated microprocessor which contains 32 Kbytes zero-wait state
RAM, general purpose configurable I/O pins, a UART, and two independent DMA channels. It has
a programmable interrupt controller with total of 6 external interrupts. A high speed synchronous
serial port is used to send configuration data to the FPGA. It has three 16-bit timers and a hard-
ware watchdog timer. The non-multiplexed address and data bus provide glueless interface to ex-
ternal RAM, U2, and external FLASH, U3. The microprocessor program resides in the FLASH.
The major tasks performed by the microprocessor include the following:

(1) Lights the display with the appropriate characters and brightness and communicates
to the display via the FPGA.

(2) Reads front panel rotary switches and buttons via the FPGA

(3) Reads external data lines i.e. Gillham altitude lines, Standby, On/Ground, Ident dis-
crete inputs via the FPGA.

(4) Receives Mode-S data from the FPGA and sends Mode-S reply data to the FPGA.

Rev. 1, May/2003 15563M01.JA Page 4-43

B KT 73

(5) Receives and transmits ARINC429 data via the ARINC429 LSI, U18.

(6) Communicates with three UARTs within U19.

(7) Provides ATE communications interface via the UART.

(8) Sets front panel display brightness by monitoring the photocell output via A/D con-
verter.

(9) The A/D converter also monitors the internal power supply voltages.

(10) Reads both the internal EEPROM on the Main Board and the external EEPROM on
the External EEPROM board (located inside configuration module).

(11) Initiates squitter by calculating the proper time intervals for the squitter and send a
signal to the FPGA to send the squitter.

(12) Checks squitter operation by reading TXSENSE signal.

(13) Communicates with the voice synthesizer U70 to generate audio message.

The 16-bit data bus and 18-bit address bus of the processor are tied to RAM and Flash. U3 is
AMD AM29LV200 2 Megabit 3.0 volt Flash memory. Processor lower and upper memory chip se-
lects, LCS and UCS are the chip selects to the RAM and Flash. The Flash has 44 pin TSOP pack-
age which is footprint compatible with 4/8/16 Megabit parts, AM29LV400/800/160. U2 is Cypress
CY62126 1 Megabit 3.3 volt SRAM.

The five processor interrupts are used as follows:

(1) INT0 is used to send an interrupt from the FPGA after the Mode-S data is sent to the
processor.

(2) INT4 will go active (high) at the end of mode-S reply.

(3) INT1 and INT2 are used to interrupt the processor by the UART A, B, C and D.

(4) INT3 is used by the ARINC429 LSI to interrupt the processor.

The processor sends and receives Mode-S data to and from the FPGA using DMA channel 0. The
sequence of events during interrogation are as follows:

(1) During a Mode-S interrogation, data flows from the FPGA to the processor. The
FPGA decodes and saves data one byte at a time. After the data is saved, the
FPGA will set the DRQ0 pin high which will initiate a DMA read from the FPGA.

(2) The processor will activate PCS5 to read the data from a known address.

(3) The FPGA decodes the address bus and PCS5. When the appropriate address oc-
curs along with PCS5, it will clear DRQ0 pin.

Rev. 1, May/2003 15563M01.JA Page 4-44

B KT 73

During Mode-S reply, data flows from processor to the FPGA. When the FPGA sets DRQ0 high,
the processor will initiate a DMA write (1 byte/DMA) to the FPGA. The FPGA loads it to a internal
shift register. The sequence of events during reply is as follows:

(1) During mode-S reply, data flows from the processor to the FPGA. The FPGA re-
ceives 1 byte of data at a time and writes it to an internal shift register.

(2) The processor will activate PCS5 when writing the data to a known address.

(3) The FPGA decodes the address bus and PCS5. When the appropriate address oc-
curs along with PCS5, it will clear DRQ0 pin.

The processor uses INT0 and INT4 interrupt inputs to set the DMA pointer to the proper direction.
When INT0 occurs, the DMA pointer will set to execute a write operation. When INT4 occurs, the
DMA pointer will set to execute a read operation. Note that INT0 occurs after a complete Mode-
S interrogation is received and INT4 occurs after a complete reply is sent out.
The processor sends display data to the FPGA using DMA channel 1. The sequence of events is
as follows:

(1) The Processor sends a pulse DSPLY_PW from its timer output 0 to the FPGA.

(2) When the FPGA detects the pulse, it will set DSP_REQ at DRQ1 pin of the proces-
sor high. The processor activates PCS3 to write the display data to FPGA.

(3) When the FPGA sees PCS3, it clears the signal at DRQ1 pin. The handshaking con-
tinues every time periodic display refresh pulse DSPLY_PW occurs.

The processor timer out1 is used as a general purpose IO. The processor holds this pin low until
the FPGA is fully configured. That will prevent the reply output, MOD_TRIG, from being set high
for a prolonged period of time during power up which may damage the transistors on the transmit-
ter board.
The processor uses the synchronous serial port to configure the FPGA. During configuration, the
pins INIT and DONE provide status outputs to the processor. The output INIT and DONE are held
low and RED_LED held high after the application of power. The processor starts the configuration
process by applying a pulse via PI022 at the program pin of the FPGA. SDATA and SCLK output
from the processor provides serial configuration data and clock to the FPGA. The INIT pin will go
high when there is a data error.
DONE pin will go high after a successful configuration is completed. The red LED DS1 will turn on
during the configuration and turn off after a successful configuration.
The chip selects PCS0 through PCS6 and MCS2 go to the FPGA except PCS2 which goes to the
429 LSI via bus translator. The pin MCS0_PIO14 is configured as IO and provides the reset pulse
to the UART and internal flip-flops of the FPGA. The internal UART of the processor is used for
the RS485 communication.
4.3.6.3 FPGA (refer to Figure 4-18)
U5, the KT 73 Main board field programmable gate array (FPGA) is a 208 pin Xilinx XCS40XL that
is programmed by the microprocessor using a dedicated synchronous serial port. FPGA program-
ming data resides in the main board Flash memory. A JTAG connector J9 may be used for de-
bugging and programming the FPGA which will last until the next power cycle.

Rev. 1, May/2003 15563M01.JA Page 4-45

B KT 73

The FPGA contains the digital logic to decode ATCRBS and Mode S interrogations and generate
appropriate replies to these interrogations. It interfaces with the following:
• The main board microprocessor U1.
• The display board through connector J3.
• The A/D converter U44.
• The serial nonvolatile memory U45.
• The external configuration memory via J6.
• UART U19.
• ARINC429 transceiver U18.
• Temperature sensor U60.
• Audio volume control U61.
• Audio synthesizer U71.
Also, it provides multiplexing control functions of the various pins in the two main board connectors
J1 and J6, which are external to KT73.
4.3.6.4 FPGA Input/Output Description
The FPGA has 44 single inputs, a 6-bit switch data bus SWDATA input, a 6-bit address bus, and
the ADDRBUS input. It has 58 single outputs, a 4-bit switch select bus SWSEL output, a 16-bit
Mode-S test points bus (TP_ModeS), and a 8-bit mode-C test points bus TP_mode-C. It has a
single bi-directional IO temp_SDA and a 16-bit bi-directional data bus.
The 40 MHz clock is provided from an on-board clock oscillator. The clock is internally divided to
20 MHz clock which is used in most of the functions. Microprocessor controls reset input (active
high). The 20 MHz clock uses a global clock buffer inside the FPGA. The microprocessor read
and write lines, pcs0 and pcs5 use global clock buffers. Remaining chip selects pcs1, pcs3, pcs6
and mcs2 do not use global clock buffer. These chip selects along with the address bus and read/
write lines are used to read and write from various addresses in the FPGA.
Amplitude video AMP_VIDn, limited video LIM_VIDn, 6dB video PW_6DBn, along with the sup-
pression inputs SUPR_9VBn and SUPR_ARCn are used to decode interrogations during mode-
C and mode-S interrogations. DPSKIN input from the receiver board is used to decode mode-S
DPSK data.
Eleven Gillham Altitude inputs ALT_A1 through ALT_D4, Ident input IDTx, standby input STBYx,
and on/ground input ONGNDx are read by the processor via FPGA.
There are two EEPROMs, one on-board and the other one is located in the external configuration
module. These EEPROMs are controlled via FPGA logic. Their read data lines are EEI_RDAT and
EEX_RDAT, chip selects are EE_ICS and EE_XCS. Data write and clock lines are EE_DAT and
EE_CLK. XEEPRM input represents logic 1 if external configuration module is present.
Audio volume control chip U61 also shares same data write and clock lines with a separate chip
select line VOLUME_CS.
The five pins A_D_DIN, A_D_DATA, A_D_CLK, and A_D_CSn and EOC provides A/D converter
interface to the processor. The four output pins RS485_429_EN, ADLP_EN, TISCNTL_EN,
TIS_EN, DISC_EN select between Gillham altitude input function and serial ports in J1 (TIS, serial
altitude, GPS) and between ARINC 429 TIS control function and RS232 ADLP/ADSB in the con-
nector J6. SQTR_HALT is an active low input applied from jumper CJ1 to turn off squitter trans-
mission.

Rev. 1, May/2003 15563M01.JA Page 4-46

B KT 73

UARTCSa, UARTCSb, UARTCSc and UARTCSd are generated by decoding the processor ad-
dress bus. These are the four chip selects for the four UART. The pin SWITCH_3DB controls 3
dB switch in the receiver board; however, this function is not currently used. Four switch select
outputs SWSEL and six switch data inputs SWDATA are used to read the current state of the four
4096 knobs on the front panel. The Mode switch input MODE_DAT and the three address bits
ANODE_A0, ANODE_A1 and ANODE_A2 are used to read the state of the Mode Switch knob on
the front panel.
DSPLY_PW input starts a display data transaction. Anode signals ANODE_A0 through
ANODE_E2, cathode signals CATH_A through CATH_R, and DSP_CSn and DSP_REQ control
display. ATCRBS and Mode-S reply monitor data. MON_DAT from the modulator board is fed
back into the FPGA which is read by the processor periodically.
RX_429INT and TX_429INT interrupt outputs from the 429 transceiver are combined and routed
through a single A429_INT output pin to the processor. TEMP_SDA and TEMP_SCL pins are
used to read and write to the temperature monitor IC. AUDIO_INHIBIT input and VOICE_RESET
output holds audio synthesizer, U70, into reset. VOICE_CLK and VOICE_DATA output and VCK
input provides interface to the synthesizer.
4.3.6.5 RESET Logic
The power valid signal PWR_VAL from the power supply board is an active high signal. When 12V
and 6V signal are both active on the power supply board, PWR_VAL will be 0 volt, which will drive
Reset to high. When either of these voltages is not present PWR_VAL will go to 4V which will drive
Reset line (U30 output) low and hold the processor in reset.
The output of a separate processor reset IC, U32, is wired-OR with the output of U30-B. When
the 3.3 volt returns to an in-tolerance condition, the U32 output will drive the reset signal in active
state for 150ms to allow the power supply and processor to stabilize.
4.3.6.6 Voltage Surge Protector
The voltage surge protector consists of CR12, C229, L10, C238, Q46, Q48, U57 and associated
bias resistors. This circuit will pass through 11V to 40V from source to drain of Q48. U57 is a
shunt regulator with a 2.495 volt internal reference. When the REF input exceeds the internal ref-
erence voltage, it will drive the cathode pin voltage towards anode pin voltage such that the REF
input, pin 8, voltage is close to the internal reference voltage. When the input voltage is 36 volts
or above, the circuit will regulate the drain output of Q48 to around 36 volts. When a nominal volt-
age (e.g., 28V) is applied at the source input, Q46 will turn on, which will turn on Q48.

The resistor network of R535 and R539 divides the drain output of Q48 and applies it to the REF
input of U57, which controls the gate of Q46. As the output voltage increases, the voltage applied
to the REF input increases. As the input voltage reaches 36 volts, the voltage applied to the REF
pin of U57 reaches 2.5 volts, which begins to regulate the output voltage via Q46 and Q48. As
the input voltage increases beyond 36 volts Q46 will gradually turn off in order to maintain 2.5 volts
at the REF input. This will gradually turn off Q48 (voltage drop will increase from source to drain)
reducing the output voltage to 36 volts.
4.3.6.7 Suppression IO
The suppression circuitry outputs a pulse on the SUPP_I/O line whose amplitude is greater than
18V for the duration that the KT 73 is transmitting. This pulse is applied to the aircraft suppression
bus. The function of the output pulse on the SUPP_I/O line is to disable nearby pulsed RF equip-
ment for the duration of the pulse. An input suppression pulse seen on the SUPP_I/O line signifies
that other pulsed RF equipment is transmitting and stops the FPGA from responding to received
interrogations for that duration.

Rev. 1, May/2003 15563M01.JA Page 4-47

B KT 73

The output suppression pulse is generated by the FPGA when KT 73 is replying to ATCRBS or
Mode-S type interrogation or during the transmission of a squitter. Prior to the suppression pulse,
C208 is at -12 volts (Suppression IO, KT73 Main board). The signal SUPR_OUT from the FPGA
turns on Q42 which turns on Q45. The voltage on the negative side of the capacitor C208 goes
to 24 volts. Since capacitor will try to hold constant voltage across it, the voltage on the positive
side will also go to 24 volts resulting in a 24 volt pulse on the suppression bus. Diode CR27 will
prevent the capacitor (+ polarity) voltage from going below ground by more than the diode drop.
Diode CR26 isolates C208 from suppression input. A suppression input will charge C185 via
R381 and R524 to +5 volts (due to clamping diode CR25-B). When this voltage exceeds the ref-
erence voltage at the non-inverting input of U47-A, its output will go low. Capacitor C186 discharg-
es through diode CR25-A and R381. R524 acts as a current limiting resistor. A similar circuit
(without a clamping diode, e.g., CR25-B) accepts 9V King suppression input. These suppression
inputs are fed as active low pulses into the FPGA.
4.3.6.8 Mode-C Reply Rate Limit Circuit
The FPGA produces 46 microsec pulse via XMIT_C pin each time an ATCRBS reply pulse is
transmitted and charges capacitor C271 via R551 and diode CR7. When the voltage at the invert-
ing input of U43-A goes over the voltage at the non-inverting input, its output at pin 1 will go low.
This will turn on Q44 and C272 charging approximately 6 volts via R477. The discharge of C271
is accomplished by R446. The discharge of C272 is accomplished by R447. C271 and C272 will
charge faster than they will discharge. Diode CR2 and Q36 provides isolation when the rate limit
circuit is not active. When the rate limit circuit is active, it decreases the effective receiver sensi-
tivity by about 30 dB. The reduction in sensitivity is caused by increasing the threshold voltage on
the video comparator U10 to a voltage which equals a receive signal level of 30dB above MTL.
4.3.6.9 MOD TRIG RST
The processor pin TMR_OUT1_PI01 is configured as a general purpose output PI01. This output
drives one input of AND gate U33 while the other input is driven by reply modulation signal. The
output MOD_TRIG drives the modulator board. MOD_TRIG is always held low except during re-
ply to prevent device failure on the transmitter board. The processor keeps PI01 low and hence
MOD_TRIG low until the FPGA is initialized. A pull down resistor R581 also ensures that
MOD_TRIG is low during power up and subsequent initialization.
4.3.6.10 Switch Interface
The front panel switches are read by the processor via the FPGA signal SWSEL1 through
SWSEL4, SW_MODE, and SWDATA0 through SWDATA5. A level translator, U8, shifts the 5 volt
input to 3.3 volt logic. The processor holds one of the 4 SW_SEL lines low and reads the switch
position of one of the 4096 switches via SWDATA0 through SWDATA5. The processor reads the
position of mode switch and the status of IDT and VFR switches via the line SW_MODE.
Voltages +90 volt and -90 volt are regulated on the main board before they go to the display board.
U7 with R570, R571 and R572 regulates -90 volt. Q1, CR1, R463, R464 and R466 regulate +90
volt line.
4.3.6.11 Display Interface
The processor via the FPGA controls the display. The processor writes appropriate cathode data
into the FPGA which drives the cathodes via 16-bit cathode bus CATH_A through CATH_R. The
cathode bus switches -90 volt to the appropriate cathodes via the connector J3. When CATH_A
goes high, it will turn on Q10 which will turn on Q26 and apply -90 volt to the cathode
DSP_CATH_A via pin 23 of J3. Similarly, other cathode bus signals from the FPGA turn on sep-
arate pair of transistors and apply -90 volts to the appropriate cathode.

Rev. 1, May/2003 15563M01.JA Page 4-48

B KT 73

Display anodes are controlled by the processor via six FPGA signals. These are ANODE_A0,
ANODE_A1, ANODE_A2, ANODE_E2, ANODE_ELX, and ANODE_MSG which go to the display
board via J3. These signals drive a 3-to-8 decoder which applies +90 volts to the appropriate an-
odes (display board).
4.3.6.12 Analog to Digital Converter
The TLV2543 is an ADC (U44) that converts the analog signals of SUPPRESS_IO, PHOTO, +3.3
volt, +5 volt, +6 volt, +12 volt, +65 volt, +90 volt, -12 volt, - 90 volt and -5 volt lines to their digital
equivalents. The digitized signals are read by the processor through the FPGA. The amount of
ambient light determines the resistance of the photocell which, in turn, determines the voltage at
the input to the A/D converter.
4.3.6.13 Serial EEPROM
The 32K bit serial EEPROM (U45) stores information for the unit when it is turned off. The EE-
PROM stores the aircraft address, maximum airspeed, VFR code, last 4096 code, flight ID, SPR
delay, fault codes (when a failure occurs) including time and temperature, etc. Use of an optional
external EEPROM Board allows a unit to be removed from one aircraft and installed in another
without reprogramming the address, airspeed, etc. of the specific aircraft.
The information for the EEPROM is read in from the front panel by means of a special program-
ming mode. The presence of an external EEPROM is determined by the logic of the signal EX-
TERNAL EEPROM at pin 2 of J6. Processor writes necessary data to the internal EEPROM and
the external EEPROM, if present. It reads the data from the external EEPROM if present; other-
wise, the internal EEPROM is used.
4.3.6.14 Transmitter Monitor
The transmitter monitor signal TX_SENSE_5V comes from the modulator board via pin 7 of J5.
U34 level shifts the signal and feeds it to the FPGA for storage. The processor reads data later
and compares it with the actual reply data.
4.3.6.15 UART
UART circuitry consists of U19 quad UART IC and U20 RS232 driver which are used to provide
the KT73 with RS-232 communications capability. Processor RD/WR and partial address and
data lines are used to read and write to the UART.
It uses the 40 MHz clock while chip selects are driven by the FPGA. Three out of four UARTs are
used; GPS, altitude, and ADLP serial communication. The ADLP port is also used for new pro-
gram loading and communicating with the KT 73 via a PC serial port. This facilitates automated
software and hardware testing.
4.3.6.16 ARINC429
The 429 circuitry consists of 429 LSI (U18), level shifter U16 and U17, transmitter driver U40, Q49
through Q52 and associated resistors. U39C/D will disconnect the driver circuit from connector
pins. Processor RD/WR and partial address and data lines go to the LSI via level shifter. Proces-
sor PCS2 drives the chip select input and clock signal is driven by the FPGA.
4.3.6.17 RS485
The UART inside the processor and a 485 driver U41 comprises RS485 circuitry. The analog
switch U58 can connect RS485 receivers and transmitters to the connector J1.

Rev. 1, May/2003 15563M01.JA Page 4-49

B KT 73

4.3.6.18 Discrete Inputs

Discrete inputs are Gillham altitude inputs, audio inhibit, standby, on/ground, and Ident inputs.
These inputs are diode isolated and fed to non-inverting inputs of comparators U21, U22, U23 and
U46. Most of the Gillham inputs share their pins with RS232, ARINC429 and RS485 IO serial
communication busses . The KT 73 can use either Gillham altitude inputs or the serial bus. The
processor enables Gillham altitude input by writing a logic ’1’ to DISC_EN signal. This will turn on
Q41, which will turn on Q43. This will apply +12 volt (SW_DISC_V+) at anodes of the diodes and
allow the comparators to switch high when discrete input is open and switch low when it is tied to
GND. The processor disables Gillham input by writing a logic ’0’ to DISC_EN signal. This will turn
off Q41 and Q43 and reverse bias the diodes by applying -12 volt to the anodes.
4.3.6.19 Analog Switches
U38, U39, U58 and U69 each contain quad analog switches which are used to multiplex KT 73 IO
pins on connectors J1 and J9. The processor disables Gillham altitude input by asserting a high
at the signal DISC_EN input of Q41. These analog switches are controlled by four signals
429_ON, TIS_ON, ADLP_ON and TISCNTL_ON. The processor writes to these signals via the
FPGA and transistors Q53 through Q56.
4.3.6.20 Video Processing Circuits
The video processor converts analog pulses from the detected log IF amplifier located in the re-
ceiver board and converts the signals to digital logic levels used by the FPGA. Upon entering the
video processing circuit the video signal is split into three channels.
Two peak detecting circuits are used. One is used for pulse width measurement and has a short
time constant in its sample and hold circuit. The other peak detector has a relatively long time
constant and is used to compare pulse amplitudes, specifically P1 versus P2 and P3 versus P4.
The third channel is a delayed video channel. The video is delayed by approximately 100nsec.
This delayed video is then compared with the two sample and hold channels resulting in a series
of pulses generated by the comparators U10, U11, and U12. These signals are sent to the FPGA
to be decoded.
An additional circuit, which provides ATCRBS rate limiting, integrates pulses from the FPGA which
are generated when the transponder replies to an ATCRBS interrogation.
The output of the integrator is compared with the delayed video channel and effectively reduces
the receiver sensitivity by 30dB if the integration circuit detects an overload condition.
In order to prevent receiver noise from interfering with the video processing operation, a DC level
is generated which is set slightly above the receiver noise level. This level is ORed with the output
of the sample and hold amplifiers and prevents spurious pulses from being delivered to the FPGA.
The sample and hold amplifiers must be discharged at a certain rate and time as specified by
MOPS DO-181C. The average recovery rate is specified as 4dB per microsecond. The FPGA
sends SAMPLE_HOLD signal which is used to start the recovery at about 3.0 microsec after the
falling edge of P1 or P3.
Upon entering the video processing circuit, the video is split into three paths. One video signal
runs through a 100ns delay line consisting of L9, C182, L7, C218, L8, and C217. R574 provides
the proper termination for the delay line. Capacitor C16 and CR4 are a speed up network driving
Q37 which is configured as an emitter follower. The output of Q37 is a low impedance source for
the video comparators.
The other two signals are used to drive sample and hold amplifiers. The pulse width channel con-
sists of R497, R397, and C184. They function as a DC level shifter with the AC amplitude re-
tained. Diode CR6 charges C423 and C219 to the peak value of the detected pulse.

Rev. 1, May/2003 15563M01.JA Page 4-50

B KT 73

Q38, in an emitter follower configuration, presents a high input impedance to the hold capacitors
C219 and C423 and provides a low output impedance for the video comparators.
Resistor R476 is used to discharge the hold capacitors C219 and C423 once the pulses are de-
coded. R497 is adjusted to set the DC level at the output of Q38 to be approximately 4dB below
the peak level of the pulses present at the emitter of Q37.
The pulse amplitude channel consists of R576, R399, and C183. They function as a DC level
shifter with the AC amplitude retained. Diode CR5 charges C232 to the peak value of the detected
pulse.
Transistor Q35, in an emitter follower configuration, presents high input impedance to the hold ca-
pacitor C232 and provides low output impedance for the video comparator U12.
Resistor R486 is used to discharge C232 once the pulses are decoded. Resistor R576 is adjusted
by monitoring reply rate of an ACL interrogation at -70dBm and -21 dBm. It is adjusted such that
at both input power levels, when P4 is equal to P3-1dB, Mode-S reply rate must exceed 90%.
When P4 is P3- 6dB, ATCRBS reply must exceed 90% at -21 dBm and -70 dBm.
The sample and hold circuit in the pulse width channel charges considerably faster than the one
in the pulse amplitude channel. With both channels there is a finite time required to charge the
hold capacitors. This is the reason for the delay line.
It is desirable to have the hold capacitor charge to its maximum value before making a comparison
with the video. However, the same current is required by the buffers following the capacitors, so
the capacitors have to be large enough to supply the current.
The pulse width channel needs to hold its value only long enough to make pulse by pulse mea-
surements. The pulse amplitude channel compares amplitude from one pulse to another making
it necessary for the hold capacitor to be much larger.
As a result of the different charge rates and sample points in the two sample and hold channels,
the pulse widths and pulse positions at the output of the video comparators are different.
The pulse position on the pulse amplitude channel will be delayed by about 100ns from the pulse
width channel. The pulse widths on the pulse amplitude channel will also vary because the sam-
ple capacitor is still charging when the first pulse is compared. This results in the first pulse (P1)
being about 50ns longer than the second pulse (P2).
Additionally, because of this slow charge rate, the pulse positions will increase from the nominal
2 microsec spacing by about 50ns. The FPGA looks at the pulse width channel,
UNLIMITED_VIDEO, to determine whether a pulse of correct width and spacing has been detect-
ed.
During the time the FPGA is measuring the pulse width, it looks at the pulse amplitude channel to
see if the pulse amplitude threshold has been exceeded. This is done 450ns after the leading
edge of a pulse on the pulse width channel.
The FPGA samples at this channel, ATCRBS RATE LIMITED VIDEO, during ATCRBS interroga-
tion. If a pulse is not detected 450ns after the leading edge of a pulse on the pulse width channel,
the FPGA assumes that a rate limit condition exists and does not generate a reply. The rate lim-
iting will occur at 1200 PRF.
The FPGA sends SAMPLE_HOLD signal to turn on Q34 3.0 microsec after the falling edge of a
pulse (P1, P3) and discharges the pulse width hold capacitors C219, C423 and pulse amplitude
hold capacitor C232.
The resistive divider combination of R573, R478 and R575 set a DC voltage for the noise thresh-
old. Q39 and Q40 provide the necessary buffering. The output of Q40 is wired OR with the output
of the pulse amplitude channel Q35. The output voltage level of Q40 is adjusted to set the tran-
sponder MTL and prevent noise from triggering the video comparator U12. The output of Q39 is
wired OR with the output of the pulse width channel Q38.

Rev. 1, May/2003 15563M01.JA Page 4-51

B KT 73

The resistive divider network of R411 and R412 lowers the noise threshold for the pulse width
channel by approximately half. This lower threshold setting enables the video comparator U11 to
make an accurate pulse width measurement while preventing noise from triggering the compara-
tor.
4.3.6.21 Voltage Regulator
The -5 volt regulator (U9) provides clean -5V used in the bias network which is particularly sensi-
tive to noise and power supply ripple. Examples are the divider networks of the PULSE WIDTH
and PULSE AMPLITUDE channels. The comparators U10, U11, and U12 require a clean supply
voltage. R413, C205 and C156 are used to provide a clean +12V_C as positive supply to the com-
parators. -12V is filtered through R493 and C207 to provide -10V_C as negative supply to the
comparators. This reduces power supply noise and ripple on the +12V_C and -10V_C lines which
are then used to power up the comparators.
4.3.6.22 Audio Circuit
The Audio circuit comprises of audio synthesizer U70, digital attenuator U61, buffer U72-A, audio
amplifier U73, and audio transformer T1. U70 synthesizes voice messages. Messages consist
of 16 bit words that are stored in the Flash memory. The processor sends the 16 bit words to a
FIFO built inside the FPGA. Necessary control logic for the FIFO and audio synthesis IC is de-
signed inside the FPGA where 16 bit words are split into 4 bit nibbles. A 625 kHz clock from the
FPGA is applied to U70 (XT input) which outputs a 7.8 kHz sampling frequency (VCK output) with
a cut off frequency 3.12 kHz. The voice chip has an on-board DAC. The DAC produces an analog
signal which is then attenuated by a digital attenuator. The attenuator shares the same data input
and clock lines as the internal and external EEPROM with a separate chip select line. Attenuation
can be controlled from the front panel to give the desired volume. The next op-amp buffers the
signal before it is ac coupled. U73A inverts and amplifies the signal. U73B invert and amplifies
U73A output. The true and inverted signals drive the transformer primary. The secondary of the
transformer is the output which will drive a 600 ohm load.
4.3.6.23 Temperature Sensor
U60 is a 9 bit digital temperature sensor with built in temperature to digital converter. The data is
read out serially by the processor. It has a bi-directional data line and a clock input. The processor
accomplishes read and write operation via the FPGA. It has a temperature accuracy of +/-2 deg.
C over a range of -25 deg. C and 100 deg. C.

Rev. 1, May/2003 15563M01.JA Page 4-52

B KT 73

FIGURE 4-17 KT 73 MAIN BOARD BLOCK DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 4-53

B KT 73

FIGURE 4-18 KT 73 FPGA BLOCK DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 4-55

B KT 73

SECTION V
MAINTENANCE

5.1 INTRODUCTION
5.1.1 GENERAL
The maintenance section contains test and alignment procedures for an operational KT 73 Mode
S Transponder, unit P/N 066-01164-0101. This section also contains troubleshooting and assem-
bly/disassembly procedures. Before maintenance is attempted it is advisable to have thorough
understanding of the theory of operation of the unit.
5.1.2 ATC TRANSPONDER TESTS AND INSPECTIONS
5.1.2.1 General
Every two years, the FAA requires that transponders, including the KT 73, be tested and inspected
and found to comply with appendix F of part 43 of chapter 91.413, ATC transponder tests and in-
spections.
5.1.2.2 Display Readability Test
At the same time that the tests noted in section 5.1.2.1 are performed, inspect the KT 73 display
to verify that the display readability is sufficient to provide operational usage in the normal lighting
conditions of the aircraft. If the display readability is unsatisfactory, contact a dealer to have the
display replaced.
5.1.3 KT 73 FIELD SOFTWARE LOAD PROCEDURE

CAUTION:
All work must be conducted in an ESD safe en-
vironment.
NOTE:
All work must be performed by Honeywell approved
Repair & Overhaul facilities personnel.

5.1.3.1 Requirements
1. An IBM compatible PC running MS Windows 95, 98, NT, or 2000.
2. KT 73 Load Media CD (P/N: 222-30035-0102).
3. A wiring harness for loading the KT 73 software.
This harness can be built using a KT 73 Bench Test kit (P/N: 050-03675-0000). Re-
fer to the installation manual (006-10563-00XX) for pin out information and figure 5-
1 of this manual for an assembly diagram. The harness must include the following
provisions.
a. 28V or 14V DC Power.
b. A female DB-9 Connector wired to the RS-232 port on the 7 pin configuration
module connector. Optionally, wire to the small card edge connector, bypass-
ing the configuration module. It is critical that TX, RX, and GROUND all be
wired. Without a signal ground, the connection will be unreliable.

Rev. 1, May/2003 15563M01.JA Page 5-1

B KT 73

NOTE:
A PC serial port pin out is shown below.

PIN Signal

1 Received Line Signal Detector (CD)

2 Received Data (RX)

3 Transmitted Data (TX)

4 Data Terminal Ready (DTR)

5 Signal Ground (GND)

6 Data Set Ready (DSR)

7 Request to Send (RTS)

8 Clear to Send (CTS)

9 Ring Indicator

5.1.3.2 Load Procedure

1. Apply power to the KT 73.
2. Turn the Mode selector to SBY.
3. Dial 4096 code 0000.
4. Press and hold the IDT button.
5. Press and hold the VFR button.
6. Continue holding the two buttons until the radio enters programming mode. (The dis-
play will change.)
7. Turn the left code knob until the display reads ENH FUNC.
8. Press the IDT button.
9. Turn the left code knob until the display reads ADLP.
10. Press the IDT button.
11. Turn the Mode selector to OFF.
12. Turn the Mode selector to ON.
13. Connect a PC to the DB-9 connector.
14. Start the KT73Loader.exe program provided on the Load Media CD.
15. Follow the on-screen prompts to load the code.
16. The load should complete successfully.
17. Turn the mode selector to TST.
18. Wait for the lamp test to complete.
19. Press the VFR button.

Rev. 1, May/2003 15563M01.JA Page 5-2

B KT 73

20. Verify that the following software versions are displayed:

a. APPL XXXX, where XXXX is the version number for the Application code in
the service bulletin.
b. BOOT XXXX, where XXXX is the version number for the Boot code in the
service bulletin.
c. FIRM XXXX, where XXXX is the version number for the Firmware in the ser-
vice bulletin.
d. VOIC XXXX, where XXXX is the version number for the Voice data in the
service bulletin.
21. Remove power from the unit.
22. Remove the old software MOD sticker from the rear of the unit.
23. Apply the new software MOD sticker to the rear of the unit.
24. The software upgrade is complete.

5.2 TEST, ALIGNMENT AND TROUBLE SHOOTING

5.2.1 TEST EQUIPMENT REQUIRED
This section contains information on special tools, fixtures, and test equipment used to test, trou-
bleshoot, align, and repair the KT73 Transponder unit. The following is a listing the test equipment
required to perform the testing and troubleshooting procedures described in this manual. Equip-
ment other than that listed can be substituted if the characteristics fulfill those required. Quantities
required are one unless otherwise specified. Refer to Figure 5-1 for a test setup diagram.
• KT 73 test harness and setup (customer fabricated, see Figure 5-1).
• IFR ATC-1400A, S-1403DL or S-1403 DME/Transponder test set.
• Oscilloscope: Tektronix TDS 380 or equivalent.
• Digital multi-meter, 3 1/2 digit, 10 mv.
• Spectrum Analyzer, Hp 8591E or equivalent (optional but recommended).
• High Frequency Probe , AGILENT (HP) 85024A or equivalent.
• Frequency counter, 250 Mhz. (optional).
• BOONTON 41A RF power meter and BOOTON 41-4a RF probe. (optional).
• 6db RF combiner HP 11636a.
• BK PRECISION Power Supply, 0 to 30 Volts, 5 Amps (or equivalent).
• PELTOR HEADSET (300 ohms) or equivalent.
• External EEPROM ASSY. P/N 200-09889-0010.
• Standard P.C. (IBM compatible) computer (laptop or desktop).
• Standard 9 pin P.C. serial (comm) port cable (generic).
• Standard 9 pin D-SUB serial connector with backshell (generic, 3 required).
• Standard 1/4 in. inline 2 conductor (mono) jack (generic).
• Standard 1/4 in. inline 3 conductor (stereo) jack (generic, 3 required).
• Bench Test Kit 050-03675-0000 which contains the following:

Rev. 1, May/2003 15563M01.JA Page 5-3

B KT 73

SYMBOL PART NUMBER DESCRIPTION UM QUANTITY

P1 030-01094-0002 CONNECTOR 12/24 P EA 1.00
P2 030-01094-0009 CONNECTOR CE EA 1.00
030-01096-0000 KEY POLARIZER EA 2.00
030-01107-0012 CONNECTOR TERM 12T EA 12.00
030-01107-0024 CONNECTOR TERM 24T EA 1.00
030-01407-0000 CONTACT FEMALE EA 7.00
030-01464-0000 HOOD W/JACKS D9 EA 3.00
030-02346-0001 CONN SUB-D CA 9S EA 3.00
030-03454-0002 CONN, RECT, RECPT, EA 1.00
222-30067-0000 KT 73 DIAGNOSTIC UTILITY EA 1.00

5.2.2 TESTING AND TROUBLESHOOTING

(a) Initial Setup

To initially setup the test system refer to Figure 5-1 and proceed as
follows:
1) Ensure all plugs and cables are secure and connected as
shown in Figure 5-1.
2) Allow a 30-minute warm up for the unit under test and the
test equipment.
3) On Transponder/DME test set ATC-1400A, set switches as
follows:

SWITCH POSITION

SUPPRESSOR OFF
CW/NORM/OFF NORM
F2/P2 - F1/P1 F2/P2
GPIB Address A2 ON
GPIB Address all others OFF

Rev. 1, May/2003 15563M01.JA Page 5-9

B KT 73

NOTE:
The following switches are on the front of the ATC-
1400A: SUPPRESSOR, CW/NORM/OFF, and F2/
P2. The following switches are on the backside of
the ATC-1400A: GPIB Address A2, GPIB Address
all others.

4) At S-1403DL or S-1403 turn (sequence) number 0 or 1 ON

all other sequence numbers off.
(b) Turn-on/Turn-off
1) Turn-on
To turn the KT 73 test system on, proceed as follows:
On KT 73 test harness ( Bench Power Supply ), place ON/
OFF power switch ON.
Verify ON/OFF POWER indicator is illuminated.
(c) Turn-off
To turn the KT 73 test system off, proceed as follows:
On the KT 73 test harness ( Bench Power Supply ) place ON/OFF
POWER switch OFF.
(3) ON/OFF and Display Check and Function

KT 73 SELECTOR KT 73 DISPLAY

SBY position Only 4096 code

5.2.5 RETURN TO SERVICE TESTS

The return to service function is a test sequence that provides a comprehensive evaluation of the
KT 73 Basic Mode S Transponder.
A. Signals and Conditions
Standard ATCRBS Interrogations: 450 PRF, 4096 code = 7777
Standard Mode S Interrogations: 45 PRF, UF-11, short replies
Mode S Address all 7’s, (56 µsec),
Standard Mode S Interrogations: 20 PRF, UF-04, RR-12 Long replies
Mode S Address “52525252” (112 µsec)

B. Unit Program Set Up:

Program the Unit under Test as follows:
1. Mode S Address = “52525252”
2. Air Speed = 75 / 150
3. Altitude Source = GILLHAM
4. Enhanced Function = NONE
5. Auto Ground= ENABLE
6. Air Volume= “63”
7. Ground Volume = “63”

C. Test Procedures
The following procedure/data sheet will assist in determining whether the transpon-
der is ready to return to service.
NOTE:
Measurement reference point is antenna end of 2.0
± 0.1 dB loss coaxial cable to the unit under test.
Make sure the antenna connector of the transponder
is connected to the RF I/O of the ATC-1400A test
set, before turning ON the transponder.

(1) Current Drain:

Aircraft Back Lighting Current:
@ +13.75 volts _______________ ma 320 ± 16 ma
@ +27.50 volts _______________ ma 160 ± 8 ma

Note:
With a standard RF level, measure the current drain
of the transponder. Aircraft DC Power Supply Cur-
rent: (Mode A, 4096 = 7777, PRF = 750)

@ +13.75 volts _______________ Amps 2.50 Amps Max.

@ +27.50 volts _______________ Amps 1.25 Amps Max.

Rev. 1, May/2003 15563M01.JA Page 5-15

B KT 73

(2) Display Dimming:

Momentarily cover the display photocell.
Does the display intensity change? ________ Yes
Display segments: Turn the mode select Switch to the “TEST” position.
Are all segments are lit? ________ Yes
(3) IDENT:
With mode select Switch in the “ON” Position, Press the Ident button Ident
Pulse Duration:
The “IDT” should be lit on the Display _______ Yes.
Note:
Use a standard ATCRBS interrogations, and stan-
dard RF level.

Ident duration:
Use an oscilloscope and measure the Ident pulse transmit duration of the
transponder. _______ sec 18 ±2 sec
(4) Suppressor In/Out:
Use standard RF level, monitor the output of the suppress in/out line, and
measure the following using an oscilloscope:
For standard ATCRBS interrogations, during transmission:
Amplitude = _______ V 18-70 volts
Duration = _______ µsec., not to exceed 35 µsec
For standard Mode S (UF-04, RR-00, “52525252”) interrogations, during
transmission:
Amplitude = ________ V 18-70 volts
Duration = ________ µsec., not to exceed 75 µsec
For standard Mode S (UF-04, RR-12, “52525252”) interrogations, during
transmission:
Amplitude = ________ V 18-70 volts
Duration = ________ µsec., not to exceed 130 µsec
For standard ATCRBS interrogations:
Does the transponder transmit when a 18-70 volt Pulse dc is applied to the
suppress in/out pin? ______ No
Does the transponder transmit when 18-70 volts dc is applied to the sup-
press in/out pin? ______ Yes
(5) 9V Suppression In:
Note:
Use a standard interrogations and RF level.

Does the transponder transmit when a 6-12 volt Pulse dc is applied to this
pin? ____ No
Does the transponder transmit when 6-12 volts dc is applied to this pin?
____ Yes

ALTITUDE :
Gillham Altitude Coding:
IFR Display
Altitude in Feet Discrete InputsY / N
900 C1 C2
1,000 B1 B2 C2
2,000 B1 B4C2
6,800 A2 A4 C4
10,000 A2 A4 B1 B4 C2
26,100 A1 A4 B1 B4 C1 C2
33,500 A1 B1 B2 B4 C2 D4
41,400 A1 A2 A4 B1 B2 B4 C1 C2 D4
60,000 B1 B2 B4 C2 D4
62,100 C1 C2 B4 D4
INVALIDC1 C2 D4 D2
(12) MODE SWITCH Confirm the following:
a. With Valid Gillham inputs and the Mode Switch in the “ALT” posi-
tion. The unit Will Reply with altitude information _____Yes
b. With Invalid Gillham inputs and the Mode Switch in the “ON” posi-
tion. The unit Will Not Reply with altitude information _____Yes
(13) External Ident: Confirm the following condition:
When the external Ident is grounded, the unit will transmit a SPI Pulse for
about 18 seconds._________ Yes
(14) External Stand By: Confirm the following condition:
When the external Stand By is grounded, the unit will go into stand by
_______ Yes
(15) Audio Output: Confirm the following condition:
Connect a 300-ohm head set to the Audio Hi and Lo Outputs.
Turn the KT73 Mode Select Switch from “ON” to “TST”.
After the Display Light All Segments Test, the unit should display “TEST
OK”, and also produce an audible announcement “TEST OK”.
_______ Yes
(16) Audio Inhibit: Confirm the following condition:
Connect a 300-ohm head set to the Audio Hi and Lo Outputs.
With the Audio Inhibit grounded, turn the KT 73 Mode Select Switch from
“ON” to “TST”.
After the Display Segments Test, the unit should display “TEST OK”, and
also produce an audible announcement ”TEST OK”. _______ Yes

Rev. 1, May/2003 15563M01.JA Page 5-20

B KT 73

(17) Serial I / O Test:

Note:
Use Diagnostic Utility CD-ROM P/N 222-30067-
XXXX.

Test Selected: Test Results:

Verify Connected Responds with communication verification: OK?

________ Yes

Current Temp Responds with Unit’s temperature: __________ Yes

Temp Extremes Responds with Unit’s Min & Max temperature:

________ Yes
Hobbs Time Responds with time: __________ Yes

Serial Number Responds with Unit’s Serial Number: _________ Yes

Software Revision Responds with Unit’s Revisions of Firmware, Boot,

Application & Voice: ________ Yes

Generic Loop-back Responds with communication verification & current

(ALT_RS232) Baud Rate: ________ Yes

Generic Loop-back Responds with communication verification & current

(GPS_RS232) Baud Rate: ________ Yes

(18) Configuration Module

Note:
This section of the test may be omitted if deemed
"Not Applicable".

a. Generator set up: PRF = 50, UF11, Address = "77777777".

b. Observe the Mode S address on the S-Menu of the generator.
c. Install configuration Module program unit’s mode address to
"11112222".
d. Turn the unit OFF, then ON.
e. Verify the Mode S address is "11112222". ____________ Yes
f. Remove the configuration Module
g. Verify the Mode S address is "11112222". ____________ Yes
h. Install configuration Module program unit’s mode address to
"52525252".
i. Turn the unit OFF, then ON.
j. Verify the Mode S address is "52525252". ____________ Yes
k. Remove the configuration Module
l. Verify the Mode S address is "52525252". ____________ Yes

Rev. 1, May/2003 15563M01.JA Page 5-21

B KT 73

(19) TIS Receive / Transmit Test (ARINC 429)

Note:
This test is optional and requires the KMD 540 MFD.

a. Setup Instructions:
1. Install a KMD 540 per procedures in the KT 73 Install Man-
ual.
2. Program the KT 73 for TIS mode.
3. Apply power to both units.
4. Turn the KT 73 Mode Select switch to the altitude position
("OFF" -> "ALT"), and displaying a valid altitude.
5. On the KMD 540, select the Traffic Page.

b. Test Procedure
1. With the KT 73 Mode Select Switch in the "ALT" position.
KMD 540 Message displayed:
"TIS ON" ___________ Y
"TIS UNAVAILABLE" ___________ Y

2. Turn the KT 73 Mode Select Switch to the "ON" position.

KMD 540 Message displayed:
"TIS ON" ___________ Y
"TIS IS NOT ENABLED. TRANSPONDER MUST BE
REPORTING ALTITUDE." ___________ Y

3. On the KT 73, interrupt the ARINC 429 receiver.

KMD 540 Message displayed:
"TIS FAIL" ___________ Y
"REPORTED TRAFFIC SYSTEM FAILURES.
TIS CONTROL" ___________ Y

4. On the KT 73, interrupt the ARINC 429 transmitter.

KMD 540 Message displayed:
"TIS FAIL" ___________ Y
"NO DATA RECEIVED
FROM TRAFFIC UNIT" ___________ Y

Rev. 1, May/2003 15563M01.JA Page 5-22

B KT 73

5.2.6 ALIGNMENT PROCEDURES SETUP

Alignment procedures in this paragraph are intended only for use when the KT 73 transponder
does not meet functional test requirements as presented in paragraph 5.2.4 of this section "Test-
ing and Troubleshooting".
The alignment should be performed with particular attention to the sequence of steps. Certain
segments of the radio must be pre-aligned using sub-sections of the alignment procedures before
a complete alignment can be accomplished.
The test equipment required to perform the alignment procedure described in this manual is the
same as previously listed. Equipment other than that listed can be substituted if their character-
istics are the same.
The setup for the alignment is similar to the test setup recommended in paragraph 5.2.1 of this
section. The IFR ATC-1400A/S-1403 must be specifically setup in order to perform the DPSK
alignment as described in Section 5.2.8 C.

5.2.7 ALIGNMENT PROCEDURES

A. Power Supply Alignment
1. With the UUT Mode Select switch "ON", adjust R16 for 6.0 ± 0.1 volts at
TP13.
2. Adjust R77 for 3.3 +/- 0.1 VDC.
B. Programming the Internal EEPROM (Reference Figure 5-2)
The unit’s build is assumed to be complete including software installation.

Note: The third knob from the left is the “Blank” knob.

FIGURE 5-2 KT 73 FRONT PANEL

Rev. 1, May/2003 15563M01.JA Page 5-23

B KT 73

1. When the unit is turned on for the first time, it will display "AA1" in the alti-
tude window and the four most significant OCTAL digits of the aircraft ad-
dress in the Ident window which will be zeros. Then it will cycle to "AA2" and
four zeros will be displayed for the 4 least significant OCTAL digits of the
aircraft address. To change the aircraft address from all 0’s to a valid ad-
dress, the KT73 will need to be put in the programming mode.
a. The KT 73 will enter the programming mode after the following front
panel control sequences:
b. Put the unit in Standby Mode.
c. Select 0000 ident code.
d. Depress the IDT button (and hold) and then the VFR button for a
minimum of 3 seconds and the first menu "A/C ADDR" appears.
e. Press the IDT pushbutton and "AA1 0000" menu appears. Turn
Ident code selector knobs to enter the four most significant OCTAL
digits of aircraft address. "5252" is suggested.
2. Depress the "IDT" pushbutton and "AA2 0000" menu appears. Turn Ident
code selector knobs to enter the four least significant OCTAL digits of air-
craft address. "5252" is suggested.
3. Set Max Air Speed: Depress the "IDT" pushbutton and "MAX AIR " menu
appears. Depress the IDT button. Turn the "CRSR" Ident code select knob
until "75 150" appears. Depress the "IDT" button.
4. Set Altitude Source: Turn the Ident code select knob until "ALT SRC" ap-
pears. Depress the IDT button. Turn the Ident code select knob until "GILL-
HAM" appears. Depress the "IDT" button.
5. Set Auto Ground: Turn the Ident code select knob until "AUTO GND" ap-
pears. Depress the "IDT" button. Turn the "CRSR" Ident control knob until
"ENABLE" appears. Depress the "IDT" button.
6. Set Air Volume: Turn the "CRSR" Ident code select knob until "AIR VOL"
appears. Depress the "IDT" button. Turn the Ident control knob until "40"
appears. Depress the "IDT" button.
7. Set Ground Volume: Turn the "CRSR" Ident code select knob until "AUTO
GND" appears. Depress the "IDT" button. Turn the Ident control knob until
"40" appears. Depress the "IDT" button.
8. Recycle the power of KT73 and the new address will replace previous all
zero address.

C. Receiver Tuning Procedure

NOTE:
The receiver cover should be left off and the Local
Oscillator should have both covers installed

1. Local Oscillator Alignment

a. Adjust the cores of IF transformers T2 through T6 to center position
and R217 to its center position.
b. Inject a CW 1030 MHz ± 10 kHz signal to the unit under test at an
RF level that can be seen at TP2 but not saturating the IF log amp.
The suggested level is - 40 dBm.

Rev. 1, May/2003 15563M01.JA Page 5-24

B KT 73

c. Connect the spectrum analyzer at TP2. (limited IF).

NOTE:
The spectrum analyzer is optional but recommend-
ed. Some steps in this procedure require a spectrum
analyzer. If not available, use a power meter and ad-
just for optimum output.

d. Set R156 for the voltage specified in TABLE 1 at the non-ground

side of C33.
NOTE
The NEC mixer transistor is graded into four IDSS
categories U71, U72, U73, and U74. This category is
marked on the top the transistor package.

IDSS CATEGORY GATE 1 BIAS SET VIA R156

U71 -0.15VDC
U72 -0.30VDC
U73 -0.60VDC
U74 -0.80VDC

TABLE 5-1 Q8 MIXER

e. Set R157 for 0.0 VDC at the non-ground side of C32.

f. Adjust C4, C18, C19, and R157 for maximum signal strength to
noise at TP2. Adjust C4 through its complete range while monitoring
the lowest and highest frequency at TP2. Use C4 to adjust the fre-
quency to be halfway between the highest and lowest frequency ob-
served. This frequency should be 60 MHz ± 29.70 kHz.
g. Reduce the CW 1030 MHz signal level if necessary for good obser-
vation and re-adjust R157, C18, and C19 for minimum DC voltage
at TP1 using the oscilloscope. Without touching R157 again, re-ad-
just R156 for minimum DC voltage.

2. I.F. Alignment
a. Inject a -60 dBm 1030 MHz ATCRBS interrogation into the receiver
input using IFR S-1403 DL/ATC-1400A. (reference figure 5-3)
b. Connect an oscilloscope to TP6 to display the video magnitude of
the interrogations (log video output).
c. Adjust T2, T3, T4, T5, and T6 for a peak video output amplitude at
TP6.
d. Video Gain Adjust: Connect the oscilloscope to TP6. With a stan-
dard ATCRBS interrogation of -70 dBm input power, observe peak
video voltage and note it for reference in the steps to follow. Change
the input power to -30 dBm and determine the difference in peak
voltage. Adjust R217 to obtain 2.40 +/- 0.07 VDC difference in peak
voltages as level is changed repetitively from - 70 to -30 dBm.

Rev. 1, May/2003 15563M01.JA Page 5-25

B KT 73

e. Install the receiver cover. Set ATCRBS level to -50 dBm and estab-
lish a reference line on the oscilloscope, using the horizontal cursor
if available, at the pulse top seen at TP6. Set the test set delta fre-
quency to 3.200 MHz. Switch between +delta and - delta repetitively
while tuning T2 through T6 to obtain a response that is as high as
possible for both +delta and - delta, while also maintaining a good
pulse shape. While tuning each slug, if two peaks are possible, use
the bottom position peak. With the delta off, the pulse top should not
be lower than 120 mV from the original reference line. Now reset the
reference line to the new pulse top position. With +delta and -delta,
the pulse tops must be within 180 mV (3 dB) of the new reference
line. Some pulse distortion is permissible at +delta and -delta, but
not permissible with the delta off.

FIGURE 5-3 RECEIVER TP6 VIDEO WITH 1030 MHz +/- 3.2 MHz

f. Verify that TSS at TP6 is less than or equal to -84 dBm. TSS, tan-
gential signal sensitivity, is the pulse signal strength needed to bring
the detected negative signal plus noise peaks tangent to the posi-
tive noise peaks as illustrated in Figure 5-4.

FIGURE 5-4 TSS EXAMPLE

g. Receiver saturation should not occur below -19 dBm input RF signal
level.

Rev. 1, May/2003 15563M01.JA Page 5-26

B KT 73

3. DPSK Detector Alignment

The purpose of this procedure is to align the receiver to allow it to be close
to providing the required performance in Mode S operation. This is accom-
plished by observing the shape and noise generated (in the phase detector
"eye") while following this procedure.
a. Set the ATC 1400A for a MODE-S interrogation (UF11 with
017777777 in the data field and 7’s in the address field), and at a
signal frequency of 1030 MHz. The MODE-S level is fixed at about
-50 dBm.
b. Use an oscilloscope(s) to monitor the log video output (TP6) and the
phase detector output (TP3). Using TP6, find a single data chip,
~250 nanosec wide, at approximately 16 to 18 nanosec from P1.
c. Display the phase detector "eye" pattern by superimposing the sig-
nals at TP3 and TP4 on the oscilloscope. Set both channels to equal
reference levels (display grid position) and vertical sensitivities. (V/
display grid square) There is a spot where no signal will be present
between the upper and lower traces of the "eye". See Figure 5-5
Sample DPSK Eye Diagram. The upper and lower traces will cross
each other and the reference position twice approximately 250
nanosec apart during a phase transition in the MODE-S data field.
Repetitively adjust C151, L24, and L25 for maximum signal level at
TP3 and TP4.

FIGURE 5-5 SAMPLE DPSK EYE DIAGRAM

Rev. 1, May/2003 15563M01.JA Page 5-27

G. Main Board Alignment (continued from previous)

1. P4 Adjust
a. Adjust the RF level of the ATCRBS/Mode S test set to -70 dBm and
set for an ACL interrogation.
b. Set the P4 level on the test set to P4 = P3 - l dB and adjust R576 for
greater than 90% Mode S reply efficiency.
c. Set the P4 level on the test set to P4 = P3 - 6dB and adjust R576 for
greater than 90% ATCRBS reply efficiency.
d. Set the P4 level, on the test set, to P4 = P3 - l dB and verify that the
Mode S reply efficiency is greater than 90%. If the Mode S reply rate
is less than 90%, then adjust R576.
e. Adjust the RF level of the test set to -2ldBm and check for a Mode
S reply rate of greater than 90%. Adjust R576 to achieve a reply rate
greater than 90%, if needed.
f. Set the P4 level, on the test set, to P4 = P3 -6dB and check for an
ATCRBS reply rate of greater than 90%. If the reply rate is less than
90%, then adjust R576 accordingly.
g. Repeat steps in 5.2.7.C.1 until all the conditions are satisfied.

Rev. 1, May/2003 15563M01.JA Page 5-31

B KT 73

2. (Setting MTL) Set the RF test set for a RF level of -75 dBm and a standard
ATCRBS interrogation. Adjust R478 for approximately 50% reply rate.
Check for greater than 90% reply rate at -74 dBm.
3. Centering SPR Position tuning by the front panel
a. The KT 73 will enter the programming mode after the following front
panel control sequence:
1. Put the unit in Standby Mode.
2. Select 0000 ident code.
3. Depress the IDT button (and hold) and then VFR button for
a minimum of 3 seconds.
b. Press the IDT until "CODE>000" menu appears.
c. Rotate three knobs, marked "FLT ID", BLANK and "BRT" until the
word "SPR" appears.
d. Press IDT to enter this code. Change SPR setting from 0 by rotating
BRT knob.
e. Interrogate the unit with UF11, RF level -21 dBm, and SPR position
offset at 0 nanosec.
f. Vary the SPR position offset both plus time and minus time by rotat-
ing BRT knob on KT73 and observe the times where the reply rate
falls below 100%.
g. Increment or decrement the delay value (-3 to +4) to obtain the best
balance of plus and minus time.
h. Test the reply rate with SPR position at 0 nanosec, +50 nanosec
and -50 nanosec on S-1403DL. Verify 100% replies. Set the RF lev-
el to MTL +l and verify 100% replies at SPR positions -50nanosec,
0 nanosec, and +50 nanosec. Set the SPR position on the IFR to
+200 nanosec and -200 nanosec. See that the reply rate is zero at
both positions.
i. Store the delay by depressing the IDT button

H. Unit Level Alignment for Interfering Pulses and SLS.

The purpose of this procedure is to provide the information required for aligning the
unit so that it will meet the required SLS and interfering pulse performance. This is
accomplished by observing the noise generated in the phase detector "eye" (by the
interfering pulse) and the percent reply indicator on the ATC 1400A while following
this procedure.
1. Refer to Procedure 5.2.8.I of this section for information concerning the
proper set up of the ATC A and ATC1403 DL to provide interfering pulses
from a single generator. With the octal number base selected, set the IFR
S-1403 DL for a MODE S interrogation (UFll with 017777777 in the data
field and 7’s in the add field), and signal frequency of 1030 MHz. The
MODE-S level should be fixed at -50 dBm. Disable the squitter by using a
shorting jumper on the two pin CJ1 of the KT73 Main Board. If Antenna B
output is not -50 dBm, the power should be set on the C020 menu, Brf win-
dow of the top S1403 DL display.
2. Adjust the ATCRBS interfering pulse level to -60 dBm with the ATC1400 A
level control.

Rev. 1, May/2003 15563M01.JA Page 5-32

B KT 73

3. Use an oscilloscope(s) to monitor the log video output (TP6) and the phase
detector output TP3 or TP4. With the interference pulse added by setting
the ATC 1400 A to DBL/INTERR/INTR PULSE to 5.0 microsec, watch the
interference pulse appear on P6 of the TP6 video signal.
4. Move the interference pulse to a spot with a double chip within 250 nanosec
of each other near the end of P6. A good spot to observe is somewhere be-
tween 16 and 18 microsec from P1.
5. Use the two channels to display TP3 and TP4 using delay sweep function
to place the scope CRT on the desired set of chips, while keeping the ex-
ternal trigger on the TAC SYNC output mentioned in 12.4.2.
6. Display the phase detector "eye" pattern by superimposing the signals at
TP3 and TP4 on the oscilloscope. Set both channels to equal reference lev-
els and vertical sensitivities. In the absence of interfering pulses, no signal
will be present between the upper and lower traces of the "eye". See Figure
5 Sample DPSK Eye Diagram. The upper and lower traces will cross each
other and the reference position during a phase transition in the MODE-S
data field. As the interfering pulse magnitude is increased relative to the
MODE-S interrogation, noise will become present in the "eye" at the posi-
tion in the data field coinciding with the location of the interfering pulse. Ad-
just C151, L24, and L25 for maximum signal level at TP3 and TP4.
7. Near the end of the MODE-S data field will be an area where two phase
changes occur 250ns apart with no phase changes occurring at least 500ns
on either side. Adjust the interfering pulse position such that it will be cen-
tered on these two phase changes.
8. Set the level of the interfering pulse to -3 dB.
9. Place the interference pulse over the first chip following the SPR (1.8 us fol-
lowing the leading edge of P6). Using the thumbwheel switch, slowly move
the interfering pulse to the end of P6 and observe the reply rate stays over
60%.
NOTE:
Steps 10, 11, and 12 are to be performed if the unit
does not achieve 60% reply rate after performing
steps 1 through 9.

Rev. 1, May/2003 15563M01.JA Page 5-38

B KT 73

WARNING:
OPERATIONS INVOLVING THE USE OF A
CLEANING SOLVENT SHOULD BE PER-
FORMED UNDER A VENTILATED HOOD.
AVOID BREATHING SOLVENT VAPOR AND
FUMES; AVOID CONTINUOUS CONTACT
WITH THE SOLVENT. WEAR A SUITABLE
MASK, GOGGLES, GLOVES, AND AN APRON
WHEN NECESSARY. CHANGE CLOTHING
UPON WHICH SOLVENTS HAVE BEEN
SPILLED.

WARNING:
OBSERVE ALL FIRE PRECAUTIONS FOR
FLAMMABLE MATERIALS. USE FLAMMABLE
MATERIALS IN A HOOD PROVIDED WITH
SPARK-PROOF ELECTRICAL EQUIPMENT
AND AN EXHAUST FAN WITH SPARKPROOF
BLADES.

B. Recommended Cleaning Agents

Table 5-2 lists the recommended cleaning agents to be used during overhaul of the
unit.
NOTE:
EQUIVALENT SUBSTITUTES MAY BE USED FOR
LISTED CLEANING AGENTS.

TYPE USED TO CLEAN

Denatured Alcohol Various, exterior and interior
DuPont Vertrel SMT Various, interior
PolaClear Cleaner (Polaroid Corp.) or CRT display filter, LCD displays, and
Texwipe TX129 (Texwipe Co.) general purpose lens/glass cleaner.
KimWipes lint-free tissue Various
(Kimberly Clark Corp.)
Cloth, lint-free cotton Various
Brush, flat with fiber bristles Various
Brush, round with fiber bristles Various
Dishwashing liquid (mild) Nylon, Rubber Grommets

TABLE 5-2 RECOMMENDED CLEANING AGENTS

Rev. 1, May/2003 15563M01.JA Page 5-39

B KT 73

C. Recommended Cleaning Procedures

CAUTION:
DO NOT ALLOW SOLVENT TO RUN INTO
SLEEVES OR CONDUIT THAT COVERS
WIRES CONNECTED TO INSERT TERMI-
NALS.
1. Exterior
(a) Wipe dust cover and front panel with a lint-free cloth dampened with
denatured alcohol.
(b) For cleaning connectors, use the following procedure.
(1) Wipe dust and dirt from bodies, shells, and cable clamps us-
ing a lint-free cloth moistened with denatured alcohol.
(2) Wipe parts dry with a clean, dry lint-free cloth.
(3) Remove dirt and lubricant from connector inserts, insulation,
and terminals using a small soft bristled brush moistened
with denatured alcohol.
(4) Dry the inserts with an air jet.
(c) Remove cover(s).
(d) If necessary, open any blocked ventilation holes by first saturating
the debris clogging the apertures with denatured alcohol and then
blowing the loosened material out with an air stream.
2. Interior
The following solvents are no longer recommended for benchtop or rework
cleaning of printed circuit boards, modules, or sub-assemblies.

FREON TF, IMC TRICHLOROETHANE

CARBON TETRACHLORIDE DETERGENT (ALL AND EQUIVALENTS)
CHLOROFORM METHYLENE CHLORIDE
TRICHLOROETHYLENE GENESOLV 2004/2010
PROPYL ALCOHOL METHYL ALCOHOL
ETHYL ALCOHOL BUTYL ALCOHOL
XYLENE PRELETE (CFC-113)

TABLE 5-3 UNSAFE CLEANING AGENTS

Rev. 1, May/2003 15563M01.JA Page 5-40

B KT 73

CAUTION:
DO NOT USE SOLVENT TO CLEAN PARTS
COMPOSED OF OR CONTAINING NYLON OR
RUBBER GROMMETS. CLEAN THESE
ITEMS WITH MILD LIQUID DISHWASHING
DETERGENT AND WATER. USE DETER-
GENT FOR THIS PURPOSE ONLY.

CAUTION:
DUPONT VERTREL SMT DOES HAVE GEN-
ERAL MATERIAL COMPATIBILITY PROB-
LEMS WITH POLYCARBONATE, POLYSTY-
RENE, AND RUBBER. IT IS RECOMMENDED
THAT THESE MATERIALS BE CLEANED
WITH DENATURED ALCOHOL.

CAUTION:
DO NOT ALLOW EXCESS CLEANING SOL-
VENT TO ACCUMULATE IN ANY OF THE AD-
JUSTMENT SCREW CREVICES AND THERE-
BY SOFTEN OR DISSOLVE THE ADJUST-
MENT SCREW EPOXY SEALANT.

CAUTION:
AVOID AIR-BLASTING SMALL TUNING COILS
AND OTHER DELICATE PARTS BY HOLDING
THE AIR NOZZLE TOO CLOSE. USE BRUSH-
ES CAREFULLY ON DELICATE PARTS.

CAUTION:
IMPROPER CLEANING CAN RESULT IN SUR-
FACE LEAKAGE AND CONDUCTIVE PARTIC-
ULATES, SUCH AS SOLDER BALLS OR ME-
TALLIC CHIPS, WHICH CAN CAUSE ELEC-
TRICAL SHORTS. SEVERE IONIC CONTAM-
INATION FROM HANDLING AND FROM
ENVIRONMENTAL CONDITIONS CAN RE-
SULT IN HIGH RESISTANCE OR OPEN CIR-
CUITS.

CAUTION:
ULTRASONIC CLEANING CAN DAMAGE
CERTAIN PARTS AND SHOULD GENERALLY
BE AVOIDED.

Rev. 1, May/2003 15563M01.JA Page 5-41

B KT 73

NOTE:
Solvents may be physically applied in several ways
including agitation, spraying, brushing, and vapor
degreasing. The cleaning solvents and methods
used shall have no deleterious effect on the parts,
connections, and materials being used. If sensitive
components are being used, spray is recommended.
Uniformity of solvent spray flow should be maxi-
mized and wait-time between soldering and cleaning
should be minimized.

NOTE:
Clean each module subassembly. Then remove any
foreign matter from the casting.

C. Diodes
Diodes used are silicon and germanium. Use long-nose pliers as a heat sink, under
normal soldering conditions. Note the diode polarity before removal.
D. Integrated Circuits
Refer to the applicable reference for removal and replacement instructions.
E. Wiring/Coaxial Cable
When repairing a wire that has broken from its terminal, remove all old solder, and
pieces of wire from the terminal, re-strip the wire to the necessary length, and re-
solder the wire to the terminal. Replace a damaged wire or coaxial cable with one of
the same type, size and length.

Rev. 1, May/2003 15563M01.JA Page 5-47

B KT 73

5.3.4 DISASSEMBLY/ASSEMBLY PROCEDURES

5.3.4.1 General
This section provides information for disassembly of the KT 73. Disassembly procedures are to
be accomplished only when repairs or modifications are required and only to the extent that is re-
quired by the repair or as directed in the modification service bulletin. This section contains the
recommended procedure for removal of all PC boards and subassemblies. Complete disassem-
bly should not normally be undertaken. Provisions have been made in the design of the unit to
make complete disassembly unnecessary except to replace a damaged mechanical part that can-
not be reached otherwise. Refer to the Illustrated Parts List (IPL) for aid in disassembly.

WARNING:
REMOVE POWER FROM THE KT 73 BEFORE
DISASSEMBLY OF ANY COMPONENT, PC
BOARD, OR SUBASSEMBLY. BESIDES BE-
ING DANGEROUS TO LIFE, VOLTAGE TRAN-
SIENTS CAN CAUSE CONSIDERABLE DAM-
AGE TO THE EQUIPMENT.

CAUTION:
THIS EQUIPMENT CONTAINS ELECTRO-
STATIC DISCHARGE SENSITIVE (ESDS) DE-
VICES. ESDS DEVICES INCLUDE, BUT ARE
NOT LIMITED TO, C-MOS, J-MOS, PMOS,
NMOS, SOCMOS,HMOS, MOS/FET, MICRO-
WAVE MIXER DIODES, SOME BIPLOAR DE-
VICES, AND SOME METAL FILM RESIS-
TORS.

MOST DAMAGE TO ESDS DEVICES RE-

SULTS IN DEGRADED PERFORMANCE OR
PREMATURE FAILURE,NOT IN CATA-
STROPHIC FAILURE AT THE TIME EXPERI-
ENCED.

CAUTION:
EXERCISE EXTREME CARE WHEN DISCON-
NECTING AND RECONNECTING MULTI-PIN
CONNECTORS TO ENSURE THAT CONNEC-
TORS ARE NOT DAMAGED BY MISALIGN-
MENT OF PINS.

Rev. 1, May/2003 15563M01.JA Page 5-48

B KT 73

5.3.4.2 Recommended Disassembly Procedures

NOTE:
View unit from front for determining left and right
sides. Tag, or by some means, identify all discon-
nected wires or coaxial cables.

NOTE:
On the KT 73 final assembly drawing (P/N 300-
09360-0000, the 073-00892-0001 right rail and heat
sink assembly is illustrated as part of the 200-09862-
0000 power supply assembly.

The 047-09543-00XX left side rail is illustrated as

part of the 200-05049-0003 chassis assembly.

The 047-09541-0002 rear rail is illustrated as part of

the 200-05049-0003 chassis assembly.

(1) Top Dust Cover Removal and Disassembly (Refer to drawing number 300-09360-
0000 and 300-05049-0000)

(a) Remove three fasteners (089-05901-0003) securing dust cover (047-09609-

0001) to right rail and heat sink (073-00892-0001).

(b) Rotate and remove three fasteners (089-05901-0003) securing dust cover
(047-09609-0001) to left side rail (047-09543-00XX).

(c) Remove one fastener (089-05901-0003) securing dust cover (047-09609-

0001) to rear rail (047-09541-0002).

(d) Remove one fastener (089-05901-0003) securing dust cover (047-09609-

0001) and power supply chassis (047-09588-0003) to swage spacer (076-
02234-0001) on main board (205-00914-XXXX).

(e) Lift dust cover (047-09609-0001) upward from rear of unit and slide toward
back of unit.

(f) Set dust cover aside.

(2) Bottom Cover Removal and Disassembly (Refer to drawing number 300-09360-
0000 and 300-05049-0000)

(a) Rotate unit and remove three fasteners (089-06006-0003) securing dust cov-
er (047-09587-0007) to right rail and heat sink (073-00892-0001).

Rev. 1, May/2003 15563M01.JA Page 5-49

B KT 73

(b) Rotate and remove one fastener (089-06006-0003) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX) at the mounting hole nearest
the front of the unit.

(c) Remove two fasteners (089-06006-0003) securing dust cover (047-09587-

0007) to the transmitter housing (073-00878-0007).

(d) Rotate and remove four fasteners (089-06006-0004) securing dust cover
(047-09587-0007) to left side rail (047-09543-00XX).

(e) Remove one fastener (089-05901-0003) securing dust cover (047-09587-

0001) to rear rail (047-09541-0002).

(f) Remove one fastener (089-05901-0004) securing dust cover (047-09587-

0001) to rear rail (047-09541-0002).

(g) Lift dust cover (047-09587-0001) upward from rear of unit and slide toward the
back of unit.

(h) Set dust cover aside.

(3) Front Panel Assembly Removal and Disassembly (Refer to drawing numbers 300-
09349-0000, 300-09360-0000, 300-05049-0000, and 300-09325-0020)

(a) Refer to paragraphs (1) and (2) for top and bottom cover removal as required.

(b) Remove two fasteners (089-06368-0003 securing the front panel assembly
(200-09349-0000) to right rail and heat sink (073-00892-0001).

(c) Rotate and remove two fasteners (089-06368-0003 securing the front panel
assembly (200-09349-0000) to left side rail (047-09543-00XX).

(d) Gently rock front panel assembly (200-09349-0000) from top to bottom while
pulling straight outward. This action will cause separation of front panel as-
sembly connector pins (display board 200-09325-0020), from main board
(205-00914-XXXX) connector (J3).

(e) Loosen eight set screws (089-06200-0004), two each per knob, and remove
the four knobs (073-01015-0005).

(f) Loosen three set screws (089-06200-0004) and remove one knob (073-
00998-0006).

(g) Rotate front panel assembly (200-09349-0000) and remove two fasteners
(089-05903-0005) and one fastener (089-05927-0010) securing display
board assembly (200-09325-0020) to bezel (200-09355-0000).

(h) Separate bezel from display board.

(i) If further disassembly is required, remove four fasteners (089-05899-0003).

(j) Remove foam carrier tape (016-01124-0001) from each side of the gas dis-
charge display (037-05107-0001).

Rev. 1, May/2003 15563M01.JA Page 5-50

B KT 73

(k) Carefully pull gas discharge display (037-05107-0001) outward. This action
will cause separation of the display connector pins from 200-09325-00XX
connector J1.

(l) Carefully remove RTV (016-01082-0000) securing eight lamps DS1 - DS8
(037-00012-0014) to support bracket (088-02511-0004).

(m) Carefully remove RTV (016-01082-0000) securing LED DS19 (007-07008-

0001) to support bracket (088-02511-0004).

(n) Remove nut/washer hardware from switches SW1 - SW 5 (031-00759-0000).

(o) Separate the support bracket from the display board.

(4) Receiver Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, and 300-08273-0020)

(a) Refer to paragraph (2) for bottom cover removal.

(b) Remove three (089-05901-0004) fasteners securing receiver board assembly

(200-08273-0020) to right rail and heat sink (073-00892-0001).

(c) Assembly including the receiver board, transmitter board, and modulator
board will now swing on the leaf hinges (047-09608-00XX).

(d) Disconnect the main board (205-00914-XXXX) ribbon cable (155-02654-

0000) connector (J5) from plug (P1), on modulator board (200-08274-0020).

(e) Disconnect the main board (205-00914-XXXX) ribbon cable (155-02654-

0001) connector (J4) from plug (P4) on receiver board assembly (200-08273-
0020).

(f) Remove two (089-06006-0003) fasteners securing the assembly to left rail
(047-09543-00XX).

(g) Remove two fastener (089-06006-0004) securing the assembly to rear rail
(047-09541-0002). Leaf hinge (047-09608-0001) will be removed as well.

(h) Remove the assembly including the receiver board, transmitter board, and
modulator board which is now separate from the rest of the unit.

(i) Remove three fasteners (089-05901-0004) securing receiver board assembly

(200-08273-0000) to transmitter housing (073-00878-0007). Leaf hinge (047-
09608-0000) will be removed as well.

(l) Remove two screws (089-06368-0003) from preselector shield cover (047-
12775-0004).

(k) Remove one screw (089-05901-0003) from preselector shield cover (047-
12775-0004).

(l) Remove preselector shield cover (047-12775-0004).

Rev. 1, May/2003 15563M01.JA Page 5-51

B KT 73

(m) Unsolder transmitter board (200-08275-0040) coaxial cable (024-00074-

0000) from receiver board assembly (200-08273-0020).

(n) Receiver board assembly (200-08273-0020) can now be removed.

(o) Remove fences, shields, and covers as necessary to access components.

Refer to sheet 3 of 300-08273-0020 for additional information.

(p) If necessary, remove two screws (089-05901-0004) and remove leaf hinge
(075-05097-0001). Leaf hinge (047-09608-0002) will be removed as well.

(5) Modulator Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, 300-08273-0020, and 300-08274-0020)

(a) Refer to paragraph (4), steps (a) through (d). If removal of entire assembly
including receiver, modulator and transmitter assemblies is desired, perform
steps paragraph (4), steps (a) through (i).

(b) Unsolder six (from transmitter board 200-08275-0040) connections (E1

through E6) on modulator board (200-08274-0020).

(c) Remove six fasteners (089-05901-0003) securing modulator board (200-

08274-0020) to transmitter housing (073-00878-0007).

(d) Remove four fasteners (089-05903-0004), bushings (091-00156-0000) and

insulators (091-00286-0002) securing four modulator board (200-08274-
0020) transistors (Q2, Q3, Q6, Q10) to transmitter housing (073-00878-0007).

(e) Modulator board assembly (200-08274-0020) may now be removed.

(6) Transmitter Board Assembly Removal and Disassembly (Refer to drawing numbers
300-09360-0000, 300-05049-0000, 300-08273-0020, 300-08274-0020 and 300-
08275-0040)

(a) Refer to paragraph (5).

(b) Remove eight fasteners (089-06006-0003) securing shield (047-12625-0003)

to transmitter housing (073-00878-0007).

(c) Unsolder coaxial cable (024-00074-0000) from connection points; center wire
from E8 and shield from E9 and withdraw cable through holes in fence/bracket
(047-12680-0002) and transmitter housing (073-00878-0007).

(d) Transmitter board assembly 200-08275-0040) including transmitter housing

(073-00878-0007) may now be removed.

(e) If necessary, remove four fasteners (089-05523-0003), two each from transis-
tor Q1 and two each from transistor Q2, ensuring that lock washers (089-
08109-0034) and flat washers (089-08158-0004) remain with each fastener.

Rev. 1, May/2003 15563M01.JA Page 5-52

B KT 73

(f) If necessary, remove two fasteners (089-06006-0002) and two fasteners

(089-06006-0003) securing shield (047-12698-0003) to transmitter housing
(073-00878-0007).

(7) Main Board Assembly Removal and Disassembly (Refer to drawing numbers 300-
09360-0000, 300-05049-0000, 300-08273-0020, and 300-09321-0000)

(a) Refer to paragraph (3), steps (a) through (d).

(b) Refer to paragraph (4), steps (b) through (h) as required.

(c) Remove two fasteners (089-05901-0004) securing main board (205-00914-

XXXX) to right rail and heat sink (073-00892-0001).

(d) Rotate unit and remove three fasteners (089-05901-0003) securing main
board (205-00914-XXXX) to left side rail (047-09543-00XX).

(e) Remove two fasteners (089-05901-0003) securing main board (205-00914-

XXXX) to rear rail (047-09541-0002).

(f) Remove one fastener (089-06006-0004) securing main board (205-00914-

XXXX) to right rail and heat sink (073-00892-0001).

(g) Carefully separate the Main board connector J2 from the power supply board
connector P1 and remove the Main board (205-00914-XXXX).

(h) Remove top (047-09574-0001) and bottom (047-09576-0001) fence covers

as required by removing two fasteners (089-06004-0002) per cover.

(8) Power Supply Board Assembly Removal and Disassembly (Refer to drawing num-
bers 300-09360-0000, 300-05049-0000, 300-08273-0020 and 300-09862-0000)

(a) Refer to paragraph (1) for top cover removal.

(b) Refer to paragraph (4), (a) through (c).

(d) Remove two standoffs (076-02232-0001 and lock washers (089-08109-0034)

from power supply board (200-09862-0000).

(e) Remove one fastener (089-05901-0003) from power supply chassis (047-
09588-0003) and remove chassis.

(f) Remove two fasteners (089-05901-0004) attaching power supply board (200-
09862-0000) to right rail and heat sink (073-00892-0001).

(g) Remove four fasteners (089-05903-0004) and bushings (091-00156-0000)

from Q1, Q6, Q8, and U6. Ensure that transistor bushings and insulators
(091-00286-0002) are saved for replacement.

Rev. 1, May/2003 15563M01.JA Page 5-53

B KT 73

(h) Remove one fastener (089-05903-0004) from U7.

(i) If the main board is not already removed, lift power supply board (200-09862-
0000) upward. This action will separate connector pins (P1) from the main
board connector (J2).

(j) Power supply board (200-09862-0000) is now removed.

(9) Optional External EEPROM Board (External Configuration Module) Assembly Re-
moval and Disassembly (Refer to drawing numbers 300-09360-0000, 300-10069-
0000, and 300-09889-0010)

(a) Grasp unit pull outward from mounting rack (047-12768-0005). Radio remov-
al tool (071-06045-0000) may be used as an aid in this task.

(b) Remove two fasteners (089-05903-0007) securing EEPROM board (200-

09889-0010) to mounting rack (047-12768-0005).

(c) Remove EEPROM board (200-09889-0010).

Rev. 1, May/2003 15563M01.JA Page 5-54

B KT 73

5.3.4.3 Recommended Assembly Procedures

This section provides procedures for assembly of the KT 73. Assembly procedure are to be fol-
lowed after the unit has been disassembled for repair, cleaning, inspection, or modification by ser-
vice bulletin.
The following table lists materials used in assembly of the unit. Equivalent substitutes may be
used for listed sealants, staking compounds, and thermal compounds.

REPRESENTATIVE TYPE QUANTITY USED

Loctite 425 Thin coat to threads of screws and retaining
nuts
Conformal Coating Humiseal #1B-31 Thin coats on all components, not on connec-
HYSOL PC 20-35M-01 tors
Adhesive-Sealant RTV 3145 Thin coat for adhesion
Thermal Compound Thin coat on power transistor insulator (both
sides)
Nylon Cable Tie As required to secure wiring
Solder, 60% Tin 40% Lead As required for connections
TABLE 5-4
SEALANTS AND STAKING COMPOUNDS

WARNING:
REMOVE ALL POWER FROM UNIT BEFORE
ASSEMBLY OF ANY MODULE. VOLTAGE
TRANSIENTS ARE DANGEROUS TO LIFE.
VOLTAGE TRANSIENTS CAN DAMAGE THE
EQUIPMENT.

CAUTION:
EXERCISE EXTREME CARE WHEN DISCON-
NECTING AND RECONNECTING MULTI-PIN
CONNECTORS TO ENSURE THAT CONNEC-
TORS ARE NOT DAMAGED BY MISALIGN-
MENT OF PINS.

Rev. 1, May/2003 15563M01.JA Page 5-55

B KT 73

MOST DAMAGE TO ESDS DEVICES RE-

SULTS IN DEGRADED PERFORMANCE OR
PREMATURE FAILURE,NOT IN CATA-
STROPHIC FAILURE AT THE TIME EXPERI-
ENCED.

NOTE:
View unit from front for determining left and right
sides.

NOTE:
On the KT 73 final assembly drawing (P/N 300-
09360-0000, the 073-00892-0001 right rail and heat
sink assembly is illustrated as part of the 200-09862-
0000 power supply assembly.

The 047-09543-00XX left side rail is illustrated as

part of the 200-05049-0003 chassis assembly.

The 047-09541-0002 rear rail is illustrated as part of

the 200-05049-0003 chassis assembly.

(1) Top Dust Cover Assembly (Refer to drawing number 300-09360-0000 and 300-
05049-0000)

(a) Install dust cover (047-09609-0001) on unit.

(b) Install one fastener (089-05901-0003) securing dust cover (047-09609-0001)

and power supply chassis (047-09588-0003) to swage spacer (076-02234-
0001) on main board (205-00914-XXXX).

(c) Install one fastener (089-05901-0003) securing dust cover (047-09609-0001)

to rear rail (047-09541-0002).

(d) Rotate and install three fasteners (089-05901-0003) securing dust cover
(047-09609-0001) to left side rail (047-09543-00XX).

Rev. 1, May/2003 15563M01.JA Page 5-56

B KT 73

(e) Install three fasteners (089-05901-0003) securing dust cover (047-09609-

0001) to right rail and heat sink (073-00892-0001).

(2) Bottom Cover Assembly (Refer to drawing number 300-09360-0000 and 300-
05049-0000)

(a) Install dust cover (047-09587-0001) on unit.

(b) Install one fastener (089-05901-0004) securing dust cover (047-09587-0001)

to rear rail (047-09541-0002).

(c) Install one fastener (089-05901-0003) securing dust cover (047-09587-0001)

to rear rail (047-09541-0002).

(d) Rotate and install four fasteners (089-06006-0004) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX).

(e) Install two fasteners (089-06006-0003) securing dust cover (047-09587-

0007) to the transmitter housing (073-00878-0007).

(f) Rotate and install one fastener (089-06006-0003) securing dust cover (047-
09587-0007) to left side rail (047-09543-00XX) at the mounting hole nearest
the front of the unit.

(g) Rotate unit and install three fasteners (089-06006-0003) securing dust cover
(047-09587-0007) to right rail and heat sink (073-00892-0001).

(3) Front Panel Assembly (Refer to drawing numbers 300-09349-0000, 300-09360-

0000, 300-05049-0000, and 300-09325-0020)

(a) Connect the support bracket (088-02511-0004) to the display board (200-
09325-0020).

(b) Install nut/washer hardware on switches SW1 - SW 5 (031-00759-0000).

(c) Install four fasteners (089-05899-0003) attaching the support bracket (088-
02511-0004) to the display board (200-09325-0020).

(d) Install foam carrier tape (016-01124-0001) on each side of the gas discharge
display (037-05107-0001).

(e) Connect gas discharge display (037-05107-0001) connector pins to 200-

09325-00XX connector J1.

(f) Secure LED DS19 (007-07008-0001) to support bracket (088-02511-0004)

with RTV (016-01082-0000) per 300-09325-0020 note 8.

(g) Secure eight lamps DS1 - DS8 (037-00012-0014) to support bracket (088-
02511-0004) with RTV (016-01082-0000) per 300-09325-0020 note 9.

Rev. 1, May/2003 15563M01.JA Page 5-57

B KT 73

(h) Install two fasteners (089-05903-0005) and one fastener (089-05927-0010)

securing display board assembly (200-09325-0020) to bezel (200-09355-
0000).

(i Install one knob (073-00998-0006) and tighten three set screws (089-06200-
0004).

(j) Install four knobs (073-01015-0005) and tighten eight set screws (089-06200-
0004), two each per knob.

(k) Install front panel assembly connector pins (on display board 200-09325-
0020) to main board (205-00914-XXXX) connector (J3).

(l) Install two fasteners (089-06368-0003 securing the front panel assembly
(200-09349-0000) to left side rail (047-09543-00XX).

(m) Install two fasteners (089-06368-0003 securing the front panel assembly
(200-09349-0000) to right rail and heat sink (073-00892-0001).

(n) Refer to paragraphs (1) and (2) for top and bottom cover installation as appli-
cable.

(4) Receiver Board Assembly (Refer to drawing numbers 300-09360-0000, 300-05049-

0000, and 300-08273-0020)

NOTE:
If any of the aluminum tape applied to the receiver
board is removed for any reason, replace with new
tape per the aluminum tape application instructions
on assembly drawing 300-08273-0020. Do not at-
tempt to reuse the original tape.

(a) If removed, install leaf hinges (075-05097-0001) and (047-09608-0002) and

install two screws (089-05901-0004).

(b) Install fences, shields, and covers as necessary. Refer to sheet 3 of 300-
08273-0020 for additional assembly information.

(c) Solder transmitter board (200-08275-0040) coaxial cable (024-00074-0000)

to receiver board assembly (200-08273-0020) per 300-09360-0000 detail A.

(d) Install preselector shield cover (047-12775-0004).

(e) Install one screw (089-05901-0003) on preselector shield cover (047-12775-

0004).

(f) Install two screws (089-06368-0003) on preselector shield cover (047-12775-

0004).

(g) Install leaf hinge (047-09608-0000) and align transmitter housing (073-00878-
0007) in receiver board assembly (200-08273-0000).

(h) Install three fasteners (089-05901-0004) securing transmitter housing (073-

00878-0007) to receiver board assembly (200-08273-0000).

Rev. 1, May/2003 15563M01.JA Page 5-58

B KT 73

(i) Install leaf hinge (047-09608-0001) in the assembly that includes the receiver
board, transmitter board, and modulator board and align to the rest of the unit
at the rear and left rails.

(j) Install two fasteners (089-06006-0004) securing the assembly and rear leaf
hinge to the rear rail (047-09541-0002).

(k) Install one (089-06006-0003) fastener securing the assembly, including the
center leaf hinge (047-09608-0000) to the left rail (047-09543-00XX) per the
note below.

(l) Install one (089-06006-0003) fastener securing the assembly, including the
front leaf hinge (089-06006-0000) to the left rail (047-09543-00XX) per the
note below.

NOTE:
The second attachment to the front and center leaf
hinges occurs during the bottom cover assembly.
Ensure that the fasteners installed in the previous
steps are installed properly to accommodate the bot-
tom cover assembly (see 300-05049-0000 for clari-
ty).

(m) Assembly including the receiver board, transmitter board, and modulator
board will now swing on the leaf hinges (047-09608-00XX).

(n) Connect main board (205-00914-XXXX) ribbon cable (155-02654-0001) con-

nector (J4) to plug (P4) on receiver board assembly (200-08273-0020).

(o) Connect main board (205-00914-XXXX) ribbon cable (155-02654-0000) con-

nector (J5) to plug (P1) on modulator board (200-08274-0020).

(p) Hinge closed the assembly and install three (089-05901-0004) fasteners se-
curing it to the right rail and heat sink (073-00892-0001).

(q) Refer to paragraph (2) for bottom cover installation.

(5) Modulator Board Assembly (Refer to drawing numbers 300-09360-0000, 300-

05049-0000, 300-08273-0020, and 300-08274-0020)

(a) Install Modulator board (200-08274-0020) on transmitter housing (073-

00878-0007).

(b) Install four fasteners (089-05903-0004), bushings (091-00156-0000) and in-

sulators (091-00286-0002) securing four modulator board (200-08274-0020)
transistors (Q2, Q3, Q6, Q10) to transmitter housing (073-00878-0007).

(c) Install six fasteners (089-05901-0003) securing modulator board (200-08274-

0020) to transmitter housing (073-00878-0007).

(d) Solder six (from transmitter board 200-08275-0040) connections (E1 through
E6) on modulator board (200-08274-0020).

Rev. 1, May/2003 15563M01.JA Page 5-59

B KT 73

(e) Refer to paragraph (4), steps (o) through (q). If entire assembly, including re-
ceiver, modulator and transmitter assemblies, is removed, perform paragraph
(4), steps (g) through (q) as required.

(6) Transmitter Board Assembly (Refer to drawing numbers 300-09360-0000, 300-

05049-0000, 300-08273-0020, 300-08274-0020 and 300-08275-0040)

(a) If removed, install two fasteners (089-06006-0002) and two fasteners (089-
06006-0003) securing shield (047-12698-0003) to transmitter housing (073-
00878-0007).

(b) If removed, install four fasteners (089-05523-0003), two each from transistor
Q1 and two each from transistor Q2, including lock washers (089-08109-
0034) and flat washers (089-08158-0004).

(c) Run coaxial cable (024-00074-0000) through holes in fence/bracket (047-

12680-0002) and transmitter housing (073-00878-0007).

(d) Solder coaxial cable (024-00074-0000) at connection points; center wire to

E8 and shield to E9.

(e) Install eight fasteners (089-06006-0003) securing shield (047-12625-0003) to

transmitter housing (073-00878-0007).

(f) Refer to paragraph (5).

(7) Main Board Assembly (Refer to drawing numbers 300-09360-0000, 300-05049-

0000, 300-08273-0020, and 300-09321-0000)

(a) If removed, install top (047-09574-0001) and bottom (047-09576-0001) fence

covers and install two fasteners (089-06004-0002) per cover.

(b) Install the Main board (205-00914-XXXX) by connecting Main board connec-
tor J2 to power supply board connector P1.

(c) Install one fastener (089-06006-0004) securing main board (205-00914-

XXXX) to right rail and heat sink (073-00892-0001).

(d) Install two fasteners (089-05901-0003) securing main board (205-00914-

XXXX) to rear rail (047-09541-0002).

(e) Rotate unit and install three fasteners (089-05901-0003) securing main board
(205-00914-XXXX) to left side rail (047-09543-00XX).

(f) Install two fasteners (089-05901-0004) securing main board (205-00914-

XXXX) to right rail and heat sink (073-00892-0001).

(g) Refer to paragraph (4), steps (g) through (q) as required.

(h) Refer to paragraph (3), steps (k) through (n).

Rev. 1, May/2003 15563M01.JA Page 5-60

B KT 73

(8) Power Supply Board Assembly (Refer to drawing numbers 300-09360-0000, 300-
05049-0000, 300-08273-0020 and 300-09862-0000)

(a) Install power supply board (200-09862-0000) connecting pins (P1) to the
main board connector (J2), if main board is installed.

(c) Install one fastener (089-05903-0004) on U7.

(d) Install four fasteners (089-05903-0004), bushings (091-00156-0000), and in-

sulators (091-00286-0002) on Q1, Q6, Q8, and U6.

(e) Install two fasteners (089-05901-0004) attaching power supply board (200-
09862-0000) to right rail and heat sink (073-00892-0001).

(f) Place power supply chassis (047-09588-0003) and attach one fastener (089-
05901-0003) to chassis.

(g) Install two standoffs (076-02232-0001 and lock washers (089-08109-0034) to

power supply board (200-09862-0000).

(h) Place power supply cover (047-09589-0001) and install four fasteners (089-
06006-0004).

(i) Hinge closed the assembly including the receiver board, transmitter board,
and modulator board and install three (089-05901-0004) fasteners securing it
to the right rail and heat sink (073-00892-0001).

(j) Refer to paragraph (1) for top cover installation.

(k) Refer to paragraph (2) for bottom cover installation.

(9) Optional External EEPROM Board Assembly (External Configuration Module) (Re-
fer to drawing numbers 300-09360-0000, 300-10069-0000, and 300-09889-0010)

(a) Install EEPROM board (200-09889-0010).

(b) Install two fasteners (089-05903-0007) securing EEPROM board (200-

09889-0010) to mounting rack (047-12768-0005).

(c) Install KT 73 into mounting rack (047-12768-0005).

5.4 TROUBLESHOOTING
This section is intended for use as a guide in isolating circuit malfunctions. The guidance present-
ed here and the figures referenced by no means profess to include all possible causes of failure,
but are presented as a guideline to be used in locating the approximate section of the unit that has
failed.
5.4.1 TROUBLESHOOTING PROCEDURES
Troubleshooting information for the KT 73 is mainly contained in the fault codes and troubleshoot-
ing procedures. The troubleshooting procedures are for use as deemed necessary, when ever a
unit fails to meet the performance requirements of the functional test procedure in the Testing
paragraphs of this section.

Rev. 1, May/2003 15563M01.JA Page 5-61

B KT 73

B KT 73

FIGURE 5-53 WAVEFORM 46

Rev. 1, May/2003 15563M01.JA Page 5-108

B KT 73

5.4.6 TROUBLESHOOTING FLOWCHARTS

Figures 5-54 through 5-60 provides a flow chart procedure for fault isolation to a likely circuit mod-
ule.
The test setup and test equipment require for troubleshooting are given in Figure 5-1. The initial
test conditions for troubleshooting are specified at the beginning of the functional test procedure
(paragraph 5.2.3.3 of this section). The flow chart troubleshooting procedure is begun when either
the KT 73 unit fails any part of the functional test or the fault number of a fault circuit is displayed
on the fault annunciator display (altitude display window) on the front panel.
If the KT 73 under test contains more than one fault, the fault with the highest priority will be dis-
played. When that fault has been corrected, return to sheet one of the troubleshooting procedure.
The next highest priority will then be displayed. The newly displayed fault is isolated by using the
appropriate branch of the flow chart. After all the faulty circuit modules have been repaired and
reinserted, the functional test should be performed to assure the KT 73 is operating satisfactorily.

CAUTION:
TURN OFF POWER BEFORE MAKING ANY
DISCONNECTIONS OR CONNECTIONS AND
BEFORE REMOVING OR REINSERTING PC
MODULES.

Rev. 1, May/2003 15563M01.JA Page 5-109

B KT 73

THIS PAGE IS RESERVED

Parts identified in this IPL by Honeywell part number meet design specifications for
this equipment and are the recommended replacement parts. Warranty informa-
tion concerning Honeywell replacement parts is contained in Service Memo #1,
P/N 600-08001-00XX.

Some part numbers may not be currently available. Consult the current Honeywell
catalog or contact a Honeywell representative for equipment availability.

6.2 REVISION SERVICE

The manual will be revised as necessary to reflect current information.

6.5 KT 73 FINAL ASSEMBLY

066-01164-0101 FINAL BILL OF MATERIAL, KT73 Rev. F

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0101
---------------------------------------------------------------
000-01007-0000 PRODUCT STRUCTURE, RF .00
004-02148-4000 MINIMUM PERFORMANC RF .00
011-07000-0001 ALUMINUM TAPE 2 IN IN 2.90
012-01005-0002 TAPE MYLAR .500 W IN 2.63
047-09587-0007 COVER BOTTOM EA 1.00
047-09588-0003 P/S CHASSIS EA 1.00
047-09589-0001 POWER BD COVER EA 1.00
047-09609-0001 TOP COVER KT 70 EA 1.00
047-12775-0004 PRESELECT SHIELD W EA 1.00
047-12842-0004 SHIELD, ASSY EA 1.00
057-01540-0000 WARNING HV TAG EA 2.00
057-02203-0001 FLAVOR STCKR EA 2.00
057-03511-0001 DECAL, CAUTION EA 1.00
057-05367-0000 AIRCRAFT IDENT TAG EA 1.00
057-05893-0001 S/N TAG , KT 73 EA 1.00
075-05097-0001 HINGE LEAF EA 1.00
076-02232-0001 STANDOFF EA 2.00
076-02233-0001 SPACER EA 2.00
089-05901-0003 SCR PHP 3-48X3/16 EA 15.00
089-05901-0004 SCR PHP 3-48X1/4 EA 11.00
089-06006-0003 SCR FHP 3-48X3/16 EA 8.00
089-06006-0004 SCR FHP 3-48X1/4 EA 9.00
089-06368-0003 SCR FHP 4-40X3/16 EA 4.00
089-08109-0034 WSHR SPLT LK #4 EA 2.00
090-00960-0000 FINGERSTOCK EA .20
090-00991-0000 PROTECTIVE CLOSURE EA 1.00
200-05049-0003 KT 73 CHASSIS ASSE EA 1.00
200-08273-0020 KT 73 RECEIVER BD EA 1.00
200-09349-0000 B.O.M. FRONT PANEL EA 1.00
200-09862-0000 KT 73 POWER SUPPLY EA 1.00
200-10069-0000 MOUNTING RACK EA 1.00
206-00387-0102 SOFTWARE SET, KT73 EA 1.00
300-09360-0000 FINAL ASSEMBLY, KT RF .00

Rev. 1, May/2003 15563M01.JA Page 6-5

Rev. 1, May/2003 15563M01.JA Page 6-15

B KT 73

6.7 KT 73 TRANSMITTER BOARD

200-08275-0040 KT 73 TRANSMITTER BOARD Rev. D

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0040
---------------------------------------------------------------
C1 106-00044-0054 CAP CH 12PF 5% EA 1.00
C10 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C11 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C12 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C13 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C14 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C15 106-00044-0016 CAP CHIP 3.3PF500V EA 1.00
C16 106-00044-0016 CAP CHIP 3.3PF500V EA 1.00
C17 111-00001-0009 CAP CR .15UF 100V EA 1.00
C18 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C19 106-04331-0026 CAPCH330PFNPO/100V EA 1.00
C2 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C20 106-05470-0026 CAP CH47PFNPO/100V EA 1.00
C21 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C22 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C23 106-05829-0020 CH 8.2PF NPO 100V EA 1.00
C24 106-00044-0009 CAP CHIP 3.9PF500V EA 1.00
C25 106-00128-0000 CAP FEEDTHRU 1KPF EA 1.00
C26 106-00128-0000 CAP FEEDTHRU 1KPF EA 1.00
C27 106-00128-0000 CAP FEEDTHRU 1KPF EA 1.00
C28 106-00123-0000 EMI FLTR FEEDTHRU EA 1.00
C30 106-00044-0016 CAP CHIP 3.3PF500V AR 1.00
C31 106-00074-0023 CAP PF 2.7 500VDC EA 1.00
C32 106-00127-0000 CAP FT 100PF 8-36 EA 1.00
C4 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C5 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C6 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
C7 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C8 102-00071-0001 CAP VAR 0.6-4.5PF EA 1.00
C9 106-00044-0003 CAP CHIP 33PF 500V EA 1.00
CR1 007-06418-0000 PIN DIODE EA 1.00
CR2 007-06179-0000 DIO SI MMBD501 EA 1.00
CR3 007-06418-0000 PIN DIODE EA 1.00
FL1 017-00293-0001 CERAMIC FILTER, 10 EA 1.00
JKT703 030-00152-0000 CONN BNC HEX EA 1.00
L1 019-02400-0020 COIL 4 T EA 1.00
L2 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L3 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L4 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L5 019-02681-0001 1/2T INDUCTOR .125 EA 1.00
L6 019-02400-0023 COIL 3TX0.110 EA 1.00
L7 019-02400-0020 COIL 4 T EA 1.00
L8 019-02400-0020 COIL 4 T EA 1.00
L9 013-00038-0003 FERRITE BEAD EA 1.00
Q1 007-00922-0000 300W MODE S NPN RF EA 1.00
Q2 007-01308-0001 XTRS 300 WATTS, MO EA 1.00
R1 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R10 139-20392-0020 RES CH 3.92OHM QW EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-17

B KT 73

200-08274-0020 MODULATOR BOARD Rev. G

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0020
---------------------------------------------------------------
C1 097-00207-0009 CAP AL 12UF 63V EA 1.00
C10 097-00204-0011 CAP AL 10UF 50V 20 EA 1.00
C11 097-00218-0005 CAP EL 22UF 100V EA 1.00
C12 106-04223-0047 CAP CH 22K X7R/50V EA 1.00
C13 106-04330-0026 CH 33PF NPO/100V EA 1.00
C14 105-00046-0004 CAP MY 3UF 100V10% EA 1.00
C15 097-00207-0008 CAP AL 270UF 25V EA 1.00
C16 106-04272-0017 CAPCH .0027 MF COG EA 1.00
C17 106-04104-0047 CH 100KX7R/50V EA 1.00
C18 106-04272-0017 CAPCH .0027 MF COG EA 1.00
C19 106-04104-0047 CH 100KX7R/50V EA 1.00
C2 105-00046-0011 CAP MY 5.0UF EA 1.00
C20 097-00214-0035 CAP AL 47UF 50V EA 1.00
C21 097-00211-0000 CAP AL 140UF 75V EA 1.00
C22 105-00046-0011 CAP MY 5.0UF EA 1.00
C24 095-00006-0072 CAP AL 3.3UF 100V EA 1.00
C3 097-00211-0001 CAP AL 78UF 100V EA 1.00
C4 106-04330-0026 CH 33PF NPO/100V EA 1.00
C5 097-00097-0016 CAP EL 220UF 80V EA 1.00
C6 106-04330-0026 CH 33PF NPO/100V EA 1.00
C7 106-04330-0026 CH 33PF NPO/100V EA 1.00
C8 097-00204-0010 CAP AL 10UF 25V 20 EA 1.00
C9 097-00204-0007 CAP AL 4.7UF 25V 2 EA 1.00
CR1 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR10 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR11 007-06444-0001 DIO 1A 100V SMD EA 1.00
CR12 999-09999-9999 PLACE HOLDER RF .00
CR2 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR3 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR4 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR5 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR6 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
CR8 007-06088-0000 DIO HC 1N5817 EA 1.00
CR9 007-06177-0000 SMD DIO SI MMBD914 EA 1.00
P1 030-03041-0005 HEADER RT DOUBLE EA 1.00
Q1 007-00549-0000 XSTR MMBT4401 EA 1.00
Q10 007-00886-0000 XSTR MOSFET IRF540 EA 1.00
Q11 00712225-0002 XSTR,IRFR9120,P-CH EA 1.00
Q12 007-00933-0000 MMBT2369 EA 1.00
Q2 007-00399-0002 XSTR D44E3 EA 1.00
Q3 007-00399-0002 XSTR D44E3 EA 1.00
Q4 007-00926-0000 MOSFET PCH VP0300L EA 1.00
Q5 007-00926-0000 MOSFET PCH VP0300L EA 1.00
Q6 007-00886-0000 XSTR MOSFET IRF540 EA 1.00
Q7 007-00532-0000 XSTR MMBT4403 EA 1.00
Q8 007-00549-0000 XSTR MMBT4401 EA 1.00
R1 139-03572-0000 RES CHIP 35.7KEW1% EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-25

B KT 73

200-09349-0000 B.O.M. FRONT PANEL, KT73 Rev. B

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0000
---------------------------------------------------------------
REF1 300-09349-0000 FRONT BEZEL ASSEM RF .00
012-01017-0001 11 ELEC TAPE 1/4 W IN 3.40
016-01124-0001 10 FOAM CARRIER TAPE IN .70
037-05107-0001 9 GAS DISCHARGE DISP EA 1.00
073-00998-0006 5 MODE CONTROL KNOB EA 1.00
073-01015-0005 4 KNOB, W/WASHER, KT EA 4.00
089-05903-0005 7 SCR PHP 4-40X5/16 EA 2.00
089-05927-0010 8 SCR BHP 4-40X5/8 EA 1.00
089-06200-0004 6 SCR SET 2-56X1/8 EA 11.00
187-01913-0001 3 .180 ID X .270 OD EA 1.00
200-09325-0020 1 KT 73 DISPLAY BOAR EA 1.00
200-09355-0000 2 BEZEL ASSEMBLY BOM EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-31

B KT 73

THIS PAGE IS RESERVED

Rev. 1, May/2003 15563M01.JA Page 6-32

B KT 73

FIGURE 6-8 KT 73 FRONT PANEL ASSEMBLY

(Dwg. No. 300-09349-0000 R-A)

Rev. 1, May/2003 15563M01.JA Page 6-33

B KT 73

6.10 KT 73 DISPLAY BOARD

200-09325-0020 KT 73 DISPLAY BOARD Rev. D

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0020
---------------------------------------------------------------
C1 106-04104-0047 CH 100KX7R/50V EA 1.00
C2 106-04104-0047 CH 100KX7R/50V EA 1.00
CR1 007-05117-0024 DIO Z 33V SOT EA 1.00
CR2 007-05117-0024 DIO Z 33V SOT EA 1.00
CR3 007-05117-0024 DIO Z 33V SOT EA 1.00
CR4 007-05117-0024 DIO Z 33V SOT EA 1.00
CR5 007-05117-0016 DIO Z 15V SOT EA 1.00
CR6 007-05117-0016 DIO Z 15V SOT EA 1.00
DS1 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS19 007-07008-0001 LED LIGHT BARS REC EA 1.00
DS2 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS3 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS4 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS5 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS6 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS7 037-00012-0014 LAMP INC T-1 14V EA 1.00
DS8 037-00012-0014 LAMP INC T-1 14V EA 1.00
J1 033-00312-0033 SOCKET, SIP, .1CTR EA 1.00
P1 030-03347-0022 HEADER .630 LONG 2 EA 1.00
Q1 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q10 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q11 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q12 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q13 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q14 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q15 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q16 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q17 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q18 007-00257-0001 MMBTA42 SO PKG EA 1.00
Q19 007-00903-0000 2N7002 MOSFET EA 1.00
Q2 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q22 007-00903-0000 2N7002 MOSFET EA 1.00
Q3 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q4 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q5 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q6 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q7 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q8 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
Q9 007-00254-0001 XSTR S PNP SOT-23 EA 1.00
R1 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R10 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R100 139-02002-0010 RES CH 20K TW 1% EA 1.00
R109 139-07502-0000 RES CHIP 75KEW1% EA 1.00
R11 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R111 139-01500-0000 RES CH 150 EW 1% EA 1.00
R113 139-04991-0000 RES CHIP 4.99KEW1% EA 1.00
R114 999-09999-9999 PLACE HOLDER RF .00
R115 999-09999-9999 PLACE HOLDER RF .00

Rev. 1, May/2003 15563M01.JA Page 6-35

B KT 73

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0020
---------------------------------------------------------------
R12 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R13 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R14 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R15 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R16 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R17 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R18 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
R19 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R2 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R20 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R21 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R22 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R23 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R24 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R25 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R26 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R27 139-04752-0020 RES CH 47500 QW 1% EA 1.00
R28 139-05113-0010 RES CH TW 1% EA 1.00
R29 139-05113-0010 RES CH TW 1% EA 1.00
R3 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R30 139-05113-0010 RES CH TW 1% EA 1.00
R31 139-05113-0010 RES CH TW 1% EA 1.00
R32 139-05113-0010 RES CH TW 1% EA 1.00
R33 139-05113-0010 RES CH TW 1% EA 1.00
R34 139-05113-0010 RES CH TW 1% EA 1.00
R35 139-05113-0010 RES CH TW 1% EA 1.00
R36 139-05113-0010 RES CH TW 1% EA 1.00
R37 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R38 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R4 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R40 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R41 139-03012-0010 RESISTOR CHIP 30.1 EA 1.00
R42 139-03012-0010 RESISTOR CHIP 30.1 EA 1.00
R43 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R44 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R45 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R46 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R47 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R48 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R49 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R5 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R50 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R51 139-05622-0010 RES CH 56.2K TW 1% EA 1.00
R52 139-03922-0010 RES CH 39.2K TW 1% EA 1.00
R53 139-06812-0010 RES CH 68.1K TW 1% EA 1.00
R54 139-04752-0010 RES CH 47.5K TW 1% EA 1.00
R55 139-01502-0010 RES CH 15 K .1W 1% EA 1.00
R56 139-03323-0010 RES CH 332K TW 1% EA 1.00
R57 139-03323-0010 RES CH 332K TW 1% EA 1.00
R58 139-03323-0010 RES CH 332K TW 1% EA 1.00
R59 139-03323-0010 RES CH 332K TW 1% EA 1.00
R6 139-02001-0010 RES CH 2.00K TW 1% EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-36

B KT 73

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0020
---------------------------------------------------------------
R60 139-03323-0010 RES CH 332K TW 1% EA 1.00
R61 139-03323-0010 RES CH 332K TW 1% EA 1.00
R62 139-03323-0010 RES CH 332K TW 1% EA 1.00
R63 139-03323-0010 RES CH 332K TW 1% EA 1.00
R64 139-03323-0010 RES CH 332K TW 1% EA 1.00
R65 139-03323-0010 RES CH 332K TW 1% EA 1.00
R66 139-03323-0010 RES CH 332K TW 1% EA 1.00
R67 139-03323-0010 RES CH 332K TW 1% EA 1.00
R68 139-03323-0010 RES CH 332K TW 1% EA 1.00
R69 139-03323-0010 RES CH 332K TW 1% EA 1.00
R7 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R70 139-03323-0010 RES CH 332K TW 1% EA 1.00
R71 139-03323-0010 RES CH 332K TW 1% EA 1.00
R72 139-03323-0010 RES CH 332K TW 1% EA 1.00
R73 139-03323-0010 RES CH 332K TW 1% EA 1.00
R74 139-03323-0010 RES CH 332K TW 1% EA 1.00
R75 139-03323-0010 RES CH 332K TW 1% EA 1.00
R76 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R77 134-05005-0002 PHOTODETECTOR EA 1.00
R78 139-03322-0010 RES CH 33.2K TW 1% EA 1.00
R79 139-03012-0010 RESISTOR CHIP 30.1 EA 1.00
R8 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R80 139-01502-0010 RES CH 15 K .1W 1% EA 1.00
R81 139-01822-0010 RES CH 18.2K TW 1 EA 1.00
R82 139-02002-0010 RES CH 20K TW 1% EA 1.00
R83 139-02002-0010 RES CH 20K TW 1% EA 1.00
R84 139-02002-0010 RES CH 20K TW 1% EA 1.00
R85 139-02002-0010 RES CH 20K TW 1% EA 1.00
R86 139-02002-0010 RES CH 20K TW 1% EA 1.00
R87 139-02002-0010 RES CH 20K TW 1% EA 1.00
R88 139-02002-0010 RES CH 20K TW 1% EA 1.00
R89 139-02002-0010 RES CH 20K TW 1% EA 1.00
R9 139-02001-0010 RES CH 2.00K TW 1% EA 1.00
R90 139-02002-0010 RES CH 20K TW 1% EA 1.00
R91 139-02002-0010 RES CH 20K TW 1% EA 1.00
R92 139-02002-0010 RES CH 20K TW 1% EA 1.00
R93 139-02002-0010 RES CH 20K TW 1% EA 1.00
R94 139-02002-0010 RES CH 20K TW 1% EA 1.00
R95 139-02002-0010 RES CH 20K TW 1% EA 1.00
R96 139-02002-0010 RES CH 20K TW 1% EA 1.00
R97 139-02002-0010 RES CH 20K TW 1% EA 1.00
R98 139-02002-0010 RES CH 20K TW 1% EA 1.00
R99 139-02002-0010 RES CH 20K TW 1% EA 1.00
SW1 031-00759-0000 SWITCH ROTARY EA 1.00
SW2 031-00759-0000 SWITCH ROTARY EA 1.00
SW3 031-00759-0000 SWITCH ROTARY EA 1.00
SW4 031-00759-0000 SWITCH ROTARY EA 1.00
SW5 031-00759-0010 ROTARY SWITCH EA 1.00
SW6 031-00753-0000 SWITCH TACTILE EA 1.00
SW7 031-00753-0000 SWITCH TACTILE EA 1.00
U1 124-00237-0003 74HCT237 3 TO 8 LI EA 1.00
U2 124-00151-0003 IC 74HCT151 SO EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-37

B KT 73

200-09355-0000 BEZEL ASSEMBLY BOM, KT73 Rev. A

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0000
---------------------------------------------------------------
016-01131-0000 6 CONTACT CEMENT #77 AR 1.00
035-01361-0028 7 PROTECTIVE COVER, EA 1.00
057-05892-0001 3 DECAL PART, KT73 EA 1.00
073-01001-0004 1 BEZEL W / PAINT EA 1.00
088-03227-0029 4 PUSH BUTTON O DECO EA 1.00
088-03227-0031 5 PUSH BUTTON O DECO EA 1.00
088-03248-0002 2 LENS, W/FAIL EA 1.00
300-09355-0000 BEZEL ASSEMBLY DRA RF .00

Rev. 1, May/2003 15563M01.JA Page 6-51

B KT 73

THIS PAGE IS RESERVED

Rev. 1, May/2003 15563M01.JA Page 6-52

Rev. 1, May/2003 15563M01.JA Page 6-57

B KT 73

6.13 KT 73 EXTERNAL EEPROM BOARD

200-09889-0010 KT 73 EXTERNAL EEPRM BOARD Rev. B

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0010
---------------------------------------------------------------
C1 106-05104-1327 CAP CH 100KX7R/16V EA 1.00
C2 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
C3 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
C4 106-05101-1026 CAP CH 100PFNPO/10 EA 1.00
ITM1 009-09889-0011 KT 73 EXTERNAL EEP EA 1.00
ITM2 030-00107-0099 POLARIZING KEY EA 1.00
J1 030-01120-0000 CONN PC BD EA 1.00
J2 030-03410-0003 CONN, RECT, PLG,FX EA 1.00
R1 139-01001-0010 RES CH 1000 .1W 1% EA 1.00
REF1 300-09889-0010 KT 73 EXTERNAL EEP RF .00
REF2 002-09889-0010 KT 73 EXTERNAL EEP RF .00
U1 120-02547-0013 SERIAL EEPROM EA 1.00
016-01040-0000 COATING TYPE AR AR 1.00
016-01140-0000 SUPERBONDER 415 AR 1.00

Rev. 1, May/2003 15563M01.JA Page 6-59

B KT 73

THIS PAGE IS RESERVED

206-00387-0102 SOFTWARE SET, KT73 Rev. -
----------------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0101 -0102
----------------------------------------------------------------------
057-05287-0101 SW MOD TAG EA 1.00 .
057-05287-0102 UNIT SFTWR V0102 EA . 1.00
125-00966-0101 KT 73 APPLICATION RF .00 .
125-00966-0102 KT 73 APPLICATION RF . .00
125-01034-0002 KT 73 BOOT SOFTWAR RF .00 .00
126-00215-0002 KT 73 FPGA FIRMWAR RF .00 .00
126-00216-0000 KT73 VOICE RF .00 .00
205-00914-0002 KT 73 MAIN BOARD S EA 1.00 1.00
222-30035-0101 KT 73 LOAD MEDIA C RF .00 .
222-30035-0102 KT 73 LOAD MEDIA C RF . .00
716-00356-0101 KT 73 CONFIG INDEX RF .00 .
716-00356-0102 KT 73 SOFTWARE CON RF . .00

205-00914-0002 KT 73 MAIN BOARD SW Rev. -

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0002
---------------------------------------------------------------
057-05252-0914 1 1DT 205-00914-0000 EA 1.00
057-05335-0002 2 DECAL 205 DASH 02 EA 1.00
125-01034-0002 KT 73 BOOT SOFTWAR EA 1.00
126-00215-0002 KT 73 FPGA FIRMWAR EA 1.00
200-09321-0000 BOM, MAIN BOARD, K EA 1.00
300-09321-0000 ASSEMBLY, MAIN BOA RF .00

Rev. 1, May/2003 15563M01.JA Page 6-137

B KT 73

6.16 KT 73 POWER SUPPLY BOARD

200-09862-0000 KT 73 POWER SUPPLY Rev. C

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0000
---------------------------------------------------------------
C1 097-00207-0006 CAP AL 330UF 50V EA 1.00
C10 106-04562-0057 CAPCH5600PFX7R/100 EA 1.00
C11 106-04104-0047 CH 100KX7R/50V EA 1.00
C12 097-00207-0006 CAP AL 330UF 50V EA 1.00
C13 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C14 097-00217-0013 CAP EL 220UF 10V EA 1.00
C15 097-00217-0013 CAP EL 220UF 10V EA 1.00
C16 097-00217-0013 CAP EL 220UF 10V EA 1.00
C17 097-07000-5205 CAP AL LOW ESR SM EA 1.00
C18 097-00217-0013 CAP EL 220UF 10V EA 1.00
C19 097-00217-0013 CAP EL 220UF 10V EA 1.00
C2 106-04104-0047 CH 100KX7R/50V EA 1.00
C20 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C21 097-07000-6101 CAP AL LOW ESR SMT EA 1.00
C22 106-04561-0016 CAP CH560PFNPO/50V EA 1.00
C23 106-04104-0047 CH 100KX7R/50V EA 1.00
C24 106-04104-0047 CH 100KX7R/50V EA 1.00
C25 097-00207-0006 CAP AL 330UF 50V EA 1.00
C26 097-00207-0006 CAP AL 330UF 50V EA 1.00
C27 106-05821-0047 CAP CH820PFX7R/50V EA 1.00
C28 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C29 097-00146-0004 CAP AL4.7UF160V20% EA 1.00
C3 097-00104-0036 CAP AL 47UF 25V EA 1.00
C30 097-00217-0008 CAP AL/0 68UF 20V EA 1.00
C31 097-07000-5205 CAP AL LOW ESR SM EA 1.00
C32 097-07000-4515 CAP AL LOW ESR 220 EA 1.00
C33 097-00217-0008 CAP AL/0 68UF 20V EA 1.00
C34 097-07000-5205 CAP AL LOW ESR SM EA 1.00
C35 097-07000-4515 CAP AL LOW ESR 220 EA 1.00
C4 097-07000-5205 CAP AL LOW ESR SM EA 1.00
C44 106-04102-0026 CH 1KPF NPO/100V EA 1.00
C45 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C46 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C47 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C48 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C49 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C5 106-04820-0026 CAP CH82PFNPO/100V EA 1.00
C50 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C51 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C52 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C53 106-04104-0057 CAP CH .1UF 100V 1 EA 1.00
C54 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C55 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C56 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C57 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C58 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C59 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C6 097-07000-6101 CAP AL LOW ESR SMT EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-139

B KT 73

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0000
---------------------------------------------------------------
C60 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C61 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C62 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C63 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C64 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C65 106-04103-0057 CAP CH 10KX7R/100V EA 1.00
C7 106-04561-0016 CAP CH560PFNPO/50V EA 1.00
C8 106-04104-0047 CH 100KX7R/50V EA 1.00
C9 106-05153-0047 CAP CH 15K X7R/50V EA 1.00
CJ1 026-00018-0001 WIRE CKTJMPR 24AWG EA 1.00
CR1 007-05039-0002 DIO Z 40.2V EA 1.00
CR10 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR11 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR12 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR13 007-06175-0003 DIO MUR460 EA 1.00
CR14 007-06141-0001 DIO UF RECOV 200V EA 1.00
CR15 007-06141-0001 DIO UF RECOV 200V EA 1.00
CR16 007-06175-0001 DIO RECT EA 1.00
CR2 007-06088-0001 DIO HC VSK140 EA 1.00
CR3 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR4 007-05115-0008 DIO Z 1N5526B EA 1.00
CR5 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR6 007-06227-0000 DIO MMBD6100 SOT23 EA 1.00
CR7 007-06141-0005 DIO UF RECOV 1000V EA 1.00
CR8 007-06175-0001 DIO RECT EA 1.00
CR9 007-06141-0005 DIO UF RECOV 1000V EA 1.00
L1 019-02695-0000 INDUCTOR EA 1.00
L2 019-02695-0000 INDUCTOR EA 1.00
L3 019-02084-0057 CH 33UH 10% EA 1.00
L5 019-02696-0000 INDUCTOR 51UH EA 1.00
L6 019-02696-0000 INDUCTOR 51UH EA 1.00
L7 019-02696-0000 INDUCTOR 51UH EA 1.00
L8 013-00172-0001 FERR BEAD SRFC MT EA 1.00
L9 013-00172-0001 FERR BEAD SRFC MT EA 1.00
P1 030-02174-0002 PIN CONN MALE EA 18.00
Q1 007-00335-0002 XSTR S PNP TIP42B EA 1.00
Q2 007-00467-0000 XSTR S NPN MMBTA06 EA 1.00
Q3 007-00467-0000 XSTR S NPN MMBTA06 EA 1.00
Q4 007-00467-0000 XSTR S NPN MMBTA06 EA 1.00
Q5 007-00542-0000 XSTR PNP MMBTA64 EA 1.00
Q6 007-00886-0000 XSTR MOSFET IRF540 EA 1.00
Q7 007-00542-0000 XSTR PNP MMBTA64 EA 1.00
Q8 007-00886-0000 XSTR MOSFET IRF540 EA 1.00
Q9 007-00813-0000 XSTR NPN S MMBTA14 EA 1.00
R1 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R10 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R11 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R12 139-09092-0000 RES CHIP 90.9KEW1% EA 1.00
R13 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R14 139-01212-0000 RES CHIP 12.1K1%EW EA 1.00
R15 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R16 133-00113-0014 RES VA 2K 20% A EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-140

B KT 73

---------------------------------------------------------------
SYMBOL PART NUMBER FIND NO DESCRIPTION UM -0000
---------------------------------------------------------------
R17 139-01022-0000 RES CHIP 10.2KEW1% EA 1.00
R18 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R19 139-01502-0000 RES CHIP 15K EW 1% EA 1.00
R2 139-08251-0000 RES CH 8.25K EW 1% EA 1.00
R20 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R21 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R22 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R23 139-00511-0000 RES CH 51.1 EW 1% EA 1.00
R24 132-05046-0000 RES WW .05 2W 5% EA 1.00
R25 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R26 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R28 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R29 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R3 139-04750-0000 RES CH 475 EW 1% EA 1.00
R30 139-00000-0004 RES CH 0 EW EA 1.00
R31 139-05111-0000 RES CHIP 5.11KEW1% EA 1.00
R32 139-04751-0000 RES CH 4.75K EW 1% EA 1.00
R33 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R34 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R35 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R36 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R37 139-02002-0000 RES CHIP 20.0KEW1% EA 1.00
R38 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R39 139-08871-0000 RES CH 8.87K EW 1% EA 1.00
R4 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R40 139-02552-0000 RES CH 25.5K EW 1% EA 1.00
R41 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R42 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R43 139-03320-0000 RES CHIP 332 EW 1% EA 1.00
R44 139-02430-0010 RES CH 243 TW 1% EA 1.00
R46 139-01212-0000 RES CHIP 12.1K1%EW EA 1.00
R47 139-03921-0000 RES CH 3.92K EW 1% EA 1.00
R48 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R49 139-01502-0000 RES CHIP 15K EW 1% EA 1.00
R5 139-01302-0000 RES CH 13K EW 1% EA 1.00
R50 139-05622-0000 RES CH 56.2K EW 1% EA 1.00
R51 139-00100-0000 RES CHIP 10 EW 1% EA 1.00
R52 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R53 139-01001-0000 RES CHIP 1K EW 1% EA 1.00
R54 132-00206-0000 RES WW .01 1% 4W EA 1.00
R55 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R56 139-04752-0030 RES CH 47.5K 1/2W EA 1.00
R57 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R58 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R59 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R6 139-04321-0000 RES CH 4.32K EW 1% EA 1.00
R7 139-01101-0000 RES CH 1.1K EW 1% EA 1.00
R74 139-01002-0000 RES CHIP 10K EW 1% EA 1.00
R75 139-00000-0004 RES CH 0 EW EA 1.00
R76 139-01003-0000 RES CHIP 100KEW1% EA 1.00
R77 133-00100-0033 RES VA 100 QW 10% EA 1.00
R8 139-05110-0000 RES CH 511 EW 1% EA 1.00

Rev. 1, May/2003 15563M01.JA Page 6-141

B KT 73

Rev. 1, May/2003 15563M01.JA Page APP-2

B KT 73

KT 73 HARDWARE/SOFTWARE CONFIGURATIONS
(Sheet 1 of 2)

Rev. 1, May/2003 15563M01.JA Page APP-3

B KT 73

KT 73 HARDWARE/SOFTWARE CONFIGURATIONS
(Sheet 2 of 2)

Rev. 1, May/2003 15563M01.JA Page APP-5

KT 76A-78A Mant. Manual PDF
80% (5)
KT 76A-78A Mant. Manual PDF
360 pages
Main Wheel Assembly Ww1124
No ratings yet
Main Wheel Assembly Ww1124
112 pages
Minimum Hold Fuel Calculation
100% (2)
Minimum Hold Fuel Calculation
9 pages
Aire Acondicionado Cessna
67% (3)
Aire Acondicionado Cessna
77 pages
CMM 32-40-09 - 2606671 Rev. 14 Oct 14 2005 (Solo de Referencia)
100% (2)
CMM 32-40-09 - 2606671 Rev. 14 Oct 14 2005 (Solo de Referencia)
221 pages
STC SA00343BO - August 2022
No ratings yet
STC SA00343BO - August 2022
4 pages
KMH 880/KTA 870: System Installation Manual
100% (1)
KMH 880/KTA 870: System Installation Manual
280 pages
King Servo SM292
No ratings yet
King Servo SM292
5 pages
R15V0L Pit
No ratings yet
R15V0L Pit
4 pages
King KMT-112 Maintenance Manual
100% (1)
King KMT-112 Maintenance Manual
29 pages
Do You: Part 1
From Everand
Do You: Part 1
Greg Hightower
No ratings yet
ADT406-AP Technical Manual
No ratings yet
ADT406-AP Technical Manual
55 pages
Kas 297a Maintenance Manual 006 05512 0003 3
No ratings yet
Kas 297a Maintenance Manual 006 05512 0003 3
184 pages
Model A-30 Altitude Digitizer Operation Manual Installation Manual
No ratings yet
Model A-30 Altitude Digitizer Operation Manual Installation Manual
6 pages
CMM 1900 A
100% (1)
CMM 1900 A
190 pages
Hawker Microvawe
No ratings yet
Hawker Microvawe
6 pages
Narco Avionics AR850 - 15Pin-Manual PDF
No ratings yet
Narco Avionics AR850 - 15Pin-Manual PDF
36 pages
EET-200E Encoder Emulator User Manual: Trans-Cal Industries, Inc
No ratings yet
EET-200E Encoder Emulator User Manual: Trans-Cal Industries, Inc
34 pages
Flightmax: Installation Manual
No ratings yet
Flightmax: Installation Manual
102 pages
Manual AP-447 Brakes
No ratings yet
Manual AP-447 Brakes
89 pages
34-15-59a PDF Component Maintenance Manual
No ratings yet
34-15-59a PDF Component Maintenance Manual
110 pages
Ata 23 I-Aea1
No ratings yet
Ata 23 I-Aea1
51 pages
King KA-52 Maintenance
No ratings yet
King KA-52 Maintenance
43 pages
Bendix King KXP 2290
No ratings yet
Bendix King KXP 2290
62 pages
GDU 104X Installation Manual
100% (2)
GDU 104X Installation Manual
70 pages
CMM 22-11-96 Display Guidance Controler
100% (1)
CMM 22-11-96 Display Guidance Controler
2,325 pages
Maintenance Manual: Test Set
No ratings yet
Maintenance Manual: Test Set
50 pages
STC Directory - RevK March 20 2012
100% (1)
STC Directory - RevK March 20 2012
152 pages
Installation Bulletin: Bulletin No: 385 APPLICABLE TO: KAP 150 and KFC 150 Flight Control Systems Subject
No ratings yet
Installation Bulletin: Bulletin No: 385 APPLICABLE TO: KAP 150 and KFC 150 Flight Control Systems Subject
4 pages
SL40SVC
No ratings yet
SL40SVC
35 pages
Bonanza 14v Wiring 5891
100% (2)
Bonanza 14v Wiring 5891
255 pages
Pa S-Tec Wiring 10243 Rev J
100% (1)
Pa S-Tec Wiring 10243 Rev J
11 pages
Elenco Apparati Avionici
25% (4)
Elenco Apparati Avionici
53 pages
EFD1000 Install PDF
No ratings yet
EFD1000 Install PDF
202 pages
190 00587 00
No ratings yet
190 00587 00
116 pages
Service Instructions FOR Radar RDR 2000 With Moving Map Installation and Gns 530 (GPS) Installation
100% (1)
Service Instructions FOR Radar RDR 2000 With Moving Map Installation and Gns 530 (GPS) Installation
42 pages
Enviro MAN 21 00 08rev17
No ratings yet
Enviro MAN 21 00 08rev17
85 pages
Flight Line Service Manual For Rate Based Autopilots
No ratings yet
Flight Line Service Manual For Rate Based Autopilots
115 pages
Enstrom F28C RFM (1998)
100% (1)
Enstrom F28C RFM (1998)
120 pages
006-00662-0009_9_KAD480-481
No ratings yet
006-00662-0009_9_KAD480-481
134 pages
ASPEN Document 900-00012-001-T-EFD-ICA
No ratings yet
ASPEN Document 900-00012-001-T-EFD-ICA
38 pages
Product Manual Me 406 Ace ACR ARTEX
No ratings yet
Product Manual Me 406 Ace ACR ARTEX
74 pages
SBFA2100CVR022
100% (1)
SBFA2100CVR022
16 pages
Model 550 Bravo: Cessna® Illustrated Parts Catalog
No ratings yet
Model 550 Bravo: Cessna® Illustrated Parts Catalog
1 page
TIO-540 Narrow Deck Parts Catalog PC-315-6
100% (1)
TIO-540 Narrow Deck Parts Catalog PC-315-6
115 pages
Bendix/King CNI5000 Installation/Maintenance Manual Rev. 3
No ratings yet
Bendix/King CNI5000 Installation/Maintenance Manual Rev. 3
142 pages
Maintenance Manual: Test Set
100% (1)
Maintenance Manual: Test Set
36 pages
182SWD-01
No ratings yet
182SWD-01
68 pages
Boletines Turbocommander
100% (1)
Boletines Turbocommander
1,012 pages
S-Tech Sys65 Autopilot Poh
No ratings yet
S-Tech Sys65 Autopilot Poh
62 pages
AND OF: Continent Airport p.0. 7707 Wichita, Kansas 67277 (316) 946-2000 Telex 41 7441
No ratings yet
AND OF: Continent Airport p.0. 7707 Wichita, Kansas 67277 (316) 946-2000 Telex 41 7441
3 pages
412 MM CH04 PDF
No ratings yet
412 MM CH04 PDF
16 pages
Baron 58 TC
No ratings yet
Baron 58 TC
106 pages
182SPC14
No ratings yet
182SPC14
894 pages
VHF 22 Ib 5230771854 PDF
No ratings yet
VHF 22 Ib 5230771854 PDF
696 pages
384-r002 Emerg Lightning Power Pack
100% (2)
384-r002 Emerg Lightning Power Pack
3 pages
Airspeed
No ratings yet
Airspeed
9 pages
Stratus 3i Installation Guide
No ratings yet
Stratus 3i Installation Guide
8 pages
CMM 24-34-08 REV.15 17-Jun-2020 M3 NICKEL-CADMIUM AIRCRAFT BATTERIES PN M3-SERIES
No ratings yet
CMM 24-34-08 REV.15 17-Jun-2020 M3 NICKEL-CADMIUM AIRCRAFT BATTERIES PN M3-SERIES
55 pages
Garmin 430 Installation Manual
No ratings yet
Garmin 430 Installation Manual
120 pages
1077 Cfe
No ratings yet
1077 Cfe
184 pages
Im2830lg (Adc-2000) PDF
No ratings yet
Im2830lg (Adc-2000) PDF
96 pages
NG Indicator - Pnº 5633-707-80-12
No ratings yet
NG Indicator - Pnº 5633-707-80-12
14 pages
Service Manual - Heraeus - Cryofuge 6000i, 8500i
No ratings yet
Service Manual - Heraeus - Cryofuge 6000i, 8500i
145 pages
Banda Bendix 2606672-1 Rev (1) .15 Sep.28, 2007
No ratings yet
Banda Bendix 2606672-1 Rev (1) .15 Sep.28, 2007
232 pages
Component Maintenance Manual With Illustrated Parts List Nickel Cadmium Battery Ultra Low Maintenance (Ulm) Model 4017CH3 P/N 024643-000
No ratings yet
Component Maintenance Manual With Illustrated Parts List Nickel Cadmium Battery Ultra Low Maintenance (Ulm) Model 4017CH3 P/N 024643-000
68 pages
Component Maintenance Manual With Illustrated Parts List: This Document Replaces and Cancels 24-31-40
100% (2)
Component Maintenance Manual With Illustrated Parts List: This Document Replaces and Cancels 24-31-40
96 pages
Local Aviation Company Is Flying High: Business
No ratings yet
Local Aviation Company Is Flying High: Business
1 page
d7b b10
No ratings yet
d7b b10
20 pages
Sare
No ratings yet
Sare
7 pages
Helicopter Sizing and Calculations
0% (1)
Helicopter Sizing and Calculations
117 pages
Boundary Layer Project
No ratings yet
Boundary Layer Project
6 pages
ATS Presentation Updated
No ratings yet
ATS Presentation Updated
80 pages
B1-11a Aeroplane Aerodynamics SR
0% (1)
B1-11a Aeroplane Aerodynamics SR
42 pages
PFPX Aircraft AddOn List
No ratings yet
PFPX Aircraft AddOn List
2 pages
Bombardier Challenger 01 Flight Controls
No ratings yet
Bombardier Challenger 01 Flight Controls
23 pages
Parte 2-1 FLM Ec 120
No ratings yet
Parte 2-1 FLM Ec 120
269 pages
Computational Modelling and Simulation of Aircraft and The Environment, Volume 2 Aircraft Dynamics
100% (1)
Computational Modelling and Simulation of Aircraft and The Environment, Volume 2 Aircraft Dynamics
208 pages
Aerospace Vehicle Design
No ratings yet
Aerospace Vehicle Design
1 page
NATS Planning Chart
No ratings yet
NATS Planning Chart
1 page
AOPA - Thunderstorms and ATC
100% (2)
AOPA - Thunderstorms and ATC
8 pages
F-35 LRIP 11 - Fact Sheet - Sept 2018
No ratings yet
F-35 LRIP 11 - Fact Sheet - Sept 2018
1 page
Rexbury To Winton (Complete Flight)
No ratings yet
Rexbury To Winton (Complete Flight)
5 pages
Basics of Flight Dynamics
100% (3)
Basics of Flight Dynamics
160 pages
FlightGroup HZS517-HZS518 RPLL-VHHH-RPLC STD122030 STD120001
No ratings yet
FlightGroup HZS517-HZS518 RPLL-VHHH-RPLC STD122030 STD120001
37 pages
Airport
No ratings yet
Airport
32 pages
Spitfire MK - Xiv/Xix: Two Wheel Retract System
100% (1)
Spitfire MK - Xiv/Xix: Two Wheel Retract System
8 pages
V-Speeds (Cessna - 172)
100% (1)
V-Speeds (Cessna - 172)
2 pages
Landing Distance Dispatch Brief PDF
100% (4)
Landing Distance Dispatch Brief PDF
48 pages
Undercarriage Retraction System Design Report
No ratings yet
Undercarriage Retraction System Design Report
6 pages
Aerodynamics of A Highly Cambered Airfoil Experimental Study
No ratings yet
Aerodynamics of A Highly Cambered Airfoil Experimental Study
13 pages
Aviation Emergency Responsen Aircraft Guidebook Compressed
83% (6)
Aviation Emergency Responsen Aircraft Guidebook Compressed
356 pages
Poster Training Program - Pub
No ratings yet
Poster Training Program - Pub
1 page
Airworthiness Standards FAA FAR Part 27
No ratings yet
Airworthiness Standards FAA FAR Part 27
84 pages
(PPL) Flight Performance and Planning
No ratings yet
(PPL) Flight Performance and Planning
4 pages
Pilot's Handbook of Aeronautical Knowledge PHAK Errata Sheet
No ratings yet
Pilot's Handbook of Aeronautical Knowledge PHAK Errata Sheet
5 pages