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SEMICONDUCTOR TECHNICAL DATA by MTP6P20E/D

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   Motorola Preferred Device

   

P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
This advanced TMOS E–FET is designed to withstand high 6.0 AMPERES
energy in the avalanche and commutation modes. The new energy 200 VOLTS
efficient design also offers a drain–to–source diode with a fast RDS(on) = 1.0 OHM
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits 
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature D

G
CASE 221A–06, Style 5
TO–220AB
S

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–Source Voltage VDSS 200 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 200 Vdc
Gate–Source Voltage — Continuous VGS ± 20 Vdc
— Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
Drain Current — Continuous ID 6.0 Adc
— Continuous @ 100°C ID 3.9
— Single Pulse (tp ≤ 10 µs) IDM 21 Apk
Total Power Dissipation PD 75 Watts
Derate above 25°C 0.6 W/°C
Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 180 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case RθJC 1.67 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

 Motorola TMOS
Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1
MTP6P20E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 200 — — Vdc
Temperature Coefficient (Positive) — 211 — mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 200 Vdc, VGS = 0 Vdc) — — 10
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 3.1 4.0 Vdc
Temperature Coefficient (Negative) — 4.0 — mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) — 0.81 1.0 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 6.0 Adc) — 6.0 7.2
(ID = 3.0 Adc, TJ = 125°C) — — 6.3
Forward Transconductance (VDS = 8.0 Vdc, ID = 3.0 Adc) gFS 1.5 3.8 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 540 750 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
Coss — 128 180
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 40 90

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time td(on) — 12 25 ns
Rise Time (VDD = 100 Vdc, ID = 6.0 Adc, tr — 32 65
VGS = 10 Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) — 24 50
Fall Time tf — 16 30
Gate Charge QT — 22 30 nC
(See Figure 8)
(VDS = 160 Vdc, ID = 6.0 Adc, Q1 — 4.0 —
VGS = 10 Vdc) Q2 — 11 —
Q3 — 9.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1) VSD Vdc
(IS = 6.0 Adc, VGS = 0 Vdc)
— 2.8 4.0
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 2.6 —
Reverse Recovery Time trr — 188 — ns
(See Figure 14)
(IS = 6.0 Adc, VGS = 0 Vdc, ta — 152 —
dIS/dt = 100 A/µs) tb — 36 —
Reverse Recovery Stored Charge QRR — 1.595 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from contact screw on tab to center of die) — 3.5 —
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —
Internal Source Inductance LS nH
(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTP6P20E
TYPICAL ELECTRICAL CHARACTERISTICS

12 12
TJ = 25°C VGS = 10 V VDS ≥ 10 V

10
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

9V 8V 25°C
100°C
8 8 TJ = – 55°C

7V 6

4 4
6V
2
5V

0 0
0 2 4 6 8 10 12 14 16 1 3 5 7 9
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

2.0 1.4
VGS = 10 V TJ = 25°C

1.6 TJ = 100°C

1.2
1.2
25°C

0.8 VGS = 10 V
1.0
– 55°C
0.4 15 V

0 0.8
0 2 4 6 8 10 12 0 2 4 6 8 10 12
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

2.0 1000
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
ID = 3.0 A

1.5
125°C
I DSS , LEAKAGE (nA)

100
(NORMALIZED)

1.0 100°C

10
0.5

0 1
– 50 – 25 0 25 50 75 100 125 150 –200 –160 –120 –80 –40 0
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTP6P20E
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal-
The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the
mined by how fast the FET input capacitance can be charged on–state when calculating td(off).
by current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com-
ing rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is
used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a
current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current.
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
t = Q/IG(AV) tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as
resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may
driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate resis-
tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is
where affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit
RG = the gate drive resistance used to obtain the data is constructed to minimize common
and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
td(on) = RG Ciss In [VGG/(VGG – VGSP)] switching losses.
td(off) = RG Ciss In (VGG/VGSP)

2000
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1600
C, CAPACITANCE (pF)

1200
Crss

800
Ciss

400
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTP6P20E
12 160 1000

VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
QT VDD = 100 V
ID = 6.0 A
10 VGS = 10 V
VGS 120 TJ = 25°C
8 Q1 Q2 100

t, TIME (ns)
6 80 tr
td(off)
10 tf td(on)
4
ID = 6.0 A
TJ = 25°C 40
2
Q3
VDS
0 0 1
0 5 10 15 20 25 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

6
VGS = 0 V
TJ = 25°C
5
I S , SOURCE CURRENT (AMPS)

0
0.5 1.0 1.5 2.0 2.5 3.0
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases non–linearly with an in-
thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance–General
temperature.
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 µs. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 12). Maximum energy at cur-
A Power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTP6P20E
SAFE OPERATING AREA

100 180
ID = 6.0 A
VGS = 20 V

EAS, SINGLE PULSE DRAIN–TO–SOURCE

SINGLE PULSE
I D , DRAIN CURRENT (AMPS)

TC = 25°C 144

AVALANCHE ENERGY (mJ)

10
100 µs
108
1 ms
1.0
10 ms
dc 72

0.1 RDS(on) LIMIT 36

THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
0.1 0.05 P(pk)
RθJC(t) = r(t) RθJC
0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
t2 TJ(pk) – TC = P(pk) RθJC(t)
SINGLE PULSE
DUTY CYCLE, D = t1/t2

0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t,TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTP6P20E
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
STYLE 5: B 0.380 0.405 9.66 10.28
1 2 3 U PIN 1. GATE C 0.160 0.190 4.07 4.82
H 2. DRAIN D 0.025 0.035 0.64 0.88
3. SOURCE F 0.142 0.147 3.61 3.73
K 4. DRAIN G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04
CASE 221A–06
ISSUE Y

Motorola TMOS Power MOSFET Transistor Device Data 7

MTP6P20E

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*MTP6P20E/D*
8 ◊ Motorola TMOS Power MOSFET Transistor Device Data
MTP6P20E/D