Design of Ultra High-Speed CMOS CML buffers and

Latches
Payam Heydari, Ravi Mohavavelu
Department of Electrical and Computer Engineering
University of California
Irvine, CA 92697-2625
E-mail: [email protected], [email protected]
Abstract - A comprehensive study of ultra high-speed current- Fig. 1. (a) A neutralized CMOS differential pair. (b) Transfer char-
mode logic (CML) buffers and regenerative CML latches will acteristics.
be illustrated. A new design procedure to systematically design
a chain of tapered CML buffers is proposed. Next, a new From Fig. 1. (a) one can see that the maximum output differen-
20GHz regenerative latch circuit will be introduced. Experi- tial voltage swing, Vodm , is only a function of the drain resistor and
mental results show a higher performance for the new latch the tail current, provided that the current switching takes place.
architecture compared to a conventional CML latch circuit at Clearly, the maximum output swing of a CML buffer is less than
ultra high-frequencies. It is also shown, both through the that of a CMOS inverter, which makes this class of buffers an
experiments and by using efficient analytical models, why ideal choice for low-power integrated circuit design.
CML buffers are better than CMOS inverters in high-speed The minimum value of the input common-mode level,
low-voltage applications. Vin ,CMmi n is achieved when the tail current begins to operate in satu-
ration. The input common-mode level reaches its maximum value,
1. INTRODUCTION Vin, CM max when the transistors MN1 and MN2 are either at pinch-off
High-speed Buffers and latches are the circuit cores of many or at cutoff [5].
high-speed blocks within a communication transceiver and a serial I SS
link. Front-end tapered buffer chain, serial-to-parallel converters, VGS, 12 + ( VGS3 + VTHN ) ≤ Vin,C M ≤ min VDD – RD ----- - + VTHN , VDD
2
clock and data recovery (CDR), multiplexers, and demultiplexers (1)
all use high-speed buffers and latches with a robust performance
in the presence of noise [1] [2]. where VGS12 is the common-mode overdrive voltage of transistors
CMOS current-mode logic buffers were first introduced in [3] MN1 and MN2. Similarly, the output common-mode level varies
to implement a giga-hertz MOS adaptive pipeline technique. the from VDD (when both MN1 and MN2 are off, and MN3 is in the lin-
CML circuits can operate with lower signal voltage and higher ear region) to VDD – RD I SS ⁄ 2 (when all transistors are in satura-
operating frequency at lower supply voltage than CMOS circuits tion). The voltage transition of the output common-mode level
can. However, CML buffers suffer from dissipating more static from VDD to VDD – R D I SS ⁄ 2 is determined by the subthreshold cur-
power than CMOS inverters. Recently, there have been efforts to rent of MN1 or MN2.
alleviate this shortcoming [4]. Due to their superior performance, To achieve the best performance in a CML buffer, a complete
CML buffers are the best choice for high-speed applications. As a current switching must take place, and the current produced by the
consequence, it is an essential need to have a systematic approach tail current needs to flow through the ON branch only. In a tapered
to optimally design CML buffers and CML buffer chains. buffer chain a CML buffer drives another buffer, which means that
This paper presents a the systematic procedure of CML buffer output terminals of the driving buffer stage are connected to the
design and introduces a new CMOS CML latch circuit. The paper input terminals of the driven stage, as shown in Fig. 2. To satisfy
is organized as follows. First, in section 2, the large-signal behav- the above performance requirement, the differential voltage swing
ior of a differential circuit is extensively illustrated. This will pre- of the first CML buffer must exceed
pare us to study the design of CMOS buffer chain. In section 3 we ∆Vin2, max = 2ISS2 ⁄ ( µn Cox ( W ⁄ L ) 2 ) of the following stage, or:
illustrate a new 0.18µm CMOS CML latch that is capable of
working at 20GHz. Finally, section 4, provides the experimental W
results that verify the accuracy of our design approach. R D1 I SS1 ≥ 2ISS2 ⁄  µ n Cox -----   (2)
L 2
VDD VDD
3. TAPPERED CML BUFFER DESIGN
A current-mode logic (CML) buffer is based on the differential RD1 RD1 RD2 RD2
architecture. Fig. 1. (a) shows a basic differential architecture. The Vout11
tail current, ISS, provides an input-independent biasing for the cir- CD1 CD1 Vout21 CD2 CD2 Vout22
Vout12
cuit. The differential circuit is easily neutralized using a pair of
capacitors (Fig. 1.(a)), CD , that will diminish the deleterious MN11 MN12
Vin21
MN21 MN22
effects of input-output coupling through the device overlap capac- Vin11 Vs1 Vin12
Vin22 Vs2
itance, CGD .
MN23 ISS2
As the differential input varies from – ∞ to + ∞, each output
MN13 ISS1
VBIAS VBIAS

node of the differential pair varies from VDD – RD ISS to V DD. Fig. 1
(b) shows the voltage variations of the output nodes in terms of the Fig. 2. Two CML buffers in cascade
differential input [5]. Furthermore, the load resistors should be small in order to
VDD
reduce the RC delay and increase the bandwidth. To guarantee a
high-speed operation, NMOS transistors of the differential pair
RD RD VDD
CD
Vout1 Vout2 must operate only in the saturation. To satisfy this requirement for
CD Vout2
Vout1
the circuit shown in Fig. 1, first, the input common-mode voltage
CL
RD ISS must be within the interval specified in Eq. (1); and secondly,
CL MN2 VDD - RDISS
Vink , max – VTHN ≤ Vout, kj ≤ VDD for k = 1, 2 and j = 1, 2 (2)
MN1
Vin1 Vin2

VBIAS
MN3 ISS
Vin1 - Vin2 which sets a maximum allowable level for the differential out-
put swing as follows:
 RDk ISSk ≤ VTHN for k = 1, 2 (3) The drain resistor, RDN , of the last output CML buffer is deter-
mined by the series impedance matching to bondwire’s characteris-
In addition, a high-speed CML output driver must drive a large tic impedance. Subsequently, ISSN of the last driver stage is
off-chip load through the bondwire and package trace. The output calculated using the output differential voltage swing and RD . The
driver must thus have a large current drive capability. This means
that NMOS transistors of the second CML buffer in Fig. 2 must be only remaining parameter in the last CML driver left is the (W/L) of
large. A large transistor has a large gate-to-channel capacitance that the source-coupled transistor pair, which is obtained from the com-
seriously degrades the propagation delay and the voltage swing of mon-mode characteristic of the last CML buffer. If the common-
the preceding predriver stage. To reduce the propagation delay of mode input voltage lies in the allowable range given by Eq. (1),
the predriver, a chain of tapered buffers is introduced between the then the tail current is equally divided between the two branches of
first predriver stage and the second buffer. The minimum delay is the differential stage, i.e.,
obtained by dividing the delay equally over all stages. This is W- 
achieved by gradually scaling up all stages with a constant taper ( Vin , CM – Vsk – VTHN ≥ Vin , CM – VBIAS –2VTHN ) = ISSk ⁄  µ n Cox ----
L

k k k
factor, u. On the other hand, the chip package interface at very high
frequencies is appropriately modeled as a transmission line that is for k = 1, 2, ..., N (5)
terminated by a load impedance, which is a series RC circuit (cf.
Fig. 3). The series load resistance, Z0, provides the high-frequency where Vin k , C M is the common-mode input voltage of the kth driver
parallel matched termination to the bondwire. Fig. 3 shows the in the buffer chain. Vin k, C M is specified by the output common-
schematic of the output CML driver driven by N-1 tapered CML mode voltage of the previous stage. Given a tapered buffer chain
buffers along with the chip-package interface being modeled as the with a constant differential voltage swing, the maximum (W/L) of
transmission line. the transistor pair of the kth CML buffer is then calculated by solv-
ing Eq. (6):
VDD
ISS
VDD – RD ----- - – VBIAS – 2VTHN = ISS k ⁄  µ n Cox W -----   (6)
RDN RDN 2   L k 
Z0
In the above equation RD I SS is the constant differential output
CDN CDN
swing of a tapered CML buffer chain.
Z0 CL CL As mentioned above, in a chain of tapered CML buffers, the
MNN1 MNN2
... Z0 Z0
minimum delay is obtained by dividing the delay equally over all
stages. However, the question is how many buffer stages are
1 u uN-1 VBIAS
MNN3 ISSN required to achieve the optimum delay. To answer this question, the
propagation delay of an arbitrarily chosen CML stage in a buffer
chain is first derived. Fig. 4 shows the kth stage in a chain of N
Fig. 3. An output CML buffer driving off-chip loads. The chip- tapered stages driving another CML stage along with the capacitors
package interface is electrically modeled using a lossless transmis- that contribute to the delay calculation.
sion line.
The common node sk+1 shown in Fig. 4 undergoes a smaller
The chip bondwires exhibit high-Q inductances. Therefore it is variation compared to the voltage variations of the input terminals
safe to model the chip-package interface using a lossless transmis- particularly in a matched differential pair. In fact, it is easily shown
sion line. To avoid potentially disastrous transmission line effects that for a maximum differential input variation of ∆Vin, max, the max-
such as slow ringing and propagation delays, the bondwires are ter- imum variation of the common node is ∆Vin, max ⁄ 2 . Therefore, the
minated both at the source using a series termination (RDN = Z0), equivalent capacitance seen at the common node sk+1 is approxi-
and at the destination using a parallel termination (Z0). Given a
well-defined output voltage swing (RD ISS) and with RD being deter- mately Cs, k + 1 = 2 CDBS, k + 1 rather than CDBS, k + 1.
mined by the matched termination, the tail current ISSN is easily cal- The 50% delay of the kth stage is as follows:
culated. For instance, an output differential voltage swing of 0.4V t d, k = 0.69RD, k (CDB, k s Cs, k + CGS, k + 1 s Cs, k + 1 ) (7)
for a 50Ω line driver requires a bias current of 8mA. Now, using a where s represents the series connection of electrical elements.
set of constraints, we present design guidelines to design a tapered The total propagation delay of the buffer chain is readily calculated:
CML buffer chain and determine appropriate values for the circuit
∑t
N
components of the CML buffer. 1⁄N
td = d, k = 0.69NRD1 (CDB1 s Cs1 + X CGS1 s Cs1 ) (8)
The propagation delay is computed using the open-circuit time k=1
constant method [6]. For instance, the delay of the simple low-volt- VDD VDD
age differential stage of Fig. 1 (a) is 0.69RD CL. Various HSPICE
simulations on high-speed CML buffers show that the delay RD,k+1
RD,k RD,k RD,k+1
obtained by the open-circuit time-constant method is within 8% of
the actual simulation.
Minimizing the overall propagation delay of CML buffer
increases the overall operation frequency of the buffer significantly. CD,k CD,k CD,k+1 CD,k+1
For a slowly varying input signal, increasing the small-signal volt-
age gain will further decrease the output transient variations and the CDB,k
Vin,k+1,1
output transition time. In a chain of tapered CML buffers, to attain a CDB,k
constant voltage swing, transistor sizes are scaled up while the Vin,k+1,2 CGS,k+1 CGS,k+1
drain resistances are scaled down with a constant scaling factor.
Vs,k+1
This will lead us to the fact that small-signal voltage gains of all
constituting stages of the buffer chain are identical. CDBS,k
VBIAS CDBS,k+1
W W W VBIAS
µn Cox -----  ISS1 RD1 = µn Cox -----  ISS2 RD2= … = µn Cox ----- ISS RD
 L 1  L 2 L
As a consequence, Eq. (5) provides us with a lower bound for the Fig. 4. The kth and (k+1)st stages of a tapered CML buffer along
maximum small-signal voltage gain at equilibrium, that is: with the parasitic capacitances
A W
= µn Cox ----- ISS RD  ≥ 2 (4) Interestingly, the functional dependence between delay and the
 v, eq L  number of stages (or taper factor) is similar to the one in a CMOS
buffer chain [7]. To be more specific, consider a chain of tapered latch in Fig. 6, that lead to a complete operation failure at very high-
CML buffers driving a lossless transmission line with a characteris- frequencies ( ≥ 10GHz ). The primary limitation is that a single tail
tic impedance of Z0. Suppose that the gate aspect-ratio of the tran- current is used for both tracking and latch circuits. Consequently,
sistor pair of the last CML line driver is X times larger than that of the bias operations of tracking and latch circuits are tightly related.
the first predriver stage. It is easily proved that if CDB1 = γ Cs1 and This will severely limit the allowable transistor sizes for a reliable
CGS1 = η Cs1 ; then it is easily proved that the optimum number of latch operation. At ultra high-frequencies ( ≥ 10GHz ) the parasitic
stages will be the numerical solution to the following equation: capacitances of transistors, MN1 and MN2, degrade the required
minimum gain for a proper tracking operation (Eq. (4)). Therefore,
γ⁄η 1 1 ⁄ N o pt
----------- +  ------------- X the tail current must be sufficiently high to achieve a wider range of
1 + γ  1 + η
1 ⁄ N opt linearity and a larger transconductance. On the other hand, the latch
X = exp ------------------------------------------------------ (9) circuit does not need a large bias current at ultra high-frequencies.
1  1 ⁄ Nop t
 ------------
- X To address the aforementioned problems, the regenerative CML
 1 + η
latch is modified so that the latch circuit and the tracking circuit use
or in the special case, if CDB1<<CGS1 then, Nopt = ln ( X ) which is two distinct tail currents. Fig. 7 shows the new CML latch circuit.
well-known result. VDD
To further increase the bandwidth (reduce the delay), the inter-
mediate stages use inductive peaking as demonstrated in Fig. 5. RD1 RD1
RD2 RD2
VDD VDD VDD
Vout
RDi RDi
RD1 RD1 RDN RDN MN3 MN4
MN1 MN2 VREF
Vin
Vout11 ..... LD,i-1 LD,i-1

CD1 CD1 V CD2

..... Vout,N1 CDN CDN Vout,N2 MNN5 MNN6 MNN7 MNN8
out12
..... CD2
..... VCLK VCLK
Vin,N1
MN12 MNN1 MNN2 ISS1 ISS2
MN11 MNi1 MNi2
Vin11 Vs1 Vin12 Vin,i1 Vin,i2 VsN
Vsi Vin,N2

MNN3 ISSN
VBIAS
MN13 ISS1
VBIAS
MNi3 ISSi VBIAS Fig. 7. The circuit schematic of the new CMOS CML latch circuit.
As observed in Fig. 7, the tracking stage and the latch stage are now
Fig. 5. Multiple stage CML buffers along with the inductive peak- separately optimized for a correct latch operation at ultra high-fre-
ing quencies. Note that it is important the source coupled pair transis-
The addition of the inductor in series with the drain resistor tors have high gain. This is obviously achieved with larger W ⁄ L
delays the current flow through the branch containing the resistor, for each transistor of the cross-coupled pair. However, this tech-
making more current available for charging the device capacitors, nique greatly limits the driving capability. Therefore the CML latch
and reducing the rise and fall times. From another perspective, the is followed by a CML buffer to recover the logic level.
addition of an inductance in series with the load capacitance intro- 4. EXPERIMENTAL RESULTS
duces a zero in the transfer function of the CML stage which helps
offset the roll-off due to parasitic capacitances. Inductive peaking In this section the performance of the CML buffer is evaluated
can increase the bandwidth to about 1.72 times larger than the by performing experiments on single stage as well as multiple
unpeaked case [6]. Inductance values are scaled with the same taper stages of the buffer. Experiments are set up to show the perfor-
factor as the drain resistors are. mance of the new CML latch depicted in Fig. 7 at 20GHz data-rate.
First, the accuracy of Eq. (9) is verified by running HSPICE simula-
3. ULTRA HIGH-SPEED LATCH DESIGN tion on a chain of CML buffers. Then, the performance of the cir-
A current-mode logic (CML) latch consists of an input tracking cuit in Fig. 7 is compared with the conventional CML latch shown
stage, MN1 and MN2, utilized to sense and track the data variation in Fig. 6.
and a cross-coupled regenerative pair, MN3 and MN4, being
employed to store the data. Fig. 6 demonstrates a CMOS CML latch 4.1. Tapered CML buffer experiment
circuitry. Similar to a CMOS tapered buffer, a single CML buffer might
VDD not be sufficient to drive an off-chip load. There are, however, more
RD RD
design trade-offs involved in the design of a CML tapered buffer
than in a CMOS tapered buffer. A superior high-frequency perfor-
mance in a CML buffer is guaranteed only if the design guidelines
Vout
explained thoroughly in Section 2 to be taken into consideration.
Vin
MN1 MN2 MN3 MN4 Fig. 8 plots propagation delay as a function of number of CML
stages for different values of X, where X is the ratio between the
MNN5 MNN6 off-chip load impedance and the load impedance of the first pre-
VCLK VCLK
driver stage. In practice, X is between 30-100.
MNN7 I −10
VBIAS SS x 10
2.5
X = 80
Fig. 6. the circuit schematic of a CMOS CML buffer. X = 50
2
Propagation Delay (sec)

The track and latch modes are determined by the clock signal X = 30
inputs to a second differential pair, MN5 and M N6. When the signal 1.5 X = 20
VCLK is "HIGH", the tail current ISS entirely flows to the tracking X = 10
circuit, MN5 and M N6 , thereby allowing Vout to track Vin. In the 1
latch-mode, the signal VCLK goes low, the tracking stage is dis-
abled, whereas the latch pair is enabled storing the logic state at the
output. 0.5

Like CML buffers, a CML latch operates with relatively small

voltage swings which is 4VTHN peak-to-peak differential-mode. Fig. 0
1 2 3 4 5 6
6 allows us to implement high-speed latch circuit. However, there Number of Stages (N)
are several shortcomings involved in the design of the regenerative Fig. 8. Delay vs. number of stages for CML tapered buffer chain.
 The delay variation in terms of the number of stages for CML
tapered buffer and CMOS tapered buffer are almost identical. How-
ever, the total propagation delay of a CML buffer chain for a given
value of X is less than that of CMOS buffer chain, which is in
accordance with what is expected. Remember that 50% propagation
delay of a CMOS inverter is inversely proportional to NMOS and
PMOS transconductance parameters and directly proportional to
the load capacitance [1]. According to (8), the propagation delay of
a CML buffer is directly proportional to the load capacitance (simi-
lar to a CMOS inverter) and the drain resistance. A larger threshold
voltage and a lower drift velocity associated with a PMOS transis-
tor cause the propagation delay of a CMOS inverter to be larger
than that of a CML buffer that uses the same transistor size.

4.2. Inductive peaking

The inductive peaking was proposed as an efficient and simple
circuit technique to speed up the buffer’s response. Figures 9 (a)
and (b) demonstrate the differential output voltage of a CML buffer
without and with the inductive peaking, respectively. The induc-
tance value is 4nH and signals are running at 5GHz. The output
voltages of CML buffer in the presence of inductance will have
larger amplitude and as a result faster rise and fall times. Fig. 10. The 20GHz conventional CML latch. (a) The input data at
20GHz. (b) The half-rate clock at 10GHz
4.3. CML Latch
The proposed CML latch circuit in Fig. 7 has a superior perfor-
mance compared to the one shown in Fig. 6 at ultra high-frequen-
cies ( ≥ 10GHz ) for the input data-rate. Figures 10 and 11
demonstrate outputs of the latch circuits at 20GHz data-rate. The
conventional CML latch fails to operate as a latch at this frequency,
whereas the new CML latch is capable of working as a latch at this
frequency.

6. CONCLUSIONS
In this paper we investigated important problems involved in the
design of a CML buffers and latches. A new design procedure to
systematically design a chain of tapered CML buffers was pro-
posed. We proved that the differential architecture of a CML buffer
makes it functionally robust in the presence of environmental noise
sources (e.g., crosstalk, power/ground noise). A new 20GHz regen-
erative latch circuit will be introduced. Experimental results show a
higher performance for the new latch architecture compared to
other existing latch circuits. It was also shown, both through the
experiments and by using efficient analytical models, why CML
buffers are better than CMOS inverters in high-speed low-voltage
applications. Without Inductive Peaking

Fig. 11. The 20GHz new CML latch. (a) The input data at 20GHz.
1.5 (b) The half-rate clock at 10GHz
Voltage

1
REFERENCES
[1] J. Rabaey, Digital Integrated Circuits: A Design Perspective,
Prentice-Hall, 1996.
0 500p 1n [2] B. Razavi, "Prospects of CMOS Technology for High-Speed Opti-
Time (lin) (TIME) cal Communication Circuits," IEEE J. Solid-State Circuits, vol.
With Inductive Peaking 37, No. 9, pp. 1135-1145, Sept. 2002.
[3] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K.
Okabe, A. Ono, H. Yamada, "A GHz MOS adaptive pipeline tech-
1.5 nique using MOS current-mode logic," IEEE J. Solid-State Cir-
cuits, vol. 31, No. 6, pp. 784-791, June 1996.
Voltage

[4] M. H. Anis, M. I. Elmasry, "Self-timed MOS current mode logic for

1 digital applications," IEEE Int’l Symp. on Circuits and Systems,
vol. 5, pp. 113-116, May 2002.
[5] B. Razavi, Design of Analog CMOS Integrated Circuits, pp. 101-
134, McGraw-Hill, 2001.
0 500p 1n
[6] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Cir-
Time (lin) (TIME) cuits, Cambridge University Press, 1998.
[7] N. Hedenstierna, K. O. Jeppson, “CMOS Circuit Speed and Buffer
Fig. 9. (a) Input and output waveforms of a CML buffer without Optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-6,
inductive peaking. (b) Input and output waveforms of a CML buffer No. 2, pp. 270-281, March 1987.
with inductive peaking