EE382M

VLSI-II
Early Design Planning:
Basic Timing Analysis & Timing Closure

SPRING 2011

Matthew Amatangelo
Mark McDermott

1/17/2011 EE382M-8 Class Notes

 Agenda: Early Design Planning for Timing Closure

 Basics of Timing
 EDP-TC What is It?
 EDP-TC Goals & Objectives
 EDP-TC Starting Point Data Requirements
 EDP-TC Methodology How-To
– Methodology Overview
– Block Size Estimation (another lecture)
– Block Timing Assertions Generation
– Delay Estimation
 EDP-TC End Products
 Specifics for the Class Project: EDP-TC Floorplanning for Design
Space Exploration & Timing Closure

1/17/2011 EE382M-8 Class Notes 2

 Acronyms

 TA - Timing Analysis
 STA - Static Timing Analysis
 DCL - Delay Calculator Language
 AT - Arrival Time
 PT - Passthrough
 RAT - Required Arrival Time
 LCB - Local Clock Buffer
 EDP - Early Design Planning
 EDP-TC - Timing Closure for EDP

1/17/2011 EE382M-8 Class Notes 3

 Basics of Timing: AT, RAT, Cycle time

Module Required Internal Arrival Module

Input Pin Arrival Time Flop-2-Flop Time (AT) Output Pin

(RAT)

COMB COMB
COMB

DFF DFF

CLK CLK

RAT = clock capture time

Period = Clk2Q delay + AT = Clk2Q delay + comb delay
- wire delay - comb delay
comb delay + setup time + wire delay
- setup time

Module X

1/17/2011 EE382M-8 Class Notes 4

 Basics of Timing: Pin-2-Pin (Pass-through)

Simple
Module Feed Module
Input Pin Input Path Output Path Output Pin
Delay Through Delay

Wire Combinational Wire

Logic (CL)
Delay

Delay through Pass-Through Block = input path delay + CL delay + output path delay

Module Z

1/17/2011 EE382M-8 Class Notes 5

Example

We will walk through the below code to show how to calculate

passthroughs, RATs and ATs.
input du_stall;
input icpu_ack_i;
input icpu_err_i;
input flushpipe;
output genpc_freeze;

reg flushpipe_r;

assign genpc_freeze = du_stall | flushpipe_r;

always @ (posedge clk or posedge rst)

if (rst)
flushpipe_r <= 1’b0;
else if (icpu_ack_i | icpu_err_i)
flushpipe_r <= flushpipe;
else if (!flushpipe)
flushpipe_r <= 1’b0;

EE382M-8 Class Notes

 Example – Arrival Time

Computing Arrival Times

rst

CLK

flushpipe_r is launched by a flop. Clock2Q delay is 134.7ps

flushpipe_r goes through a NOR2 and INV for a delay of 72.28ps
Total Arrival Time is C2Q + Logic Delay + Wire Delay = 134.7 + 72.28 + WD
AT for genpc_freeze is 206.98ps (ignoring wire delay)

1/17/2011 EE382M-8 Class Notes 7

 Example – Required Arrival Time

Computing Required Arrival Times

rst

CL
K

RAT for icpu_err_i and icpu_ack_i includes delay through a NOR, Inv, Mux, as well as the
setup time to a flop
RAT for flushpipe includes 2 mux delays and the setup time (use the worst case here, since
flushpipe has 2 paths to the flop).
Since this path is receiving, assume the gates are minimum sizes.
Since we won’t have the nice fanout of 3 working for us in this case, it’s time for some
Logical Effort fun! (Also applies to Arrival Time calculations.)

1/17/2011 EE382M-8 Class Notes 8

 Example – Required Arrival Time

Computing Required Arrival Times

rst
Cell Cin G P
NOR2 5 9 37
CL INV 3 9 21
K
MUX2 6 8 32

The g and p values for the NOR, MUX, and Inv are listed in the table to the right.
To use, multiply ‘g’ by ‘h’, which is the Cout/Cin value, and add ‘p’
The NOR has h=3/5 (inv/nor), so its formula is 9*3/5+37 = 42.4ps (note that it’s larger than
the FO3 value in the spreadsheet -> this shows that logical effort is not quite accurate…)
The inv is driving a minimum mux, so its h is 6/3 (mux/inv). Delay = 9*2+21 = 39ps
The mux is driving a flop (assume cin=6), so its h is 6/6. Delay = 8*1+32 = 40ps

1/17/2011 EE382M-8 Class Notes 9

 Example – Required Arrival Time

Computing Required Arrival Times

rst

CL
K

We now have everything we need to compute the RATs for the three inputs. Remember that for
a RAT, you subtract the delay from the usable clock period!
For icpu_err_i, the RAT is Clock Period - NOR - INV - MUX - Setup = 900 - 42.4 - 39 - 40 - 100 =
678.6ps
icpu_ack_i sees the same path, so it’s RAT is also 678.6 ps
flushpipe sees Clock Period - MUX - MUX - Setup = 900 - 40 - 40 - 100 = 720ps
NOTE that again, these do not include any wire delay!!!

1/17/2011 EE382M-8 Class Notes 10

 Example – Internal F2F Path

Computing Internal Flop-to-Flop Times

rst

CL
K

You need to verify that all internal paths meet timing as well.
In this case you would make sure that the C2Q + Mux Delay + Mux Delay + Setup
time is less than the clock period (900ps)
Delay = 134.7 + 40 + 40 + 100 = 314.7 ps < 900 ps -> In this case we meet timing

1/17/2011 EE382M-8 Class Notes 11

ATRAT file for previous example
 The ATRAT file should look like the following for the previous
example:

– BLOCK_NAME or1200_freeze
– START_RAT_SECTION
– PIN icpu_ack_i CLK rise 678.6
– PIN icpu_err_i CLK rise 678.6
– PIN flushpipe CLK rise 720
– START_AT_SECTION
– PIN genpc_freeze CLK rise 206.98
– START_PASS_THROUGH_SECTION
– PASS_THROUGH du_stall genpc_freeze 72.28

EE382M-8 Class Notes

General Guidelines

 Need to have a RAT or PASSTHROUGH for all input pins (you may have both
and you may have multiple RATS or PASSTHROUGHs)

 Need to have an AT or PASSTHROUGH for all output pins (again, you may have
both and also multiple ATs or PASSTHROUGHs)

 All assign statements are combinational in nature, so they are PASSTHROUGHs

unless all the variables are state variables

 All always @ (posegde CLK … ) blocks are sequential and provide conditions for
setting a state variable. If they receive an input pin there will be a RAT. If they
drive an output pin, there will be an AT

 Any always @ block that does not have CLK involved is again combinational. It
would synthesize into a latch, but this is wrong. It is combinational and will
have a PASSTRHROUGH unless all elements are state variables
EE382M-8 Class Notes
 EDP-TC What Is It?

 The process to identify and close on chip area and timing

objectives and constraints during the micro-architectural design
phase.

 Rapid Design space exploration during micro-architectural phase

– Drive changes to the micro-architecture to enable achieving area and timing
goals.
– Enabling Rapid Convergence on Area & timing closure during design
implementation phase.

1/17/2011 EE382M-8 Class Notes 14

 EDP-TC Goals & Objectives

 End result is a micro-architectural starting point that is known in

advance to have an implementation that can meet the program
goals for not just area but also timing
 Get designers thinking about physical implementation required
to meet the various timing objectives while still in the micro-
architectural design phase
 Give designers a methodology & process for:
– rapidly evaluating the micro-architectural and timing effects of chip physical
design decisions (rapid design space exploration).
– chip floor planning targeted at closing not just area but also all key timing
requirements.

1/17/2011 EE382M-8 Class Notes 15

 Nature of EDP-TC

 Simplified analysis compared to implementation phase

– Using 1 PVT* late mode timing point
• Assume monotonic switching per gate (no MIS)
• Some pessimism built into uncertainty
– Parasitic’s are estimated and based on placement
• During implementation phase the goal will be to use extracted parasitics
– Wires between blocks assume some max edge rate
• i.e., virtual repeaters, time of flight wire delay calculations
– Transparency is not modelled
– All arrival and required times are absolute (class project)
• All launch/capture pairs assumed synchronous
• Analysis performed without LCBs

* Process/Voltage/Temperature

1/17/2011 EE382M-8 Class Notes 16

 EDP-TC Starting Point Data Requirements

 Initial chip size, form factor and I/O requirements.

 Initial chip timing goals.
 Initial top level floorplannable block list & functionality.
 Initial chip & top level floorplannable block connectivity.
 For each floorplannable block
– initial sizes
– initial form factors
– initial pin positions
– initial timing assertions
 These initial starting points normally evolve during the EDP-TC
process.

1/17/2011 EE382M-8 Class Notes 17

 EDP-TC Methodology How-To

 Methodology Overview
 Block Size Estimation (another lecture)
 Block Timing Assertions Generation
– How do you get the numbers
 Delay Estimation

1/17/2011 EE382M-8 Class Notes 18

 Methodology Overview (Big Picture)

 Determine chip I/O definition from architectural specification

– I/O placement (next levels of packaging & system considerations)
 Determine initial cut at top level floorplannable blocks from
architectural and/or functional descriptions and specifications.
 Generate first pass top level netlist specifying interconnection of
top level floorplanable blocks and chip I/O’s
 Estimate initial top level floor-planable block sizes
– Analyze the block’s component parts
• Use prior implementations of similar functions as a starting point
• Perform first pass logic realization on some sub-blocks
 Estimate chip size
– Floorplan-able block area + wiring uplift (~25-30%)

1/17/2011 EE382M-8 Class Notes 19

 Methodology Overview (Big Picture - cont)

 Produce chip floorplans

– determine initial form factors
• block attributes (memory cell)
• connectivity (bus widths)
• Wire-ability
 Iterate on floorplan to close area & timing constraints
– Given initial floorplan, estimate timing of top level critical timing paths
based on top level connectivity, block placement, and pin placements
– Modify block form factor, placement, pin placement and
architectural/functional description if required to improve timing and or
area.
• Changes to architectural specifications will yield updates to the number of blocks,
their sizes and /or form factors, and the netlist (connectivity) of the top level
blocks.
 Done when you have an architectural specification and a
floorplan that achieves area and timing goals.

1/17/2011 EE382M-8 Class Notes 20

 Block Timing Assertions Generation

 Block Timing Assertions - What Are They?

 Usage of Block Timing Assertions in EDP-TC.
 Clock Cycle Adjusts in Slack Calculations.
 Estimating Delays for Initial Floorplans.
 How Timing Contracts (Block Assertions) Are used in the
Implementation Phase of the Design.

1/17/2011 EE382M-8 Class Notes 21

 Block Timing Assertions --- What Are They?

 Basic Block Timing Model

– Depicts timing information about paths in a particular block
• 3 types of paths modeled in a block
– capture: block input to register
– launch: register to block output
– purely combinatorial: delay from block input to output

 Basic Block Assertions

– Input Pin Required Arrival Times (RAT)
• For each input pin on a block
– latest time a signal can arrive at that pin and still get successfully captured in the register
inside the block fed by that pin.
 Calculated by: RAT = {AT(clock @ register)} - {Internal logic & wire delay between pin
and register} - {register setup requirement}
– combinatorial: RAT = Need to analyze entire path from register launch to register capture,
along with combinatorial delay for the portion of the path inside this block.

1/17/2011 EE382M-8 Class Notes 22

 Block Timing Assertions --- What Are They? (con’t.)

 Basic Block Assertions (con’t.).

– Output Pin Arrival Times: (AT)
• For each input pin on a block
– latest time that a signal launched from a register inside the block that feeds the pin arrives
at the pin.
 Calculated by: AT = {AT(clock@register)} + {Internal logic & wire delay between register
and pin} + {register launch delay}
– combinatorial: AT = same problem as combinatorial RAT described on preceding page.

– Block assertions determined by block alone except for purely combinatorial

paths
• Preferable to eliminate if possible both wire feed-throughs & purely combinatorial
paths from all top level blocks.
– Want assertions & block timing properties to be floorplan independent to enable rapid
iteration.

1/17/2011 EE382M-8 Class Notes 23

 Path Types Modelled in a Block

Output(s)

Internal logic & wire Internal logic bound Internal logic & wire
Input(s) delay from input pin by F2F timing delay from register
to register to output pin

COMB Dout
Din
Delay
Delay
RAT: determined DFF DFF
AT: determined
by CLK arrival
from CLK’ launch
RAT = AT(CLK) - Din - DFFsetup AT = AT(CLK’) + Dout +DFFc-q

CLK CLK’

Clock Skew =
CLK - CLK’

RAT: determined AT: determined by

by capture register Dinout launching register
block & global wire Delay
block & global wire
delay & Dinout delay & Dinout

Delay for wire and combinatorial logic

1/17/2011 EE382M-8 Class Notes 24

 Usage of Block Timing Assertions in EDP-TC
 Every pin of every block and the chip top level block has both an
AT and a RAT.
– Connectivity determines which are combined to determine the slack (timing
goodness) of a path.
 Calculate the slack for a path sourced from one block and sunk in
another.
– Avoid purely combinatorial paths and feedthroughs when possible
• Avoid these at the full chip level
– Slack calculation must consider phase of launching and capturing clocks in a
path
• all events derived from one cycle of the master clock (ignore multicycle paths for
now)
• no zero cycle setup paths exist
• A cycle adjustment is made to this calculation when the leading edge of the master
clock corresponds to the capture event of the path and the trailing edge
corresponds to the launching event.
 When all paths have slack >= 0 the block assertions constitute the
Timing Contracts for each block.
1/17/2011 EE382M-8 Class Notes 25
 Assertion Generation for Combinatorial Paths

AT: determined from CLK launch at

source block: AT’+Dwire1+Dinout

AT RAT AT RAT
Dwire1 Dinout Dwire2

DFF DFF

Module Z

CLK CLK’
Module X Module Y

RAT: determined from capturing

block: RAT’-Dwire2-Dinout

Clock Skew = CLK - CLK’

1/17/2011 EE382M-8 Class Notes 26

Usage of Block Timing Assertions

AT(X.pin)

Dout Din
Dwire
DFF DFF

CLK
CLK’
Module X Module Y

RAT(Y.pin)

Slack(path of X.CLK->Y.pin) = RAT(Y.pin) - { AT(X.pin) + Dwire } + Adjust

EE382M-8 Class Notes

 How Timing Contracts are Used

 Implementation phase starts at the end of EDP-TC.

 Given that EDP-TC closed chip timing at 0 slack, the Block

Assertions are the Timing Contracts.

 Each block during design is timed stand alone against these

contracts, or budgets. Affects synthesis (auto or manual).
– The RATs are now the assumed arrival times at the blocks inputs.
– The ATs are now the assumed required times at the blocks outputs.

 The contracts (assertions) are typically periodically updated from

full chip timing runs to reflect actual design changes.
– It’s important to continue to have a complete & consistent set of contracts
that, if achieved by each block, yields a chip which meets the timing
objective.
1/17/2011 EE382M-8 Class Notes 28
 e.g., Contracts applied to block level timing

AT(X.pin) RAT(Z.pin)

600 ps 100 ps
200 ps
DFF DFF

Dwire

CLK
CLK’
Module X Module Y

Module X Module Y
Level Level
Timing: RAT(X.pin) = 600 Timing: AT(Y.pin) = T-100

1/17/2011 EE382M-8 Class Notes 29

 Wire Delay Estimation

 Wire delay calculation & analysis overview.

 Elmore Delay
 Wire Delay Estimation Summary
– Time of Flight
– Elmore Delay
– Lumped RC product
– RC Ladders

1/17/2011 EE382M-8 Class Notes 30

Analyzing On-Chip Interconnect

 Simplified interconnect analysis.

– Time of Flight (EDP-TC)
• Simplest approach for EDP-TC.
– Given in picoseconds per millimeter
– Assume optimal signal regeneration (buffering satisfies max allowable slew)
• routing parasitic expressed as some delay per unit distance
• determined for the process technology with spice simulations
• assume certain levels of interconnect (parallel plate and fringing fields), coupling,
and buffering
– Lumped RC product
• Overly conservative for long wires.
– RC Ladders.
• Limiting Case, R * C * (Length^2 / 2).
– Elmore Delay Model.
• Typically much less conservative from RC Ladders.
• Effective estimates for Multi-Drop Nets.
 Save more complex analysis for implementation phase
– shielding, inductance, 3D fields, etc. (poles/residues, AWE, 3D field solvers,
…)
EE382M-8 Class Notes
Elmore RC Delay Calculation Model

 More realistic RC delay than lumped RC for long nets.

 Able to handle multi-drop nets.

 The formula can be written from inspection of the RC tree.

 Calculable in linear time.

 Provable upper bound on RC delay.

– Can still significantly overestimate RC delay in some cases.

EE382M-8 Class Notes

 Elmore RC Delay Calculation Model (con’t).

7 8

R7 R8

C7 C8

1 2 4 5 6
3

R1 R2 R3 R4 R5 R6
+
Vin - C1 C2 C3 C4 C5 C6

3 4 5 6
Td6 = R1C1 + (R1+R2)(C2+C7+C8) + (  Rn) (C3) + (
Rn (C4) + (Rn) (C5) + ( Rn ) (C6)
n=1 n=1 n=1 n=1

1/17/2011 EE382M-8 Class Notes 33

Wire Delay Estimation Summary

 Time of flight is simplest and probably best for initial floorplan

timing.
– Use delay per wire length that considers best estimate for technology,
routing layers, coupling, etc. as measured in early circuit analysis (spice)

 Use Elmore Delay on selected nets as more estimated routing

information becomes available
– Especially if the use of wide wires or upper level metal for low impedance
wiring is required to close timing

EE382M-8 Class Notes

EDP-TC End Products

 What comes out of the EDP-TC process

– Floorplan
– Block size & shape (discussed in another lecture)
– Pin positions
– Timing contracts (assertions)

EE382M-8 Class Notes

Specifics for the Class Project EDP-TC

 Starting point is Verilog description

– Embodies architectural specification
– Chip I/O boundary is given
– Top level floorplannable blocks and connectivity specified in Verilog
 Step 1 - Estimate Block Sizes & Shapes
 Step 2 - Determine Chip size & shape & initial I/O placement
based on step 1, the Verilog, and class input assumptions.
– In this class we are only concerned with chip size.
 Create initial placement based on size, shape & connectivity
 Create initial timing assertions for each block based on
functionality
 Iterate on chip floorplan, block placement, pin placement,
routing, engineering wires and block definition & assertions
utilizing information derived from the timing process.

EE382M-8 Class Notes

 Initial Floorplan Timing Activities for Class Project

constraints

Block owner Block owner

estimates block creates/updates
size and delivers Re-Floorplan
AT/RAT estimates
to integrator to assertion file

Floorplan file

Chip
Run Timing
Floorplan
Script

NO
Floorplan file
Slack >= 0?

YES
ATs/RATs == Contracts

1/17/2011 EE382M-8 Class Notes 37

Create Initial Timing Assertions

 Verilog describes block’s functional definition

 Cycle time: xxx ps
 I/O timing specification: Define it if one doesn’t exist
 Assume t = 0 at the node where clock is delivered to the blocks
sequential logic
– This is an EDP approach to avoid concern with estimating the delay through
the LCB (local clock buffer). Skew associated with LCBs will be handled by
timing tool.
 Estimate register launch delay and required setup time
 Assume 0ps of delay for clock skew, jitter and mistracking,
normally accounted for in timing analysis tool. Need to insert
explicitly if analysis is done “by hand”.

EE382M-8 Class Notes

Create Initial Timing Assertions (cont’d)

 Estimate block component implementation

– Derive propagation delays between INPUTS, OUTPUTS, and registers (prior
examples)
– Turn these delays into block ATs and RATs

 Note: Internal (reg-to-reg) paths must meet frequency targets. In

other words, these AT/RAT files assume internal paths of the
cluster meet frequency.
– Essentially representing clusters with blackbox model
• Internal paths hidden
• Models are inherently appropriate up to the max frequency of that designed (and
duty cycle, if half cycle paths used)
– Run at lower level of hierarchy to include internal paths

EE382M-8 Class Notes

Perform Timing Analysis

 Calculate RATs for block inputs, ATs for block outputs

– consider initial timing model including clock arrival
• establish block-consistent clock arrival at registers
 Iteration to zero slack
– can change:
• wire delay == floorplan and/or block pin positions (if process supports this)
• assertions
– launch time (block design)
– capture time (block design)
– arc delays

EE382M-8 Class Notes

Capture Results

 Floorplan
 Timing contracts
 Pin positions

EE382M-8 Class Notes

 How to run the in-class timer

Block pin names

and location (.v)
Netlist
Top level connectity (.v)

Wire metal

timer RESULTS

block
timing
model (atrat)

1/17/2011 EE382M-8 Class Notes 42

 Schematic

1/17/2011 EE382M-8 Class Notes 43

 Timer Files

 ATRAT files from block owners:

– define (1) signal arrival times, (2) required arrival times, or tests, and (3)
delays through circuit elements. Every element type in the design must
have an ATRAT file; in this case: b1.atrat, b2.atrat, b3.atrat, b4.atrat,
b5.atrat, b6.atrat, io.atrat
 Netlist file:
– delineates the element connectivity including pin type, location,
and wire type. The netlist file in this test case is ad.layout. For the top level
view of the class project this file is owned by the integration team.
 Output files:
– log - execution run log
– pathlog - details of paths encountered
– slackrpt - succinct slack-ordered path report

1/17/2011 EE382M-8 Class Notes 44

Input File Example: atrat file

output pins,
BLOCK_NAME b1 launching event and time from
START_AT_SECTION launch that signal arrives at pin
PIN t clk rise 400
START_RAT_SECTION
PIN y clk rise 900
START_PASS_THROUGH_SECTION
PASS_THROUGH x t 100

input pins,
capture event and time after (for now)
this event that the arrival is required

in-to-out arcs,
paths from input pins to output
pins with propagation delay

EE382M-8 Class Notes

Netlist Example: ad.layout
Pin name and location relative to block origin point
INSTANCE i_b1 b1 x y
PIN I x wi11 450 150 M4_10W_10S M3_10W_10S
PIN I y wi21 450 150 M4_10W_10S M3_10W_10S
PIN O t w12 450 150 M4_10W_10S M3_10W_10S
INSTANCE i_b2 b2 x y
PIN I x w12 950 150 M4_10W_10S M3_10W_10S
PIN O t w23 950 150 M4_10W_10S M3_10W_10S
INSTANCE i_b3 b3 x y
PIN I x w23 1200 0 M4_10W_10S M3_10W_10S
PIN O t w34 1500 300 M4_10W_10S M3_10W_10S
INSTANCE i_b4 b4 x y
PIN I x w34 1600 0 M4_10W_10S M3_10W_10S
PIN I y w64 1600 200 M4_10W_10S M3_10W_10S
PIN O t w4o1 1800 0 M4_10W_10S M3_10W_10S
PIN O u w4o2 1800 200 M4_10W_10S M3_10W_10S
INSTANCE i_b5 b5 x y
PIN I x w12 1000 1200 M4_10W_10S M3_10W_10S
PIN I y w4o2 1000 1200 M4_10W_10S M3_10W_10S
PIN O t w23 1000 1200 M4_10W_10S M3_10W_10S
INSTANCE i_b6 b6 x y
PIN O t w64 1200 1000 M4_10W_10S M3_10W_10S
INSTANCE i_b3a b3 x y
PIN I x w64 800 2200 M4_10W_10S M3_10W_10S
PIN O t wi21 800 2200 M4_10W_10S M3_10W_10S
INSTANCE i_io io x y
PIN I po1 w4o1 2400 0 M4_10W_10S M3_10W_10S
PIN I po2 w4o2 2400 400 M4_10W_10S M3_10W_10S
PIN O pi1 wi11 0 0 M4_10W_10S M3_10W_10S
PIN O pi2 wi21 0 400 M4_10W_10S M3_10W_10S

EE382M-8 Class Notes

Output

• Log messages:
•####WARNING: Net wi21 has multiple drivers

•ERROR: Cannot propagate beyond pin(i_b2:x) -> Missing RAT!

•###WARNING: Found a loop - breaking loop at i_b4:b4:u

Backtracking loop traversal

i_b3:b3:x <> i_b5:b5:t <> i_b5:b5:y <> i_b4:b4:u <> i_b4:b4:x <>
i_b3:b3:t <> i_b3:b3:x <> i_b5:b5:t <> i_b5:b5:y <> i_b4:b4:u

• Paths:
i_b6:t -> i_b4:y -> i_b4:u -> i_b5:y -> i_b5:t -> i_b3:x -> i_b3:t ->
i_b4:x -> i_b4:u -> i_io:po2 -816.629
i_b6:t -> i_b4:y -> i_b4:u -> i_b5:y -> i_b5:t -> i_b3:x -> i_b3:t -
> i_b4:x -> i_b4:t -> i_io:po1 -707.747
i_b6:t -> i_b4:y -> i_b4:u -> i_io:po2 -73.55
i_b6:t -> i_b3a:x -> i_b3a:t -> i_b1:y -66.1875
i_b1:t -> i_b5:x -> i_b5:t -> i_b3:x -> i_b3:t -> i_b4:x -> i_b4:u -
> i_io:po2 -64.3805
i_io:pi1 -> i_b1:x -> i_b1:t -> i_b5:x -> i_b5:t -> i_b3:x -> i_b3:t
-> i_b4:x -> i_b4:u -> i_io:po2 15.845

EE382M-8 Class Notes