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    Experiment-2: Ishaan Aggarwal

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    vishal sharma
    This document describes designing and implementing a 4-bit binary to gray code converter using dataflow modeling. It includes the VHDL code for the binary to gray code converter entity and architecture, as well as a VHDL testbench. The testbench applies all possible 4-bit binary inputs and verifies the output of the binary to gray code converter and subsequent gray code to binary converter match the original inputs.

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    Experiment-2: Ishaan Aggarwal

    Uploaded by

    vishal sharma
    83 views8 pages
    This document describes designing and implementing a 4-bit binary to gray code converter using dataflow modeling. It includes the VHDL code for the binary to gray code converter entity and architecture, as well as a VHDL testbench. The testbench applies all possible 4-bit binary inputs and verifies the output of the binary to gray code converter and subsequent gray code to binary converter match the original inputs.

    Original Description:

    Original Title

    EXP2_UE195063

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    This document describes designing and implementing a 4-bit binary to gray code converter using dataflow modeling. It includes the VHDL code for the binary to gray code converter entity and architecture, as well as a VHDL testbench. The testbench applies all possible 4-bit binary inputs and verifies the output of the binary to gray code converter and subsequent gray code to binary converter match the original inputs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    83 views8 pages

    Experiment-2: Ishaan Aggarwal

    Uploaded by

    vishal sharma
    This document describes designing and implementing a 4-bit binary to gray code converter using dataflow modeling. It includes the VHDL code for the binary to gray code converter entity and architecture, as well as a VHDL testbench. The testbench applies all possible 4-bit binary inputs and verifies the output of the binary to gray code converter and subsequent gray code to binary converter match the original inputs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    Experiment-2

    To design and implement a 4-bit Binary to Gray code converter using Dataflow Modeling.
    ─

    Ishaan Aggarwal
    UE195063
    ECE Sec-1
    1

    AIM:
    To design and implement a 4-bit Binary to Gray code converter using Dataflow
    Modeling.

    Code:
    2

    I. VHDL Code
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity bin2gray is
    port( bin : in std_logic_vector(3 downto 0); --binary input
    G : out std_logic_vector(3 downto 0) --gray code output
    );
    end bin2gray;

    architecture gate_level of bin2gray is

    begin

    --xor gates.
    G(3) <= bin(3);
    G(2) <= bin(3) xor bin(2);
    G(1) <= bin(2) xor bin(1);
    G(0) <= bin(1) xor bin(0);

    end;

    II. VHDL TestBench Code


    library IEEE;
    use IEEE.std_logic_1164.all;
    3

    entity testb is
    end testb;
    architecture behavior of testb is
    component bin2gray is
    port( bin : in std_logic_vector(3 downto 0);
    g : out std_logic_vector(3 downto 0)
    );
    end component;

    component gray2bin is
    port( g : in std_logic_vector(3 downto 0);
    bin : out std_logic_vector(3 downto 0)
    );
    end component;

    signal bin,g,bin_out : std_logic_vector(3 downto 0) := (others => '0');

    begin
    uut1: bin2gray port map (
    bin => bin,
    g => g
    );
    uut2: gray2bin port map (
    g => g,
    4

    bin => bin_out


    );

    stim_proc: process
    begin
    bin <= "0000"; wait for 15 ns;
    bin <= "0001"; wait for 15 ns;
    bin <= "0010"; wait for 15 ns;
    bin <= "0011"; wait for 15 ns;
    bin <= "0100"; wait for 15 ns;
    bin <= "0101"; wait for 15 ns;
    bin <= "0110"; wait for 15 ns;
    bin <= "0111"; wait for 15 ns;
    bin <= "1000"; wait for 15 ns;
    bin <= "1001"; wait for 15 ns;
    bin <= "1010"; wait for 15 ns;
    bin <= "1011"; wait for 15 ns;
    bin <= "1100"; wait for 15 ns;
    bin <= "1101"; wait for 15 ns;
    bin <= "1110"; wait for 15 ns;
    bin <= "1111"; wait for 15 ns;
    wait;
    end process;

    end;
    5

    EDA Playground:

    Logisim:

    Circuit Diagram:
    6

    Simulation Cases:
    7

    Observation Table(Results):

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