L D College of Engineering, Ahmedabad

Information Technology Department

Semester: 3rd (IT) Subject: DIGITAL ELECTRONICS (2131004)

ASSIGNMENT – 1

Q-1: State four basic Number Systems in Digital Electronics.

Q-2: Convert the following Binary Numbers to Decimal:

1) 1101101 2) 10.10001 3) 101110.0101 4) 1110101.110

Q-3: Convert the following Decimal Numbers to Binary:

1) 12.0625 2) 104 3) 128 4) 197.56

Q-4: Convert the following Decimal Numbers to Octal:

1) 3956 2) 420.6 3) 8476.47

4) 63718 5) 6.625 6) 13.3125

Q-5: Convert the following Octal Numbers to Decimal:

1) 2056 2) 2057.64 3) 6534.04

4) 567 5) 665 6) 77.55

Q-6: Convert the following Octal Numbers to HEX:

1) 256 2) 2035 3) 1762.46 4) 6054.263

Q-7: Convert the following Binary Numbers to Octal:

1) 110101.101010 2)10101111001.0111

Q-8: Convert the following HEX Number to Decimal:

1) 5C7 2) AB6 3)2EB7 4) AA1

5) AF9.B0D 6) A08F.EA 7) 8E47.AB 8) A0F9.0EB

Q-9: Convert the following Decimal Numbers to HEX:

1) 63718 2) 2047 3) 4796

4) 1248.56 5) 8957.75 6) 41209.0572

Q-10: Convert the following HEX Numbers to Octal:

1) 2AB 2) 42FD 3) 4F7.A8 4) BC70.0E

2) 1011011011 2) 01011111011.011111

Q-12: Convert the following HEX Numbers to Binary:

1) 4BAC 2) 3A9E.B0D

ASSIGNMENT – 2

Q-1: Explain the following terms:

1) Bit 2) Byte 3) Nibble 4) Word Length

Q-2: Obtain 9’s and 10’s complement of following Decimal Numbers:

1. 90090 4. 13579 7. 4526.075

2. 00000 5. 3465 8. 1056.074

3. 10000 6. 782.54 9. 99999

Q-3: Obtain 1’s and 2’s complement of following Binary Numbers:

1. 1010101 5. 10111.1

2. 0111000 6. 10011.00

3. 0000001 7. 01100.01

4. 0101010 8. 0.01111

Q-4: Perform Subtraction with following Decimal Numbers using 1) 9’s complement & 2) 10’s complement.
Check the answer by straight subtraction.

1. 5250 – 321 5. 274 - 86

2. 753 – 864 6. 93 - 615

3. 3570 – 2100 7. 574.6 – 279.7

4. 20 – 1000 8. 376.3 – 765.6

Q-5: Perform Subtraction with following Binary Numbers using 1) 1’s complement & 2) 2’s complement.
Check the answer by straight subtraction.

1. 11010 – 1101 5. 0.1001 – 0.0110

2. 10010 – 10011 6. 0.01111 – 0.01001

3. 11010 – 10000 7. 11011 - 10100

4. 100 – 110000 8. 11100 - 00100

1. 8620

2. 4499

3. 7890

Q-7: What is Weighted and Non Weighted Code? What is Self Complementary Code? Briefly describe with
their examples.

ASSIGNMENT – 3

Q-1: Simplify following Boolean Functions to a minimum number of literals:

1. xy + xy’

2. (x + y) (x + y’)

3. xyz + x’y + xyz’

4. zx + zx’y

5. (A + B)’ (A’ + B’)’

6. y(wz’ + wz) + xy

Q-2: Reduce following Boolean Expressions to the required no. of literals:

1. ABC + A’B’C + A’BC + ABC’ + A’B’C’ (TO 5 LITERALS)

2. BC + AC’ + AB + BCD (TO 4 LITERALS)

3. [(CD)’ + A]’ + A + CD + AB (TO 3 LITERALS)

4. (A + C + D) (A + C + D’) (A + C’ + D) (A + B’) (TO 4 LITERALS)

Q-3: Find the complement of following Boolean Functions using a) De Morgan’s Theorem & b) Duality.

1. (BC’ + A’D) (AB’ + CD’)

2. B’D + A’BC’ + ACD + A’BC

3. [(AB)’A] [(AB)’B]

4. AB’ + C’D’

Q-4: Obtain the truth table of the following function and implement it by using Logic Gates:

F = xy + xy’ + y’z

F = ABC + AB’C + AB’D + BD’

1. F(A,B,C,D) = D(A’ + B) + B’D

2. F(W,X,Y,Z) = Y’Z + WXY’ + WXZ’ + W’X’Z

3. F(A,B,C) = (A’ + B) (B’ + C)

4. F(X,Y,Z) = (XY + Z) (Y + XZ)

Q-6: Convert following to the other Canonical Form:

1. F(X,Y,Z) = ∑(1,3,7)

2. F(A,B,C,D) = ∑(0,2,6,11,13,14)

3. F(X,Y,Z) = π(0,3,6,7)

4. F(A,B,C,D) = π(0,1,2,3,4,6,12)

ASSIGNMENT – 4

Q-1: Obtain simplified expressions in Sum of Products for the following Boolean Functions:

1. F(X,Y,Z) = ∑(2,3,6,7)

2. F(A,B,C,D) = ∑(7,13,14,15)

3. F(A,B,C,D) = ∑(4,6,7,15)

4. F(W,X,Y,Z) = ∑(2,3,12,13,14,15)

Q-2: Obtain simplified expressions in Product of Sums for the following Boolean Functions:

1. F(X,Y,Z) = π(0,1,4,5)

2. F(A,B,C,D) = π(0,1,2,3,4,10,11)

3. F(W,X,Y,Z) = π(1,3,5,7,13,15)

Q-3: Obtain simplified expressions in Sum of Products for the following Boolean Functions:

1. ABD + A’C’D’ + A’B + A’CD’ + AB’D’

2. K’LM’ + K’M’N + KLM’N’ + LMN’

3. F(A,B,C,D,E) = ∑(0,1,4,5,16,17,21,25,29)

4. X’Z + W’XY’ + W(X’Y + XY’)

5. D(A’ + B) + B’(C + AD)

1. X’Z’ + Y’Z’ + YZ’ + XYZ

2. (A’ + B’ + D) (A’ + D’) (A + B + D’) (A + B’ + C +D)

3. W’YZ’ + VW’Z’ + VW’X + V’WZ + V’W’Y’Z’

Q-5: Simplify following Boolean Function using Don’t Care conditions, in 1) Sum of Products & 2) Product
of Sums:

1. F = A’B’D’ + A’CD + A’BC

D = A’BC’D + ACD + AB’D’

2. F= W’(X’Y + X’Y’ + XYZ) + X’Z’(Y + W)

D = W’X(Y’Z + YZ’) + WYZ

3. F = B’DE’ + A’BE + B’C’E’ + A’BC’D’

D = BDE’ + CD’E’

Q-6: Implement Boolean Function with NAND Gates.

1. (AB + A’B’) (CD’ + C’D)

Q-7: Implement Boolean Function with NOR Gates.

1. AB’CD’ + A’BCD’ + AB’C’D + A’BC’D

Q-8: Simplify following Boolean Functions by using Tabulation Method

1. F(A,B,C,D,E,F,G) = ∑(20,28,52,60)

2. F(W,X,Y,Z) = ∑(0,2,3,6,7,8,10,12,13)

ASSIGNMENT – 5

Q-1: Explain Half Adder with its logic diagram and truth table. Derive Boolean functions for Sum and Carry.

Q-2: Explain Half Subtractor with its logic diagram and truth table. Derive Boolean functions for Difference
and Borrow.

Q-3: Implement Full Subtractor with two Half Subtractors and an OR Gate.

Q-4: Show how Full Adder can be converted to a Full Subtractor with the addition of one inverter circuit.

Q-5: Design a combinational circuit that converts an Excess – 3 code to the BCD code.

Q-6: Design a combinational circuit that converts a 4- bit Binary code to BCD code . The binary number
ranges from 0 to 15.

Q-7: 4.15, 4.16, 4.21, 4.22, 4.26 (From Morris Mano Book)
 ASSIGNMENT – 6

Q-1: Explain 4 – bit binary parallel adder with logic diagram.

Q-2: Explain BCD Adder with its block diagram and Truth Table.

Q-3: Explain 4 – bit Magnitude comparator in detail. Also describe that whether 2 – bit Magnitude
comparator is possible or not. Derive equations for both.

Q-4: What is Decoder? Explain 3 to 8 line (Binary to Octal) Decoder.

Q-5: What is Encoder? Explain Octal to Binary Encoder.

Q-6: Explain Look Ahead Carry Generator.

Q-7: What is Multiplexer and Demultiplexer? Define in brief.

Q-8: Derive the logic Diagram and Truth Table of 4 to 1 line MUX and Quadruple 2 to 1 line MUX.

Q-9: Derive the logic Diagram and Truth Table of 2 to 4 line Decoder with Enable Input (Demultiplexer).

ASSIGNMENT – 7

Q-1: What are the differences between Combinational Logic Circuit and Sequential Logic Circuit? Explain
both with their block diagrams?

Q-2: What is Flip Flop? What are the types of flip flops? What is Latch?

Q-3: Explain RS Flip Flop and clocked RS Flip Flop with their Truth Tables.

Q-4: Explain D Flip Flop with their Truth Table and logic diagram.

Q-5: Explain JK Flip Flop with their Truth Table and logic diagram.

Q-6: Explain T Flip Flop with their Truth Table and logic diagram.

Q-7: Explain Master – Slave Flip Flop with their Truth Table and logic diagram.

Q-8: What is Edge Triggered Flip Flop? Explain with one example.

Q-9: What do you mean by Counter? Explain with Clock Input Timing Diagram. Also briefly mention types
of it.

Q-10: How will you design 3-bit binary Asynchronous and Synchronous counter with Clock Pulse
generation?

Q-11: Explain and draw the diagram of 4-bit binary Ripple Counter.

Q-12: Explain BCD Ripple Counter and draw the diagram of it using JK Flip flop.

Q-13: What do you mean by Synchronous Counter? Draw the diagram of it. Also explain binary Up-Down
Counter.
Q-14: What is Register? Why is it used? Explain 4-bit Register.

Q-15: Explain 4-bit Register with Parallel Load. Draw the diagram of it.

Q-16: What is Shift Register? Explain 4-bit Bidirectional Shift Register using diagrams.

Q-17: Explain 4-bit Universal Shift Register with diagram.

Q-18: 7.6, 7.7 (From Morris Mano Book)

ASSIGNMENT-8

Q-1: Write Short Notes on following Digital Logic Families:

1) RTL 2) DTL 3) TTL 4)ECL 5)CMOS 6)MOSFET

ASSIGNMENT-9

Q-1: Define State Machine. Explain the need of it.

Q-2: Define following:

1) State 2) State Table 3) Transition Table 4) State Diagram

5) Present State 6) Next State 7) Lock out Condition

8) Input Forming Logic 9) Output Forming Logic 10) Self Starting Counter

11) Critical Races 12) Noncritical Races 13) Cycles in Asynch. Ckt

Q-3: Distinguish between Mealy and Moore Finite State Machines with example and diagrams.

Q-4: 6.11 and 6.20 (from Morris Mano book)

Q-5: Design and explain following counters:

1) BCD (Decade) MOD-10 Ripple counter using T flipflop.

2) BCD (Decade) MOD-10 Synchronous counter using JK flipflop.

3) 3-bit Up Down Asynchronous Counter.

4) Synchronous Counter for 013764 and repeat using JK Flipflop.

5) 4-bit binary Ripple Counter.

7) 4-bit Ring Counter

Q-6: Write short notes on following:

1) State Assignment

2) State Reduction

Q-7: Differentiate Flow Table and Primitive Flow Table in asynchronous sequential circuit.

ASSIGNMENT-10

Q-1: Write Short Notes on following:

1) Programmable Logic Array

2) Programmable Array Logic

Q-2: What is ROM? Explain with block diagram. Explain types of ROM in brief.

Q-3: Differentiate between PLA, PAL and PROM.

Q-4: Define FPGA. Explain its basic architecture along with necessary diagram. Also define LUT, Logic Block
and Logic Element with respect to FPGA.