Chapter

Metal Oxide Semiconduc-

tor (MOS) Capacitor 7
Introduction
In this chapter we will study about the heart of MOSFET device that is MOS capacitor. MOSFET will
be discussed in analog electronics here we will discuss only MOS capacitor. In this chapter we will study how
application of potential on the metal can invert the semiconductor surface close to oxide.

7.1 The Two Terminal MOS Structure

The two terminal MOS capacitor structure is shown in (Figure :7.1) The metal may be aluminium or
some other type of metal, although in many cases, it is actually a high-conductivity polycrystalline silicon that
has been deposited on the oxide; however, the term metal is usually still used. The parameter tox in the figure is
the thickness of the oxides and ox is the permittvity of the oxide.

Metal

tox insulator(oxide)
ox

Semiconductor
substrate

Fig 7.1 The basic MOS capacitor structure

The oxide act as an insulator and thus no current can flow between the two terminals. Thus current in
the MOS structure is always zero. We assume that oxide is ideal insulator with zero charges and metal has
infinite positive and negative changes.

Gate M O S Body

Fig 7.2 Block Representation of MOS Capacitor

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 241

The semiconductor can be p or n type semiconductor and it has finite concentration of changes. No
electric field can be found inside metal, but electric field can exist inside oxide and inside semiconductor.

Band diagram of MOS structure Metal oxide Semiconductor before making acontact

Vacuum level
exi
EC

em ex

EFm E g = 9 eV EC
Efi
Efs
EV

EV
Metal Silicon dioxide p-type silicon

Fig 7.3 Band diagram of Metal, oxide and semiconductor before forming a contact.
We can see that m that is work function of metal, thus the amount of energy to liberate electrn from
metal or amount of energy required to make electron free from metal is m. The oxide SiO2 has band gap of
9.1e V and we have p type semiconductor.
We can see that s > m thus when the Metal, oxide and semiconductor are joined to make MOS
structure then at equilibrium the fermi level of whole structure should be a straight line with no slope thus to
from a contact to the electrons will flow from metal to semiconductor as s > m.
Since electrons will flow from metal to semiconductor in this case then depletion region exist in
semiconductor, the metal will obtain positive charges and ptype semiconductor will have depletion region with
negative charges. Thus at equilibrium the band diagram will be as show in (Fig 7.4) and we assume that whole
oxide will be depleted because thickness of oxide is very less.

Vacuum level
Metal Oxide p-type semiconductor

eVox0
Oxide
conduction band
exi

B ex
A
ex  D
em EC
Eg
= 2

em C
E fi
efp
es0
EF
EV

M O S
depletion region

Fig 7.4 Energy band diagram through the MOS structure in thermal equilibrium after contact

GATE MASTERS PUBLICATION

 242 Electronic Devices And Circuits

The Fermi level is a constant through the entire system at thermal equilibrium. We may define ( m  as
a modified metal work function the potential required to inject an electron from the metal into the conduction
band of the oxide. Similarly,   is defined as a modified electron affinity. The voltage Vox0 is the potential drop

across the oxide for zero applied gate voltage and is not necessarly zero because of the difference between m
and  . The potential s0 is the surface potential for this case.)
Thus before contact the metal and semiconductor were not having same energy of electrons but when
contact is made then fermi level of whole structure become straight line but we can see that in band diagram
variation in EC and Ev in (Fig 7.4) show presence of electric field from metal-oxide interface to inside the
semiconductor till the point in semiconductor where depletion region exist. Thus at equilibrium electric exist in
oxide and in semiconductor.
The potential difference between point A and B is potential across oxide and potential difference between
C and D is potential across semiconductor. Thus at equilibrium we have potential stored across semiconductor
and oxide. This potential is due to difference between m and s, when contact is made the fermi level of whole
device become a straight line and thus we can say that so and Voxo are due to m – s  0. Thus if we sum the
energies from the Fermi level on the metal side to the Fermi level on the semiconductor side, we have
Eg
em eVox 0  = ex   e s 0  e fp (7.1)
2
Equation (9.63) can be rewritten as

  Eg 
Vox0 + s0 =  m   x  2e   fp   (7.2)
   
We can define a potential ms as

  Eg 
ms   m   x    fp   (7.3)
  2e  

which is know as the metal-semiconductor work function difference.

Or simply can say that
s – m = Vox0 + s0 (7.4)
In the previous case we used metal as gate of the device, we may se degenerately doped polysilicon
deposited on the oxide as the gate Fig:7.5(b) show energy band diagram of MOS capacitor with n+ polysilicon
gate and p-type substrate. In this case before making contact we assume that fermi level of n+ polysilicon is at
EC, thus EF = EC for n+ polysilicon. In Fig:7.5 (a) the band diagram before making contact is shown
Vacuum level
EC eVox ex 
ex m ex EC
s Eg
9.1 eV ex 2
EF = EC Efi
EC EC EF = EC efp EF
EV
Efs n + poly
EV EV
EV
EV S
n+ polysilicon oxide p-Substrate M O

(a) (b)

Fig : 7.5 (a) n + polysilicon gate MOS structure band diagram before (b) band diagram
after making contact

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 243

 Eg 
Here m – s = x   x    Fp  (7.5)
 2e 

g E 
 ms =  2 e   fp  (7.6)
 
Here also –ms = Vox0 + s0 (7.7)
Similarly we may have MOS capacitor with p+ polysilicon gate, hare EF = EV thus the band diagram
afte making contect will be as shown Fig : 7.6

ex

EC

p + poly Eg EC
2 Efi
efn
EF = EV EF
EV
M O S

Fig7.6 p + polysilicon gate MOS structure band diagram

we see that

 Eg   Eg   Eg 
 ms    x     x    fp      fp  
  e   2e   2e  

Example : 7.1

To calculate the metal-semiconductor work function difference ms for a given MOS system and
semiconductor doping.
For an aluminum-silicon dioxide junction,  m = 3.20 V and for a silicon-silicon dioxide junction,   =
3.25 V. We may assume that Eg = 1.11 eV. Let the p-type doping be Na = 1014 cm–3.

Solution : 7.1
For silicon at T = 300 K, we may calculate fp as

N a   1014 
fp = Vt in   = (0.0259) In   = 0.228 V
10 
 ni   1.5  10 
Then the work function difference is

GATE MASTERS PUBLICATION

 244 Electronic Devices And Circuits

 Eg 
ms = m         fp  = 3.20–(3.25 + 0.555 + 0.228)
 2e 
or ms = – 0.83 V

7.2 MOS Capacitor at Equilibrium

We have already analyzed MOS capacitor at equilibrium and see the band diagram of the structure. We
have observed that semiconductor has depletion region at equilibrium. Lets analyze the charge density, electric
equilibrium

t ox
M O S
M O S
eNaxd
eNaxd si
Gate M O S Body xd ox
x
xd x

–eNa
(a) change density (b) electric field

Fig 7.7 The charge density and electric field in MOS structure at equilibrium
We assume that width of depletion region is xd, the semiconductor is p-type and has charge density of
eNa. Thus total negative charges in depletion region of semiconductor is eNaxd the equal and opposite positive
charges will get accumulated at metal-oxide interface also. Since Metal has inifite charges thus there will be
approximately zero depletion width inside it thus in charge density plot we have shown charge density at metal-
oxide interface with a delta function and area of this delta function will be eNaxd and since it is showing positive
charge density thus it is drawn upward. We have also assumed that there are no charge inside oxide. Thus we
get charge density plot as shown in Fig 7.7(a). To get the electric field plot we use Poisson equation
Thus

dE 
=
dx 
Thus inside Metal E = 0 as  = 0 and at interface of metal-oxide we get a delta function in charge
density plot, thus
eN a x d
Eox = (7.9)
 ox
Also the electric field from metal to semiconductor in the structure is perpendicular to the interface
thus we will use the continuity equation to get electric field value at edge of semiconductor-oxide to semiconductor
side. Thus
Dsi = Dox
 si Esi = ox Eox
eN a x d
 Esi = (7.10)
 si

eN a x d
Thus electric field at the oxide-semiconductor interface toward semicondutor side is Esi = .
 si

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 245
Now in this region  = – eNa thus electric field will decay and it will become zero at x = xd.
The potential can be found by intergrating electric field plot. Integration of electric field plot in oxide
will give potential across oxide and integration of electric field in semiconductor will give potential across
semiconductor.
eN a xd
Vox0 = .tox (7.11)
ox

1 eN a xd2
and  s0 = (7.12)
2 ox
Thus s – m = Vox0 + s0

eN a xd 1 eN a xd2
= tox  (7.13)
ox 2  si

Study Note
If in a question we have s – m. then using above quadratic equation we can find depletion region width xd at
equilibrium

7.3 Applying Voltage to MOS Structure

When external voltage is applied to MOS structure then it might support or oppose the internal electric
field. The applied external voltage Va and electric field due to it is shown in Fig 7.8

E ext

M O S

E int

Va

Fig 7.8 External voltage is applied to MOS structure

When Va is applied such that external electric field support internal electric field then obviously the
electric field inside the MOS structure will increase and this increase in electric field will be due to increase in
charge density. There will be zero depletion region in metal and to get more negative ions the depletion region
will increase in semiconductor . Since Vox0 and s0 are the potential across oxide and semicondutor at equilibrium.
Now after applying external voltage Va is voltage across oxide is Vox and across semicondutor is s then
Va = (Vox – Vox0) + (s – s0) (7.14)
= Vox + s – Vox0 – s0 (7.15)
Va = Vox + s + ms (7.16)
Thus is Va is applied electric field will increase which increase depletion region width in semicondutor.
Thus electric field plot inside MOS structure will be

GATE MASTERS PUBLICATION

 246 Electronic Devices And Circuits

M O S
eNa xd3
ox V3

eNa xd2 eNa xd3 V 3 > V 2 > V 1

ox V2 si

eNa xd1 eNa xd2

ox si
V1 eNa xd1
si
xd1 xd2 xd3
depletion width increasing

Fig 7.9 Electric field inside MOS struture with increasing applied voltage
Thus we can see that more the applied voltage more is electric field and more is depletion width inside
semicondutor. Also we can see that Vox and s that is potential across oxide and semicondutor increase when
some external voltage is applied. It is very obvious that if in Fig :7.8 we apply negative value of Va then externa
electric field will appose internal electric field and electric field and depletion region inside semicondutor will
reduce. The value of external applied voltage for which electric field inside MOS struture become zero is called
flat band voltage.

In general if depletion width in semicondutor is xd then

REMEMBER
eN a x d 1 e N a x d2
Vox = .t ox and s =
 ox 2  si

7.3.1 Flat Band voltage

Flat band voltage is that external applied voltage for which no band bending exist. We have seen that at
equilibrium the band diagram of MOS structure had band bending in oxide and semicondutor as m  s. Thus
if we apply Va (external voltage) to MOS structure then band bending will change. If electric field due to
external applid voltage support internal electric field then band bending will increase and if it oppose internal
electric field then band bending will reducre. since
Va = (Vox – Vox0) + (s – s0) (7.17)
Since at flat band there is no band bending thus no electric field inside structure thus no potential
across oxide and semiconductor. That is
Vox = 0, s = 0
 VFB = (0 – Voxo) + (0 – so)
= – (Voxo + so)
VFB = + ms (7.18)

7.3.2 Threshold voltage

Let us analyze the band diagram of MOS struture when positive gate voltage is applied. We know that
when positive gate voltage is applid then positive charges go to metal and equivalent negative charges are
accumulated inside depletion voltage more positive charges get accumulated at metal and to maintain charge

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 247

neutrality depletion region width will increase inside semicondutor. Another way to look at this point is that
when Va is positive (Fig 7.8), then external electric field pushes holes in p-type semicondutor away from oxide-
semicondutor interface and thus more the electric field lead to larger depletion region width inside semicondutor.
Due to increase in Va, Vox and s also increase due to which band bending increase as shown in Fig 7.10

Vox0 Vox
EC EC

EFi EFi
s0
fp s

EF EF
EV EV

M O S M O S

(a) (b)

Vox Vox

EC
EC
EFi EFi
s s Fp
Fp EF
EF EV
EV

M O S M O S

(c) (d)

Vox

EC

EFi
Fp
s fp EF

EV

M O S

(e)

Fig 7.10 (a) band diagram of MOS structure equilibrium (b) band diagraom of MOS structure when V a > 0 is
applied (c) band diagram of MOS structure when s = Fp (d) band diagram of MOS sturcture when s > Fp (e)
band diagram of MOS structure when s = 2F
In Fig :7.10(a) we show band diagram of MOS structure at equilibirum and as the applied voltage Va

GATE MASTERS PUBLICATION

 248 Electronic Devices And Circuits

is increased the total electric field increase due to which more band bending occur and we can see the band
bending in Fig 7.1(b), (c), (d), (e). In the above figure we can see that as band bending increase the EFi is
coming close to EF thus the p-type substrate is becoming less p-type. In band diagram of Fig : 7.10 (c) the EFi =
EF at oxide semicondutor interface (s = Fp). Thus at the interface the semicondutor become intrinsic and on
further increase of Va the band bending will increase that will make the semicondutor at the oxide-semicondutor
interface n-type as EFi will go beyond EF. Thus a very significant property of MOS is that we can invert the
characteristic of semicondutor at oxide-semicondutor ductor interface by apply gate voltage.
If Fp is the gap between EFi and EF in p-type semicondutor, thus fp define the amount of doping in
semicondutor. If by applying gate voltage the band bending at oxide-semicondutor EFi go beyond EF such that EF
– Fi = Fp. then the n-type semicondutor produced at oxide-semicondutor interface will have approximately
same concentration of electrons as the concentration of holes in p-type substrate, or the n-type region created
at oxide-secmicondutor interface has same conductivity as that of the p-type substrate. The band diagram for
this condition is shown in Fig 7.10(e) and this condition is called inversion and here s = 2Fp.

N a 
Here  Fp = VT ln   (7.19)
 ni 
Thus at complete inversion s = 2Fp and depletion region width will be

2 s 2 Fp
xdT = e Na
(7.20)

Study Note
The depletion region width is

2 s  s
xd = e Na

 s Fp
Thus xdT = 2 (7.21)
e Na

The applied voltage (Va) at which s = 2Fp or inversion take place at oxide-semicondutor interface is
called threshold voltage. Thus at inversion condition
VTh = (Vox – Vox0) + (s – s0) (7.22)
VTh = Vox + s + ms
Here  s = 2 Fp

s Fp
and xdT = 2 e Na

eN a x d
Since Vox = tox
 ox

eN a x d T
 at threshold Vox = tox (7.23)
 ox

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 249
The charge distribution in MOS structure at threshold is shown in (Figure :7.11)

M O

xdT

Fig 7.11 Charge density in MOS structure at threshold.

Thus we can say that area of delta function in Fig 7.11 is eNaxdT. Also
|Qss| = |charges in semicondutor per unit area|= eNaxdT
eN a x d T
 Vox = tox
 ox

Qss
= tox (7.24)
ox
If we take Cox as oxide capacitance per unit area
Qss
 Vox = C (7.25)
ox

Thus the threshold voltage will be

Q ss
VTH = C + 2Fp + ms (7.26)
ox

Q ss
 VTH = C +2Fp + VFB (7.27)
ox

Since ms = VFB thus we can write equation equation 7.26 as equation 7.27.

REMEMBER Learn the proof of VTH equation because many times in GATE questions have been asked related
to equation (7.26) and (7.27). We can see that VTH can be changed by

1. Cox increase lead to VTH decrease

2. tox increase lead to VTH increase

3. doping of substrate increase will make VTH to increase

4. ms increase VTH increase

Similarly many more conlusion can be seen through equation (7.26) and (7.27)

7.3.3 Effect of non zero oxide charges

Till now we assumed that oxide is ideal and has zero charges inside itself. Now if we take non zero
charges in oxide, that is Qox is charge per unit area in oxide and let us take Qox > 0. Remember that MOS

GATE MASTERS PUBLICATION

 250 Electronic Devices And Circuits

structure work on concept of charge neutrality, let us do analysis to make things more clear.

MOS structure at equilibrium with non zero oxide charges

At equilibrium when metal oxide and semicondutor are connected to make contact then there will be
non zero potential generated across oxide (Vox0) and semicondutor (s0) as m  s. Even if Qox  0 then also at
equilibrium the condition will remain same as that of ideal case that is
Vox0 + s0 = – ms (7.28)

Study Note
This condition of equation (7.28) will always be satisfied even if oxide has charges or not because this condition is
due to m s and when contact is made then EF of whole device should be a straight line with zero slope.

Flat band voltage

Flat band voltage is that voltage at which no band bending occur in band diagram of MOS structure.
Since no band bending occur it means no electric field exist inside MOS structure and this means no depletion
region exist in semicondutor. We have already calculated the flat band voltage for ideal case, now let us calculate
flat band voltage for case when oxide has charges. Since oxide has charges and we will assume that oxide
charges are present at oxide semicondutor interface.
Since Vox0 + s0 = – ms
and when external voltage is applied then
Va = (Vox – Vox0) + (s – s0)
Fig 7.12 show the charge density inside MOS structure at flat band. Qox show charge density in oxide
and semicondutor has no charge density as no depletion rregion exist and Qm show charge density in metal
present at metal-oxide interface. We can also see that Qox is present at oxide-semicondutor interface.

M O S
Qm Qox

Fig 7.12 Charge density in MOS structure at equilibrium

Thus applying charge neutrality
Qm + Qox = 0
 Qm = – Qox
–Q ox
 Vox = C (7.29)
ox

Study Note

ox
We can write equation (7.29) because oxide capacitance per unit area is Cox = t and charge density across oxide
ox

is – Qox and + Qox. Thus voltage is charge/capacitance.

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 251

Thus the flat band volatge

–Q ox
VFB = – Vox0 + (s – s0)
C ox
Since no charge exist in semicondutor, thus s = 0
Qox
 VFB = –Vox0 – s0 –
Cox

Qox
VFB = ms – (7.30)
Cox

Threshold Voltage
We know that threshold voltage is that applied voltage at which inversion of the semicondutor as
semicondutor-oxide interface take place and for this s = 2Fp. Since MOS structure work only on the concept
of charge neutrality we have seen in the previous (ideal) case where no oxide charge exist then metal oxide
interface had charge density equal to eNaxdT that is equal and opposite to charge density in semicondutor. Since
in this case also s = 2Fp, thus

2  s 2  Fp
xdT =
e Na

 s  Fp
xdT = 2
e Na
Thus the plot of charge density will be as shown in Fig 7.13(a)
We can see that (charge neutrality)
Qm + Qox – eNaxdT = 0
 Qm = eNaxdT – Qox (7.31)

M O S
M S
Qox Eox O
Qm
Esi

xdT

xdT
– eNa

(a) (b)

Fig 7.13(a) charge density plot (b) electric field plot in MOS structure
Now we can find the electric field plot using poisson equation. No electric field exist in metal, the
electric field in oxide will be
dE 
=
dx 
 In oxide  = ox and effect of delta charge density (Qm) will be seen in oxide

GATE MASTERS PUBLICATION

 252 Electronic Devices And Circuits

 Qm
 E =  ox dx 
ox

eN a xdT  Qox
Eox =  ox (7.32)

Now this electric field is perrendicular from Metal to oxide to semicondutor thus to find value of electric
field at oxide semicondutor interface toward semicondutor side we use bounday condition and poission equation
taking effect of Eox and Qox respectively . Thus

 E ox ox  
Esi =      .dx
 si  si

E ox ox Qox
= 
si si

eN a xdT  Qox Qox

= 
 si  si

eN a xdT
Esi = (7.33)
 si
Then in semicondutor due to charge density – eNa the electric field will decay and
eN a  xdT  x 
E = . 0 < x < xdT. (7.34)
 si
Thus we can see that electric field is as shown in Fig 7.13(b). Thus Vox can be calculated by intergrating
electric field in oxide Fig :7.13 (b). Thus

 eN a xdT  Qox 
Vo x =   tox
  ox 

eN a xdT  Qox
Vox =
Cox

Qss  Qox
Vo x = (7.35)
Cox

Study Note
|Qss| is magnitude of charge density inside semicondutor and Cox is capacitance per unit area.
Thus at threshold using
Va = (Vox – Vox0) + (s – s0)
 VTH = Vox + s – Vox0 – s0

Qss  Qox
VTH = + 2Fp + ms (7.36)
Cox

Thus from above equation we can see that when Qox is positive then VTH reduces from the ideal value
equation (7.27). The simple reason behind this is that we need charge density equal to – eNaxdT inside

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 253

semicondutor at threshold, now when no oxide charge is present then external supply has to provide charge
density of + eNaxdT to metal thus positive supply is to be applied. When positive oxide charge density is present
in oxide then for maintaining charge density external supply has to provide charge density of eNaxdT – Qox only
and if negative charge density exist in oxide then charge density of eNaxdT + Qox should be provided by external
supply to maintain charge neutrality. Thus VTH increase when Qox is negative and decrease when Qox is positive.
We can write equation (7.36) using (7.30) as
eN a xdT
VTH =  2 Fp  VFB (7.37)
Cox

Example :7.2

To calculate the flat-band voltage for an MOS capacitor a p-type semiconductor substrate. Consider an
MOS structure with a p-type semiconductor substrate doped to Na = 1016 cm–3, a silicon dioxide insulator
with a thickness of tox = 500A, and n+ polysilicon gate. Assume that Qox = 1011 electronic charges per cm2.
The work function diffrence, from is ms = – 1.1 V.
Solution 7.2
The oxide capacitance can be found as

ox  3.9  8.85  10 

14

Cox =  = 6.910–8 F/cm2
t ox 500  10 8

The equivalent oxide surface charge density is

Qox = (1011)(1.61019) = 1.610–8 C/cm2

The flat-band voltage is then calculated as

Qox
VFB = ms– ms  = – 1.33 V
Cox

Example :7.3

To design the oxide thickness of an MOS system to yield a specified threshold voltage. Consider an n+
polysilicon gate and p-type silicon substrate doped to Na = 31016cm–3. Assume Qox = 1011cm–2. Determine
the oxide thickness such that VTH = +0.65 V. (Assume ms = –1.13 V)

Solution 7.3
The various parameters can be calculated as

N a   3  1016 
 Fp = Vt In   = (0.0259) In   = 0.376 V
10 
 ni   1.5  10 

1/2
 4 s fp 
1/2 

 4
 
 4 11.7  8.85  10  0.376  
and xdT =  eN   = 0.18 m
 a    
1.6  10 19 3  1016 

GATE MASTERS PUBLICATION

 254 Electronic Devices And Circuits

then |QSS(max)| = eNaxdT = (1.610–19)(31016)(0.1810–4)

or |QSS(max)| = 8.6410–8 C/cm2
The oxide thickness can be determined from the threshold voltage equation

 t ox 
VTH = (|QSS(max)|– Qox)    +ms + 2Fp
 ox 
Then

   
 8.64  10 8  1011 1.6  10 19 
  
0.65 = tox – 1.13+2(0.376)
 
3.9 
8.85  10 14

or 0.65 = 2.0105tox–0.378
Which yields tox = 504 A

7.3.4 Various region of operation of MOS structure

In the previous section we have seen how applied voltage can invert the semicondutor at oxide-
semicondutor interface. Here we will see a bigger picture of various region of operation of MOS strucure.

1. Accumulation region
When external voltage is applied to MOS structure such that positive is conneted to semicondutor as
shown in Fig :7.14(a). We can see that external electric field is from semicondutor to metal.

 Efield 
 
 
M O S  
 
p-type  
semiconductor 

Va Va

EC

Efi
Gate M O
Fp
Negative
voltage
applied EF
s
EV

(c)

Fig 7.14 (a) external voltage applied for accumulation mode (b) capactor equivalent of MOS structure (c)
band diagram of MOS structure in accumulation mode

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 255

Remember that current will never flow in MOS structure as insultor is present. Thus MOS structure
can be seen as a capcitor as shown in Fig :7.14(b). When voltage Va is applied as shown in Fig :7.14 then
external electric field will be from semicondutor to metal, this electric field will push majority carrier holes
toward oxide-semicondutor interface. Thus the accumulation of the holes at oxide-semicondutor interface
represent plate of capacitor with positive charges and metal show plate of capacitor with negative charges.
The energy-band diagram of the MOS capacitor with the p-type substrate, for the case when a negative
voltage is applied to the top metal gate, the holes in the p-type substrate are attracted to the semiconductor oxide
interface. The majority carrier concentration near the surface becomes large than the equilibirum hole concentration
in substrate; hence, this condition is called carrier accumulation on the surface, is shown in Fig :7.14(a). The
oxide electric field is directed towards the gate electrode. The negative surface potential also causes the valence
band to bend towards Fermi level at the interface, which implies that there is an accumulation of holes. The
Fermi level is a constant in the semiconductor since there is no current through the oxide.
In Fig 7.14 (c) we can see that band bending occur and since here band bending is toward EF we take it
as negative thus we say that hare surface potential of semicondutor is negative( here s is negative). In bulk
region
EFi – EF =  Fp
and concentration of holes

 Fp 
Po = Na = ni exp  V 
 T 
Thus at oxide semicondutor interface

EF – EFi = (Fp + s )
 connection of holes

 Fp  s 
P o = ni exp  V 
 T 

 s 
= Na exp  V  (7.38)
 T 
Thus the concentration of holes increase at oxide semicondutor interface and it is exponentially related
to s.

Study Note
This mode of operation is called accumulation mode of operation as holes get acculated at oxide-semicondutor
interface

2. Depletion mode of opertion

We have already analyzed what happen when external voltage is applied to MOS structure with p-type
substrate with positive applied at metal as shown in Fig 7.15. The band diagram will be as shown in Fig 7.10(a)
at equilibrium and when voltage Va is applied the band diagram will be as shown in Fig 7.15 (b), here external
electric field will support internal electric field thus total electric field will increase. This electric field will push
majority carrier holes in semicondutor away from oxide semicondutor interface and depletion region width in
semicondutor will increase, the semicondutor close to oxide will become less p-type and the band bending will

GATE MASTERS PUBLICATION

 256 Electronic Devices And Circuits

take place and band diagram will be as shown in Fig 7.10 (b). As the applied voltage will increase and s that is
potential across semicondutor will increase, (here s will be positive) band bending increase and the band
diagram changes from Fig 7.10(a) to Fig 7.10(c). In Fig 7.10(c) we can see that s = Fp and semicondutor at
oxide-semicondutor interface has EF = EFi and semicondutor become intrinsic.

E ext

E field
 
  M O S
 
 
 
  E int
 

Va

(a) (b)

Fig 7.15 (a) Capacitor equivalent of MOS structure (b) Voltage applied with positive at metal
When value of s lie between 0 and Fp then MOS capcitor is said to be in depletion mode of operation.
Here the width of depletion region is xd and

2 s s
xd = e Na
(7.39)

Thus charge density that is – eNaxd is proportional to s .

In Fig 7.15(a) we have shown the MOS structure as a capacitor, here positive plate of capacitor is metal
and negative plate is the depletion region in semicondutor.

3. Weak inversion mode of operation

When the applied voltage in Fig 7.15(b) is increased further then electric field increase and the depletion
region width inside semicondutor increase and band bending increase. The increase in s and further band
bending lead to EFi going be low EF in semiconductor at oxide semiconductor interface. Thus the semicondutor
at the oxide semiconductor interface will become n-type. Thus this is called weak inversion region. The band
diagram will be same as shown in Fig 7.10(d) and if we increase Va further then s = 2Fp and band diagram will
be as shown in Fig 7.10(e). Thus when s = 2Fp then n region close to oxide-semiconductor interface will have
same conductivity as the conductivity of bulk p-type substrate and we assume that at this point complete inversion
take place.
In weak inversion the value of s exist between Fp and 2Fp. In this region also we assume that the
negative charges are the ions in depletion region of semiconductor. Thus negative plate of capacitor is depletion
region of semiconductor and positive plate is metal. Thus the charge density in weak inversion will remain same
as – eNaxd and

2 s s
xd = e Na (7.40)

The value of Va for which s = 2Fp is called threshold voltage

REMEMBER Remember that in weak inversion and depletion mode of operation the negative charge in
semiconductor is due to ions in depletion region only.

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 257

4. Strong Inversion
In depletion and weak inversion mode of operation we assumed that negative charges in semiconductor
are due to depletion region only and thus due to negatiave ions only. Thus we get that charge density was
proportional to s . Here we have neglected that the electric field which is pushing back holes away from
oxide-semiconductor interface will also attract electrons to the oxide semiconductor interface thus negative
charges will be due to electron also.

Study Note
But the approximation stated above is valid and we can carry on with this approximation

Now when applied is increased above VTH then we assume that electrons will be attracted to oxide-
semiconductor interface and with increase in voltage when the positive charge at plate of capacitor increase then to
balance this, negative charges will come at the plate of capacitor by not the ions of depletion region of semiconductor
but by the the electrons. Thus now with increase in applied voltage (Va) the depletion region width do not
increase as now balance or charge neutrality is done by electrons. Thus maximum depletion region width in
semiconductor is

2 s 2 Fp
xdT = e Na

s Fp
= 2 (7.41)
e Na
Thus in strong inversion the charge density is due to electron, thus when s > 2Fp then charge density
 
in semiconductor will be proportional to exp  s  . The simple explaination to this is that when s is the amount
V T 
of band bending then EF come close to EC and we know that relationship that electron concentration is
exponentially related to (EC – EF) since it reduces as s increase so electron concentration increase in the
semiconductor at semiconductor-oxide interface.

Study Note
When fs ³ 2fFp the electron concentration increases rapidly with very small changes in surface potential, the space
charge width has essentially reached a maximum value.

Fig :7.16 show the total charge density (C/cm2) in the silicon as a function of the surface potential. At
flat band, the total charge is zero. For 0  s  fp, we are operating in the depletion mode since the inversion
charge has no yet been formed. In this region acceptors in Si are depleted off creating immobile negative ion
layer at the oxide-semiconductor interface. This region is called the depletion region. For fp  s  2fp, the
Fermi energy at the surface is in the upper half of the band diagram, which implies an n-type material, but we
don’t have threshld inversion point. In this region where inversion have just started is called weak inversion
region, For s > 2fp inversion charge density increase rapidly (exponentially) with increase in surface potential,
this region is called strong invertion region.

GATE MASTERS PUBLICATION

 258 Electronic Devices And Circuits

10–4
p-type Si (300 K)
N a = 41015cm–3 (Strong inversion)
 e 
10–5  exp  s 
(Accumulation)  2kT 
 e | s | 
 exp 

|Qs|(C/cm2)

10–6  2kT 
2fp
10–7
Flat band
Weak
10–8
Depletion inversion
EV  fp EC
–9
10
–0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
s(V)

Figure :7.16 Variation of surface charge density for p-type Si MOS (accumulation charge and invertion
charge) as a function potential

7.4 Capacitor-Voltage Characteristic

The MOS capacitor structure is the heart of the MOSFET, A great deal of information about the MOS
device and the oxide-semiconductor interface can be obtained form the capacitances versus voltage or C-V
characteriestics of the device. The capacitances of a device is defined as
dQ
C =
dV
where dQ is the magnitude of the differential in charge on one plate as a function of the differential
change in voltage dV across the capacitor. The capacitance is a small-signal or ac parameter and is measured by
superimmposing a small ac voltage on an applied dc gate voltage. The capacitance, then, is measured as a
function of the applied dc gate voltage.

7.4.1 Ideal C-V Characteristic

First we will consider the ideal C-V characteristic of the MOS capacitor and then discuss some of the
deviations that occur from these idealized results. We will initially assume that there is zero change trapped in the
oxide and also that there is no change trapped at the oxide-semiconductor interface.
There are three operating conditions of interest in the MOS capacitor: accumulation, depletion and
inversion Fig 7.17(a) shows the energy-band diagram of a MOS capacitor with a p-type substrate for the case
when a negative voltage is applied to the gate, inducing an accumulation layer of holes in the semiconductor at
the oxide-semiconductor interface. A small differential change in voltage across the MOS struture will cause a
differential change in charge on the metal gate and also in the hole accumulation charge, as shown in Fig 7.17(b).
The differential changes in charge density occur at the edges of the oxides, as in a parallel-plate capacitor. The
capacitance C per unit area of the MOS capacitor for this accumulation mode is just the oxide capacitance, or

ox
C (acc) = Cox= (7.43)
t ox

Fig 7.18(a) shows the energy-band diagram of the MOS device when a small positive voltage is applied

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 259

to the gate, inducing a space charge region in the semiconductor. Fig 7.18(b) shows the charge distribution
through the device for this condition. The oxide capacitance and the capacitance of the depletion region are in
series. A small differential change in voltage across the capacitor will cause a differential change in the space
charge width. The corresponding differential changes in charge densities are shown in the figure. The total
capacitance of the series combination is

1 1 1
=  (7.44)
C  depl  Cox CSD

|dQ’|

+Q’
EC
Efi
EF
–Q’
EV
|dQ’|

(a) (b)

Fig 7.17 (a) Energy-band diagram through a MOS capacitor for the accumulation mode (b) Differential
charge distribution at accumulation for a differential change in gate volatage

|dQ|
EC
+Q
E fi
EF dx
Xd
EV

xd |dQ|
–Q

(b)
(a)

Fig 7.18(a) Energy-band diagram through a MOS capacitor for the depletion mode (b) Differential charge
distribution at depletion for a differential change in gate voltage

Cox CSD
or C(depl) = (7.45)
Cox  CSD
Since Cox = ox/tox and CSD = s/xd, Equatin (7.45) can be written as
Cox  ox
C (depl) =  (7.46)
Cox  
1 tox   ox  xd
C SD  s 
As the space charge width increase, the total capacitance C (depl) decreases.We had defined the threshold
inversion point to be condition when the maximum depletion width is reached but there is essentially zero
inverison charge density. This condition will yield a mininum capacitance C min which is given by

GATE MASTERS PUBLICATION

 260 Electronic Devices And Circuits

ox
C min = (7.47)
 
t ox   ox  x dT
 s 
Fig 7.19(a) shows the energy-band diagram of this MOS device for the inversion condition. In the ideal
case, a small incremental change in the voltage across the MOS capacitor will cause a differential change in the
inversion layer charge density. The space charge width does not change. If the inversion charge can respond to
the change in capacitor voltage as indicated in Fig 7.19(b), then the capacitance is again just the oxide capacitance,
or
ox
C (inv) = C ox  (7.48)
t ox
Fig 7.20 shows the ideal capacitance versus gate voltage, or C-V characteristic of the MOS capacitor
with a p-type substrate. The three dashed segments correspond to the three components Cox, C SD, and C min,
The solid curve is the ideal net capacitance of the MOS capacitor. Moderate inversion, which is indicated in the
figure, is the transition region between the point when only the space charge density changes with gate voltage
and when only the inversion charge density changes with gate voltage.
Metal Oxide p-type semiconductor
|dQ’|
EC
+Q’
E fi
EF
XdT
EF EV

xdT S –Q’
M O
|dQ’|
(b)
(a)

Fig 7.19 (a) Energy-band diagram through an MOS capacitance for the mode (b) Differential charge
distibution at inversion for a low-frequency change in gate voltage

Cox C Cox

Accumulation CFB CSD Strong

inversion
Moderate
inversion
Depletion
C min

VFB 0 VT VG

Fig 7.20 Ideal low-frequency capacitance versus gate voltage of a MOS capacitor with a p-type substrate.
Individual capacitance components are also shown.
The point on the curve that corresonds to the flat-band condtion is of interest. The flat-band condition
occurs between the accumulation and depletion conditions. The capacitance at flat band is given by

 ox
C FB 
    kT   s 
tox   ox     (7.40)
 s   e   eN a 

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 261
We may note that the flat-band capacitance is a function of oxide thickness as well as semiconductor
doping. The general location of this point on the C-V plot is shown in Fig 7.20.

Example :7.4

To calculate Cox, C min and C FB for an MOS capacitor. Consider a p-type silicon substrate at T = 300 K
doped to Na = 1016cm–3. The oxide is silicon dioxide with a thickness of 550 A and the gate is aluminum.

Solution 7.4:
The oxide capacitance is

ox  3.9  8.85  10 

–14

Cox =  = 6.2810–8F/cm2
t ox 550  10 –8

To find the minimum capacitance, we need to calculate

   1016 
fp = V t In  N a  = (0.0259) In  10  = 0.347 V
 ni   1.5  10 
and
1/ 2

xdT
 4  
=  s fp 
1/ 2


 
 4 11.7  8.85  10 –14  0.347  
 = 0.3010–4 cm

 eN a   
1.6  10 19
10 16
  
Then

ox 3.9   8.85  10 –14 

C min =  = 2.2310–8F/cm2
   3.9 
t ox   ox  x dT 550 10  –8

11.7

 0.3  10
–4

 s   

We may note that

Cmin .23  10 –8
Cox = 6.28  10 –8 = 0.355

The flat-band capacitance is

ox
C FB =
    k T   s 
t ox   ox    
 s   e   eN a 

3.9   8.85  10 14 

=
 3.9  11.7   8.85  10 –14 
550 10  –8
   0.0259 
 11.7  1.6 10 10 
–9 16

= 5.0310–8F/cm2

GATE MASTERS PUBLICATION

 262 Electronic Devices And Circuits

We may also note that

C FB 5.03  10 –8
C ox = = 0.80
6.28  10 –8

The same type of ideal C-V characteristics are obtained for an MOS capacitor with an n-type substrate by
changing the sign of the voltages axis. The accumulation condition is obtained for a positive gate bias and
the inversion condition is obtained for a negative gate bias. The ideal curve is shown in Fig 7.21

C
Strong Accumulation
inversion Depletion
Moderate
inversion

0 VG

Fig 7.21 Ideal low-frequency capacitance versus gate voltage of a MOS capacitor with an n-type substrate

7.4.2 Frequency Effects

Fig 7.19(a) showed the MOS capacitor with a p-type substrate and biased in the inversion condition.
We have argued that a differential change in the capacitor voltage in the ideal case causes a differential change
in the inversion layer charge density. However, we must consider the source of electrons that produces a change
in the inversion charge density.
There are two source of electrons that can change the charge density of the inversion layer. The first
source is by diffusion of minority carrier electrons from the p-type substrate across the space charge region.
This diffusion process is that in a reverse-biased pn junction that generates the ideal reverse saturation current.
The second source of electrons is by thermal generation of electron-hole pairs within the space charge region.
This process is again the same as that is a reverse-biased pn junction generating the reverse-biased generation
current. Both the these processes generate electrons at a particular rate. The electron concentration in the
inversion layer, then, cannot change instantaneously.
If the ac voltage across the MOS capacitor changes Low
frequency
rapidly, the change in the inversion layer charge will
not be able to respond. The C-V characteristics will C

then be a function of the frequency of the ac signal Accumulation

High
used to measure the capacitance. frequency

In the limit of a very high frequency, the

inversion layer charge will not respond to a Inversion
differential change in capacitor voltage. At a high-
0 VG
signal frequency, the differeitial change in charge
Fig 7.22: Low frequency and high frequency capacitance versus
occurs at the metal and in the space charge width in gate voltage of a MOS capacitor with a p type substrate.
the semiconductor. capacitance of the MOS capcitor
is then C min which we discussed earlier.
The high-frequency and low-frequency limits of the C-V characteristic are shown in Fig 7.22. In general,
high frequency corresponds to a value on the order of 1MHz and low frequency corresponds to values in the
range of 5 to 100 Hz. Typically, the high-frequency characteristic of the MOS capacitor are measured.

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 263

7.4.3 Fixed Oxide Charge Effects

In all of the discussion concerning C-V charatieristic so far, we have assumed an ideal oxide in which
there are no fixed charge at oxide or oxide-semiconductor interface. These two types of charges will change the
C-V charateristic.
We previously discussed how the fixed oxide charge affects the threshold voltage. The charge will also
affect the flat-band voltage, the flat-band voltage is given by

Qox
VFB = ms  C
ox

where Qox is the equivalent fixed oxide charge and ms is the metal-semiconductor work function
difference. The flat-band voltage shifts to more negative voltages for a positive fixed charge. Since the oxide
charge is not a function of gate voltage, the curves shows a parallel shift with oxide charge, and the shape of the
C-V curves remains the same as the ideal charateristic. Fig 7.23 shows the high frequency characteristics of a
MOS capacitor with a p-type substrate for several values of fixed positive oxide charge.
The C-V characteristic can be used to determine the equivalent fixed charge. For a given MOS structure,
ms and Cox are know, so the ideal flat-band voltage and flat-band capacitance can be calculated. The experimental
value of flat-band voltage can be measured from the C-V curve and the value of fixed oxide charge can then be
determined. The C-V measurements are a valuable diagnostic tool to characterize a MOS device. This
characterization is especially useful in the study of radiation effects on MOS devices.

Qox3 > Qox2 > Qox1 > 0

C
Cox Qss = 0(ideal)

Cmin
VFB3 VFB2 V FB1 VFB0 0 VG

Fig 7.23 High-frequency capacitance versus gate voltage of a MOS capacitor with a p-type substrate for
several value of effective trapped oxide charge

7.5 MOS Structure with n type Substrate

We have analyzed the MOS structure with p-substrate, now if we change the semiconductor to n-type
then the analysis will be exactly similar but apposite as that for MOS with p substrate.
We can see in Fig 7.24(b) the band diagram of MOS with n-type substrate when contact is not made
between metal, oxide and semiconductor. Now when contact is made then electron flow from semiconductor to
metal as m > s. Now the semiconductor close to oxide-semiconductor become less n-type and depletion
region is created in semiconductor and band bending occur as show in Fig :7.24(c). Here point A is at lower
potential than B and C is at lower potential then D. Here we will take Vox0 and s0 as potential difference
between A and B, C and D repectively.
We can see that Vox0 and s0 are due to m  s and Vox0 and s0 are negative here, also
Vox0 + s0 = –ms (7.50)
We can see that when external voltage is applied as shown in Fig :7.24(a) then there are various mode
of operation which exist in MOS structure. These mode are

GATE MASTERS PUBLICATION

 264 Electronic Devices And Circuits

1. Accumulation mode
When Va is positive then external applied voltage produce external electric field from metal to
semiconductor, this electric field will pull majority carrier electron from n substrate to oxide-semiconductor
interface. Thus electron will get accumulated at oxide semiconductor interface. Here accumulation region exist
for Va > 0. The band diagram will be as shown in Fig :7.24(d). If we take MOS as a capacitor then positive plate
of capacitor is metal and negative plate is semiconductor. We can see that semiconductor at semiconductor-
oxide interface become more n-type.
Vaccum
exi level
EC
em
M O S ex es
n type 9 eV
semiconductor
E Fm EC
Metal E FS
Va
EV
oxide
EV
semiconductor
(a) (b)

Accumulation of electron
eVox0
B EC
--- -- -
es0 D EF
EC
EF Gate M O
positive
gate voltage EV

EV
Metal Oxide Semiconductor
(C) (d)

EC
EC
EF EF
Gate M O Gate M O s Fn
negative s negative
Efi E fi
gate voltage gate voltage
EV
EV

(e) (f)

Fig 7.24 (a) MOS sturcture with external applied voltage (b) band diagram of MOS before forming contact
(c) band diagram after making contact (d) band diagram in accumulation mode (e) (f) band diagram in weak
inversion mode

2. Depletion mode of operation

When negative gate voltage is applied in Fig 7.24(a) then external electric field is such that it pushes
electron away from oxide-semiconductor interface and depletion region with negative ions of donor is present.
This depletion region now act as positive plate of capacitor and metal act as negative plate of capacitor. As the
applied voltage Va become more negative then s the semiconductor potential increase and depletion width

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 265

increase. The band diagram will be as shown in Fig 7.24(e). The depletion mode of operation exist when
0 < |s|< Fn as when |s| = Fn then semiconductor at oxide-semiconductor interface become intrinsic. as
shown in band diagram Fig 7.24(f).

3. Weak inversion
When external applied voltage Va is increased further then band bending will increase and EFi will go
above EF in band diagram for the semiconductor close to oxide-semiconductor interface. Thus semiconductor
become p-type near the oxide-semiconductor interface. Thus inversion take place when |s|> Fn. The complete
inversion is assumed when |s|= 2Fn that is p-type inverted region near oxide semiconductor interface has
same conductivity as that of n-type bulk region. The band diagram of MOS structure when s = 2Fn is shown
in Fig 7.25(a). In Figure 4.25(a) we can see that depletion region width is xdT

2 s s 2 s 2 Fn
xdT = .  (7.51)
e Nd e Nd

EC
EF
Gate M O Fn Fn
negative E fi
voltage
applied EV

xdT

(a)

M O S M O S
eNd

xdT

eN x
– d dT
eN x si
Qm – d dT
ox

(b) (c)

Fig 7.25 (a) The band diagram (b) charge density (c) electric field in MOS structure at threshold.
Here Nd is doping is substrate. The charge density will be as shown in Fig 7.25(b). The delta charge
density will be of area – eNdxdT. The electric field plot will be found by applying poission equation. The electric
field will be as shown in Fig 7.25(c). The electric field in oxide will be
 – eN d xdT
Eox =  ox d x  (7.52)
ox
and electric field at oxide-semiconductor interface toward semiconductor will be calculated using
boundary condition
E ox  ox – eN d x dT
Esi =  (7.53)
 si  si

GATE MASTERS PUBLICATION

 266 Electronic Devices And Circuits

Then in semiconductor electric field reduce as constant space chare density exist in semiconductor
thus
– eN d
E =  xd T  x  , 0 < x < xdT.
 si
Thus the applied voltage to get inversion, s = –2Fn, is
VTH = (Vox – Vox0) + (s – s0) (7.54)
= Vox + s – Vox0 – s0
We can calculate Vox from Fig 7.25(b)
eN d xdT
Vox = tox (7.55)
 ox

 Q ss
Vox = (7.56)
C ox
Here |Qss| is magnitude of charge density in depletion regin of semiconductor it is equal to eNdxdT
ox
Fig 4.25 and Cox = that is oxide capacitance per unit area.
t ox
and  s = – 2Fn

 Q ss
 VTH =  2 Fn  m s (7.57)
C ox
Thus the threshold voltage will be negative for MOS structure with n substrate. Also we can see that the
Flat band voltage can be easily calculated using equation (7.54) by keeping s = 0 and Vox = 0 as at Flat band
no depletion region or electric field exist in MOS structure. Thus
VFB = – Vox0 – s0 (7.58)
VFB = ms (7.59)
Here we can also include effect of oxide charges in MOS sturcture. We know that MOS structure
function on concept of charge neutrality it means that at threshold when charge density in semiconductor is
eNdxdT and xdT is depletion width due to s = 2Fn then metal must get – eNdxdT charge density and then we get
electric field as shown in Fig 7.25(c). Now let us say that oxide has charge density Qox then to maintain charge
neutrality metal need only
Q
 m  Q
ox  eN d xdT
 
Charge Charge density Charge density
= 0
density on in oxide in semiconductor
metal

Qm = – eNdxdT – Qox
Thus if Qox is negative then we need less Qm than what we need in ideal case when oxide no charges, and
if oxide has positive charge density then more Qm is needed. Thus |VTH|will increase when Qox is positive and
|VTH|will decrease if Qox is negative. Thus we modify equation (7.57)

 Q ss Q ox
 VTH =   2 Fn  m s (7.60)
C ox C ox

 Q ss
VTH =  2 Fn V FB (7.61)
C ox

Qox
and VFB = m s  (7.62)
C ox

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 267

4. Strong Inversion
When Va is increased further then the depletion layer width do not increase inside semiconductor
because now the positive charges coming to semiconductor oxide interface will be not due to ions but due to
holes. Thus maximum depletion region width is xdT and after this holes get accumulated at oxide-semiconductor
interface.

Study Note
The explaination is similar to that of MOS with p substrate

7.6 Depletion Mode MOS Sturcture

The MOS structure we studied till now were those where we need to make a inverted layer in p or n
semiconductor by application of external voltage. The MOS structure are used in design of enhancement mode
MOSFET, but there may be other structure where the oxide-semiconductor interface already has inverted
semconductor layer as shown in Fig 7.26(a) and 7.26(b)

– +
– +
– +
– +
Gate p-type Body Gate n-type Body
M O – M O +
semiconductor semiconductor
– +
– +
– +
– +
p-type layer
n-type layer
(a) (b)

Fig 7.26 Depletion mode MOS structure (a) p-type substrate (b) n-type substrate.
In these structure already inverted layer is present. When the gate voltage in Fig 7.26(a) is positive
then obviously the electric field will push back holes and will increase negative charge density in oxide-
semiconductor interface but when gate voltge is negative then the negaitve charge density in oxide semiconductor
interface will reduce and the value of VTH for this structure is that voltage where the inverted region is removed.
Thus VTH for MOS structure of Fig 7.26(a) is negative. Similarly in MOS structure of Fig 7.26(b) the inverted
region will be removed when gate voltage is positive thus VTH will be positive for this MOS structure.

GATE MASTERS PUBLICATION

 268 Electronic Devices And Circuits

metal-semiconductor work function difference of

ms = –0.35 V is required. Determine the silicon
doping required to meet this specification when
the gate is (a) n+ polysilicon, (b) p+ polysilicon.

1 Subjective Practice Problems

1 . The dc charge distribution of four ideal MOS

6 . Consider an n+ polysilicon-silicon dioxide-n-type
silicon MOS capacitor. Let N d = 1015 cm –3 .
capacitors are shown in Figure. For each case: Calculate the flat-band voltage for (a) tox = 500 A
(a) Is the semiconductor n-or p-type ? when Qox is (i) 1010cm–2, (ii) 1011cm–2, and (iii)
(b) Is the device biased in the accmulation, 51011cm –2. (b) Repeat part (a) when tox =
depletion, or inversion mode? 250 A.
(c) Draw the energy-band diagram in the
semiconductor region. 7 . An Al-silicon dioxide-silicon MOS capacitor has
an oxide thickness of 450 A and a doping of Na =
1015cm–3. The oxide charge density is Qox =
31011cm–2. Calculate (a) the flat-band voltage
and (b) the threshold voltage.
M O S M O S

(a) (b) 8 . Consider an MOS capacitor with an n+ polysilicon

gate and n-type silicon substrate. Assume Na =
10 16 cm –3 and let E F – E C = 0.2 eV in the
n+polysilicon. Assume the oxide has a thickness
of tox = 300 A. Also assume that (polysilicon) =
M O S M O S
(signal-crystal silicon). (a) Sketch the energy-
band diagrams (i) for VG = 0, and (ii) at flat band.
(c) (d)
(b) Calculate the metal-semiconductor work
2 . Calculate the maximum space charge width xdT
function difference. (c) Calculate the treshold
and the maximum space charge density
voltage for the ideal case of zero fixied oxide
|QSS(max)|in p-type silicon, galium arsenide,
charge and zero interface states.
and germanium semiconductors of an MOS
structure. Let T = 300 K and assume Na =
9 . An ideal MOS capacitor with an aluminum gate
1016cm–3 Repeat part if T = 200 K.
has a silicon dioxide thickness of tox = 400 A on
a p-type silicon substrate doped with an acceptor
3 . Consider n-type silicon in an MOS structure. Let
concentration of Na = 1016cm–3. Determine the
T = 300 K. Determine the semiconductor doping
capacitances Cox, C FB, C min, and C (inv) at (a)
so that | Q SS (max)|= 7.510 –9 C/cm 2 .
f = 1 Hz and (b) f = 1 MHz. (c) Determine VFB
Determine the surface potential that results in
and VT.
the maximum space charge width.

1 0 .Consider an SOS capacitor shown in Figure.

4 . Determine the metal-semiconductor work
Assume the SiO2 is ideal (no trapped charge)
function difference ms in an MOS structure with
and has a thickness of tox = 500 A. The doping
p-type silicon for the case when the gate is (a)
concentration are Nd = 1016cm–3 and Na =
n+ polysilicon, and (b) p+ polysilicon. let Na =
1016cm–3, (a) Sketch the energy band diagram
61015cm –3.
through the device for (i) flat-band, (ii) VG =
+3V, and (iii) VG = –3 V. (b) Calculate the flat-
5 . Consider a MOS structure with n-type silicon. a

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 269
band voltage. (c) Estimate the voltage across the
oxide for (i) VG = +3 V and (ii) VG = –3 V. (d)
tox

VG n type SiO2 p type

1 Objective Practice Problems

1 . Consider the dc charge distribution of an ideal

MOS capacitor shown in figure below.

1 1 .The high-frequency C-V characteristic curve of +Q’

an MOS capacitor is shown in Figure. The area

of the device is 210 –3 cm 2 . The metal-
semiconductor work function difference is ms =
–0.50 V, the oxide is SiO2, the semiconductor is
Ionized acceptor
silicon, and the semiconductor doping
concentration is 210 16 cm –3 . (a) Is the – Q’

semiconductor n or p type? (b) What is the oxide electrons

thickness? (c) What is the equivalent trapped
oxide density? (d) Determine the flat-band
What is the type of semiconductor and mode of
capacitance. of biasing ?
C (F )
(a)n-type, depletion (b) n-type, inversion
200 (c)p-type, depletion (d) p-type, inversion

CFB

2 . Consider the dc charge distribution of an ideal

MOS capacitor shown in figure below.

20
+Q’
VFB 0 VG
= –0.8 V

1 2 .Consider the high-frequency C-V plot shown in

Figure. (a) Indicate which points correspond to Ionized acceptor
flat-band, inversion, accumulation, threshold, and – Q’

depletion mode.
M O S
C

5 What is the type of of semiconductor and mode

4
of biasing ?

(a) n-type, depletion (b)n-type, inversion

3
(c) p-type, depletion (d)p-type, inversion
1 2 3 . Consider the dc charge distribution of an ideal
MOS capacitor shown in figure below.
0 VG

GATE MASTERS PUBLICATION

 270 Electronic Devices And Circuits

(c) 1.610–7C/cm2 (d) 4.810–8C/cm2

’
+Q
Common Data For Q. 7 and 8 :

Holes Consider n-type silicon in an MOS structure at

T = 300 K.
7 . What will be the semiconductor doping so that
maximum space charge density, |QSS(max)|=
– Q’ 7.510–9C/cm2.
M O S
(a) 6.541016cm–3 (b) 6.541014cm–3
What is the type of semiconductor and mode of
(c) 3.271014cm–3 (d) 6.641014cm–3
biasing ?
8 . The surface potential that results in the
(a) n-type, depletion (b) n-type, accumulation
maximum space charge width is
(c) p-type, depletion (d)p-type, accumulation
(a) 0.518 V (b) – 0.518 V
4 . Consider the dc charge distribution of an ideal
(c) 0.259 V (d) – 0.259 V
MOS capacitor shown in figure below.
9 . Consider an MOS structure with n-type silicon.
Holes
A metal-semiconductor work function difference
+Q
’
of ms = – 0.35 V is required. For an aluminium-
Ionized donor silicon dioxide junction, m = 3.20 V and for a
silicon-silicon dioxide junction  = 3.25 V and
Eg = 1.11 eV. If the gate is aluminium, then the
silicon doping required to meet the specification
is
– Q’
(a) 3.421014cm–3 (b) 2.281014cm–3
M O S
(c) 2.28104cm–3 (d) 3.43104cm–3
What is the type of semiconductor and mode of
biasing ? Common Data For Q. 10 and 11 :

(a) n-type, depletion (b) n-type, inversion An ideal MOS capacitor with an aluminium
gate has a silicon dioxide thickness of tox =
(c) p-type, depletion (d) p-type, inversion 400 A on a p-type silicon substrate doped with
Common Data for Q. 5 and 6 : an acceptor concentration of Na = 1016cm–3.

Consider a p-type silicon semiconductor of an 1 0 . The oxide capacitance, Cox will be

MOS structure. Let T = 300 K and assume Na (a) 8.6310–8F/cm2 (b) 5.5710–9F/cm2
= 1016cm–3.
(c) 3.4510–5F/cm2 (d) 2.2110–8F/cm2
5 . The maximm space charge width, xdT is
1 1 .The flat-band capacitance, C FB will be
(a) 0.30 m (b) 310–12 cm
(a) 2.5210–7F/cm2 (b) 6.4310–8F/cm2
(c) 0.18 m (d) 1.8810–12 cm
(c) 1.6510–8F/cm2 (d) 4.2310–9F/cm2
6 . The maximum space charge density
|QSS(max)|is Common Data For Q. 12 and 13 :

(a) 2.1910–4C/cm2 (b) 410–3C/cm2 A MOSFET has the following parameters :

n+poly gate, tox = 80 A, Nd = 1017cm–3, Qss =

GATE MASTERS PUBLICATION

 Metal Oxide Semiconductor (MOS) Capacitor 271
51010cm–2 and ms = –20.32 V 1 6 .What is the value of ND ?

1 2 .What is the threshold voltage of this MOSFET (a) 2.451019/cm3 (b) 2.45109/cm3

(a) –1.53 V (b)–0.32 V (c) 7.291014/cm3 (d)7.29104/cm3

(c) –1.21 V (d)–0.814 V 1 7 .Complete the following table making use of the
ideal sturcture C-V characteristic in figure
1 3 .The device is

(a) enhancement PMOS (b) depletion PMOS C

(c) enhancement NMOS (d)depletion NMOS

a b
1 4 .Which of the following plot identify the voltage
corresponding to accumulaton (ACC), c
depletion (Depl), and inversion (INV) in ideal
n-type devices ? d e

VG
ACC Depl INV
INV Depl ACC
(a) VS (b) VS

0 VT For each of the biasing conditions named in the

VT 0
table employ letters ( a – e ) to identify the
corresponding bias point on the ideal MOS-C C-V
Depl Depl ACC INV
(c) INV ACC
VS (d) VS characteristic.

VT 0 0 VT
Bias Condition Capacitance (a–e)
Inversion
Common Dta For Q. 15 to 16 : Depletoin
Flat band
The energy band diagram for an ideal MOS-C
VG = VT
operated at T = 300 K is sketched in figure below.
Accumulation
Note that the applied gate voltage causes band
bending in the semiconductor such that EF = Ei
(a) a,c,b,d,e (b) a,c,e,d,b
at the Si – SiO2 interface and ni = 1010/cm3.
(c) e,c,b,d,a (d) a,b,c,d,e
Common Data For Q. 18 to 21 :

Figure shows the dimensional energy band

Ec
diagram for an ideal MOS-C operated at T =
E FM
300 K with VG  0. Note that EF = Ei at the
E FS Si-SiO2 interface.
Ei 0.29 eV
0.56 eV
Ei
Ec
0.29 eV
+ + x Ei 0.56 eV
0 W
EF
1 5 .What is the value of s (surface potential) ?
0.6eV
E FM E
(a) 0.29 V (b)–0.29 V
(c) 0.59 V (d)–0.59 V

GATE MASTERS PUBLICATION

 272 Electronic Devices And Circuits

1 8 .What is the vlaue of surface potential (s) ? Common Data For Q. 25 and 26 :

(a) 0.3 V (b)–0.3 V An Al-silicon dioxide-silicon MOS capacitor

has an oxide thickness of 450 A and a doping of
(c) 0.56 V (d)–0.56 V
Na = 1015cm–3. For Al-silicon dioxide junction,
1 9 .For the value of ni = 1010, the of NA is m = 3.20 V and  = 3.25 V, Eg = 1.11 eV. the
oxide charge density is Qox = 31011cm–2.
(a) 9.71014/cm3 (b) 1.0731015/cm3
2 5 .The flat-band voltage will _____ volt.
(c) 1.0731019/cm3 (d)9.71021/cm3
2 6 .What will be the threshold voltage (in volt) ?
2 0 .For the value of VG = 0.6, the value of x0 is

(a) 0.10 m (b) 0.1010–4m

Common Data For Q. 27. and 28 :
(c) 0.70 m (d)0.710–4m
An NMOS device has the following parameter
2 1 .For the value of VG = 0.6 V, what is the voltage
n+ poly gate, tox = 400 A, Na = 1015cm–3, Qox
drop (ox) across the oxide?
= 51010cm–2 and ms = 1.0 V
(a) 0.3 V (b) 0.56 V
2 7 .What is the threshold voltage, Vsss (in volt) ?
(c) 0.6 V (d)0.9 V
2 8 .What is the value of source to body voltage, VSB
2 2 .In the MOS process, structure like the gate of a (in volt) such that the threshold voltage, VT =
transistor are used to make capacitors as well. If 0?
the oxide thickness is 4 nm, what area is needed
Common Data For Q. 29 to 31 :
to achieve a capacitance of 1 pF? (the
permittivity of silicon dioxde is 3.9 o) An NMOS-C is maintained at T = 300 k, x0 =
0.1 m and the silicon doping is NA = 1015/cm3
(a) 1.1610–6cm2 (b) 3.8210–5cm2
and ni = 1010/cm3
(c) 4.5110–6cm2 (d) None of the above
2 9 .If s = F, then the depletion width (w) will be
Common Data For Q. 23 and 24 : ________ m .

A 400 A oxide is grown on p-type silicon with 3 0 .What is the value of Es (in kV/cm) when s =
Na = 51015cm–3. The flat band voltage is F ?
–0.9 V. (assume negligible oxide charge)
3 1 .If the area of the MOS-C is 310–2cm2, what
2 3 .At the threshold inversion point, the surface is the oxide thickness (x0) in m ?
potential will be ____volt.

2 4 .What will be the threshold voltage (in volt) ?



GATE MASTERS PUBLICATION