4 - Continuous Time Simulation
4 - Continuous Time Simulation
• Other Topics:
• Mixed-Signal Simulation
• Finite Element Modeling and Multi-physics
Continuous-Time Simulation
• Examples in the field of electronics include Circuit-level simulators such as SPICE,
Spectre and ADS.
• Require some model of the computational elements of the circuit and some way
of handling time.
• Circuit elements are modeled as transistors, resistors, … etc and wires with propagation delays
determined by their geometric structure and the underlying technology.
• Relies on basic physical principles and thus can be highly accurate and general.
Continuous-Time Case Study:
DAE Solver (cont.)
• Simulation begins in the node-extraction phase of static analysis.
• The node extractor provides the simulator with the capacitance and resistance of the wires, transistors, and
resistors that the design comprises of.
• Delays can then be accurately determined. These parameters are determined by the technology and the
geometric properties of the structures.
• All this information is combined to produce a system of coupled, nonlinear ordinary differential equations
(ODE).
• Mainly by applying KCL at every node.
• These are converted into differential algebraic equations (DAE) using numerical integration.
Continuous-Time Case Study:
SPICE Models
• This information is combined with built-in or user- Simplified MOS model
supplied device models.
• This is called the direct method which is often used to solve these equations:
• based on Newton's method, sparse-matrix techniques, and numerical
integration.
• Observation: a circuit can often be partitioned into several sections that do not interact very much, or that interact in a
limited fashion.
• This led to the development of a class of circuit simulators based on relaxation techniques instead of on Newton's method.
• Regardless of method chosen, this relatively expensive computation is performed for each node in the system at each time
step.
• This accounts for the relatively long running times of circuit-level simulators.
Continuous-Time Simulation:
Delay Modeling
• Two types of delay for circuits:
• Delay through "active components" and
• Delay through wires
• Circuit-level simulators inherently calculate active-component and wire delay
• Since they are normally taken into account in the equations that are solved.
• Logic-level simulators assume a simplified model of delay for efficiency
• Simplest is using a unit delay through active components and assuming zero delay through wires.
• Many variations are possible. For example a functional simulator might use a table of delays for various functional
blocks.
• The table could be based on actual observed delays from off-the-shelf components.
• Relatively complex logic-level simulators combine delay models with the simplification provided in assuming a fixed set of
logic levels.
• For example, RSIM uses a linear model of transistors to determine delay and final logic values for each node. The
model takes into account the capacitance at each node and the drive capabilities, and is carefully tuned for each
technology so that accurate results are obtained.
Continuous-Time Simulation:
Delay Modeling (cont.)
• For simple delay models, such as a unit-delay or table-driven approach,
• the simulator needs only the connectivity of the circuit and the type of each node.
• When accurate circuit delays are required,
• a more complex delay model is used.
• These delay models approximate the fine-grain behavior of nodes and wires.
• The time that it takes a wire to change state, say from near 0 volts to near 5 volts, is
determined by the resistance R and capacitance C of the wire.
• The delay depends exponentially on the product RC.
• Thus, the simulator must be given the resistance and capacitance of each node and wire, in
addition to device type and connectivity information.
Continuous-Time Simulation:
Delay Modeling (cont.)
• The RC information is calculated in the node-extraction phase of design analysis.
• Consider a wire made of polysilicon in a MOS technology.
• The resistance is determined by its volume and the resistivity of the polysilicon.
• The resistivity of the material and the depth of the wires are fixed for a particular
implementation process. The node extractor only calculates length and width.
• Similarly, the capacitance depends on wire area, separation from the underlying substrate,
and the permittivity of the insulator.
• The separation distance and the permittivity are fixed for the implementation process.
• Non-planar technologies such as bipolar may also require complex calculations to determine
the resistance and capacitance of nodes and wires. As usual, the cost is time.
Continuous-Time Simulation:
Other Modeling Details
• Noise.
• Temperature.
• High-order modal modeling.
• Electrostatic Effects.
• Parasitic Resistance, Capacitance,
Inductance.