Computer Engineering Dushyant Rathod (210280107541) : Practical: - 4

Computer Engineering Dushyant Rathod (210280107541)
Practical: - 4
Aim: Write Assembly language Program to implement subtraction between two number
using 2's complement - in GNU Simulator
Theory:
In 8085, the SUB instruction is used 2’s complemented method for
subtraction. When the first operand is larger, the result will be positive. It will not
enable the carry flag after completing the subtraction. When the result is negative,
then the result will be in 2’s complemented form and carry flag will be enabled.
We are using two numbers at location 8000H and 8001H. When the numbers are
78H and 5DH, then the result will be (78 – 5D = 1B) and when the numbers are
23H and CFH, then the result will be (23 – CF = 154) Here 1 indicates the number
is negative. The actual result is 54H. It is in 2’s complemented form.
Instructions:
LDA 2050H
MOV B,A
LDA 2051H
CMA
INR A
ADD B
STA 2052H
HLT
L D COLLEGE OF ENGINEERING Page 1


Practical: - 5
Aim: Write Assembly language Program to implement Multiplication Algorithm between

two numbers - in GNU Simulator (Using Circular Right and Circular Left Instruction)
ss
Theory:
1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.

2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is
continuously decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the incremented bit of Qn
by 1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be checked on the
following parameters as follows:
0. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the arithmetic
shift right operation (ashr) to the partial product AC. And the bits of Qn and Qn
+ 1 is incremented by 1 bit.
i. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M) will be
added to the AC (Accumulator register). After that, we perform the right shift
operation to the AC and QR bits by 1.
ii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M) will be
subtracted from the AC (Accumulator register). After that, we perform the right
shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.
Instructions:
MVI C,08H
LXI H,2052H
UP: STC
CMC
LDA 2051H
RAR
STA 2051H
JNC ZRO
LDA 2050H
ADD M
STA 2052H

STC
CMC
ZRO: LDA 2050H
RAL
STA 2050H
DCR C
JNZ UP
HLT

Practical: - 6
Aim: Implement the flowchart of signed magnitude Addition and subtraction in logisim
Simulator
 The two signs A, and B, are compared by an

 exclusive-OR gate.
 If the output of the gate is 0 the signs are identical;
 If it is 1, the signs are different.
 For an add operation, identical signs dictate that the magnitudes be added. For a
 subtract operation, different signs dictate that the magnitudes be added.
 The magnitudes are added with a microoperation EA  A + B, where EA is a register that
 combines E and A. The carry in E after the addition constitutes an overflow if it is equal
 to 1. The value of E is transferred into the add-overflow flip-flop AVF.
 The two magnitudes are subtracted if the signs are different for an add operation or
 identical for a subtract operation. The magnitudes are subtracted by adding A to the 2's
 complemented B. No overflow can occur if the numbers are subtracted so AVF is cleared
to 0.

 1 in E indicates that A >= B and the number in A is the correct result. If this numbs is zero,
 the sign A must be made positive to avoid a negative zero.
 0 in E indicates that A < B. For this case it is necessary to take the 2's complement of the
value in A. The operation can be done with one microoperation A A' +1.
 However, we assume that the A register has circuits for microoperations complement and
increment, so the 2's complement is obtained from these two microoperations.
 In other paths of the flowchart, the sign of the result is the same as the sign of A. so no
change in A is required. However, when A < B, the sign of the result is the complement of
 the original sign of A. It is then necessary to complement A, to obtain the correct sign.
 The final result is found in register A and its sign in As. The value in AVF provides an
overflow indication. The final value of E is immaterial.
 Figure shows a block diagram of the hardware for implementing the addition and
 subtraction operations.
 It consists of registers A and B and sign flip-flops As and Bs.
 Subtraction is done by adding A to the 2's complement of B.
 The output carry is transferred to flip-flop E , where it can be checked to determine the
relative magnitudes of two numbers.
 The add-overflow flip-flop AVF holds the overflow bit when A and B are added.
 The A register provides other microoperations that may be needed when we specify the
sequence of steps in the algorithm.
Practical: - 7
Aim: Implement the flowchart of signed magnitude multiplication in logisim Simulator


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Computer Engineering Dushyant Rathod (210280107541)

L D COLLEGE OF ENGINEERING Page 1

L D COLLEGE OF ENGINEERING Page 2

Aim: Write Assembly language Program to implement Multiplication Algorithm between

1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.

L D COLLEGE OF ENGINEERING Page 3

L D COLLEGE OF ENGINEERING Page 4

 The two signs A, and B, are compared by an

Computer Engineering Dushyant Rathod (210280107541)

L D COLLEGE OF ENGINEERING Page 5

Computer Engineering Dushyant Rathod (210280107541)

Aim: Implement the flowchart of signed magnitude multiplication in logisim Simulator

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