Module 1

NUMBER REPRESENTATION

An n-bit vector B is represented in binary number system as bn-1bn-2……..b1b0.

A signed number can be represented in any of the following systems

 Sign and Magnitude form

 1’s Complement form
 2’s Complement form

Introduction to CPU arithmetic

Representation of Signed Number

If we want to represent a negative number in binary format, one way of doing this is use a
sign bit. A sign bit is usually used with a binary number of a fixed number of bits and is always
the bit furthest to the left of the binary number.

Sign-Magnitude Representation
The most significant bit of the number to indicate the sign. Use the same representation
as positive number, but with 1 for the sign bit.
Eg.
Using 8 bits
5 0 0000101
-5 1 0000101
Addition and Subtraction operations on these numbers are hard .

Signed Number Arithmetic

a) 1's Complement Addition

Add two numbers and if carry occurs then the carry is added to the result.

b) 1's Complement Subtraction

Take the 1’s complement of the subtrahend
Add to the minuend
If carry occurs then add carry to the result.
Example 1: consider 35 - 22 both represented as 7-bit numbers with a sign bit.
+35 in binary is: 00100011
+22 in binary is: 00010110
-22 in binary is: 10010110
 -22 in 1's complement is: 11101001

The sum to be calculated is therefore the sum of the binary for +35 and the 1's
complement for -22:

00100011
+ 11101001
---------------
100001100
This addition produces a 9th bit. In 1's complement addition, if this occurs, the extra bit is
carried to the LSB column and added. Hence:
00001100
+1
-----------------
00001101
The final answer has a 0 for its sign bit. This tells us two things:
 the answer is positive
 the answer is represented in binary notation
The answer is the positive binary number 0001101=1310.

Example 2: 22 - 35, again both represented as 7-bit numbers with a sign bit.
+22 in binary is: 00010110
+35 in binary is: 00100011
-35 in binary is: 10100011
-35 in 1's complement is: 11011100

The sum to be calculated is below

00010110
+ 11011100
----------------
=11110010
This time the addition does not produce a 9th bit, but the sign bit is 1. In this case it again
tells us two things:
the answer is negative
the answer is represented in 1's complement notation
So to get the final answer we need to turn our answer into binary. If the 1's complement notation
is 11110010 then the binary representation is 10001101 (note - the sign bit doesn't change, it's
still a negative number!). This is the binary for -13.

2's Complement Subtraction

 Take the 2’s complement of the subtrahend
Add to the minuend
If carry occurs then discard the carry.
A situation occurs because the magnitude of the results of arithmetic operations has become
too large for the fixed word length of the computer to represent them properly.
(If the result is out of the range then overflow occurs.)
Serial & Parallel Adder
Adders are the basic building blocks of all the arithmetic circuits, adders add two binary
numbers and give out sum and carry as output. Basically we have two types of adders.
Half adder and Full adder.

BCD Adder
In the BCD representation system each digit is encoded into its binary equivalent with
four (4) bits.
BCD Adder Design
When we add two BCD numbers we can get sum ranges from 0-19. Consider a 4 bit binary adder
the adder output named K (carry output) P3P2P1P0 . if this out put is lass than or equal to 9 then
that is a valid BCD number. If it is greater than 9 there should be some corrective action taken.
This circuit is given below. And the out put of the corrective
network named as CoutZ3Z2Z1Z0

If KP3P2P1P0=CoutZ3Z2Z1Z0 there is no corrective procedure is needed. On the other

hand when two decimal is added and the adder produce the output KP3P2P1P0= 01010,
01011,……10011which corresponds to decimal sums of 10 through 19, corrective action
must be taken to get appropriate values for CoutZ3Z2Z1Z0.
Following table shows the corrective action
Multiplication

Rules of Binary Multiplication

0x0=0
0x1=0
1x0=0
1 x 1 = 1, and no carry or borrow bits
For example,

00101001 × 00000110 = 11110110

0 0 1 0 1 0 0 1 = 41(base 10)
× 0 0 0 0 0 1 1 0 = 6(base 10)
---------------------------------------
=0 0 1 1 1 1 0 1 1 0 = 246(base 10)
A number of methods exist to perform integer multiplication.
1. Repeated addition: add the multiplicand to itself “multiplier” times.
2. Shift and add -- traditional “pen and paper” way of multiplying (extended to binary
format)
3. High speed (special purpose) hardware multipliers

Figure shows the hardware implementation of multiplication

The circuit has a register Q to hold the multiplier, a register M to hold the multiplicand, a
register A and a flip flop C which is initially cleared to 0. It also consists of an n-bit adder
and a control sequencer. One of the inputs to the adder is the contents of register A and
the other input is either the contents of register M or a 0. The bit q0 determines whether
an add or a no add operation should take place. If the bit q0 is a 1 the multiplexer selects
the contents of register M as one of the inputs to the n-bit adder, the control sequencer
issues an add signal, the addition is performed and the result is stored back in register A.
The contents of C, A and Q is shifted one bit position right. If the bit q0 is a 0 no addition
is performed, but shifting takes place. This should be repeated n times for multiplying
two n bit numbers. The final product will be in registers A and Q after n cycles.

Example
Array Multiplier

Binary multiplication of positive operands can be implemented in a combinational two

dimensional array.

Each cell in the figure is a combination of AND gate and a Full Adder. A typical cell is
given in the following figure.
The AND gate in each cell determines whether a multiplicand bit mj is added to the
incoming partial product bit, based on the value of the multiplier bit qj. Each raw i adds
the multiplicand to the incoming partial product ppi to generate pp(i+1) if qi=1. If qi=0
ppi is passed downward unchanged.

The AND gate in each cell determines whether a multiplicand bit mj is added to the
incoming partial product bit, based on the value of the multiplier bit qj. Each raw i adds
the multiplicand to the incoming partial product ppi to generate pp(i+1) if qi=1. If qi=0
ppi is passed downward unchanged.
Signed Multiplication-Booth’s Algorithm
If two operands are unsigned numbers multiplication is easy. But any of the number is
negative normal multiplication will not work. Example of signed number multiplication is given
below.
The possible solutions are
Solution 1
Convert to positive if required
Multiply as above
If signs of both operands were different, take the 2’s complement of the result.
Solution 2
Booth’s algorithm
Booth algorithm uses the following principle
2n+2n-1+……………2n-k= 2n+1-2n-k
So the product can be generated one addition and one subtraction of the multiplicand.
This scheme extends to any number of blocks of 1s in the multiplier.
Eg:, M*(01111010)=M*(+1 0 0 0 -1 +1 -1 0)
In general the Booth scheme, when moving from 0 to 1 then -1 is selected and moving
from 1 to 0 then +1 is selected as the multiplier scanning from left to right. This
algorithm clearly extends to any number of blocks of 1s in a multiplier, including the
situation in which a single 1 is considered as a block. If the first bit is 1 then consider the
previous bit is 0.
Advantages of Booths algorithm
Treats positive and negative numbers uniformly.
String of 1’s and 0’s can be skipped with shift operation for faster execution.
Example:
Let the multiplicand A=110011 and multiplier B=101100.

Flow Chart
The Multiplicand is placed in M register and multiplier is loaded into register Q.
Registers A and Q-1 is cleared initially. A bit of multiplier is examined together with the
bit in Q-1. If these bits are same (0-0,1-1) then all bits of A,Q,Q-1 are shifted right 1 bit. If
two bits are differ then the multiplicand is added to or subtracted from A depending on 0-
1 or 1-0 then right shift occurs. In either case the right shift An-1 to An-2 occurs and An-1
maintains the same bit for maintaining the sign. This is called Arithmetic shift.

Example
 Division
Unsigned Division

Consider the following example of unsigned number division.

Restoring Division

Register A is initially loaded with 0 and it consists of n+1 bits, where n is the number of
bits in the dividend. Dividend is loaded in register Q and Register M is loaded with the divisor.
After division is complete n bit quotient is in register Q and remainder is in register A. extra bit
on A and M accommodates the sign bit during subtractions.
Algorithm:

Do the following n times

1) Shift A & Q left one bit
2) Subtract M from A and place the result back to A.
3) If the sign of A is 1 then set q0 to 0 and add M back to A,
otherwise set q0 to 1.

Flow Chart
Example:
A= 000000, M=00011, Q=1000

Quotient=0010 in Register Q, Remainder=0010 in Register A

Non restoring Division
In this method restoring can be avoided

Algorithm:

Step 1: Do the following n times

a) If the sign of A is 0 , then shift A &Q left one bit and subtract M from A,
otherwise shift A &Q left one bit and add M to A
b) If the sign of A is 0 then set q0 to 1, otherwise set q0 to 0.
Step2: If the sign of A is 1 then add M to A.
Step2 is needed to leave the proper positive remainder in A at the end of n cycles of step
1.
Example: Example: 1000/11
A= 000000, M=00011, Q=1000

Quotient=0010 in Register Q
Remainder=11111 in Register A is negative, so restore the remainder by perform
A+M=11111+00011=0010

Hardware circuit non restoring and restoring division is same.

Signed Division
Algorithm:
Step 1: Load divisor into M register and dividend into Q register.
Step 2: Shift A, Q left 1 bit position.
Step 3: If M and A have – same signs, perform A ← A – M
– otherwise, A ← A + M
Step 4: Preceding operation is successful if sign of A is same before and after operation.
– If operation is successful or A=0, then Q0←1.
– If operation is unsuccessful and A≠0, then Q0←0 and restore previous
value of A.
Step 5:. Repeat steps 2 through 4 as many times as there are bit positions in Q.
Step 6: Remainder is in A.
– If sign of divisor and dividend are same, quotient is in Q.
– Otherwise, correct quotient is twos complement of Q.

Example: 7/(-3)

Quotient=0010 in Register Q
Remainder is in register A=0001
Quotient=0010 in Register Q but the sign of divisor and dividend are different so the
actual quotient is 2’s complement of (Q) = 1110
 Second module

Arithmetic operations on floating Point Numbers

Floating point numbers based on the scientific notation and is capable of representing
very large and very small numbers without increase the number of bits and also used to
represent the numbers has both fractional and integer part (real numbers). For example,
123.456 could be represented as 1.23456 × 102. In hexadecimal, the number 123.abc
might be represented as 1.23abc × 162. General form is M*2E

IEEE standard for floating point representation

IEEE Standard 754 floating point is the most common representation today for real
numbers on computers. IEEE floating point numbers have three basic components:
the sign,
the exponent, and
the mantissa.
Mantissa is also known as the significant is the magnitude of the number.
Exponent is the number of places the decimal point (binary point) is to be moved.
Sign bit denotes the sign of the number. 0 denotes a positive number and 1
denotes a negative number.
IN IEEE standard there are three forms to represent the floating point numbers.
Single precision
Double precision
Extended precision
Instead of signed exponent E, the value E is represented as a biased exponent E’. Bias is
chosen to be large enough to convert to every integer in the range to a positive number.
For single precision, the exponent field is 8 bits, and has a bias of 127.
So the range of the number that can be represented is 0<=E’<=255 and -126<=E<=127.

For double precision, the exponent field is 11 bits, and has a bias of 1023.
So the range of the number that can be represented is 1<=E’<=2046 and
-1022<=E<=1023.

When the decimal point is placed to the right of the first significant digit, the
number is said to be normalized.
In normalized form the number representation is (-1)S (1+M) 2E’-127 As computation proceed,
a number that does not fall in the representable range of normal numbers might be generated. In
single precision form if exponent <-126 then underflow occurs and exponent >127 then overflow
occurs.
Special Cases:
1) E’=0 and M=0 Value 0 is represented
2) E’=0 and M!=0 Denormal number is represented (number smaller than smallest normal
number=0.M*2-126)
3) E’=255 and M=0 Value α is represented
4) E’=255 and M!=0 Not a Number (Invalid Operation)

Arithmetic operations on floating Point Numbers

a) Add/Subtract Rule
1) Choose the number with the smallest exponent and shift its mantissa right n times where n is
the difference between the exponents.
2) Set the exponent of the result as that of the larger exponent.
3) Perform addition or subtraction on the mantissa and determine the sign of the result.
4) Normalize the resulting value if necessary.
Flowchart

b) Multiply Rule
1) If any exponent is zero then result=0.
2) Else add the exponents and subtract 127.
3) Multiply the mantissas and determine the sign of the result.
4) Normalize & round the resulting value if necessary.
 Flowchart for multiplication

Divide Rule
1) Check for zero if divisor is 0 then divide error Else dividend is 0 then result is 0.
2) Else subtract the exponents and add 127.
3) Divide the mantissas and determine the sign of the result.
4) Normalize and round the resulting value if necessary
Flowchart for division

The hardware circuit for Floating point addition-subtraction unit is given

below.
Hardware implementation for division

In step 1, compare the exponent to determine how far to shift the smaller exponent. Shift
count value n= EA’-EB’ is determined by the subtractor unit. The value n is sent to the shifter
unit. The sign of the difference determine which mantissa to be shifted. The sign sent to the
Swap circuit. If the sign is 0 then EA’> EB” and mantissa MA and MB are sent straight through
the swap network. MB sent to the shifter unit and shift n times right.MA sent directly to the
adder/sub unit. If the sign is 1 then EA’< EB’ and mantissa swapped and sent to the shifter.
In step 2, the exponent of the result E’ is determined as EA’ if EA’>=EB’ or EB’ if EA’<EB’
based on the difference resulting from comparing exponent in step 1.
In step 3, the control logic determines whether the mantissas are to be added or subtracted. This
is decided by the sign of the operands and the operation that is to be performed on the operands.
The control logic also determines the sign of the result SR.In step 4, normalize the result. The
number of leading zeros in M determines the number of bit shift X to be applied to M. The
normalized value is rounded to generate the 23 bit mantissa MR. The value X is subtracted from
E’ to generate the correct exponent ER’.
ALU design
ALU is a multi operation combinational circuit. It can perform a set of arithmetic and
logic operations using K select lines. Using K select lines it can perform 2k operations.
Consider the block diagram of 4 bit ALU.

A ns B are the inputs. S2= mode select ( select the arithmetic or logic operation)
S1 S0 specifies the operation to be performed. S0 S1 and Cin combine to generate 8
operations.
Design of ALU has 3 stages.
1) Design the arithmetic section independent of the logic section
2) Determine the logic operations obtained from the arithmetic circuit in step 1,
assuming that the input carries to all stages are 0.
3) Modify the arithmetic circuit to obtain the required logic operations
1) Design of Arithmetic circuit
The basic component in the ALU is a Parallel adder.
Consider the above figure we obtain the following 8 functions.

Logic diagram
2) Design of Logic circuit
Using the same 2 select lines we can perform 4 logic operations. The Function table of
logic operations is given below.

Design the circuit according to the function table.

3) The logic circuit can be combined with arithmetic circuit to produce the ALU.
Selection variables S0 S1 are common to both sections. Third selection variable S2 is
used to differentiate the arithmetic or logic operations.
 Module 3

CONTROL UNIT
The processor fetches one instruction at a time and performs the operation specified.

Instructions are fetched from successive memory locations until a branch or a jump
instruction is encountered. The processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program Counter (PC).

For executing an instruction, the following steps are done

 Fetch the contents of the memory location pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]

 Assuming that the memory is byte addressable, increment the contents of the PC by 4
(fetch phase).
PC ← [PC] + 4

 Carry out the actions specified by the instruction in the IR (execution phase).
 Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines
Carry-in
XOR TEMP

. HARDWIRED CONTROL

To execute instructions, the processor must have some means of generating the control
signals needed in the proper sequence. The two categories are hardwired control and
microprogrammed control. Hardwired system can operate at high speed; but with little
flexibility.
 CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

.
 In a hardwired organization, the control logic is implemented with gates, flip-flops,
decoders and other digital circuits. Hardwired control received its name because the control was
implemented in hardware and could not be easily changed. A hardwired control as the name
implies, requires changes in the wiring if the design has to be modified or changed. The control
unit is implemented as a state machine, with combinatorial circuits generating each of the control
functions on the basis of the current state and certain variables such as the op-code of the user
instruction undergoing execution. Its input logic signals are transformed into output logic signals
which are the control signals. A hardwired control unit must contain complex logic for
sequencing through the many micro-operations of the instruction cycle.
The hardwired implementations were faster, but too costly for most machines. It has the
advantage that it can be optimized to produce a fast mode of operation. The situation that arises
when the control unit is require to check the status of the condition or status flags in order to
choose between alternative courses of action; the hardwired control will handle this situation by
including an appropriate logic function like; End=T7.ADD + T6.BR+(T6.N+T4.N). BRN +… in
the encoder circuitry. For a given level of technology, hardwired control will be faster, since
there is no delay for microinstruction fetch from ROM before the control unit can produce a
control word.
MICROPROGRAMMED CONTROL

In microprogrammed control, a program generates the control signals. A control word (CW) is a
word whose individual bits represent the various control signals. A sequence of CWs
corresponding to the control sequence of a machine instruction constitutes the micro routine for
that instruction, and the individual control words in this micro routine are referred to as
microinstructions. The micro routines for all instructions in the instruction set of a computer are
stored in a special memory called the control store. The control unit can generate the control
signals for any instruction by sequentially reading the CWs of the corresponding micro routine
from the control store. To read the control, words sequentially from the control store, a micro
programmed counter is used.

Basic organization of a micro programmed control unit

Every time a new instruction is loaded into the IR, the output of the block labeled “starting
address generator” is loaded into the PC. The PC is then automatically incremented by the
clock, causing successive microinstructions to be read from the control store. Hence, the control
signals are delivered to various parts of the processor in the correct sequence.
To support micro program branching, the organization of the control unit should be modified.
The starting and branch address generator loads a new address into the PC.
To allow implementation of a conditional branch, input to this block consists of the external
inputs and condition codes as well as the contents of the instruction register. In this control unit,
the PC is incremented every time a new microinstruction is fetched from the micro program
memory, except in the following situations:

 When a new instruction is loaded into the IR, the PC is loaded with the starting address
of the micro routine for that instruction.
 When a branch microinstruction is encountered and the branch condition is satisfied, the
PC is loaded with the branch address.
When an End microinstruction is encountered, the PC is loaded with the address of the first CW
in the micro routine for the instruction fetch cycle

Micro program Sequencing

If all microprograms require only straightforward sequential execution of microinstructions

except for branches, letting a μPC governs the sequencing would be efficient. However, there are
two disadvantages:
  Having a separate microroutine for each machine instruction results in a large total
number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the required branches.
Example: Add src, Rdst

It has four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect
forms).

IR

External Condition
Inputs codes

Decoding circuits

AR

Control store

Next address I R

Microinstruction decoder

Control signals

.
Microinstruction sequencing organization