Beee Unit-Ii
Beee Unit-Ii
Beee Unit-Ii
1 Introduction
active and passive components are
The term IC meansintegrated circuit where all the
are produced by the monolithic process. In
fabricated on the same chip. Most of the ICs
elements like
this process, all the active elements like transistors and all the passive
on a single piece of semiconductor material,
resistances, capacitances are fabricated
or a substrate. Such a monolithic process
generally silicon. This is called silicon water
makes low costmass production of ICs possible.
With the help of ICs the circuit design becomes very simple. The variety of useful
circuits can be built without the necessity of knowing about the complex internal
circuitry. The components used in ICs have different look than the corresponding
conventional components but their electronic functioning is same, infact more reliable.
1. Small size:
Practically size of an IC is thousands of times smaller than the discrete circuit.
2. Low cost:
6. Highly reliable
Due to absence of soldered connections and less interconnections, the ICs are
highly
reliable from the pertormance point of view. Due to low power consumption, the
temperature rise of ICs is also low which further increas s the reliability, accuracy and
IC package
P
Metal can Dual-in-tine Flat pack
(TO) (DIP
TOongist Fig
Straight
leads
Dual-in-line
formed leads Radial formed
leads
10 lead version
terminal V EE V.
ii The negative supply voltage or
- -
t VEE Noninverted
output in phase with
input
The op-amp is fabricated on a tiny silicon chip and packaged in a suitable case. Fine
gauge wires are used to connect the chip to the external leads.
Input 2
Intermediate Buffer and level Output Output
Input
stage stage shifting stage stage
Input1+
The output of the input stage drives the next stage which is an intermediate stage.
This is another differential amplifier with dual input, unbalanced ie. single ended
output. The overall gain requirement of the op-amp is very high. The input stage alone
cannot provide such a high gain. The main function of the intermediate stage is to
provide an additional voltage gain required. Practically, the intermediate stage is .not a
single amplifier but the chain of cascaded amplifiers called multistage amplifiers.
2.8.3 Level Shifting Stage
All the stages directly coupled to each other. As the op-amp amplifies d.c. signals
are
i0s
ViosIVdet-Vacel
Vdot
Small O Output
741
o
o output
voltage Vios 741
of 9 voltage
is zero
present
Vdc2
(a) (b)
The Vios Ccan be positive or negative hence absolute value of the Vios is mentioned in
the data sheet.
The smaller the value of Vios, better is the matching of the input terminals.
The input offset voltage depends on the temperature.
Many time voltage to one of the
input terminals is applied with the proper polarity
so as to null the
output, keeping other input terminal grounded. For ideal op-amp, Vios
is zero, hence
practical op-amp model is generally shown as in the Fig. 2.32 with the
indication of the input offset
voltage. For op-amp 741C the input offset voltage is 6 mV.
ldeal
op-amp
O-
Practical
op-amp
-Op-amp
Input
b1
1
Input
2
. . .
difference between the currents flowing into the two input terminals of
The algebraic
offset current and denoted os Mathematically it is
the op-amp is called input as
expressed as,
Iios |Ib1-Ib2l
Where Ipi Current entering into noninverting input terminal.
I Ib1+Ib2
2
value of h, is 500 nA.
Ideally it should be zero while for op-amp 741C, maximum
2.13.4 Differential Input Resistance
It is the ratio of output voltage to the differential input voltage, when op-amp is in
without any feedback. It is also called large signal voltage gain
open loop configuration,
and denoted as AoL
Va
AOL
Va
For op-amp 741C, it is typically 200,000.
2.13.7 CMRR
It is the ratio of differential voltage gain Ad to the common mode voltage gain A.
CMRR =Ad
Ac
the
but open loop voltage gain AoL and A, is measured by using
Now Ad is nothing
circuit as shown in the Fig. 2.35.
to both the input terminals of op-amp. Then
The common mode input Ve is applied
mode gain A. can be obtained as,
output Voc is measured. Then
common
the
VOc
NcC
Common
Noc
741 o Output
mode input for
common
mode input
v.O NEE
It is generally very small and not specified in the data sheet. The CMRR is generally
for the op-amp and is expressed in dB. For op-amp 741C it is 90 dB.
specified
Key Point Higher the value of CMRR, better is the ability of the op-amp to reject the
common mode signal.
Thus note that the op-amp output voltage gets saurated at +Vcc and - VEE and
it can not produce output voltage more than + Vcc and - VE Practically
saturation voltages +Vsat and - Vsat are slightly less than +Vcc and - VEE
For op-amp 741C, the saturation voltages are t 13 V for supply voltages t 15 V. Thus
it can produce undistorted sine wave of the maximum amplitude 13 V, for a.c. input
applied to it.
in V/usec. Thus
The slew rate is specified
dVo 0)
Slew rate = S =
.
dt max
The slew rate is caused due to limited charging rate of the compensating capaciter-
of an op-amp, when a high
and current limiting and saturation 'of the internal stages
The internal capacitor voltage cannot
frequency, large amplitude signal is applied.
For large charging rate, the capacitor
change instantaneously. It is given by dt
should be small or charging current should be large.
Hence the slew rate for the op-anmp whose maximum internal capacitor charging
current is known, can be obtained as
1) no loading on
drive it and there is
its input impedance is infinite. Any source
can
3) The output voltage Vo is independent of the current drawn from the output
terminals. Thus its output impedance is zero and hence output can drive an infinte
number of other circuits.
These properties are expressed generally as the characteristics of an ideal op-amp. 1e
op-amp.
The input impedance is denoted as Rin and is infinite for an ideal op-amp. This
ensures that no current can flow into an ideal op-amp.
The output impedance is denoted as Ro and is zero for an ideal op-amp. This ensures
that the output voltage of the op-amp remains same, irrespective of the value of the load
resistance connected.
The range of frequency over which the amplifier performance is satisfactory is called
its bandwidth. The bandwidth of an ideal op-amp is infinite. This means the operating
frequency range is from 0 to o This ensures that the gain of the op-amp will be
constant over the frequency range from d.c. (zero frequency) to infinite frequency. So
op-amp can amplify d.c. as well as a.c. signals.
Infinite CMRR : (p = o)
The ratio of differential_gain and common mode gain is defined as CMRR. Thus
infinite CMRR of an ideal op-amp ensures zero common mode gain. Due to this
common mode noise output voltage is zero for an ideal op-amp.
step type which changes instantaneously then the output also must change rapidly as
input changes. If output does not change with the same rate as input then there occurs
distortion in the output. Such a distortion is not desirable. Infinite slew rate indicates
that output changes simultaneously with the changes in the input voltage.
The parameter slew rate is actually defined as the maximum rate of change of output
h) No effect of temperature:
The characteristics of op-amp do not change with temperature.
The power supply rejection ratio is defined as the ratio of the change in input offset
voltage due to the change in supply voltage producing it, keeping other power supply
voltage constant. It is also called power supply sensitivity.
So if is constant and due to
VEE change in Vcc there is change in input offset voltage
then PSRR is expressed as,
A A Vios
PSRR A ccIVEE Constant
PSRR = 4 Vios
A VEE
IvC Constant
It is expressed in
mV/V or uV/V and its ideal value is zero.
These ideal characteristics of
op-amp are summarized in the Table 2.5.
V
Bandwidth B.W.
C.M.R.R.
Slew rate
S
Power supply rejection ratio
PSRR 0
Table 2.5 ldeal
op-amp characteristics
2.16 Voltage Transfer Curve of Op-amp
The graph of output voltage Vo plotted against the differential input voltage Va i
aceiuming gain constant is called voltage ransfer curve or characteristics of op-amp.
loop gain of
Ideally open
VAoLVd
op-amp is oo,
AoL Vo
Va oc
N sat
Va Vo 0 Ao
N
Thus for zero input, the output
of op-amp is always at saturation VsattVcc
level Vsat due to infinite gain. N sa
Thus voltage transfer curve for
ideal op-amp is a vertical line as
shown in the Fig. 2.41.
Fig. 2.41 ldeal voltage transfer curve
Practically AoL is finite for the op-amp. For op-amp 741C, it is 2x10°.
V = AoL Va
tVsat 2x10 Vd
The saturation voltages are almost t 15 V.
t15
Va = t 75 V
2x10
Hence practically till Va is between - 75 uV and + 75 uV, the output will vary
linearily with input. But once V exceeds t 75 uV, the output is saturated.
is shown in the Fig. 2.42.
Thus the practical voltage transfer curve as
V
+Vsat
a b
N -+Vd
Nsat
Fig. 2.42 Practical voltage transfer curve
Thus,
i) If Va is greater than corresponding to b, the output attains +Vsat
ii) If Va is less than corresponding to a, the attains
output -
Vsat
ii)Thus range a-b is input range for which output varies linearily with the input. But
bul
as
Ao is very high, practically this range is very small.
DIOC
op-amP
1.2 Basics of Differential Amplifier
Key Point The differential amplifier amplifies the difference between wo input voltage
signals. Hence it is also called difference amplifier.
Vo = Ad (V1 - V2)
...(2)
VoAd Vd
can be expressed as,
Hence the differential gain
..(4
Vo
AdVd
Generally the differential gain is expressed in its decibel (dB) value as,
Ad 20 Log10 (A d) in dB .(5)
But the output voltage of the practical differential amplifier not only depends on the
difference voltage but also depends on the average common level of the two inputs
Such an average level of the two input signals is called common mode signal denoted
as V
Ve = +V2 ...(6)
2
Practicaliy, the differential amplifier produces the output voltage proportional to such
common mode signal, also.
Key Point The gain with which it amplifies the common mode signal to produce the output
is called common mode gain of the differential amplifier denoted as A
Vo AVe ...(7)
Thus there exists some finite output for V1 =
V2 due to such mode
common gain A
in case of practical differential amplifiers.
So the total output of any differential
amplifier can be expressed
V Ad Va +Ac Ve (8)
This shows that if input is 25
one
uV and other is -25 V then the output of the
+
amplifier will not be same, with the inputs as 600 uV and 650 uV, though the difference
between the two sets of the
inputs is 50 uV.
Key Point For an ideal differential amplifier, the differential gain A4
the mode
must be infinite while
common gain must be zero. This ensures zero output for V1 =
V2
But due to mismatch in the internal circuitry, there is
output available for some
V =
V2 and gain A, is not
practically The value of zero.
such common mode
small while the value of
gain Ac is
very very the differential gain
Ad always very large.
is
At this stage, we can define ore
important parameter of the differertial amplifier
known as common mode rejection ratio
(CMRR).
TECHNICAL PUBIJCATIONG"A. 4 ,
12.3 Common Mode Rejection Ratio (CMRR)
When the same voltage is applied to both the inputs, the differential amplifier is said
operated in a
to be common mode configuration. Many disturbance signals, noise signals
appear as a common input signal to both the input terminals of the differential
It is defined as the ratio of the differential voltage gain Aj to common mode voltage
gain Ac
CMRR =
p =| A 9)
Key Point ldeally the common mode voltage gain is zero, hence the ideal value of CMRR is
inifinite.
For a practical differential amplifier Aj is large and A is small hence the value of
CMRR is also very large.
V = Ad Va+Ac Ve = Aa Va|l+A
d d
1Ve
Vo =
1+
AaVa Ad)Va
Ac
Aa . .(11)
Vo =
Va|lCMRR Va
This equation explains that as CMRR is practically very large, though both V, and Va
components are present, the output is mostly proportional to the difference signal only.
The common mode component is greatly rejected.
1.3 Transistorised Differential Amplifier
The transistorised ditterential
amplitier basically uses the emitter VcC
biased circuits which are identical in
characteristics. Such two identical
emitter biased cireuits are shown in
the Fig. 1.3.
Rc Rc2
Souce
Fig. 1.5 Differential mode operation
As e that the sine wave n the baNe ot Q
positive going while on the base of
gative going. Witlh a positive going ignal on the bare of Q, an amplified
atiye Hoing signal develops on the collector of Q Due to positive going signal,
vurtent thonngh R alO inereases and henee a positive going wave is developed across
R u e to negative going signal on the base of Q2, an amplified positive going signal
develops on the collector of Q. And a negative going signal develops across R
wuse ot emitter follower action of Q2
So signal voltages across R, due to the effect of Q and Q2 are equal in magnitude
and 180out of phase, due to matched pair of transistors. Hence these two signals cancel
ah other and there is no signal across the emitter résistance. Hence there is no ac.
current flowing through the emitter resistance. Hence R in this case does not
signal
intrduce negative feedback.
While Vo is the output taken across collector of Q 1 and collector of Q2. The two
outputs on collector 1 and 2 are equal in magnitude but opposite in polarity. And V is
the ditterence between these two signals, e,g. +10-(-10) = +20.
Re Rc
C
Rs1 Zero
Rs2
w
RE
-VEE
provides a negative feedback. This feedback reduces the commón mode gain of
differential amplifier.
While the two signals causes in phase signal voltages of equal magnitude to appear
across the two collectors of Qi and Q2. Now the output voltage is the difference
between the two collector voltages, which are equal and also same in phase,
e.g. (10) - (10) = 0. Thus the difference output Vo is almost zero, negligibly small,
ldeally it should be zero.
Re Rc Rc2 Vo
Rs Rs Rs
ww wof
Vs Vs2Vs1 Vsz
RE RE
NEE VEE
(a) Dual input balanced output (b) Dual input unbalanced output
9+Vcc +Vcc
RcZ Rc Rc
Rs1 Rs1
wwot wwoft
RE
O
NEE EE
(c) Single input balanced output (d) Single input unbalanced output
ii) Single input, balanced output differential amplifier.
Vo 10
Va 1 mV
AOL 104
(-V2) = Vo ==00
V1 = V2
.(1)
Thus we can say that under linear range of operation there is virtually short circuit
between the two input terminals, in the sense
that their voltages are same. No current flows
R R
w w - Vo
I I
from the input terminals to the ground. The
Fig. 3.1 shows the concept of the virtual ground. v Virtual
short
I = 0
I = VinVA
R
I = in ... (1)
R
Now from the output side, considering the direction of current I we can write,
VA-Vo
R
I = V (2
R
Vo R
AyF VVi in (Gain with
R feedback) . (3
Vn
(Input)
Timet
Vo Phase shift
(Output) of 180
Timet
Observations
4. If R >
R1, the gain is greater than 1
If R < R, the gain is less than 1.
5. If the ratio of R, and R is K whuch is other than one, the cireuit is called scale
changer while for R R 1 it is called phase inverter.
magnitude of output is same as that of the input but its sign is opposite to that of the
input.
Vo =Vin for R =R
VA VB =Vin (1)
From the output side we can write,
I= VA
RE
I =-Vn
RE 2
V-in=
R
Vin
R
V in.
Rr R R
R in RR
R R
pnduoS Or Op-amp
(R+Rr)Rr R+Rr
Vin R Rr R
AVF Vin=1 R
(4)
Vin
(Input)
Timet
Vo No
(Output). Phase
shift
Timet
0
3.4.1 Comparison
the ideal inverting and non-inverting
ne lable 3.1 provides the comparison of
amplifier op-amp circuits.
Ideal non-inverting amplifier
Sr. No. ldeal inverting amplifier
Voltage gain
= 1 +(R;/Ri)
Voltage gain = - Rs/R
No VA
Vo (2)
. 3)
Vo =Vin
For this circuit, the voltage gain is unity.
V-VA (2)
R1 R1
2 V2-Va2
R2 R2
(3)
I = Vo_Vo
R (5)
By properly selecting Rf, R1 and R2, we can have weighted addition of the input
signals like aV1 + bV2, as indicated by the equation (6).
VA = VB . (8)
R2
R
the current of op-amp is zero,
But as input
I +l2 =F .(10)
-VBV2
+
-V» 0
R R2
V
R R2 -V R2
=
(R V +R, V2) .(11)
(R +R2)
Now at node A,
as Vg VA (12)
R
and
VVA_ V-VB .(13)
R R
R VsRR
V R+R]
B R .(14)
R (R+Rilv+R
R (R+R2)
(R+R)
R (R+R2)
V2 (15)
The equation (15) shows that the output is weighted sum of the inputs.
R = R =R = Rf, we get
Vo V1 +V2 (16)
Key Point As there is no phase difference between input and output, it is called
1o-inverting summer amplifier.
R = R2 = R
R
and
R
Difference Amplifier Dec.-11
3.11 Subtractor or
Similar to the summer circuit, the subtraction of two input voltages is pøssible with
the help of op-amp circuit, called subtractor or differerneé ampliier circuit.
The circuit diagram is shown in the R
Fig 3.28. wW
2R
And Vo2 be the output, with input V
write,
R
R
V, w
Vo
R2
Fig. 3.29
Vol=
R RV1 ...(1)
R
w
|
R
A Vo2
R2
R
Let potential of node B is Vg. The potential of node A is same as B ie. Va =
Vg
Applying voltage divider rule to the input V2 loop,
Rr
VB R2 tRf-V2 (2)
Now I =A VB (3)
R Ri
And I = Vo2-VA Vo2-VB (4)
R R
Equating the equations (3) and (4) e
Ve Vo2-VB
Ri Rf
Vo2 +RR Ve
R
RfV
Va2 1+R V (5)
RV+|1+RRRr V2 RRV* R
RE V2
No +(V2Vi) ..(8)
Key Point Thus the output voltage is proportional to the difference between the two npu
voltages. Thus it acts as a subtractor or difference amplifier.
3.18 Integrator May-04, Dec.-04
In an integrator circuit, the output voltage is theintegration of the input voltage. The
integrator circuit can be obtained without using active devices like op-amp, transistors
etc. In such a case a n integrator is called passive integrator. While an integrator us
will diser:s
active integrator. In this section, we
an active devices like op-amp is called
integrator circuit.
the operation of active op-amp
3.18.1 Ideal Active Op-amp Integrator
Consider the op-amp integrator circuit
as shown in the Fig. 3.63.
I = Vin-VA in (1)
R RI
From output side we can write,
d (VA V,)
I = Cr
dt
dVo
I =
= -c.
dt (2)
Vin Ci dt (3)
R
Integrating both sides,
0
Rdtdt=-C
R dt dt
i.e. - dt =- C¢ Vo (4)
R
Vin dt +V,(0)
Vo R,Cr (5)
There ,(0) is the constant of integration, indicating the initial output voltage.
3.18.2 Input and Output Waveforms
For simplicityy
Let us see the output waveforms, for various input signals. o-
Vo (0) 0 V.
=
expressed as,
.(6)
Vin (t) = A for t 20 -time(t)-
0
And =0 fort <0
with RjCf = 1 and
From equation (5),
V(0) = 0, Fig. 3.65 Step input signal
We can write,
V) =-| Vin() dt = -
Adt =
- A | dt = -
A [U
0
V 0)=-At (7)
time-
Mathematically it can be expressed as, 0 T/2
This is the expression for the input Fig. 3.67 Square wave input signal
signal for one period.
As discussed earlier, the output for step
input is a straight line with a slope of -A.
So for the period 0 to T/2 output will be
V)
straight line with slope A. From t = T/2
O T/2 3T/2 2T
tillt =T, the slope of the straight line will time
V (t) =
m(-cos t) . (11)
Thus it can be seen that the output of an integrator is a cosine waveform for a input
Due to inverting integrator, the output waveform is as shown in the Fig. 3.69.
C Vi, () Vo(t)
R Step Ramp
Vin o www-
Integrator
3.20 Differentiator
Dec.-05
The circuit which produces the differentiation of the input voltage at its output is
called differentiator. The differentiator circuit which does not use any active device is
called passive differentiator. While the differentiator using an active device like op-amp
is called an açtive differentiator. Let us discuss first the operation of ideal active
op-amp differentiator circuit.
I: VAV= No
R
(2)
Rr
Equating the two equations,
d Vin
C = Vo (3)
dt R
V - C R, dVin
in . (4)
dt
The equation shows that the output is C1Rf times the differentiation of the input and
product CRf is called time constant of the differentiator.
The negative sign indicates that there is a phase shift of 180° between input and
main advantage of such
output. The an
4.1 Introduction
It is seen that op-amp in open loop configuration produces the output voltage which
is either at its positive
saturation or at its negative saturation level. This is because open
loop gain of op-amp is very large. The output saturation voltages are denoted as sat
and Vsat are usually given by,
-
+Vsat+Vcc-1V . (1)
though this property of op-amp is not suitable for linear applications, it is suitable for
various nonlinear switching circuits such as comparators, crossing detectors, Schmitt
triggers etc. Such nonlinear circuits using op-amp are discussed in this chapter. In these
circuits many timespositive feedback is used and op-amp generally does not require
any frequency compensation.
4.2 Basic Comparator
The op-amp in open loop configuration can be used as a basic comparator. When two
inputs are applied to the open loop op-amp then it compares the two inputs. Depending
upon the comparison, it produces output voltage which is either positive saturation
voltage (+ Vsat) or negative saturation voltage(- Vsat
A comparator is a circuit which
+Vcc
compares a signal VN
voltage applied at one input of an op-amp with a - Vo
known reference voltage at the other input, and
Op-amp
Vp
produce either a
high or a low output voltage,
depending on which input is higher. As comparator
-VEE
output has two voltage levels, either high or low, it is Fig. 4.1
Op-amp as a comparator
not linearly proportional to input voltage.
The op-amp as a comparator is shown in the Fig. 4.1.
Let VN = Voltage of inverting terminal
Vsat as AoL
Depending upon to which terminals, the input is applied, the comparators are
classified as,
i) Noninverting comparator ii) Inverting comparator
4.3 Basic Noninverting Comparator
Dec-11
In this comparator, the input voltage is applied to the nonin verting terminal and no
reference voltage is applied to other terminal. So inverting terminal is grounded. The
input voltage is denoted as Vin while the voltage applied to other terminal with which
V. is compared is denoted as Vref In the basic comparator, Vref = 0 V. The basic
noninverting comparator is showr. in the Fig. 4.2.
Vret 0 Ncc
+V9at for Vin> Vref
Op-amp -o Vout
-Vsat for VinVre
Vin NEE
equal to - VEE
saturates.
IS very very high even tor very small Vin the op-amp output
op-amp (Ao
are + Vsat and Vsat
-
Vin Vin
For 0-a
N sat V=+Vsat
For 0- b
V-Vsat
(a) ldeal
(b) Practical
Fia, 4.4 Transfer characteristics of basic
noninverting comparator
4.4 Inverting Comparator
Vin
p Vp
0VL 10V
Vret
-VpL -Vp
Vinreft . VinVre
*Vsat
+ sat
0V
LOV
-Vsat
sat Vin Vref V,nVre
and output waveforms for inverting comparator
Fig. 4.9 Input
is shown in the Fig. 4.10.
Transfer characteristics for inverting comparator
with + Vref
VinVref<
-Vjin
Vref
V> Vref
4.10 Transfer characteristics for inverting comparator
Fig.