Power And Delay Efficient Exact Adder For

Approximate Multiplier
Kavipranesh V V , Janarthanan J , Naga Amruth T , Harisuriya T M , Prabhu E
1, 2,3,4,5 Department of Electronics and Communication, Amrita School of Engineering, Coimbatore
Amrita Vishwa Vidyapeetham,
[email protected] , [email protected]

Abstract— Approximate results are required in many embedded utilization of the whole system should be condensed. Adders and
data processors as they reduce time delay and power. As error multipliers take the advantages of the power consumption which
tolerance adder (ETA) has decreased power drastically trading with are proposed from the past work that uses the approximate
accuracy. This work focuses on reducing delay on existing adders computing techniques. There are many power consumption models
when replaced with a fast adder. When compared to the past works for example which is given in [13] The main goal is to reduce the
on ETA, the proposed work has high power utilization and more power consumption with least time delay.
accuracy of speed. The proposed design is compared and synthesized
for the power and delay. When observed the existing ETA designs, the II. PRIOR WORKS
proposed work achieves significant improvement in power dissipation
about 17.13%, 4.6%, 15.4%, 5.35% decrement for 4, 8, 16, 32 bits In the previous paper, they introduced the model of Error
respectively, and significant improvement in delay about 28.90%, Tolerant in VLSI (Very Large Scale Integration) system using this;
23.59%, 20.08%, 24.44% decrement for 4, 8, 16, 32 bits respectively. new type of adder called ETA is proposed. There is a trade of
particular amount of power saving for considerable accuracy and
Keywords—VLSI,error tolerance,DSP,adders performance is proposed. Comparing with the fast adders the ETA
[1] performed better in both speed and power consumption.
I. INTRODUCTION Approximate multiplier which is proposed in [2] has an adder block
In digital VLSI design, low power consumption plays an which is called ETA. In the existing paper, the power consumption
important role in all the electronic devices. One requires and latency are improved with small negligible amount of error.
system/devices should produce determined and exact output. But There was a comparison on the hardware implementation of exact
this accuracy is rarely needed in our worldly experience. Consider and inexact adder [15]. The result showed that, there was a 4.5%
an example, in a system, the signal which is obtaining from outside decrease in accuracy of META multiplier and 17.39% decrease in
is considered to be analog which is sampled many times to obtain power consumption and 13.49% decrease in delay. They showed an
digital signal [3]. This digital signal is then transmitted into a noisy improvement in performance and energy efficiency by trade of
channel to convert into an analog signal. This method produces an between power saving and accuracy.
unwanted error. To handle with this error some adders are proposed
III. ERROR TOLERANT ADDER
which do not provide well in its area, power and accuracy [4].
The most fundamental and commonly used arithmetic
To improve the efficiency, there are some proposed novel operations in the digital systems (DSP, in microprocessor, some
concepts and techniques based on the digital VLSI design. specific integrated circuits and data processing application) are the
Designers have methods from low level to transistor device level. addition of two binary numbers. ETA a type of adder which
Error tolerance (ET) [8]-[9] and PCMOS [10]-[11] are some increases the speed of addition, the one main advantage is that it
technology. If a system/device contains faults that affects the consumes less power and delay. In designing on adder one should
interior and exterior errors and that device that provides estimated consider the amount of power consumed. The most common trade
results is said to be error tolerant system/device. off is seen is the power and delay in many circuits. To obtain that
In improving energy efficiency, approximate computing trade-off this adder is introduced in the field which consumes low
had been an effective approach in recent years. This type of power and increases the speed.
approximations is adopted in embedded systems. The key A. Need For ETA
component of modern embedded devices is embedded digital signal
processing (DSP) [3]. The multiplication block in DSP is usually To maintain the large data sets there is need of large adders
taken as a complex block. To decrease the complication, the power which is quick in responses and fast in producing results. Due to the

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 low speed performance of the RCA (Ripple Carry Adder) it is not 3) When the information bits are "one," the verifying procedure
suitable for large adders. There are some adders which are designed
with low power consumption. The trade off among the power and halted and from that bit ahead, all total bits to the privilege are set
delay is always experienced. To overcome this trade-off, ETA is the to "one"
better solution. ETA consumes low power and less delays with the
cost some accuracy. The addition technique is examined from the example. By
minimizing the way of propagation carry in the inexact block also,
B. Proposed Addition Arithematic: playing out the arithmetic operation in two different parts all the
The delay is occurred because the propagation of carry is from while, the general delay time is extraordinarily decreased, same as
the LSB to MSB. The power utilization of an adder is expected to the power utilization.
the error which is obtained by the propagation of carry. In this
manner, if the propagation of carry can be wiped out or diminished,
an incredible change in speed execution and power utilization can C. Minimum Acceptable Accuracy:
be accomplished. To start with divide the info bits into two sections: The precision of the adder is firmly identified with the input
an exact part that incorporates a few higher request bit and inexact design. Expect that the contribution of an adder is irregular; there
part that is comprised of lower arrange bits that are left out with. exists a likelihood that we can get a worthy outcome .The exactness
The extent of each piece requires a bit much be equivalent. characteristic of the Error Tolerant Adder is dictated by the
separating methodology and width of adder. In this section, the
connections among the base adequate precision, the
acknowledgment likelihood, the separating methodology, and the
extent of adder are examined. Initially assume the extraordinary
circumstance where we acknowledge just the superbly right
outcome. The base worthy precision in this "great" circumstance is
100%. As indicated by the proposed addition number-crunching,
we can acquire rectify comes about just when the 2 information bits
on each position in the inexact part are not equivalent to "one" in
the meantime. In this way it can be infer a condition to figure the
acknowledgment likelihood related with the proposed Error
Tolerant Adder with various piece width and separating procedures.
The equation is:
∗
P(ACC=100%)= (1)
where is total number of bits in the input and N is th
Fig. 1. 8-bit arithematic addition number of bits in the inaccurate part.
The addition procedure begins from the centre at the two inverse IV. PROPOSED ERROR TOLERANT ADDER
bearings all the while. The expansion of the higher request operands
The block drawing of an ETA as shown in Fig 2, consists most
of the information bits is processed from LSB to MSB and typical
clear structure comprises of 2 sections: an exact part furthermore,
addition technique is used [12]. Accuracy has been secured since
an inexact part. The exact part is developed utilizing a fast adder’s,
the top request bit assume a extra critical part than the lesser arrange
for example, the RCA, CSK (Carry Skip Adder) [5], CSL (Carry
its. The lesser arrange operands of the information bits need an
Select Adder) [6]-[14], or CLA (Carry Look Ahead Adder) [7]. The
exceptional addition system. A carry flag will not be created or then
inexact part comprises of 2 obstructs: a carry free adder blocks
again taken in at any piece place to dispense with the propagation
(CFAD) and a CB (Control Block). The control signals are
of carry way. To limit the general blunder because of the disposal
generated from the control block, to decide the functioning method
of the carry path, an extraordinary system is adjusted as shown in
of the CFAD.
the Fig 1, and it is depicted as take after:
1) Verify from MSB to LSB of the bit location.
2) When the inputs are “zero” or unique, ordinary one-piece
addition is done and an activity continues to subsequently piece
position;

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 V. EXPERIMENTALS RESULTS
We synthesised the proposed ETA among the existing ETA, using
VIVADO. The power comparison is shown in Table I. The time
delay comparison is shown in Table II and the power delay product
is shown in Table III.
VIVADO software was used to synthesis our proposed ETA
and the existing ETA. The results obtained and verified in
ModelSIM Altera with the verilog codes.
Compared the synthesised results of proposed ETA among the
existing ETA, it is seen that ETA performs better in conditions of
time delay, power, and PDP. The Power delay product of 4, 8, 16,
32 bits of proposed ETA is seen that 35.55%, 22.67%, 24.46%, and
23.72% better than 4, 8, 16, 32 bit of conventional ETA.

TABLE I. COMPARISON OF POWER

Fig. 2. Blocks of ETA
No. of Power Consumption (mW)
Bits ETA_RCA Proposed ETA_CIA
A. Exact Block
4 6.574 5.61
There is little number of bits in the inexact part as opposed to
the number of bits used in exact part. The total delay is estimated 8 12.624 12.063
by the inexact part, and in the exact part the RCA, it is used because
16 24.438 21.167
of its less power consuming characteristics.
32 43.912 41.682
In the exact block the RCA is replaced by a carry-increment
adder which will reduce the power consumption, which is more
efficient compared to the conventional adders and conventional
TABLE II. COMPARISON OF TIME DELAY
ETA. The power delay product of the proposed ETA is less when
compared with the conventional ETA. Time Delay (ns)
No. of Bits
ETA_RCA Proposed ETA_CIA
4 5.361 4.159
B. Inexact Block
8 5.919 4.789
The inexact part is the most basic segment in the conventional
Error Tolerant Adder as it decides the precision, time delay, and 16 7.108 5.919
usage of power of the adder. The inexact part comprises of 2 32 8.837 7.101
hinders: the CFAD and the CB. The CFAD is comprised of twenty
adjusted XOR gates, with every one of which is utilized to produce
an aggregate bit. M1, M2, M3 are added as the three extra transistor PDP (mWns)
No. of Bits
to a XOR gate. The control signal CTL impending from CB, which ETA_RCA Proposed ETA_CIA
drives the circuit. M1 and M2 will on when CLT=0, which turns off
M3. M3 will be turned on when the CLT=1, which turns off M1, 4 36.20819 23.33199
M2, Where the output is connected to the VDD. 8 74.7037 57.76971
The CB has the capacity to recognize the primary bit location at 16 173.7053 131.2065
the point if the information bits are "one," and to set the control
motion on this location and also those to its right side to high. There 32 388.0503 295.9839
are 20 control flag producing cells (CSGCs) and every CSGC
creates a specific motion to the altered XOR gates at the comparing The Fig 3. Depicts the comparison of power between
bit location in the CFAD. Rather than a long path of 20 CSGCs, the conventional ETA and proposed ETA. There is gradual increase in
CB is masterminded in 5 equivalent estimated gatherings, with the power consumption as the number of input bits increase. The
extra associations among the 2 neighbouring gatherings. There is a Fig 4. The graph shows the comparison of time delay. It can be
link between the furthest MSB cell and the furthest MSB cell in the inferred from the graph that the time delay of the proposed ETA is
next gathering. The additional associations permit the engendered less than the conventional ETA. The Fig 5. Shows the Power delay
high control signal to "skip" starting with 1 gathering then onto the product of conventional and proposed ETA. The PDP is decreased
next as opposed to going through all the 20 cells. drastically than the conventional ETA.

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 observation with fast adders and conventional ETA shows that new
ETA is better than the fast adders and conventional ETA in power
utilization. There is a significant tradeoff between power and area,
the power has been decreased at the cost of slight increase in area.
Such designs are used in DSP applications. Future works can focus
on extrapolating this design with any other improved fast adders or
higher order adder which could reduce the power furthermore, these
designs are of conventional adders in it. Development must be made
in multiplier circuits so that this design could be used in image
processing applications.
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VI. CONCLUSION
A novel type adder, the ETA, a ETA with much more power
reduction and performance enhancement is proposed. Widespread

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