International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869, Volume-3, Issue-1, January 2015

Design of Low Power & Reliable Networks on

Chip through Joint Crosstalk Avoidance and
Multiple Error Correction Coding
Padmini G. Kaukshik, Neha Santosh Parihar, Pranoti B.Patil
supply noise, alpha particles, electromagnetic interference
Abstract Achieving reliable operation under the influence (EMI) and transistor variability .Faults affecting the links
of deep-submicrometer noise sources including crosstalk noise at result in incorrect interpretation of the data and/or control
low voltage operation is a major challenge for network on chip signals and are usually addressed using error
links. detection/correction coding such as simple parity or
In this seminar, a coding scheme is presented that
Hamming codes[6,7].
simultaneously addresses crosstalk effects on signal delay and
detects up to seven random errors through wire duplication and
Crosstalk noise has posed as one of the most challenging
simple parity checks calculated over the rows and columns of the problems in timing closure and power consumption of
two-dimensional data. This high error detection capability modern VLSI circuits. Short wire spacing and high aspect
enables the reduction of operating voltage on the wire leading to ratio of the interconnects in deep- sub micrometer processes
energy saving. increase the coupling capacitance and in turn affects the
The results show that the proposed scheme reduces the integrity and timing of signals and contributes to the increase
energy consumption up to 53% as compared to other schemes at of interconnect power consumption[3,5,8]. To address the
iso-reliability performance despite the increase in the overhead crosstalk and other transient fault noise sources
number of wires. In addition, it has small penalty on the network
simultaneously,researchers have proposed joint error
performance, represented by the average latency and
comparable codec area overhead to other schemes. correction/detection note that CAC reduces the bus power
consumption through the reduction of adjacent wire
switching activity .The joint code proposed in pointed out that
Index Terms Plasma antenna; Keywords Network on there is diminishing return in power reduction when error
Chip . Crosstalk avoidance . Multiple error correction. Low correction capability exceeds four errors. This observation
power. Transient errors .Joint codes could be valid for systems with low noise deviations. For
systems with highernoise deviations, it is possible to achieve
larger power saving by adopting higher error
I. INTRODUCTION detection/correction capabilities schemes .In this paper, we
Transmission Network on chip (NoC) is a set of small propose a new joint coding scheme that can detect up to seven
routing components connected by relatively short wires which errors and simultaneously reduce the crosstalk effect through
has been proposed as the main solution for communication duplication, as opposed to previous works that achieve up to
between the many blocks in a monolithic chip replacing the only 4 errors detection. The encoding scheme is based on
long traditional buses[1][2]. This becomes indispensable for parity codes generated by arranging the data into
chip integration scalability as more blocks are integrated in a two-dimensional arrays and calculating the parity for each
single chip due to the continuous scaling down of independent row and column and finally duplicating all the
semiconductor technology. One of the major challenges in bits. In order to achieve high detection capability, the two
NoC is the communication reliability due to the small feature copies of each bit are compared in addition to checking the
sizes, high operating frequency and low operating voltage of parities at the decoder.
the chips. Faults affecting semiconductor devices can be
classified as permanent, intermittent and transient faults ,
which negatively impact NoCs communication reliability[3]. II. LITERATURE REVIEW
Permanent faults are irreversible changes due to Several error detection/correction schemes for NoC
manufacturing defects or device wearout. Under temperature environments were proposed. Cyclic Redundancy Check
and voltage variations, hardware instabilities may result into (CRC), simple parity and Hamming codes were analyzed for
intermittent faults manifesting as burst of errors that the NoC environment [6,7,18].The use of orthogonal latin
repeatedly occur in same locations Transient faults can be square codes was proposed in to provide up to four error
caused by several noise sources such as crosstalk noise, power correction capability. the authors proposed the usage of
multiple groups of Hamming codes to provide higher error
detection and correction. The drawback of this scheme is that
Manuscript received January 18, 2015. it is not able to detect more than two random errors in each
Padmini G. Kaukshik, Professor in EXTC Department, Jawaharlal
group.
Darda Institute Of Engineering And Technology, Yavatmal,India
Neha Santosh Parihar, Final Year (EXTC) Student, Jahawarlal Darda The authors proposed the use of type-II Hybrid Automatic
Institute Of Engineering And Technology, Yavatmal,India Repeat Request (HARQ) scheme where only the rows codes
Pranoti B.Patil, Final Year (EXTC) Student, Jahawarlal Darda Institute are sent in the first transmission and the rest of the check bits
Of Engineering And Technology, Yavatmal,India. are sent if uncorrectable errors are detected. Despite its

128 www.erpublication.org
Design of Low Power & Reliable Networks on Chip through Joint Crosstalk Avoidance and Multiple Error Correction
Coding

capability of detecting/correcting multiple errors, it could not case delay of a wire( 1+4) is where is the delay of a
detect/correct more than two errors for any row.. It is worth crosstalk-free wire and is the ratio of the coupling
mentioning here that these schemes addressed the transient capacitance to the bulk capacitance.
fault noise sources excluding the crosstalk noise on signal
delay. This works addressed the timing effects of crosstalk, FIGURE I.(a)mesh (b)torus based NOCs
however they did not provide fault tolerance against other .
sources of transient fault noise. Some techniques include
shielding, repeater insertion and skewed transitions.
To simultaneously achieve crosstalk-based timing reduction
and single error correction capability, Duplicate-Add-Parity
(DAP) code was proposed by duplicating the data bits and
adding one parity bit [3].On the other hand, DAPX, a
modification of DAP, duplicated the parity bit to reduce the
crosstalk delay effect on this particular bit. Other schemes
which have similar correction capability and addressed
crosstalk through duplication approach are the Dual Rail
(DR), Boundary Shift Code (BSC) and Modified Dual Rail
code (MDR). These schemes have simple codec but are
limited by the correction of only single errors.
Triplication coding with green bus encoding alongside with
voltage scaling was proposed in [8]. However due to its single
error correction in a group of three bits, slight decrease in the
voltage swing can be achieved as compared to DAP. Note The purpose of the crosstalk avoidance code is to reduce the
that, in the ultra deep submicrometer (UDSM) technology, delay of the line to ( 1+P)
multiple errors are expected to occur and thus single error where p=1, 2, or 3 is called the maximum coupling. As a result
correction capability will not be sufficient .Crosstalk aware of reduction in the coupling capacitance, the CACs will
multi-bit error detection/correction codes were proposed, in reduce the energy dissipation per line in a NoC link.
double error correction was achieved through joint crosstalk
avoidance and double error correction code (CADEC)
scheme. The scheme proposed to encode the data using IV. ERROR CORRECTION CODING SCHEME
Hamming single error correction code and then encode the
resulting check bits and the data bits using DAP approach. In general, it is possible to achieve higher error detection than
This idea was extended to triple error correction in joint correction with the same amount of redundancy since a block
crosstalk avoidance and triple error correction (JTEC) code code with Hamming distance, D can detect up to(D-1) errors
and extended to quadruple error detection in JTEC with while it can correct only [(D-1)/2]errors .However, the
simultaneous quadruple error detection (JTEC-SQED) code. drawbacks of the error detection schemes are the
The increased error detection/correction allows the links to communication latency and energy consumption imposed by
operate at lower voltage swing to reduce the power the retransmissions. Despite these disadvantages, In this we
consumption while achieving the required reliability. demonstrate that with precise selection of the voltage swings
In this seminar, a new coding scheme is proposed that of the links, the performance and energy consumption of the
combines two dimensional parities with duplication to jointly NoC will not be highly impacted by the retransmission
provide high error detection and crosstalk avoidance
capability. This joint scheme achieves up to seven random
errors detection in which the high detection capability is not A. DUPLICATED TWO-DIMENSIONAL PARITIES
limited to address burst errors .This allows for further (DTDP) Scheme(DTDP)
reduction in the voltage swing with respect to previous works,
leading to higher energy savings .
This coding scheme is designed based on two principles: wire
duplication to reduce crosstalk effect on signal delay and
two-dimensional parities to provide error detection. By
III. CODIND IN NOCS
arranging the data in a two-dimensional matrix and
A few NoC interconnect architectures have been proposed by calculating the parity for each row and column, the equals to
different research groups. Figure.shows two of the most 4. This configuration allows the possibility to correct one
commonly used NoC architectures. Data exchange between error and detect up to two errors, or to detect 3 errors without
the functional blocks takes place in the form of packets. any error correction capability. Through wire duplication, the
Generally, wormhole switching is adopted for. This scheme scheme achieves twofold objective. First, the crosstalk effect
divides packets into fixed-length flow control units (flits), on signal delay manifested in CIBD can be reduced through
with I/O buffers storing only a few flits. The first flit, i.e., the reduction of effective coupling capacitance. Second, the
header flit, of a packet contains routing information. Header duplication doubles the to 8, ,which leads to a maximum of
flit decoding enables the switches to establish the path and seven random errors detection (7ED) capability. Despite the
subsequent flits simply follow this path in a pipelined fashion. increase in the number of wires, this report it shows that the
The delay of an inter-switch wire in the NoC link depends on energy saving through the wire supply voltage reduction
the transitions on the wire and wires adjacent to it. The worst

129 www.erpublication.org
 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-3, Issue-1, January 2015
exceeds the energy consumed by the additional wires under implementations, therefore, to illustrate the decoding
isoreliability performance. mechanism.

FIG.III.DPTR 7E decoder
B. DTDP-7ED ENCODER
Fig.2 shows the encoding process where the K data bits are
arranged in R rows and C columns and then parities are
calculated for each rows and columns respectively. Row
parity
Can be defined as
for
Q =0 to R-1, column parity PCQ can be defined as
for
Q=0 to C-1.The resultant codeword is duplicated before
being sent over the link.The duplication produces 2(C+1)
and 2(R+1) codeword bits per row and column respectively
as shown in fig.(a).Fig(b) shows the encoder implementation .

FIG.II. DTDP-7ED encoder

V. RELIABILITY

A. BIT RATE ERROR:

The bit rate error (BER), can be represented using the

Gaussian noise model, with zero mean ,N2 is the variance of
noise source and Vsw is the voltage swing on the wires. The
BER can be given by:
= Q ( )

Q(x) = dy
The reduction of Vsw reduces the power consumed in the
links. However ,at any noise level, increases with the
reduction of Vsw and the model in accounts for decrease in
Fig. 1(b) shows the encoder implementation. It can be noticed noise margin due to reduced voltage swing This increases the
that the critical path delay is the generation as it takes the rows probability of flit errors resulting in lower reliability. One
parities as inputs to its XOR chain. Since the proposed coding possibility to compensate the low reliability is through the use
scheme is based on ARQ error control policy, it requires a of error detection or correction codes. These codes will
retransmission buffer and retransmission request signal require encoder and decoder in addition to extra wires for the
coming from the decoder. For simplicity reason, they are not check bits which form the overhead power consumption that
shown here in this figure. Note that upon receiving should be minimized. It was shown in [6], [12] that by
retransmission request, the encoder encodes the data in the reducing , quadratic power saving on the links can be
retransmission buffer instead of the new data. The selection of achieved surpassing the overhead power consumption,
and of the data arrangement matrix affects the codeword size resulting in overall power saving.
before duplication,CW , where CW = K+R+C+1.
B. UNDETECTABLE ERROR PROBABILITY
C. DTDP-7E DECODER The undetected error probability, , is the probability that a flit
As Fig. 3(a) shows, the codeword bits received are arranged has errors that cannot be detected by the error detection or
in a two-dimensional matrix similar to the two-dimensional correction scheme. Note that each scheme has different
matrix after duplication in the encoding process with R+1 detection capability, thus has different undetected error
rows and columns C+1. The decoding is applied to each row probability model. For the case of uncoded flits, the is the
and column by calculating the parities to check for errors and same as the word error probability.
generating the retransmission request signals,RetR andRetC The probability to receive bits error free is(1-)L . The
for each individual row and column except the last row. The probability to have at least one erroneous bit in this bit word,
final retransmission requestRetReq is set when at least defined as word error probability, can be given by
oneRetR or oneRetC signal is set. TheRetReq signal is also Pword error() = 1-(1-)L
used to indicate to the next stage in the router pipeline the
validity of the decoder output data. C. RETRANSMISSION PROBABILITY:
Decoder implementation in Fig. 3(b) shows that the signal and Coding schemes with error detection and/or correction
output data bits are generated by the row decoder block Q capabilities can be further categorized into one of the three
while the column decoder block Q generates the RetCqsignal. error control policies: automatic repeat request (ARQ),
Note that both row and column decoder blocks have similar forward error correction (FEC), or hybrid ARQ (HARQ). The

130 www.erpublication.org
Design of Low Power & Reliable Networks on Chip through Joint Crosstalk Avoidance and Multiple Error Correction
Coding

number of retransmissions for each coding scheme differs VIII. RESULT AND CONCLUSION
according to the adopted error control policy, causing In this seminar , a crosstalk aware seven error detection
different effect on the communication latency and energy. coding scheme was proposed. The undetected error
A retransmission is requested when the decoder detects an probability and retransmission probability of the proposed
error that cannot be corrected, therefore the flit retransmission scheme were derived. The residual flit error probability, a
probability of coding scheme X can be expressed by : representative of the schemes reliability, was compared as a
Pret-x= Punc-x Pund-x function of BER. The results show that the proposed scheme,
Where Punc isthe probability that a flit has error(s) that DTDP-7ED, can achieve the same reliability under higher
cannot be corrected by the schemes decoder and Pund is the BER, allowing the link to work in lower voltage swing. The
probability that a flit has undetected errors. reduced voltage swing enabled DTDP-7ED to reduce the
average power and energy consumptions as compared to the
other schemes despite the increase in energy with the increase
VI. POWER AND CONSUMPTION of noise due to retransmissions. It was shown that providing
With the assumption of same router architecture implemented higher error detection brings energy savings when working in
for all the coding schemes, the difference in power noisy environments. Furthermore, using ARQ error control
consumption comes from the encoder, decoder and links. policy with higher error detection achieves energy savings
Thus the average power p, can be given by: with relatively small impact on performance, highly suitable
P = Pencoder + Pdecoder + Plink for medium to high reliability systems.
Plink =(L.CL.wire +(L-1).Cc.C) V2 .F
IX. FUTURE SCOPE
Where CL is the number of wires in the link,CC and are the self This error detection/correction technique to investigate joint
and coupling capacitance of wire and between wires crosstalk avoidance and multiple error correcting codes and
respectively, C and Wire are the wire self-transition and their performance in NoC fabrics .But this coding technique
coupling transition activity factor respectively, is the supply can detect upto only 7.This conclude that the minimum
voltage and the operating frequency. The first term in the number of erros that causes the DTDP-7E decoding failure is
equation represents the link self switching power eight. This suggests that higher order error correcting codes
consumption, while the second term represents the link power will be more area efficient than retransmission-based
consumption due to the coupling capacitance. mechanisms.
FIG.IV.Power And Comsumption REFERENCES

[1] amlanganguly, student member, ieee, parthapratimpande, member,

ieee, and benjaminbelzer, member, crosstalk-aware channel coding
schemes for
[2] energy efficient and reliable noc interconnects ieee,ieee transactions
on very large scale integration (vlsi) systems, vol. 17, no. 11,
november 2009.
[3] d.jagadeeswari,studentm.e applied electronics velammal engineering
college, chennai, india . static and transient fault isolation in noc
using error correction code and inbuilt test. international journal of
advanced research in electronics and communication engineering
(ijarece) volume 3, issue 4, april 2014
[4] amlanganguly&parthapratimpande&benjaminbelzer&cristiangrecude
sign of low power & reliable networks on chip through joint crosstalk
avoidance and multiple error correction coding received: 27
november 2006 / accepted: 4 august 2007 # springer science +
business media, llc 2007
[5] parthapratim pande1, amlan ganguly1, brett feero1, benjamin belzer1,
cristian grecu2, design of low power & reliable networks on
chipthrough joint crosstalk avoidance and forward errorcorrection
coding proceedings of the 21st ieee international symposium on
defect and fault-tolerance in vlsi systems (dft'06) 0-7695-2706-x/06
$20.00 2006
VII. ADVANTAGES OF DTDP SCHEME [6] wameedh n. flayyih, k. samsudin, s. j. hashim, fakhrul z. rokhani,
member, ieee,
The error correction scheme DTDP, can detect upto 7 [7] yehea i. ismail, fellow, ieee .crosstalk-aware multiple error detection
errors which ass compared to other error correction scheme based on two-dimensional parities for energy efficient
schemes. network on chip ieee .
The error correction scheme, DTDP, ensures the high error
correction capability enables the reduction of operating
voltage on wire leading to energy saving.
The resuls shows that the encoding reduces power
consumption upto 53% as compared to other schemes at
isoreliability performance despite the increase in the
overhead number of wires.

131 www.erpublication.org