HD6437050 HD64F7050 HD64F7051

REJ09B0273-0500
The revision list can be viewed directly by

clicking the title page.
The revision list summarizes the locations of

revisions and additions. Details should always
be checked by referring to the relevant text.
SH7050 Group, SH7050F-ZTAT™,
32
SH7051F-ZTAT™
Hardware Manual
Renesas 32-Bit RISC Microcomputer

SuperH RISC engine Family/SH7050 Series
HD6437050
HD64F7050
HD64F7051
Rev. 5.00
Revision Date: Jan 06, 2006
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
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The information described here may contain technical inaccuracies or typographical errors.
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from these inaccuracies or errors.
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information contained herein.
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Rev. 5.00 Jan 06, 2006 page ii of xx

Preface
The SH7050 series (SH7050, SH7051) is a single-chip RISC microcontroller that integrates a
RISC CPU core using an original Renesas architecture with peripheral functions required for
system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one state (one
system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit
internal architecture enhances data processing power. With this CPU, it has become possible to
assemble low-cost, high-performance/high-functionality systems even for applications such as
real-time control, which could not previously be handled by microcontrollers because of their
high-speed processing requirements.
In addition, the SH7050 series includes on-chip peripheral functions necessary for synchronous
configuration, such as large-capacity ROM and RAM, a direct memory access controller
(DMAC), timers, a serial communication interface (SCI), A/D converter, interrupt controller
(INTC), and I/O ports.
ROM and SRAM can be directly connected by means of an external memory access support
function, greatly reducing system cost.
There are versions of on-chip ROM: mask ROM and flash memory. The flash memory can be
programmed with a programmer that supports SH7050 series programming, and can also be
programmed and erased by software.
This hardware manual describes the SH7050 series hardware. Refer to the programming manual
for a detailed description of the instruction set.
Related Manual
SH7050 series instructions
SH-1/SH-2/SH-DSP Software Manual (Document No. REJ09B0171-0500O)
Please consult your Renesas sales representative for details of development environment system.
Rev. 5.00 Jan 06, 2006 page iii of xx

Rev. 5.00 Jan 06, 2006 page iv of xx
Main Revisions for This Edition
Item Page Revision (See Manual for Details)
All  All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
Changes due to change in package codes.
FP-168B → PRQP0168JA-A
2.3.3 Instruction 35 Table amended
Format Source Destination
Instruction Formats Operand Operand
Table 2.9
d format — dddddddd: PC
Instruction Formats 15 0 relative
xxxx xxxx dddd dddd
d12 format — dddddddddddd:

15 0 PC relative
xxxx dddd dddd dddd
13.2.8 Bit Rate 385 Description amended

Register (BRR) Synchronous mode:
φ
N= × 106 − 1
8 × 22n−1 × B
22.2 DC 655 Table amended

Characteristics Item Pin Symbol Min Typ Max Unit
Table 22.2 DC Reference During A/D AIref — 1.0 5 mA
Characteristics power conversion
supply
current
Table 22.3 656 Table amended

Permitted Output Item Symbol Min Typ Max Unit
Current Values Output low-level permissible current (per pin) IOL — — 8.0 mA
Note: To assure LSI reliability, do not exceed the output values listed in this table.
Rev. 5.00 Jan 06, 2006 page v of xx

Rev. 5.00 Jan 06, 2006 page vi of xx
Contents
Section 1 Overview ............................................................................................................. 1

1.1 Features ............................................................................................................................. 1
1.2 Block Diagram .................................................................................................................. 7
1.3 Pin Arrangement and Pin Functions ................................................................................. 8
1.3.1 Pin Arrangement .................................................................................................. 8
1.3.2 Pin Functions ....................................................................................................... 9
1.3.3 Pin Assignments................................................................................................... 15
Section 2 CPU ...................................................................................................................... 21

2.1 Register Configuration...................................................................................................... 21
2.1.1 General Registers (Rn)......................................................................................... 21
2.1.2 Control Registers ................................................................................................. 22
2.1.3 System Registers.................................................................................................. 23
2.1.4 Initial Values of Registers.................................................................................... 23
2.2 Data Formats..................................................................................................................... 24
2.2.1 Data Format in Registers...................................................................................... 24
2.2.2 Data Format in Memory....................................................................................... 24
2.2.3 Immediate Data Format ....................................................................................... 25
2.3 Instruction Features........................................................................................................... 25
2.3.1 RISC-Type Instruction Set................................................................................... 25
2.3.2 Addressing Modes ............................................................................................... 29
2.3.3 Instruction Format................................................................................................ 33
2.4 Instruction Set by Classification ....................................................................................... 36
2.5 Processing States............................................................................................................... 48
2.5.1 State Transitions................................................................................................... 48
Section 3 Operating Modes............................................................................................... 51

3.1 Operating Mode Selection ................................................................................................ 51
Section 4 Clock Pulse Generator (CPG) ....................................................................... 53

4.1 Overview........................................................................................................................... 53
4.1.1 Block Diagram ..................................................................................................... 54
4.1.2 Pin Configuration................................................................................................. 55
4.2 Clock Operating Modes .................................................................................................... 55
4.3 Clock Source..................................................................................................................... 56
4.3.1 Connecting a Crystal Oscillator ........................................................................... 56
4.3.2 External Clock Input Method............................................................................... 57
Rev. 5.00 Jan 06, 2006 page vii of xx

4.4 Notes on Using.................................................................................................................. 58
Section 5 Exception Processing....................................................................................... 61

5.1 Overview........................................................................................................................... 61
5.1.1 Types of Exception Processing and Priority ........................................................ 61
5.1.2 Exception Processing Operations......................................................................... 62
5.1.3 Exception Processing Vector Table ..................................................................... 63
5.2 Resets ................................................................................................................................ 65
5.2.1 Power-On Reset ................................................................................................... 65
5.3 Address Errors .................................................................................................................. 66
5.3.1 Address Error Sources ......................................................................................... 66
5.3.2 Address Error Exception Processing.................................................................... 67
5.4 Interrupts ........................................................................................................................... 67
5.4.1 Interrupt Sources.................................................................................................. 67
5.4.2 Interrupt Priority Level ........................................................................................ 68
5.4.3 Interrupt Exception Processing ............................................................................ 68
5.5 Exceptions Triggered by Instructions ............................................................................... 69
5.5.1 Types of Exceptions Triggered by Instructions ................................................... 69
5.5.2 Trap Instructions .................................................................................................. 69
5.5.3 Illegal Slot Instructions ........................................................................................ 70
5.5.4 General Illegal Instructions.................................................................................. 70
5.6 When Exception Sources Are Not Accepted .................................................................... 71
5.6.1 Immediately after a Delayed Branch Instruction ................................................. 71
5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 71
5.7 Stack Status after Exception Processing Ends .................................................................. 72
5.8 Notes on Use ..................................................................................................................... 73
5.8.1 Value of Stack Pointer (SP) ................................................................................. 73
5.8.2 Value of Vector Base Register (VBR) ................................................................. 73
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ...... 73
Section 6 Interrupt Controller (INTC) ........................................................................... 75

6.1 Overview........................................................................................................................... 75
6.1.1 Features................................................................................................................ 75
6.1.2 Block Diagram ..................................................................................................... 76
6.1.4 Register Configuration......................................................................................... 77
6.2 Interrupt Sources............................................................................................................... 78
6.2.1 NMI Interrupts ..................................................................................................... 78
6.2.2 User Break Interrupt ............................................................................................ 78
6.2.3 IRQ Interrupts ...................................................................................................... 78
6.2.4 On-Chip Peripheral Module Interrupts ................................................................ 79
Rev. 5.00 Jan 06, 2006 page viii of xx

6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 79
6.3 Description of Registers.................................................................................................... 84
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 84
6.3.2 Interrupt Control Register (ICR).......................................................................... 86
6.3.3 IRQ Status Register (ISR).................................................................................... 87
6.4 Interrupt Operation............................................................................................................ 89
6.4.1 Interrupt Sequence ............................................................................................... 89
6.4.2 Stack after Interrupt Exception Processing .......................................................... 91
6.5 Interrupt Response Time................................................................................................... 92
6.6 Data Transfer with Interrupt Request Signals ................................................................... 93
6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 94
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 94
Section 7 User Break Controller (UBC) ....................................................................... 95

7.1 Overview........................................................................................................................... 95
7.1.1 Features................................................................................................................ 95
7.1.2 Block Diagram ..................................................................................................... 96
7.2 Register Descriptions ........................................................................................................ 97
7.2.1 User Break Address Register (UBAR) ................................................................ 97
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 98
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 100
7.3 Operation .......................................................................................................................... 102
7.3.1 Flow of the User Break Operation ....................................................................... 102
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 104
7.3.3 Program Counter (PC) Values Saved................................................................... 104
7.4 Use Examples.................................................................................................................... 105
7.4.1 Break on CPU Instruction Fetch Cycle................................................................ 105
7.4.2 Break on CPU Data Access Cycle ....................................................................... 106
7.4.3 Break on DMA/DTC Cycle ................................................................................. 106
7.5 Cautions on Use ................................................................................................................ 107
7.5.1 On-Chip Memory Instruction Fetch..................................................................... 107
7.5.2 Instruction Fetch at Branches............................................................................... 107
7.5.3 Contention between User Break and Exception Handling................................... 108
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 108
Section 8 Bus State Controller (BSC) ........................................................................... 109

8.1 Overview........................................................................................................................... 109
8.1.1 Features................................................................................................................ 109
8.1.2 Block Diagram ..................................................................................................... 110
Rev. 5.00 Jan 06, 2006 page ix of xx

8.1.5 Address Map ........................................................................................................ 112
8.2 Description of Registers.................................................................................................... 115
8.2.1 Bus Control Register 1 (BCR1) ........................................................................... 115
8.2.2 Bus Control Register 2 (BCR2) ........................................................................... 116
8.2.3 Wait Control Register 1 (WCR1)......................................................................... 119
8.2.4 Wait Control Register 2 (WCR2)......................................................................... 121
8.2.5 RAM Emulation Register (RAMER)................................................................... 122
8.3 Accessing Ordinary Space ................................................................................................ 124
8.3.1 Basic Timing........................................................................................................ 124
8.3.2 Wait State Control................................................................................................ 125
8.3.3 CS Assert Period Extension ................................................................................. 127
8.4 Waits between Access Cycles ........................................................................................... 128
8.4.1 Prevention of Data Bus Conflicts......................................................................... 128
8.4.2 Simplification of Bus Cycle Start Detection ........................................................ 130
8.5 Bus Arbitration.................................................................................................................. 131
8.6 Memory Connection Examples......................................................................................... 132
Section 9 Direct Memory Access Controller (DMAC) ............................................ 135

9.1 Overview........................................................................................................................... 135
9.1.1 Features................................................................................................................ 135
9.1.2 Block Diagram ..................................................................................................... 137
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 140
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 141
9.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 142
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 143
9.2.5 DMAC Operation Register (DMAOR) ................................................................ 148
9.3 Operation .......................................................................................................................... 150
9.3.1 DMA Transfer Flow ............................................................................................ 150
9.3.2 DMA Transfer Requests ...................................................................................... 152
9.3.3 Channel Priority ................................................................................................... 155
9.3.4 DMA Transfer Types........................................................................................... 158
9.3.5 Address Modes .................................................................................................... 159
9.3.6 Dual Address Mode ............................................................................................. 160
9.3.7 Bus Modes ........................................................................................................... 167
9.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category............................................................................................................... 168
9.3.9 Bus Mode and Channel Priority Order................................................................. 169
Rev. 5.00 Jan 06, 2006 page x of xx

9.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 169
9.3.11 Source Address Reload Function ......................................................................... 186
9.3.12 DMA Transfer Ending Conditions....................................................................... 188
9.3.13 DMAC Access from CPU.................................................................................... 189
9.4 Examples of Use ............................................................................................................... 189
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 189
9.4.2 Example of DMA Transfer between External RAM and External Device
with DACK .......................................................................................................... 190
9.4.3 Example of DMA Transfer between A/D Converter and Internal Memory
(Address Reload On)............................................................................................ 190
9.4.4 Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On) .......................................................................................... 192
9.5 Cautions on Use ................................................................................................................ 194
Section 10 Advanced Timer Unit (ATU) ..................................................................... 195

10.1 Overview........................................................................................................................... 195
10.1.1 Features................................................................................................................ 195
10.1.2 Block Diagrams ................................................................................................... 200
10.1.3 Inter-Channel and Inter-Module Signal Connection Diagram ............................. 208
10.1.4 Prescaler Diagram................................................................................................ 209
10.1.6 Register and Counter Configuration .................................................................... 212
10.2.1 Timer Start Register (TSTR)................................................................................ 216
10.2.2 Timer Mode Register (TMDR) ............................................................................ 218
10.2.3 Prescaler Register 1 (PSCR1) .............................................................................. 220
10.2.4 Timer Control Registers (TCR) ........................................................................... 221
10.2.5 Timer I/O Control Registers (TIOR).................................................................... 225
10.2.6 Trigger Selection Register (TGSR)...................................................................... 233
10.2.7 Timer Status Registers (TSR) .............................................................................. 235
10.2.8 Timer Interrupt Enable Registers (TIER) ............................................................ 252
10.2.9 Interval Interrupt Request Register (ITVRR)....................................................... 264
10.2.10 Down-Count Start Register (DSTR) .................................................................... 267
10.2.11 Timer Connection Register (TCNR).................................................................... 271
10.2.12 Free-Running Counters (TCNT) .......................................................................... 274
10.2.13 Input Capture Registers (ICR) ............................................................................. 276
10.2.14 General Registers (GR)........................................................................................ 277
10.2.15 Down-Counters (DCNT) ..................................................................................... 278
10.2.16 Offset Base Register (OSBR) .............................................................................. 279
10.2.17 Cycle Registers (CYLR) ...................................................................................... 280
10.2.18 Buffer Registers (BFR) ........................................................................................ 281
Rev. 5.00 Jan 06, 2006 page xi of xx

10.2.19 Duty Registers (DTR) .......................................................................................... 282
10.3 Operation .......................................................................................................................... 283
10.3.1 Overview.............................................................................................................. 283
10.3.2 Free-Running Count Operation and Cyclic Count Operation .............................. 285
10.3.3 Output Compare-Match Function ........................................................................ 286
10.3.4 Input Capture Function ........................................................................................ 288
10.3.5 One-Shot Pulse Function ..................................................................................... 289
10.3.6 Offset One-Shot Pulse Function .......................................................................... 290
10.3.7 Interval Timer Operation ..................................................................................... 292
10.3.8 Twin-Capture Function........................................................................................ 294
10.3.9 PWM Timer Function .......................................................................................... 295
10.3.10 Buffer Function.................................................................................................... 297
10.3.11 One-Shot Pulse Function Pulse Output Timing ................................................... 298
10.3.12 Offset One-Shot Pulse Function Pulse Output Timing ........................................ 299
10.3.13 Channel 3 to 5 PWM Output Waveform Actual Cycle and Actual Duty ............ 300
10.3.14 Channel 3 to 5 PWM Output Waveform Settings and Interrupt Handling
Times ................................................................................................................... 301
10.3.15 PWM Output Operation at Start of Channel 3 to 5 Counter ................................ 303
10.3.16 PWM Output Operation at Start of Channel 6 to 9 Counter ................................ 304
10.3.17 Timing of Buffer Register (BFR) Write and Transfer by Buffer Function .......... 305
10.4 Interrupts ........................................................................................................................... 306
10.4.1 Status Flag Setting Timing................................................................................... 306
10.4.2 Interrupt Status Flag Clearing .............................................................................. 311
10.5 CPU Interface.................................................................................................................... 313
10.5.1 Registers Requiring 32-Bit Access ...................................................................... 313
10.5.2 Registers Requiring 16-Bit Access ...................................................................... 314
10.5.3 8-Bit or 16-Bit Accessible Registers.................................................................... 315
10.5.4 Registers Requiring 8-Bit Access ........................................................................ 316
10.6 Sample Setup Procedures.................................................................................................. 316
10.7 Usage Notes ...................................................................................................................... 329
10.8 Advanced Timer Unit Registers And Pins ........................................................................ 343
Section 11 Advanced Pulse Controller (APC) ............................................................ 345

11.1 Overview........................................................................................................................... 345
11.1.1 Features................................................................................................................ 345
11.1.2 Block Diagram ..................................................................................................... 346
11.2.1 Pulse Output Port Control Register (POPCR)...................................................... 348
11.3 Operation .......................................................................................................................... 349
Rev. 5.00 Jan 06, 2006 page xii of xx

11.3.1 Overview.............................................................................................................. 349
11.3.2 Advanced Pulse Controller Output Operation ..................................................... 350
11.4 Usage Notes ...................................................................................................................... 353
Section 12 Watchdog Timer (WDT) .............................................................................. 355

12.1 Overview........................................................................................................................... 355
12.1.1 Features................................................................................................................ 355
12.1.2 Block Diagram ..................................................................................................... 356
12.2.1 Timer Counter (TCNT)........................................................................................ 357
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 358
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 360
12.2.4 Register Access.................................................................................................... 361
12.3 Operation .......................................................................................................................... 362
12.3.1 Watchdog Timer Mode ........................................................................................ 362
12.3.2 Interval Timer Mode ............................................................................................ 364
12.3.3 Clearing the Standby Mode ................................................................................. 364
12.3.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 365
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 365
12.4 Notes on Use ..................................................................................................................... 366
12.4.1 TCNT Write and Increment Contention .............................................................. 366
12.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 366
12.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 366
12.4.4 System Reset With WDTOVF ............................................................................. 367
12.4.5 Internal Reset With the Watchdog Timer ............................................................ 367
Section 13 Serial Communication Interface (SCI) .................................................... 369

13.1 Overview........................................................................................................................... 369
13.1.1 Features................................................................................................................ 369
13.1.2 Block Diagram ..................................................................................................... 370
13.2.1 Receive Shift Register (RSR) .............................................................................. 373
13.2.2 Receive Data Register (RDR) .............................................................................. 373
13.2.3 Transmit Shift Register (TSR) ............................................................................. 374
13.2.4 Transmit Data Register (TDR)............................................................................ 374
13.2.5 Serial Mode Register (SMR)................................................................................ 375
13.2.6 Serial Control Register (SCR).............................................................................. 377
Rev. 5.00 Jan 06, 2006 page xiii of xx

13.2.7 Serial Status Register (SSR) ................................................................................ 380
13.2.8 Bit Rate Register (BRR) ...................................................................................... 384
13.3 Operation .......................................................................................................................... 394
13.3.1 Overview.............................................................................................................. 394
13.3.2 Operation in Asynchronous Mode ....................................................................... 396
13.3.3 Multiprocessor Communication........................................................................... 406
13.3.4 Clock Synchronous Operation ............................................................................. 414
13.4 SCI Interrupt Sources and the DMAC .............................................................................. 425
13.5 Notes on Use ..................................................................................................................... 426
13.5.1 TDR Write and TDRE Flags................................................................................ 426
13.5.2 Simultaneous Multiple Receive Errors ................................................................ 426
13.5.3 Break Detection and Processing .......................................................................... 427
13.5.4 Sending a Break Signal........................................................................................ 427
13.5.5 Receive Error Flags and Transmitter Operation
(Clock Synchronous Mode Only) ........................................................................ 427
13.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous
Mode .................................................................................................................... 427
13.5.7 Constraints on DMAC Use .................................................................................. 429
13.5.8 Cautions for Clock Synchronous External Clock Mode ...................................... 429
13.5.9 Caution for Clock Synchronous Internal Clock Mode......................................... 429
Section 14 A/D Converter ................................................................................................. 431

14.1 Overview........................................................................................................................... 431
14.1.1 Features................................................................................................................ 431
14.1.2 Block Diagram ..................................................................................................... 432
14.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) ............................................. 437
14.2.2 A/D Control/Status Register 0 (ADCSR0)........................................................... 438
14.2.3 A/D Control Register 0 (ADCR0)........................................................................ 442
14.2.4 A/D Control/Status Register 1 (ADCSR1)........................................................... 444
14.2.5 A/D Control Register 1 (ADCR1)........................................................................ 445
14.2.6 A/D Trigger Register (ADTRGR) ....................................................................... 446
14.3 CPU Interface.................................................................................................................... 447
14.4 Operation .......................................................................................................................... 448
14.4.1 Single Mode......................................................................................................... 448
14.4.2 Scan Mode ........................................................................................................... 450
14.4.3 Analog Input Setting and A/D Conversion Time................................................. 452
14.4.4 External Triggering of A/D Conversion .............................................................. 454
14.4.5 A/D Converter Activation by ATU...................................................................... 455
Rev. 5.00 Jan 06, 2006 page xiv of xx

14.4.6 ADEND Output Pin ............................................................................................. 455
14.5 Interrupt Sources and DMA Transfer Requests ................................................................ 456
14.6 Usage Notes ...................................................................................................................... 456
Section 15 Compare Match Timer (CMT) ................................................................... 459

15.1 Overview........................................................................................................................... 459
15.1.1 Features................................................................................................................ 459
15.1.2 Block Diagram ..................................................................................................... 460
15.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 462
15.2.2 Compare Match Timer Control/Status Register (CMCSR) ................................. 463
15.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 464
15.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 465
15.3 Operation .......................................................................................................................... 465
15.3.1 Period Count Operation ....................................................................................... 465
15.3.2 CMCNT Count Timing........................................................................................ 466
15.4 Interrupts ........................................................................................................................... 466
15.4.1 Interrupt Sources and DTC Activation ................................................................ 466
15.4.2 Compare Match Flag Set Timing......................................................................... 467
15.4.3 Compare Match Flag Clear Timing ..................................................................... 468
15.5 Notes on Use ..................................................................................................................... 469
15.5.1 Contention between CMCNT Write and Compare Match................................... 469
15.5.2 Contention between CMCNT Word Write and Incrementation .......................... 470
15.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 471
Section 16 Pin Function Controller (PFC) ................................................................... 473

16.1 Overview........................................................................................................................... 473
16.3.1 Port A IO Register (PAIOR) ................................................................................ 479
16.3.2 Port A Control Register (PACR).......................................................................... 479
16.3.3 Port B IO Register (PBIOR) ................................................................................ 484
16.3.4 Port B Control Register (PBCR) .......................................................................... 484
16.3.5 Port C IO Register (PCIOR) ................................................................................ 488
16.3.6 Port C Control Registers 1 and 2 (PCCR1, PCCR2)............................................ 488
16.3.7 Port D IO Register (PDIOR) ................................................................................ 494
16.3.8 Port D Control Register (PDCR).......................................................................... 494
16.3.9 Port E IO Register (PEIOR)................................................................................. 500
16.3.10 Port E Control Register (PECR) .......................................................................... 500
16.3.11 Port F IO Register (PFIOR) ................................................................................. 504
Rev. 5.00 Jan 06, 2006 page xv of xx

16.3.12 Port F Control Registers 1 and 2 (PFCR1, PFCR2) ............................................. 504
16.3.13 Port G IO Register (PGIOR) ................................................................................ 510
16.3.14 Port G Control Registers 1 and 2 (PGCR1, PGCR2) ........................................... 510
16.3.15 CK Control Register (CKCR) .............................................................................. 516
Section 17 I/O Ports (I/O) ................................................................................................. 517

17.1 Overview........................................................................................................................... 517
17.2 Port A................................................................................................................................ 517
17.2.2 Port A Data Register (PADR) .............................................................................. 518
17.3 Port B ................................................................................................................................ 519
17.3.2 Port B Data Register (PBDR) .............................................................................. 520
17.4 Port C ................................................................................................................................ 522
17.4.2 Port C Data Register (PCDR) .............................................................................. 523
17.5 Port D................................................................................................................................ 524
17.5.2 Port D Data Register (PDDR) .............................................................................. 525
17.6 Port E ................................................................................................................................ 527
17.6.2 Port E Data Register (PEDR)............................................................................... 528
17.7 Port F................................................................................................................................. 529
17.7.2 Port F Data Register (PFDR) ............................................................................... 530
17.8 Port G................................................................................................................................ 531
17.8.2 Port G Data Register (PGDR) .............................................................................. 532
17.9 Port H................................................................................................................................ 533
17.9.2 Port H Data Register (PHDR) .............................................................................. 534
17.10 POD (Port Output Disable) ............................................................................................... 534
Section 18 ROM (128 kB Version) ................................................................................ 535

18.1 Features ............................................................................................................................. 535
18.2 Overview........................................................................................................................... 536
18.2.1 Block Diagram ..................................................................................................... 536
18.2.2 Mode Transitions ................................................................................................. 537
18.2.3 On-Board Programming Modes........................................................................... 538
18.2.4 Flash Memory Emulation in RAM ...................................................................... 540
18.2.5 Differences between Boot Mode and User Program Mode ................................. 541
Rev. 5.00 Jan 06, 2006 page xvi of xx

18.2.6 Block Configuration ............................................................................................ 542
18.3 Pin Configuration.............................................................................................................. 542
18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 544
18.5.3 Erase Block Register 1 (EBR1) ........................................................................... 548
18.6 On-Board Programming Modes........................................................................................ 550
18.6.1 Boot Mode ........................................................................................................... 551
18.6.2 User Program Mode............................................................................................. 555
18.7 Programming/Erasing Flash Memory ............................................................................... 556
18.7.1 Program Mode ..................................................................................................... 556
18.7.2 Program-Verify Mode.......................................................................................... 557
18.7.3 Erase Mode .......................................................................................................... 559
18.7.4 Erase-Verify Mode .............................................................................................. 559
18.8 Protection .......................................................................................................................... 561
18.8.1 Hardware Protection ............................................................................................ 561
18.8.2 Software Protection.............................................................................................. 562
18.8.3 Error Protection.................................................................................................... 563
18.9 Flash Memory Emulation in RAM ................................................................................... 565
18.10 Note on Flash Memory Programming/Erasing ................................................................. 567
18.11 Flash Memory Programmer Mode .................................................................................... 567
18.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 568
18.11.2 Programmer Mode Operation .............................................................................. 570
18.11.3 Memory Read Mode ............................................................................................ 571
18.11.4 Auto-Program Mode ............................................................................................ 575
18.11.5 Auto-Erase Mode................................................................................................. 578
18.11.6 Status Read Mode ................................................................................................ 579
18.11.7 Status Polling ....................................................................................................... 581
18.11.8 Programmer Mode Transition Time .................................................................... 582
18.11.9 Notes On Memory Programming......................................................................... 583
18.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM
Versions ............................................................................................................................ 583
Section 19 ROM (256 kB Version) ................................................................................ 585

19.1 Features ............................................................................................................................. 585
19.2 Overview........................................................................................................................... 586
19.2.1 Block Diagram ..................................................................................................... 586
19.2.2 Mode Transitions ................................................................................................. 587
19.2.3 On-Board Programming Modes........................................................................... 588
Rev. 5.00 Jan 06, 2006 page xvii of xx

19.2.4 Flash Memory Emulation in RAM ...................................................................... 590
19.2.5 Differences between Boot Mode and User Program Mode ................................. 591
19.2.6 Block Configuration ............................................................................................ 592
19.3 Pin Configuration.............................................................................................................. 593
19.6 On-Board Programming Modes........................................................................................ 604
19.6.1 Boot Mode ........................................................................................................... 605
19.6.2 User Program Mode............................................................................................. 609
19.7 Programming/Erasing Flash Memory ............................................................................... 610
19.7.1 Program Mode (n = 1 for Addresses H'0000 to H'1FFFF,
n = 2 for Addresses H'20000 to H'3FFFF) ........................................................... 610
19.7.2 Program-Verify Mode (n = 1 for Addresses H'0000 to H'1FFFF,
19.7.3 Erase Mode (n = 1 for Addresses H'0000 to H'1FFFF,
19.7.4 Erase-Verify Mode (n = 1 for Addresses H'0000 to H'1FFFF,
19.8 Protection .......................................................................................................................... 615
19.8.1 Hardware Protection ............................................................................................ 615
19.8.2 Software Protection.............................................................................................. 616
19.8.3 Error Protection.................................................................................................... 617
19.9 Flash Memory Emulation in RAM ................................................................................... 619
19.10 Note on Flash Memory Programming/Erasing ................................................................. 621
19.11 Flash Memory Programmer Mode .................................................................................... 621
19.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 622
19.11.2 Programmer Mode Operation .............................................................................. 624
19.11.3 Memory Read Mode ............................................................................................ 625
19.11.4 Auto-Program Mode ............................................................................................ 629
19.11.5 Auto-Erase Mode................................................................................................. 631
19.11.6 Status Read Mode ................................................................................................ 633
19.11.7 Status Polling ....................................................................................................... 635
19.11.8 Programmer Mode Transition Time .................................................................... 636
19.11.9 Cautions Concerning Memory Programming ...................................................... 637
19.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM
Versions ............................................................................................................................ 637
Rev. 5.00 Jan 06, 2006 page xviii of xx

Section 20 RAM .................................................................................................................. 639
20.1 Overview........................................................................................................................... 639
20.2 Operation .......................................................................................................................... 640
Section 21 Power-Down State ......................................................................................... 641

21.1 Overview........................................................................................................................... 641
21.1.1 Power-Down States.............................................................................................. 641
21.1.3 Related Register ................................................................................................... 643
21.2.1 Standby Control Register (SBYCR) .................................................................... 644
21.2.2 System Control Register (SYSCR) ...................................................................... 645
21.3 Hardware Standby Mode .................................................................................................. 646
21.3.1 Transition to Hardware Standby Mode ................................................................ 646
21.3.2 Exit from Hardware Standby Mode ..................................................................... 646
21.3.3 Hardware Standby Mode Timing......................................................................... 646
21.4 Software Standby Mode.................................................................................................... 647
21.4.1 Transition to Software Standby Mode ................................................................. 647
21.4.2 Canceling the Software Standby Mode................................................................ 649
21.4.3 Software Standby Mode Application Example.................................................... 650
21.5 Sleep Mode ....................................................................................................................... 651
21.5.1 Transition to Sleep Mode..................................................................................... 651
21.5.2 Canceling Sleep Mode ......................................................................................... 651
Section 22 Electrical Characteristics.............................................................................. 653

22.1 Absolute Maximum Ratings ............................................................................................. 653
22.2 DC Characteristics ............................................................................................................ 654
22.2.1 Notes on Using..................................................................................................... 656
22.3 AC Characteristics ............................................................................................................ 657
22.3.1 Clock Timing ....................................................................................................... 657
22.3.2 Control Signal Timing ......................................................................................... 659
22.3.3 Bus Timing .......................................................................................................... 662
22.3.4 Direct Memory Access Controller Timing .......................................................... 666
22.3.5 Advanced Timer Unit Timing and Advanced Pulse Controller Timing .............. 668
22.3.6 I/O Port Timing.................................................................................................... 669
22.3.7 Watchdog Timer Timing...................................................................................... 670
22.3.8 Serial Communication Interface Timing.............................................................. 670
22.3.9 A/D Converter Timing......................................................................................... 671
22.3.10 Measuring Conditions for AC Characteristics ..................................................... 673
22.4 A/D Converter Characteristics .......................................................................................... 674
Rev. 5.00 Jan 06, 2006 page xix of xx

Appendix A On-Chip Supporting Module Registers ................................................ 675
A.1 Addresses .......................................................................................................................... 675
A.2 Registers............................................................................................................................ 692
A.3 Register States at Reset and in Power-Down State ........................................................... 808
Appendix B Pin States ....................................................................................................... 812

B.1 Pin States at Reset and in Power-Down, and Bus Right Released State ........................... 812
B.2 Pin States of Bus Related Signals ..................................................................................... 815
Appendix C Product Code Lineup.................................................................................. 816
Appendix D Package Dimensions .................................................................................. 817
Rev. 5.00 Jan 06, 2006 page xx of xx

Section 1 Overview
Section 1 Overview
1.1 Features
The SH7050 series is a single-chip RISC microcontroller that integrates a RISC CPU core using
an original Renesas architecture with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one state (one
system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit
internal architecture enhances data processing power. With this CPU, it has become possible to
assemble low-cost, high-performance/high-functionality systems even for applications such as
real-time control, which could not previously be handled by microcontrollers because of their
high-speed processing requirements.
In addition, the SH7050 series includes on-chip peripheral functions necessary for synchronous
configuration, such as large-capacity ROM and RAM, a direct memory access controller
(DMAC), timers, a serial communication interface (SCI), A/D converter, interrupt controller
(INTC), and I/O ports.
ROM and SRAM can be directly connected by means of an external memory access support
function, greatly reducing system cost.
TM
There are versions of on-chip ROM: mask ROM and F-ZTAT (Flexible Zero Turn Around
Time) with flash memory. The flash memory can be programmed with a programmer that supports
SH7050 series programming, and can also be programmed and erased by software. This enables
the chip to be programmed on the user side while mounted on a board.
The features of the SH7050 series are summarized in table 1.1.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 5.00 Jan 06, 2006 page 1 of 818

REJ09B0273-0500
Section 1 Overview
Table 1.1 SH7050 Series Features
Item Features
CPU • Original Renesas architecture
• 32-bit internal architecture
• General register machine
 Sixteen 32-bit general registers
 Three 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture (basic operations are executed between
registers)
 Delayed unconditional/conditional branch instructions reduce pipeline
disruption during branches
 C-oriented instruction set
• Instruction execution time: Basic instructions execute in one state
(50 ns/instruction at 20 MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and
multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits)
executed in two to four states
• Five-stage pipeline
Rev. 5.00 Jan 06, 2006 page 2 of 818

REJ09B0273-0500
Section 1 Overview
Item Features
Operating states • Operating modes
 Single-chip mode
 8/16-bit bus expanded mode (area 0 only set by mode pins)
• Mode with on-chip ROM
• Mode with no on-chip ROM
• Processing states
 Power-on reset state
 Program execution state
 Exception handling state
 Bus-released state
 Power-down state
• Power-down state
 Sleep mode
 Software standby mode
 Hardware standby mode
Interrupt • Nine external interrupt pins (NMI, IRQ0 to IRQ7)
controller (INTC)
• 66 internal interrupt sources
(ATU × 44, SCI × 12, DMAC × 4, A/D × 2, WDT × 1, UBC × 1, CMT × 2)
• 16 programmable priority levels
User break • Requests an interrupt when the CPU or DMAC generates a bus cycle with
controller (UBC) specified conditions
• Simplifies configuration of an on-chip debugger
Clock pulse • On-chip clock pulse generator (maximum operating frequency: 20 MHz)
generator
• On-chip clock-multiplication PLL circuit (×1, ×2, ×4)
(CPG/PLL)
External input frequency range: 4 to 10 MHz
Rev. 5.00 Jan 06, 2006 page 3 of 818

REJ09B0273-0500
Section 1 Overview
Item Features
Bus state • Supports external memory access (SRAM and ROM directly connectable)
controller (BSC)
 8/16-bit external data bus
• External address space divided into four areas, with the following
parameters settable for each area:
 Bus size (8 or 16 bits)
 Number of wait cycles
 Chip select signals (CS0 to CS3) output for each area
• Wait cycles can be inserted using an external WAIT signal
• External access in minimum of two cycles
• Provision for idle cycle insertion to prevent bus collisions
(between external space read and write cycles, etc.)
Direct memory • DMA transfer possible for the following devices:
access controller
 External memory, external I/O, external memory, on-chip supporting
(DMAC)
(4 channels) modules (excluding DMAC, UBC, BSC)
• DMA transfer requests by external pins, on-chip SCI, on-chip A/D
converter, on-chip ATU
• Cycle stealing or burst transfer
• Relative channel priorities can be set
• Channels 0 and 1: Selection of dual or single address mode transfer,
external requests possible
Channels 2 and 3: Dual address mode transfer and internal requests only
• Source address reload function (channel 2 only)
• Can be switched between direct address transfer mode and indirect
address transfer mode (channel 3 only)
 Direct address transfer mode: Transfers the data at the transfer source
address to the transfer destination address
 Indirect address transfer mode: Regards the data at the transfer source
address as an address, and transfers the data at that address to the
transfer destination address
Rev. 5.00 Jan 06, 2006 page 4 of 818

REJ09B0273-0500
Section 1 Overview
Item Features
Advanced timer • Built-in two-stage prescaler
unit (ATU)
• Total of 18 counters: ten free-running counters, eight down-counters
• Maximum 34 pulse inputs or outputs can be processed
 Four 32-bit input capture inputs
 Eight 16-bit one-shot pulse outputs
 Eighteen 16-bit input capture inputs/output compare outputs
 Four 16-bit PWM outputs
 One 16-bit input capture input (no pin)
Advanced pulse • Maximum eight pulse outputs
controller (APC)
Watchdog timer • Can be switched between watchdog timer and interval timer function
(WDT)
• Internal reset, external signal, or interrupt generated by counter overflow
(1 channel)
Serial • Selection of asynchronous or synchronous mode
communication
• Simultaneous transmission/reception (full-duplex) capability
interface (SCI)
(3 channels) • Built-in dedicated baud rate generator
• Multiprocessor communication function
A/D converter • 10-bit resolution
• Sixteen channels
 Two sample-and-hold circuit function units
(independent operation of 12 channels and 4 channels)
 Selection of single mode or scan mode
• Can be activated by external trigger or ATU compare-match
• ADEND output at end of A/D conversion (A/D1 module only)
Compare-match • Selection of 4 counter input clocks
timer (CMT)
• A compare-match interrupt can be requested independently for each
(2 channels)
channel
I/O ports • Total of 118 pins (multiplex ports): 102 input/output, 16 input
 Input or output can be specified bit by bit
Rev. 5.00 Jan 06, 2006 page 5 of 818

REJ09B0273-0500
Section 1 Overview
Item Features
Large-capacity Model
on-chip memory Memory
SH7050 SH7051
Mask ROM 128 kB — —
Flash memory — 128 kB 256 kB
RAM 6 kB 6 kB 10 kB
Product lineup On-Chip Operating Operating

Model Product Code Package
ROM Voltage Frequency
SH7050 Mask 5.0 V 4 to 20 MHz HD6437050F20 168-pin plastic
ROM QFP
(PRQP0168JA-A)
Flash 5.0 V 4 to 20 MHz HD64F7050SF20
memory
SH7051 Flash 5.0 V 4 to 20 MHz HD64F7051SF20
memory
Rev. 5.00 Jan 06, 2006 page 6 of 818

REJ09B0273-0500
Section 1 Overview
1.2 Block Diagram
PC6/CS2/IRQ6/ADEND
PF9/CS3/IRQ7/PULS5
PF4/BREQ/PULS7
PF5/BACK/PULS6
PB11/A21/POD
PC2/WAIT
PC1/WRH
PB10/A20
PA15/A15
PA14/A14
PA13/A13
PA12/A12
PA11/A11
PA10/A10
PC0/WRL
PC5/CS1
PC4/CS0
PB9/A19
PB8/A18
PB7/A17
PB6/A16
PC3/RD
PA9/A9
PA8/A8
PA7/A7
PA6/A6
PA5/A5
PA4/A4
PA3/A3
PA2/A2
PA1/A1
PA0/A0
RES
Port/control signals Port/address signals
HSTBY
MD3
MD2
MD1
MD0 PD15/D15
NMI PD14/D14
WDTOVF PD13/D13
ROM (flash/mask) RAM PD12/D12
PD11/D11
Port/data signals
PD10/D10
CK PD9/D9
EXTAL PD8/D8
XTAL Clock pulse PD7/D7
PLLVCC generator PD6/D6
Direct memory PD5/D5
PLLVSS
CPU access PD4/D4
PLLCAP
controller PD3/D3
VCC (×15)
Multiplier (4 channels) PD2/D2
VSS (×15)
AVref PD1/D1
AVCC (×2) PD0/D0
Interrupt
AVSS (×2) Bus state controller
controller
FWE (NC*)
PG0/ADTRG/IRQOUT
PG1/SCK0
Serial communi-
PH15/AN15 Advanced timer PG2/TxD0
cation interface
PH14/AN14 unit PG3/RxD0
(3 channels)
PH13/AN13 PG4/SCK1
PH12/AN12 PG5/TxD1
PH11/AN11 Compare-match PG6/RxD1
A/D Watchdog
PH10/AN10 timer PF8/SCK2/PULS4
converter timer
PH9/AN9 (2 channels) Port PG7/TxD2
PH8/AN8 PG8/RxD2
PH7/AN7 PF0/IRQ0
Port
PH6/AN6 PF1/IRQ1
PH5/AN5 PF2/IRQ2
PH4/AN4 PF3/IRQ3
PH3/AN3 PG14/IRQ4/TIOA5
Port Port PG15/IRQ5/TIOB5
PH2/AN2
PH1/AN1 PF7/DREQ0/PULS3
PH0/AN0 PF6/DACK0/PULS2
PC14/TOH10
PC13/TOG10
PC12/TOF10/DRAK1
PC11/TOE10/DRAK0
PC10/TOD10
PC9/TOC10
PC8/TOB10
PC7/TOA10
PG13/TIOD4
PG12/TIOC4
PG11/TIOB4
PG10/TIOA4
PG9/TIOD3
PE14/TIOC3
PE13/TIOB3
PE12/TIOA3
PE7/TIOB2
PE6/TIOA2
PE5/TIOF1
PE4/TIOE1
PE3/TIOD1
PE2/TIOC1
PE1/TIOB1
PE0/TIOA1
PE11/TID0
PE10/TIC0
PE9/TIB0
PE8/TIA0
PB5/TCLKB
PB4/TCLKA
PB0/TO6 PF5/DREQ1/PULS1
PB1/TO7 PF4/DACK1/PULS0
PB2/TO8
PB3/TO9
: Peripheral address bus (24 bits)

: Peripheral data bus (16 bits)
: Internal address bus (24 bits)
: Internal upper data bus (16 bits)
Note: * MASK ROM version : Internal lower data bus (16 bits)
Figure 1.1 Block Diagram
Rev. 5.00 Jan 06, 2006 page 7 of 818

REJ09B0273-0500
1.3
1.3.1
PB9/A19
PB8/A18
PB7/A17
VSS
PB6/A16
VCC
PA15/A15
PA14/A14
PA13/A13
PA12/A12
PA11/A11
VSS
PA10/A10
VCC
PA9/A9
PA8/A8
PA7/A7
PA6/A6
PA5/A5
VSS
PA4/A4
VCC
PA3/A3
PA2/A2
PA1/A1
PA0/A0
PB5/TCLKB
VSS
PB4/TCLKA
VCC
PB3/TO9
PB2/TO8
PB1/TO7
PB0/TO6
PG15/IRQ5/TIOB5
VSS
PG14/IRQ4/TIOA5
PG13/TIOD4
PG12/TIOC4
PG11/TIOB4
PG10/TIOA4
PG9/TIOD3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
REJ09B0273-0500
PB10/A20 43 168 PG8/RxD2
Section 1 Overview
PB11/A21/POD 44 167 PG7/TxD2
Note: * MASK ROM version

PC0/WRL 45 166 PG6/RxD1
PC1/WRH 46 165 PG5/TxD1
VCC 47 164 VSS
PC2/WAIT 48 163 PG4/SCK1
Pin Arrangement
VSS 49 162 PG3/RxD0

PC3/RD 50 161 PG2/TxD0
WDTOVF 51 160 PG1/SCK0
PC4/CS0 52 159 PG0/ADTRG/IRQOUT
PC5/CS1 53 158 VCC
PC6/CS2/IRQ6/ADEND 54 157 PH15/AN15
VCC 55 156 PH14/AN14
Rev. 5.00 Jan 06, 2006 page 8 of 818

PC7/TOA10 56 155 PH13/AN13
VSS 57 154 PH12/AN12
PC8/TOB10 58 153 PH11/AN11
PC9/TOC10 59 152 AVSS
PC10/TOD10 60 151 PH10/AN10
PC11/TOE10/DRAK0 61 150 AVCC
PC12/TOF10/DRAK1 62 149 AVref
PC13/TOG10 63 148 PH9/AN9
VSS 64 147 PH8/AN8
PC14/TOH10 65 146 PH7/AN7
PE0/TIOA1 66 145 PH6/AN6
Pin Arrangement and Pin Functions
PE1/TIOB1 67 144 AVSS

PE2/TIOC1 68 143 PH5/AN5
PRQP0168JA-A
PE3/TIOD1 69 142 AVCC
VSS 70 141 PH4/AN4
PE4/TIOE1 71 140 PH3/AN3
VCC 72 139 PH2/AN2
Figure 1.2 Pin Arrangement

PE5/TIOF1 73 138 PH1/AN1
PE6/TIOA2 74 137 PH0/AN0
PE7/TIOB2 75 136 VSS
PE8/TIA0 76 135 PF11/BREQ/PULS7
PE9/TIB0 77 134 PF10/BACK/PULS6
PE10/TIC0 78 133 PF9/CS3/IRQ7/PULS5
VCC 79 132 PF8/SCK2/PULS4
PE11/TID0 80 131 PF7/DREQ0/PULS3
VSS 81 130 VCC
PE12/TIOA3 82 129 PF6/DACK0/PULS2
PE13/TIOB3 83 128 PF5/DREQ1/PULS1
PE14/TIOC3 84 127 PF4/DACK1/PULS0
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
CK
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
NMI
RES
MD3
MD2
MD1
MD0
XTAL
EXTAL
HSTBY
PD0/D0
PD1/D1
PD2/D2
PD3/D3
PD4/D4
PD5/D5
PD6/D6
PD7/D7
PD8/D8
PD9/D9
PLLVSS
PLLVCC
PLLCAP
PF0/IRQ0
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PD10/D10
PD11/D11
PD12/D12
PD13/D13
PD14/D14
PD15/D15
FWE (NC*)
Section 1 Overview
1.3.2 Pin Functions
Table 1.2 summarizes the pin functions.
Table 1.2 Pin Functions
Type Symbol Pin No. I/O Name Function

Power supply VCC 13, 21, 29, Input Power supply For connection to the power
37, 47, 55, supply.
72, 79, 89, Connect all VCC pins to the
97, 105, system power supply. The
113, 130, chip will not operate if there
158 are any open pins.
VSS 7, 15, 23, Input Ground For connection to ground.
31, 39, 49, Connect all VSS pins to the
57, 64, 70, system ground. The chip will
81, 91, 99, not operate if there are any
107, 115, open pins.
136, 164
Flash memory FWE 118 Input Flash write Connected to ground in
enable normal operation.
Apply VCC during on-board
programming. (Not included
in mask ROM version.)
Clock PLLVCC 121 Input PLL power On-chip PLL oscillator power
supply supply.
For power supply connection,
see section 4, Clock Pulse
Generator.
PLLVSS 123 Input PLL ground On-chip PLL oscillator
ground.
For power supply connection,
see section 4, Clock Pulse
Generator.
PLLCAP 122 Input PLL On-chip PLL oscillator
capacitance external capacitance
connection pin.
For external capacitance
connection, see section 4,
Clock Pulse Generator.
Rev. 5.00 Jan 06, 2006 page 9 of 818

REJ09B0273-0500
Section 1 Overview

Clock EXTAL 110 Input External clock For connection to a crystal
resonator. An external clock
source can also be
connected to the EXTAL pin.
XTAL 108 Input Crystal For connection to a crystal
resonator.
CK 125 Output System clock Supplies the system clock to
peripheral devices.
System RES 126 Input Power-on Executes a power-on reset
control reset when driven low.
WDTOVF 51 Output Watchdog WDT overflow output signal.
timer overflow
BREQ 135 Input Bus request Driven low when an external
device requests the bus.
BACK 134 Output Bus request Indicates that the bus has
acknowledge been granted to an external
device. The device that
output the BREQ signal
recognizes that the bus has
been acquired when it
receives the BACK signal.
Operating MD0 to 120, 119, Input Mode setting These pins determine the
mode control MD3 111, 109 operating mode. Do not
change the input values
during operation.
HSTBY 124 Input Hardware When driven low, this pin
standby forces a transition to
hardware standby mode.
Interrupts NMI 112 Input Nonmaskable Nonmaskable interrupt
interrupt request pin.
Acceptance on the rising
edge or falling edge can be
selected.
IRQ0 to 106, 114, Input Interrupt Maskable interrupt request
IRQ7 116, 117, 6, requests pins.
8, 54, 133 0 to 7 Level input or edge input can
be selected.
Rev. 5.00 Jan 06, 2006 page 10 of 818

REJ09B0273-0500
Section 1 Overview

Interrupts IRQOUT 159 Output Interrupt Indicates that an interrupt has
request been generated.
output Enables interrupt generation
to be recognized in the bus-
released state.
Address bus A0–A21 17–20, 22, Output Address bus Address output pins.
24–28, 30,
32–36, 38,
40–44
Data bus D0–D15 85–88, 90, Input/ Data bus 16-bit bidirectional data bus
92–96, 98, output pins.
100–104
Bus control CS0–CS3 52–54, 133 Output Chip select Chip select signals for
0 to 3 external memory or devices.
RD 50 Output Read Indicates reading from an
external device.
WRH 46 Output Upper write Indicates writing of the upper
8 bits of external data.
WRL 45 Output Lower write Indicates writing of the lower
8 bits of external data.
WAIT 48 Input Wait Input for wait cycle insertion
in bus cycles during external
space access.
Direct memory DREQ0– 131, 128 Input DMA transfer Input pin for external requests
access DREQ1 request for DMA transfer.
controller (channels 0, 1)
(DMAC) DRAK0– 61, 62 Output DREQ request These pins output the input
DRAK1 acknowledg- sampling acknowledgment for
ment (channels external requests for DMA
0, 1) transfer.
DACK0– 129, 127 Output DMA transfer These pins output a strobe to
DACK1 strobe the external I/O of external
(channels 0, 1) DMA transfer requests.
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Section 1 Overview

Advanced TCLKA 14 Input ATU timer ATU counter external clock
timer unit TCLKB 16 clock input Input pins.
(ATU) TIA0 76 Input ATU input Channel 0 input capture input
TIB0 77 capture pins.
TIC0 78 (channel 0)
TID0 80
TIOA1 66 Input/ ATU input Channel 1 input capture
TIOB1 67 output capture/output input/output compare output
TIOC1 68 compare pins.
TIOD1 69 (channel 1)
TIOE1 71
TIOF1 73
TIOB2 75 output capture/output input/output compare output
compare pins.
(channel 2)
TIOB3 83 output capture/output input/output compare/PWM
TIOC3 84 compare/ output pins.
TlOD3 1 PWM output
(channel 3)
TIOC4 4 compare/ output pins.
TIOD4 5 PWM output
(channel 4)
compare/ output pins.
PWM output
(channel 5)
TO6 9 Output ATU PWM Channel 6 to 9 PWM output
TO7 10 output pins.
TO8 11 (channels
TO9 12 6 to 9)
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Section 1 Overview

Advanced TOA10 56 Output ATU one-shot Channel 10 down-counter
timer unit TOB10 58 pulse (channel one-shot pulse output pins.
(ATU) TOC10 59 10)
TOD10 60
TOE10 61
TOF10 62
TOG10 63
TOH10 65
Advanced PULS0– 127–129, Output APC pulse APC pulse output pins.
pulse PULS7 131–135 outputs 0 to 7
controller
(APC)
Serial TxD0– 161, 165, Output Transmit data SCI0 to SCI2 transmit data
communication TxD2 167 (channels output pins.
interface (SCI) 0 to 2)
RxD0– 162, 166, Input Receive data SCI0 to SCI2 receive data
RsD2 168 (channels input pins.
0 to 2)
SCK0– 160, 163, Input/ Serial clock SCI0 to SCI2 clock
SCK2 132 output (channels input/output pins.
0 to 2)
A/D converter AVCC 142, 150 Input Analog power A/D converter power supply.
supply
AVSS 144, 152 Input Analog ground A/D converter power supply.
AVref 149 Input Analog Analog reference power
reference supply input pin.
power supply
AN0–AN15 137–141, Input Analog input Analog signal input pins.
143,145–
148, 151,
153–157
ADTRG 159 Input A/D conversion External trigger input for
trigger input starting A/D conversion.
ADEND 54 Output ADEND output A/D1 channel 15 conversion
timing monitor output pin.
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Section 1 Overview

I/O ports POD 44 Input Port output Input pin for port pin drive
disable control when general port is
set for output.
PA0–PA15 17–20, 22, Input/ Port A General input/output port
32–36 Input or output can be
specified bit by bit.
PB0–PB11 9–12, 14, Input/ Port B General input/output port
16, 38, output pins.
PC0–PC14 45, 46, 48, Input/ Port C General input/output port
50, 52–54, output pins.
56, 58–63, Input or output can be
65 specified bit by bit.
PD0–PD15 85–88, 90, Input/ Port D General input/output port
PE0–PE14 66–69, 71, Input/ Port E General input/output port
PF0–PF11 106, 114, Input/ Port F General input/output port
116, 117, output pins.
127–129, Input or output can be
131–135 specified bit by bit.
PG0–PG15 159–163, Input/ Port G General input/output port
165–168, output pins.
1–6, 8 Input or output can be
PH0–PH15 137–141, Input Port H General input port pins.
143, 145–
148, 151,
153–157
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Section 1 Overview
1.3.3 Pin Assignments
Table 1.3 Pin Assignments
Pin No. MCU Mode Programmer Mode

1 PG9/TIOD3 VCC
2 PG10/TIOA4 VCC
3 PG11/TIOB4 N.C.
4 PG12/TIOC4 N.C.
5 PG13/TIOD4 VCC
6 PG14/IRQ4/TIOA5 N.C.
7 VSS VSS
8 PG15/IRQ5/TIOB5 N.C.
9 PB0/TO6 N.C.
10 PB1/TO7 N.C.
11 PB2/TO8 N.C.
12 PB3/TO9 N.C.
13 VCC VCC
14 PB4/TCLKA N.C.
15 VSS VSS
16 PB5/TCLKB N.C.
17 PA0/A0 A0
18 PA1/A1 A1
19 PA2/A2 A2
20 PA3/A3 A3
21 VCC VCC
22 PA4/A4 A4
23 VSS VSS
24 PA5/A5 A5
25 PA6/A6 A6
26 PA7/A7 A7
27 PA8/A8 A8
28 PA9/A9 OE
29 VCC VCC
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Section 1 Overview

30 PA10/A10 A10
31 VSS VSS
32 PA11/A11 A11
33 PA12/A12 A12
34 PA13/A13 A13
35 PA14/A14 A14
36 PA15/A15 A15
37 VCC VCC
38 PB6/A16 A16
39 VSS VSS
40 PB7/A17 VSS (HD64F7050S)/A17 (HD64F7051S)
41 PB8/A18 CE
42 PB9/A19 WE
43 PB10/A20 N.C.
44 PB11/A21/POD N.C.
45 PC0/WRL N.C.
46 PC1/WRH N.C.
47 VCC VCC
48 PC2/WAIT N.C.
49 VSS VSS
50 PC3/RD N.C.
51 WDTOVF N.C.
52 PC4/CS0 N.C.
53 PC5/CS1 N.C.
54 PC6/CS2/IRQ6/ADEND N.C.
55 VCC VCC
56 PC7/TOA10 N.C.
57 VSS VSS
58 PC8/TOB10 N.C.
59 PC9/TOC10 N.C.
60 PC10/TOD10 N.C.
61 PC11/TOE10/DRAK0 N.C.
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Section 1 Overview

62 PC12/TOF10/DRAK1 N.C.
63 PC13/TOG10 N.C.
64 VSS VSS
65 PC14/TOH10 N.C.
66 PE0/TIOA1 N.C.
67 PE1/TIOB1 N.C.
68 PE2/TIOC1 N.C.
69 PE3/TIOD1 N.C.
70 VSS VSS
71 PE4/TIOE1 N.C.
72 VCC VCC
73 PE5/TIOF1 N.C.
74 PE6/TIOA2 N.C.
75 PE7/TIOB2 N.C.
76 PE8/TIA0 N.C.
77 PE9/TIB0 N.C.
78 PE10/TIC0 N.C.
79 VCC VCC
80 PE11/TID0 N.C.
81 VSS VSS
82 PE12/TIOA3 N.C.
83 PE13/TIOB3 N.C.
84 PE14/TIOC3 N.C.
85 PD0/D0 I/O0
86 PD1/D1 I/O1
87 PD2/D2 I/O2
88 PD3/D3 I/O3
89 VCC VCC
90 PD4/D4 I/O4
91 VSS VSS
92 PD5/D5 I/O5
93 PD6/D6 I/O6
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Section 1 Overview

94 PD7/D7 I/O7
95 PD8/D8 N.C.
96 PD9/D9 N.C.
97 VCC VCC
98 PD10/D10 N.C.
99 VSS VSS
100 PD11/D11 N.C.
101 PD12/D12 N.C.
102 PD13/D13 N.C.
103 PD14/D14 N.C.
104 PD15/D15 N.C.
105 VCC VCC
106 PF0/IRQ0 N.C.
107 VSS VSS
108 XTAL XTAL
109 MD3 VCC
110 EXTAL EXTAL
111 MD2 VCC
112 NMI A9
113 VCC VCC
114 PF1/IRQ1 N.C.
115 VSS VSS
116 PF2/IRQ2 N.C.
117 PF3/IRQ3 N.C.
118 FWE (NC*) FWE
119 MD1 VSS
120 MD0 VCC
121 PLLVCC PLLVCC
122 PLLCAP PLLCAP
123 PLLVSS PLLVSS
124 HSTBY VCC
125 CK N.C.
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Section 1 Overview

126 RES RES
127 PF4/DACK1/PULS0 N.C.
128 PF5/DREQ1/PULS1 N.C.
129 PF6/DACK0/PULS2 N.C.
130 VCC VCC
131 PF7/DREQ0/PULS3 N.C.
132 PF8/SCK2/PULS4 N.C.
133 PF9/CS3/IRQ7/PULS5 N.C.
134 PF10/BACK/PULS6 N.C.
135 PF11/BREQ/PULS7 N.C.
136 VSS VSS
137 PH0/AN0 N.C.
138 PH1/AN1 N.C.
139 PH2/AN2 N.C.
140 PH3/AN3 N.C.
141 PH4/AN4 N.C.
142 AVCC VCC
143 PH5/AN5 N.C.
144 AVSS VSS
145 PH6/AN6 N.C.
146 PH7/AN7 N.C.
147 PH8/AN8 N.C.
148 PH9/AN9 N.C.
149 AVref VCC
150 AVCC VCC
151 PH10/AN10 N.C.
152 AVSS VSS
153 PH11/AN11 N.C.
154 PH12/AN12 N.C.
155 PH13/AN13 N.C.
156 PH14/AN14 N.C.
157 PH15/AN15 N.C.
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Section 1 Overview

158 VCC VCC
159 PG0/ADTRG/IRQOUT N.C.
160 PG1/SCK0 N.C.
161 PG2/TxD0 N.C.
162 PG3/RxD0 N.C.
163 PG4/SCK1 N.C.
164 VSS VSS
165 PG5/TxD1 N.C.
166 PG6/RxD1 N.C.
167 PG7/TxD2 N.C.
168 PG8/RxD2 N.C.
Note: * Mask ROM version
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REJ09B0273-0500
Section 2 CPU
Section 2 CPU
2.1 Register Configuration

The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four
32-bit system registers.
2.1.1 General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for
data processing and address calculation. R0 is also used as an index register. Several instructions
have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15. Figure 2.1 shows the general registers.
31 0
R0*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer)*2
Notes: 1. R0 functions as an index register in the indirect indexed register addressing

mode and indirect indexed GBR addressing mode. In some instructions, R0
functions as a fixed source register or destination register.
2. R15 functions as a hardware stack pointer (SP) during exception processing.
Figure 2.1 General Registers
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REJ09B0273-0500
Section 2 CPU
2.1.2 Control Registers
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR),
and vector base register (VBR). The status register indicates processing states. The global base
register functions as a base address for the indirect GBR addressing mode to transfer data to the
registers of on-chip peripheral modules. The vector base register functions as the base address of
the exception processing vector area (including interrupts). Figure 2.2 shows a control register.
31 9 8 7 6 5 4 32 1 0
SR M Q I3 I2 I1 I0 ST SR: Status register
T bit: The MOVT, CMP/cond, TAS, TST,

BT (BT/S), BF (BF/S), SETT, and CLRT
instructions use the T bit to indicate true
(1) or false (0). The ADDV, ADDC,
SUBV, SUBC, DIV0U, DIV0S, DIV1,
NEGC, SHAR, SHAL, SHLR, SHLL,
ROTR, ROTL, ROTCR, and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow.
S bit: Used by the MAC instruction.
Reserved bits. This bit always read 0.
The write value should always be 0.
Bits I0–I3: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
and DIV1 instructions.
Reserved bits. 0 is read. Write only.
31 0 Global base register (GBR):

GBR Indicates the base address of the indirect
GBR addressing mode. The indirect GBR
addressing mode is used in data transfer
for on-chip peripheral modules register
areas and in logic operations.
31 0 Vector base register (VBR):

VBR Stores the base address of the exception
processing vector area.
Figure 2.2 Control Register Configuration
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REJ09B0273-0500
Section 2 CPU
2.1.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply
and accumulate registers store the results of multiply and accumulate operations. The procedure
register stores the return address from the subroutine procedure. The program counter stores
program addresses to control the flow of the processing. Figure 2.3 shows a system register.
31 0
Multiply and accumulate (MAC)
MACH registers high and low (MACH,
MACL MACL): Stores the results of
multiply and accumulate operations.
31 0 Procedure register (PR): Stores

PR a return address from a
subroutine procedure.
31 0 Program counter (PC): Indicates

PC the fourth byte (second instruction)
after the current instruction.
Figure 2.3 System Register Configuration
2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification Register Initial Value

General registers R0–R14 Undefined
R15 (SP) Value of the stack pointer in the vector address table
Control registers SR Bits I3–I0 are 1111 (H'F), reserved bits are 0, and other
bits are undefined
GBR Undefined
VBR H'00000000
System registers MACH, MACL, PR Undefined
PC Value of the program counter in the vector address
table
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REJ09B0273-0500
Section 2 CPU
2.2 Data Formats
2.2.1 Data Format in Registers
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure
2.4).
31 0
Longword
Figure 2.4 Data Format in Registers
2.2.2 Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if you try to access word data starting from an
address other than 2n or longword data starting from an address other than 4n. In such cases, the
data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack
pointer (SP, R15), uses only longword data starting from address 4n because this area holds the
program counter and status register (figure 2.5).
Address m + 1 Address m + 3
Address m Address m + 2
31 23 15 7 0
Byte Byte Byte Byte
Address 2n Word Word
Address 4n Longword
Figure 2.5 Data Format in Memory
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REJ09B0273-0500
Section 2 CPU
2.2.3 Immediate Data Format
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
2.3 Instruction Features
2.3.1 RISC-Type Instruction Set
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using
the pipeline system. Instructions are executed in 50 ns at 20 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data (table 2.2).
Table 2.2 Sign Extension of Word Data
SH7050 Series CPU Description Example of Conventional CPU

MOV.W @(disp,PC),R1 Data is sign-extended to 32 ADD.W #H'1234,R0
ADD R1,R0 bits, and R1 becomes
H'00001234. It is next
......... operated upon by an ADD
.DATA.W H'1234 instruction.
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
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REJ09B0273-0500
Section 2 CPU
Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the
instruction that follows the branch instruction and then branching reduces pipeline disruption
during branching (table 2.3). There are two types of conditional branch instructions: delayed
branch instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions

BRA TRGET Executes an ADD before ADD.W R1,R0
ADD R1,R0 branching to TRGET BRA TRGET
Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are

executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation
operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64bit
→ 64-bit multiplication/accumulation operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4 T Bit

CMP/GE R1,R0 T bit is set when R0 ≥ R1. The CMP.W R1,R0
BT TRGET0 program branches to TRGET0 BGE TRGET0
when R0 ≥ R1 and to TRGET1
BF TRGET1 when R0 < R1. BLT TRGET1
ADD #–1,R0 T bit is not changed by ADD. T bit SUB.W #1,R0

CMP/EQ #0,R0 is set when R0 = 0. The program BEQ TRGET
branches if R0 = 0.
BT TRGET
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REJ09B0273-0500
Section 2 CPU
Immediate Data: Byte (8 bit) immediate data resides in instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. An immediate
data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode
with displacement (table 2.5).
Table 2.5 Immediate Data Accessing
Classification SH7050 Series CPU Example of Conventional CPU

8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0
16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0
.................
.DATA.W H'1234
32-bit immediate MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0
.................
.DATA.L H'12345678
Note: @(disp, PC) accesses the immediate data.
Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. Loading the immediate data when the instruction is
executed transfers that value to the register and the data is accessed in the indirect register
addressing mode (table 2.6).
Table 2.6 Absolute Address Accessing

Absolute address MOV.L @(disp,PC),R1 MOV.B @H'12345678,R0
MOV.B @R1,R0
..................
.DATA.L H'12345678
Note: @(disp,PC) accesses the immediate data.
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REJ09B0273-0500
Section 2 CPU
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-
existing displacement value is placed in the memory table. Loading the immediate data when the
instruction is executed transfers that value to the register and the data is accessed in the indirect
indexed register addressing mode (table 2.7).
Table 2.7 Displacement Accessing

16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(H'1234,R1),R2
MOV.W @(R0,R1),R2
..................
.DATA.W H'1234
Note: @(disp,PC) accesses the immediate data.
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REJ09B0273-0500
Section 2 CPU
2.3.2 Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing Instruction
Mode Format Effective Addresses Calculation Equation
Direct register Rn The effective address is register Rn. (The operand —
addressing is the contents of register Rn.)
Indirect register @Rn The effective address is the content of register Rn. Rn
addressing
Rn Rn
Post-increment @Rn+ The effective address is the content of register Rn. Rn

indirect register A constant is added to the content of Rn after the (After the
addressing instruction is executed. 1 is added for a byte instruction
operation, 2 for a word operation, and 4 for a executes)
longword operation.
Byte: Rn + 1
Rn Rn → Rn
Rn + 1/2/4 Word: Rn + 2
+
→ Rn
Longword:
1/2/4
Rn + 4 → Rn
Pre-decrement @–Rn The effective address is the value obtained by Byte: Rn – 1
indirect register subtracting a constant from Rn. 1 is subtracted for → Rn
addressing a byte operation, 2 for a word operation, and 4 for Word: Rn – 2
a longword operation. → Rn
Rn Longword:
Rn – 4 → Rn
Rn – 1/2/4
– Rn – 1/2/4 (Instruction
executed with
1/2/4 Rn after
calculation)
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REJ09B0273-0500
Section 2 CPU
Indirect register @(disp:4, The effective address is Rn plus a 4-bit Byte: Rn +
addressing with Rn) displacement (disp). The value of disp is zero- disp
displacement extended, and remains the same for a byte Word: Rn +
operation, is doubled for a word operation, and is disp × 2
quadrupled for a longword operation.
Longword: Rn
Rn + disp × 4
disp + Rn + disp × 1/2/4

(zero-extended)
×
1/2/4
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. Rn + R0
register
addressing Rn
+ Rn + R0
R0
Indirect GBR @(disp:8, The effective address is the GBR value plus an Byte: GBR +
addressing with GBR) 8-bit displacement (disp). The value of disp is zero- disp
displacement extended, and remains the same for a byte opera- Word: GBR +
tion, is doubled for a word operation, and is disp × 2
quadrupled for a longword operation.
Longword:
GBR GBR + disp ×
4
disp + GBR
(zero-extended) + disp × 1/2/4
×
1/2/4
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REJ09B0273-0500
Section 2 CPU
Indirect indexed @(R0, The effective address is the GBR value plus the R0. GBR + R0
GBR addressing GBR)
GBR
+ GBR + R0
R0
Indirect PC @(disp:8, The effective address is the PC value plus an 8-bit Word: PC +
addressing with PC) displacement (disp). The value of disp is zero- disp × 2
displacement extended, and is doubled for a word operation, and Longword:
quadrupled for a longword operation. For a PC &
longword operation, the lowest two bits of the PC H'FFFFFFFC
value are masked. + disp × 4
PC
(for longword)
&
PC + disp × 2
H'FFFFFFFC or
+
PC & H'FFFFFFFC
disp + disp × 4
(zero-extended)
×
2/4
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REJ09B0273-0500
Section 2 CPU
PC relative disp:8 The effective address is the PC value sign-extended PC + disp × 2
addressing with an 8-bit displacement (disp), doubled, and
added to the PC value.
PC
disp + PC + disp × 2
(sign-extended)
×
disp:12 The effective address is the PC value sign-extended PC + disp × 2

with a 12-bit displacement (disp), doubled, and
added to the PC value.
PC
disp + PC + disp × 2
(sign-extended)
×
Rn The effective address is the register PC value PC + Rn

plus Rn.
PC
+ PC + Rn
Rn
Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, —
addressing OR, and XOR instructions are zero-extended.
#imm:8 The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions are sign-extended.
#imm:8 The 8-bit immediate data (imm) for the TRAPA —
instruction is zero-extended and is quadrupled.
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REJ09B0273-0500
Section 2 CPU
2.3.3 Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The
meaning of the operand depends on the instruction code. The symbols are used as follows:
• xxxx: Instruction code

• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Source Destination
Instruction Formats Operand Operand Example
0 format — — NOP
15 0
xxxx xxxx xxxx xxxx
n format — nnnn: Direct MOVT Rn

15 0 register
xxxx nnnn xxxx xxxx Control register nnnn: Direct STS MACH,Rn
or system register
register
Control register nnnn: Indirect STC.L SR,@-Rn
or system pre-decrement
register register
m format mmmm: Direct Control register or LDC Rm,SR
15 0 register system register
xxxx mmmm xxxx xxxx mmmm: Indirect Control register or LDC.L @Rm+,SR
post-increment system register
register
mmmm: Direct — JMP @Rm
register
mmmm: PC — BRAF Rm
relative using
Rm
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REJ09B0273-0500
Section 2 CPU
Source Destination
nm format mmmm: Direct nnnn: Direct ADD Rm,Rn
15 0 register register
xxxx nnnn mmmm xxxx mmmm: Direct nnnn: Indirect MOV.L Rm,@Rn
register register
mmmm: Indirect MACH, MACL MAC.W
post-increment @Rm+,@Rn+
register
(multiply/
accumulate)
nnnn*: Indirect
post-increment
register
(multiply/
accumulate)
mmmm: Indirect nnnn: Direct MOV.L @Rm+,Rn
post-increment register
register
mmmm: Direct nnnn: Indirect MOV.L Rm,@-Rn
register pre-decrement
register
mmmm: Direct nnnn: Indirect MOV.L
register indexed register Rm,@(R0,Rn)
md format mmmmdddd: R0 (Direct MOV.B
15 0 indirect register register) @(disp,Rm),R0
xxxx xxxx mmmm dddd with
displacement
nd4 format R0 (Direct nnnndddd: MOV.B
15 0 register) Indirect register R0,@(disp,Rn)
xxxx xxxx nnnn dddd with displacement
nmd format mmmm: Direct nnnndddd: MOV.L

15 0 register Indirect register Rm,@(disp,Rn)
xxxx nnnn mmmm dddd with displacement
mmmmdddd: nnnn: Direct MOV.L
Indirect register register @(disp,Rm),Rn
with
displacement
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REJ09B0273-0500
Section 2 CPU
Source Destination
d format dddddddd: R0 (Direct MOV.L
15 0 Indirect GBR register) @(disp,GBR),R0
xxxx xxxx dddd dddd with
displacement
R0(Direct dddddddd: MOV.L
register) Indirect GBR with R0,@(disp,GBR)
displacement
dddddddd: PC R0 (Direct MOVA
relative with register) @(disp,PC),R0
displacement
— dddddddd: PC BF label
relative
d12 format — dddddddddddd: BRA label
15 0 PC relative (label = disp +
xxxx dddd dddd dddd PC)
nd8 format dddddddd: PC nnnn: Direct MOV.L

15 0 relative with register @(disp,PC),Rn
xxxx nnnn dddd dddd displacement
i format iiiiiiii: Immediate Indirect indexed AND.B

15 0 GBR #imm,@(R0,GBR)
xxxx xxxx iiii iiii iiiiiiii: Immediate R0 (Direct AND #imm,R0
register)
iiiiiiii: Immediate — TRAPA #imm
ni format iiiiiiii: Immediate nnnn: Direct ADD #imm,Rn
15 0 register
xxxx nnnn iiii iiii
Note: * In multiply/accumulate instructions, nnnn is the source register.
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REJ09B0273-0500
Section 2 CPU
2.4 Instruction Set by Classification

Table 2.10 Classification of Instructions
Operation No. of
Classification Types Code Function Instructions
Data transfer 5 MOV Data transfer, immediate data transfer, 39
peripheral module data transfer, structure
data transfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Arithmetic 21 ADD Binary addition 33
operations ADDC Binary addition with carry
ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1 Division
DIV0S Initialization of signed division
DIV0U Initialization of unsigned division
DMULS Signed double-length multiplication
DMULU Unsigned double-length multiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiply/accumulate, double-length
multiply/accumulate operation
MUL Double-length multiply operation
MULS Signed multiplication
MULU Unsigned multiplication
NEG Negation
NEGC Negation with borrow
SUB Binary subtraction
SUBC Binary subtraction with borrow
SUBV Binary subtraction with underflow
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REJ09B0273-0500
Section 2 CPU
Operation No. of
Logic 6 AND Logical AND 14
operations NOT Bit inversion
OR Logical OR
TAS Memory test and bit set
TST Logical AND and T bit set
XOR Exclusive OR
Shift 10 ROTL One-bit left rotation 14
ROTR One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL One-bit arithmetic left shift
SHAR One-bit arithmetic right shift
SHLL One-bit logical left shift
SHLLn n-bit logical left shift
SHLR One-bit logical right shift
SHLRn n-bit logical right shift
Branch 9 BF Conditional branch, conditional branch with 11
delay (Branch when T = 0)
BT Conditional branch, conditional branch with
delay (Branch when T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
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REJ09B0273-0500
Section 2 CPU
Operation No. of
System 11 CLRMAC MAC register clear 31
control CLRT T bit clear
LDC Load to control register
LDS Load to system register
NOP No operation
RTE Return from exception processing
SETT T bit set
SLEEP Shift into power-down mode
STC Storing control register data
STS Storing system register data
TRAPA Trap exception handling
Total: 62 142
Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation,
and execution states in order by classification.
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REJ09B0273-0500
Section 2 CPU
Table 2.11 Instruction Code Format
Item Format Explanation

Instruction OP.Sz SRC,DEST OP: Operation code
Sz: Size (B: byte, W: word, or L: longword)
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*1
Instruction MSB ↔ LSB mmmm: Source register
code nnnn: Destination register
0000: R0
0001: R1
.
.
.
1111: R15
iiii: Immediate data
dddd: Displacement
Operation →, ← Direction of transfer
(xx) Memory operand
M/Q/T Flag bits in the SR
& Logical AND of each bit
| Logical OR of each bit
^ Exclusive OR of each bit
~ Logical NOT of each bit
<<n n-bit left shift
>>n n-bit right shift
Execution — Value when no wait states are inserted*2
cycles
T bit — Value of T bit after instruction is executed. An em-dash (—)
in the column means no change.
Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see
the SH-1/SH-2/SH-DSP Software Manual.
2. Instruction execution cycles: The execution cycles shown in the table are minimums.
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) and the register used by the next instruction are the
same.
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REJ09B0273-0500
Section 2 CPU
Table 2.12 Data Transfer Instructions
Execu-
tion
Instruction Instruction Code Operation Cycles T Bit
MOV #imm,Rn 1110nnnniiiiiiii #imm → Sign extension → 1 —
Rn
MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign 1 —
extension → Rn
MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1 —
MOV Rm,Rn 0110nnnnmmmm0011 Rm → Rn 1 —
MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 —
MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1 —
MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1 —
MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) → Sign extension → 1 —
Rn
MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) → Sign extension → 1 —
Rn
MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) → Rn 1 —
MOV.B Rm,@–Rn 0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn) 1 —
MOV.W Rm,@–Rn 0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn) 1 —
MOV.L Rm,@–Rn 0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn) 1 —
MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) → Sign extension → 1 —
Rn,Rm + 1 → Rm
MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → Sign extension → 1 —
Rn,Rm + 2 → Rm
MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm 1 —
MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 → (disp + Rn) 1 —
MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 1 —
MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 1 —
MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) → Sign 1 —
extension → R0
MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → Sign 1 —
extension → R0
MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 1 —
MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) 1 —
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REJ09B0273-0500
Section 2 CPU
Execu-
tion
MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 —
MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 —
MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign 1 —
extension → Rn
MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign 1 —
extension → Rn
MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 —
MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1 —
MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1 —
MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 1 —
MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign 1 —
extension → R0
MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign 1 —
extension → R0
MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 1 —
MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0 1 —
MOVT Rn 0000nnnn00101001 T → Rn 1 —
SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → Swap the bottom two 1 —
bytes → Rn
SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → Swap two 1 —
consecutive words → Rn
XTRCT Rm,Rn 0010nnnnmmmm1101 Rm: Middle 32 bits of 1 —
Rn → Rn
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REJ09B0273-0500
Section 2 CPU
Table 2.13 Arithmetic Operation Instructions
Execu-
tion
ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1 —
ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1 —
ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T → Rn, 1 Carry
Carry → T
ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm → Rn, 1 Overflow
Overflow → T
CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 → T 1 Comparison
result
CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T 1 Comparison
result
CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn≥Rm with 1 Comparison
unsigned data, 1 → T result
CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ Rm with signed 1 Comparison
data, 1 → T result
CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with 1 Comparison
unsigned data, 1 → T result
CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed 1 Comparison
data, 1 → T result
CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 → T 1 Comparison
result
CMP/PZ Rn 0100nnnn00010001 If Rn ≥ 0, 1 → T 1 Comparison
result
CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm have 1 Comparison
an equivalent byte, result
1→T
DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division 1 Calculation
(Rn/Rm) result
DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB 1 Calculation
of Rm → M, M ^ Q → T result
DIV0U 0000000000011001 0 → M/Q/T 1 0
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REJ09B0273-0500
Section 2 CPU
Execu-
tion
DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of 2 to 4* —
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of 2 to 4* —
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
DT Rn 0100nnnn00010000 Rn – 1 → Rn, when Rn 1 Comparison
is 0, 1 → T. When Rn result
is nonzero, 0 → T
EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is sign- 1 —
extended → Rn
EXTS.W Rm,Rn 0110nnnnmmmm1111 A word in Rm is sign- 1 —
extended → Rn
EXTU.B Rm,Rn 0110nnnnmmmm1100 A byte in Rm is zero- 1 —
extended → Rn
EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zero- 1 —
extended → Rn
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of 3/ —
(Rn) × (Rm) + MAC → (2 to 4)*
MAC 32 × 32 + 64 →
64 bit
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)* —
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bit
MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL, 2 to 4* —
32 × 32 → 32 bit
MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of 1 to 3* —
Rn × Rm → MAC
16 × 16 → 32 bit
MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of 1 to 3* —
Rn × Rm → MAC
16 × 16 → 32 bit
NEG Rm,Rn 0110nnnnmmmm1011 0–Rm → Rn 1 —
NEGC Rm,Rn 0110nnnnmmmm1010 0–Rm–T → Rn, Borrow 1 Borrow
→T
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REJ09B0273-0500
Section 2 CPU
Execu-
tion
SUB Rm,Rn 0011nnnnmmmm1000 Rn–Rm → Rn 1 —
SUBC Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T → Rn, 1 Borrow
Borrow → T
SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, 1 Overflow
Underflow → T
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Execu-
tion
AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 —
AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 —
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → 3 —
(R0 + GBR)
NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 —
OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 —
OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 —
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → 3 —
(R0 + GBR)
TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T; 1 → 4 Test
MSB of (Rn)* result
TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the result is 1 Test
0, 1 → T result
TST #imm,R0 11001000iiiiiiii R0 & imm; if the result is 1 Test
0, 1 → T result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if 3 Test
the result is 0, 1 → T result
XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 —
XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 —
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → 3 —
(R0 + GBR)
Note: * The on-chip DMAC bus cycles are not inserted between the read and write cycles of
TAS instruction execution. However, bus release due to BREQ is carried out.
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REJ09B0273-0500
Section 2 CPU
Table 2.15 Shift Instructions
Execu-
tion
ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB
ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB
ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB
ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB
SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB
SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB
SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB
SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB
SHLL2 Rn 0100nnnn00001000 Rn<<2 → Rn 1 —
SHLR2 Rn 0100nnnn00001001 Rn>>2 → Rn 1 —
SHLL8 Rn 0100nnnn00011000 Rn<<8 → Rn 1 —
SHLR8 Rn 0100nnnn00011001 Rn>>8 → Rn 1 —
SHLL16 Rn 0100nnnn00101000 Rn<<16 → Rn 1 —
SHLR16 Rn 0100nnnn00101001 Rn>>16 → Rn 1 —
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REJ09B0273-0500
Section 2 CPU
Table 2.16 Branch Instructions
Exec.
BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 3/1* —
1, nop
BF/S label 10001111dddddddd Delayed branch, if T = 0, disp × 2 + 3/1* —
PC → PC; if T = 1, nop
BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 3/1* —
0, nop
BT/S label 10001101dddddddd Delayed branch, if T = 1, disp × 2 + 2/1* —
PC → PC; if T = 0, nop
BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → 2 —
PC
BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC 2 —
BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 2 —
+ PC → PC
BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, 2 —
Rm + PC → PC
JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2 —
JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, 2 —
Rm → PC
RTS 0000000000001011 Delayed branch, PR → PC 2 —
Note: * One state when it does not branch.
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REJ09B0273-0500
Section 2 CPU
Table 2.17 System Control Instructions
Exec.
CLRT 0000000000001000 0→T 1 0
CLRMAC 0000000000101000 0 → MACH, MACL 1 —
LDC Rm,SR 0100mmmm00001110 Rm → SR 1 LSB
LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1 —
LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1 —
LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3 LSB
LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3 —
LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3 —
LDS Rm,MACH 0100mmmm00001010 Rm → MACH 1 —
LDS Rm,MACL 0100mmmm00011010 Rm → MACL 1 —
LDS Rm,PR 0100mmmm00101010 Rm → PR 1 —
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm 1 —
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm 1 —
LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1 —
NOP 0000000000001001 No operation 1 —
RTE 0000000000101011 Delayed branch, stack area 4 —
→ PC/SR
SETT 0000000000011000 1→T 1 1
SLEEP 0000000000011011 Sleep 3* —
STC SR,Rn 0000nnnn00000010 SR → Rn 1 —
STC GBR,Rn 0000nnnn00010010 GBR → Rn 1 —
STC VBR,Rn 0000nnnn00100010 VBR → Rn 1 —
STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 2 —
STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 2 —
STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, BR → (Rn) 2 —
STS MACH,Rn 0000nnnn00001010 MACH → Rn 1 —
STS MACL,Rn 0000nnnn00011010 MACL → Rn 1 —
STS PR,Rn 0000nnnn00101010 PR → Rn 1 —
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REJ09B0273-0500
Section 2 CPU
Exec.
STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1 —
STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1 —
STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn) 1 —
TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm) 8 —
→ PC
Note: * The number of execution cycles before the chip enters sleep mode: The execution
cycles shown in the table are minimums. The actual number of cycles may be
increased when (1) contention occurs between instruction fetches and data access, or
(2) when the destination register of the load instruction (memory → register) and the
register used by the next instruction are the same.
2.5 Processing States
2.5.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.6 shows the transitions between the states.
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REJ09B0273-0500
Section 2 CPU
From any state

when RES = 0
RES = 0
HSTBY = 1
Power-on reset state
RES = 1
When an interrupt source

or DMA address error occurs
Exception processing state
Bus request
cleared
Bus request NMI interrupt
generated source occurs
Exception Exception
Bus release state processing processing
source occurs ends
Bus request Bus request

generated cleared
Bus request Bus request

generated cleared Program execution state
SBY bit SBY bit set
cleared for SLEEP
for SLEEP instruction
instruction
Sleep mode Software standby mode
Hardware standby mode
Power-down state
From any state when
RES = 0 and HSTBY = 0
Figure 2.6 Transitions between Processing States
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REJ09B0273-0500
Section 2 CPU
Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset
results. When the RES pin is high and MRES is low, a manual reset will occur.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception processing vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode.
This state has two modes: sleep mode and standby mode.
Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device
that has requested them.
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REJ09B0273-0500
Section 3 Operating Modes
3.1 Operating Mode Selection

The SH7050 series has five operating modes that are selected by pins MD3 to MD0 and FWE. The
mode setting pins should not be changed during operation of the SH7050 series, and only the
setting combinations shown in table 3.1 should be used.
Table 3.1 Operating Mode Selection
Pin Settings
Operating On-Chip Area 0
Mode No. FWE MD3 MD2 MD1 MD0 Mode Name ROM Bus Width
Mode 0 0 * * 0 0 MCU expanded mode Disabled 8 bits
Mode 1 0 0 1 16 bits
Mode 2 0 1 0 Enabled Set by BCR1
Mode 3 0 1 1 MCU single-chip mode Enabled —
Mode 16 1 0 0 Boot mode Enabled Set by BCR1
Mode 17 1 0 1 —
Mode 18 1 1 0 User program mode Enabled Set by BCR1
Mode 19 1 1 1 —
Mode 13 0/1 1 1 0 1 Writer mode
Note: * Pins MD3 and MD2 set the clock operating mode. For details of the clock mode
settings, see section 4.2, Clock Operating Modes.
There are two normal operating modes: single-chip mode and expanded mode.
Modes in which the flash memory can be programmed are boot mode and user program mode (the
two on-board programming modes) and writer mode in which programming is performed with an
EPROM programmer (a type which supports programming of this device).
For details, see the sections on ROM.
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Section 4 Clock Pulse Generator (CPG)
4.1 Overview
The clock pulse generator (CPG) supplies clock pulses inside the SH7050 series chip and to
external devices. The SH7050 series CPG consists of an oscillator circuit and a PLL multiplier
circuit. There are two methods of generating a clock with the CPG: by connecting a crystal
resonator, or by inputting an external clock. The oscillator circuit oscillates at the same frequency
as the input clock. A chip operating frequency of 1, 2, or 4 times the oscillator frequency can be
selected by means of the PLL multiplier circuit.
The CPG is halted in software standby mode and hardware standby mode.
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4.1.1 Block Diagram
A block diagram of the clock pulse generator is shown in figure 4.1.
CPG
EXTAL
Oscillator circuit
XTAL
PLL multiplier circuit

PLLVCC
Multiplier
PLLVSS circuit
PLLCAP f×4
Frequency
Frequency divider circuit
MD3 division
selection f×2
MD2 circuit
Frequency
divider circuit
f×1
CK
(system clock)
Internal clock
Figure 4.1 Block Diagram of the Clock Pulse Generator
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4.1.2 Pin Configuration
The pins relating to the clock pulse generator are shown in table 4.1.
Table 4.1 CPG Pins
Pin Name Abbreviation I/O Description

External clock EXTAL Input Crystal resonator or external clock input
Crystal XTAL Input Crystal resonator connection
System clock CK Output System clock output
Mode setting MD3 Input Sets PLL multiplication mode
Mode setting MD2 Input Sets PLL multiplication mode
PLL power supply PLLVCC Input PLL multiplier circuit power supply
PLL ground PLLVSS Input PLL multiplier circuit ground
PLL capacitance PLLCAP Input PLL multiplier circuit oscillation external
capacitance pin
4.2 Clock Operating Modes

The clock operating mode is set with the MD3 and MD2 pins.
Clock mode selection is possible in operating modes 0 to 3 and 16 to 19. In this case, do not set
both the MD3 and MD2 pin to 1. In programmer mode, the clock operating mode cannot be
changed.
The relationship between the mode pins and the clock operating mode is shown in table 4.2.
Table 4.2 Clock Operating Mode Settings
Input PLL Operating

Frequency Multiplication Frequency Range
Clock Mode MD3 MD2 Range (MHz) Factor (MHz)
Mode 0 0 0 4–10 ×1 4–10
Mode 1 0 1 4–10 ×2 8–20
Mode 2 1 0 4–5 ×4 16–20
Note: Crystal resonator and external clock input
For the chip operating frequency, a frequency of 1, 2, or 4 times the input frequency can be
selected as the internal clock by means of the on-chip PLL circuit. The system clock (CK pin)
output frequency is the same as that of the internal clock.
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The MD3 and MD2 pins should not be changed while the chip is operating, as normal operation
will not be possible in this case.
4.3 Clock Source

Clock pulses can be supplied from a connected crystal resonator or an external clock.
4.3.1 Connecting a Crystal Oscillator
Circuit Configuration: Figure 4.2 shows the example of connecting a crystal resonator. Use the
damping resistance (Rd) shown in table 4.3. An AT-cut parallel-resonance type crystal resonator
should be used. Load capacitors (CL1, CL2) must be connected as shown in the figure.
The clock pulses generated by the crystal resonator and internal oscillator are sent to the PLL
multiplier circuit, where a multiplied frequency is selected and supplied inside the SH7050 chip
and to external devices.
The crystal manufacturer should be consulted concerning the compatibility between the crystal
and the chip.
CL2
EXTAL
CL1
XTAL
Rd
CL1 = CL2 = 18Ð22 pF (recommended value)
Figure 4.2 Connection of the Crystal Oscillator (Example)
Table 4.3 Damping Resistance Values (Recommended Values)
Frequency (MHz)
Parameter 4 8 10
Rd (Ω) 500 200 0
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Crystal Oscillator: Figure 4.3 shows an equivalent circuit of the crystal oscillator. Use a crystal
oscillator with the characteristics listed in table 4.4.
L CL Rs
EXTAL XTAL
C0
Figure 4.3 Crystal Oscillator Equivalent Circuit
Table 4.4 Crystal Oscillator Parameters (Recommended Values)
Frequency (MHz)
Parameter 4 8 10
Rs max (Ω) 120 80 60
C0 max (pF) 7 7 7
4.3.2 External Clock Input Method
An example of external clock input connection is shown in figure 4.4. When the external clock is
stopped in standby mode, ensure that it goes high.
When the XTAL pin is placed in the open state, the parasitic capacitance should be 10 pF or less.
Even when an external clock is input, provide for a wait of at least the oscillation settling time
when powering on or exiting standby mode in order to secure the PLL settling time.
Open XTAL
External clock input EXTAL
Figure 4.4 External Clock Input Method (Example)
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4.4 Notes on Using

Notes on Board Design: When connecting a crystal oscillator, observe the following precautions:
• To prevent induction from interfering with correct oscillation, do not route any signal lines
near the oscillator circuitry.
• When designing the board, place the crystal oscillator and its load capacitors as close as
possible to the XTAL and EXTAL pins.
Figures 4.5 show the precautions regarding oscillator block board settings.
Crossing of signal
lines prohibited
CL1
XTAL
CL2
EXTAL
Figure 4.5 Cautions for Oscillator Circuit System Board Design
PLL Oscillation Power Supply: Place oscillation stabilization capacitor C1 and resistor R1 close
to the PLL and CAP pin, and ensure that no other signal lines cross this line. Supply the C1
ground from PLLVSS.
Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source,
and be sure to insert bypass capacitors CPB and CB close to the pins.
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R1 C1
PLLCAP
Rp
PLLVCC
CPB
PLLVSS
VCC
CB
VSS
Recommended values
CPB, CB: 0.1 µF
Rp: 200 Ω
R1: 3 kΩ
C1: 470 pF (laminated ceramic)
Figure 4.6 Points for Caution in PLL Power Supply Connection
PLLVSS
PLLCAP
PLLVCC
EXTAL
MD3
XTAL
VSS
Figure 4.7 Actual Example of Board Design
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Section 5 Exception Processing
5.1 Overview
5.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority shown in table 5.1. When several exception processing sources occur at once,
they are processed according to the priority shown.
Table 5.1 Types of Exception Processing and Priority Order
Exception Source Priority

Reset Power-on reset High
Address CPU address error
error DMAC address error
Interrupt NMI
User break
IRQ
On-chip peripheral modules: • Direct memory access controller
(DMAC)
• Advanced timer unit (ATU)
• Compare match timer (CMT)
• A/D converter (A/D)
• Serial communications interface
(SCI)
• Watchdog timer (WDT)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay Low
branch instruction* or instructions that rewrite the PC* )
1 2
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.
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5.1.2 Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing
shown in table 5.2.
Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing
Exception Source Timing of Source Detection and Start of Processing

Reset Power-on reset Starts when the RES pin changes from low to high.
Address error Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Interrupts Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Instructions Trap instruction Starts from the execution of a TRAPA instruction.
General illegal Starts from the decoding of undefined code anytime except after
instructions a delayed branch instruction (delay slot).
Illegal slot Starts from the decoding of undefined code placed in a delayed
instructions branch instruction (delay slot) or of instructions that rewrite the
PC.
When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:

The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception processing vector table (PC and SP are respectively the H'00000000 and
H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for
manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. 0
is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits
(I3–I0) of the status register (SR). The program begins running from the PC address fetched
from the exception processing vector table.
2. Exception processing triggered by address errors, interrupts and instructions:

SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the
interrupt priority level is written to the SR’s interrupt mask bits (I3–I0). For address error and
instruction exception processing, the I3–I0 bits are not affected. The start address is then
fetched from the exception processing vector table and the program begins running from that
address.
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5.1.3 Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in
memory. The exception processing vector table stores the start addresses of exception service
routines. (The reset exception processing table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception processing, the start addresses of
the exception service routines are fetched from the exception processing vector table, which
indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Exception Processing Vector Table
Vector
Exception Sources Numbers Vector Table Address Offset
Power-on reset PC 0 H'00000000–H'00000003
SP 1 H'00000004–H'00000007
(Reserved by system) 2 H'00000008–H'0000000B
(Reserved by system) 3 H'0000000C–H'0000000F
General illegal instruction 4 H'00000010–H'00000013
(Reserved by system) 5 H'00000014–H'00000017
Slot illegal instruction 6 H'00000018–H'0000001B
(Reserved by system) 7 H'0000001C–H'0000001F
CPU address error 9 H'00000024–H'00000027
DMAC address error 10 H'00000028–H'0000002B
Interrupts NMI 11 H'0000002C–H'0000002F
User break 12 H'00000030–H'00000033
: :
31 H'0000007C–H'0000007F
Trap instruction (user vector) 32 H'00000080–H'00000083
: :
63 H'000000FC–H'000000FF
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Vector
Exception Sources Numbers Vector Table Address Offset
Interrupts IRQ0 64 H'00000100–H'00000103
IRQ1 65 H'00000104–H'00000107
IRQ2 66 H'00000108–H'0000010B
IRQ3 67 H'0000010C–H'0000010F
IRQ4 68 H'00000110–H'00000113
IRQ5 69 H'00000114–H'00000117
IRQ6 70 H'00000118–H'0000011B
IRQ7 71 H'0000011C–H'0000011F
On-chip peripheral module* 72 H'00000120–H'00000124
: :
255 H'000003FC–H'000003FF
Note: * The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in section 6, Interrupt Controller, and table 6.3, Interrupt
Exception Processing Vectors and Priorities.
Table 5.4 Calculating Exception Processing Vector Table Addresses
Exception Source Vector Table Address Calculation

Resets Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts, Vector table address = VBR + (vector table address offset)
instructions = VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
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5.2 Resets
5.2.1 Power-On Reset
When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES
pin should be kept at low for at least the duration of the oscillation settling time when applying
power or when in standby mode (when the clock circuit is halted) or at least 20 tcyc (when the
clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip
peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins
during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3–I0) of
the status register (SR) are set to H'F (1111).
4. The values fetched from the exception processing vector table are set in the program counter
(PC) and SP and the program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
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5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.5.
Table 5.5 Bus Cycles and Address Errors
Bus Cycle
Bus
Type Master Bus Cycle Description Address Errors
Instruction CPU Instruction fetched from even address None (normal)
fetch Instruction fetched from odd address Address error occurs
Instruction fetched from other than on-chip None (normal)
peripheral module space*
Instruction fetched from on-chip peripheral Address error occurs
module space*
Instruction fetched from external memory space Address error occurs
when in single chip mode
Data CPU or Word data accessed from even address None (normal)
read/write DMAC Word data accessed from odd address Address error occurs
Longword data accessed from a longword None (normal)
boundary
Longword data accessed from other than a Address error occurs
long-word boundary
Byte or word data accessed in on-chip None (normal)
Longword data accessed in 16-bit on-chip None (normal)
Longword data accessed in 8-bit on-chip Address error occurs
External memory space accessed when in Address error occurs
single chip mode
Note: * See section 8, Bus State Controller.
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5.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the
executing instruction then finishes, address error exception processing starts up. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the address error that occurred and the program starts executing from
that address. The jump that occurs is not a delayed branch.
5.4 Interrupts
5.4.1 Interrupt Sources
Table 5.6 shows the sources that start up interrupt exception processing. These are divided into
NMI, user breaks, IRQ and on-chip peripheral modules.
Table 5.6 Interrupt Sources
Number of
Type Request Source Sources
NMI NMI pin (external input) 1
User break User break controller 1
IRQ IRQ0–IRQ7 (external input) 8
On-chip peripheral module Direct memory access controller (DMAC) 4
Advanced timer unit (ATU) 44
Compare match timer (CMT) 2
A/D converter 2
Serial communications interface (SCI) 12
Watchdog timer (WDT) 1
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller, and table 6.3, Interrupt Exception Processing Vectors and Priorities, for more
information on vector numbers and vector table address offsets.
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5.4.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts up
processing according to the results.
The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral
module interrupt priority levels can be set freely using the INTC’s interrupt priority level setting
registers A through H (IPRA to IPRH) as shown in table 5.7. The priority levels that can be set are
0–15. Level 16 cannot be set.
Table 5.7 Interrupt Priority Order
Type Priority Level Comment

NMI 16 Fixed priority level. Cannot be masked.
User break 15 Fixed priority level.
IRQ 0–15 Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
On-chip peripheral module 0–15 Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
5.4.3 Interrupt Exception Processing
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask bits (I3–I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3–I0. For NMI, however, the priority level is 16, but the value set in
I3–I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the
exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins.
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5.5 Exceptions Triggered by Instructions
5.5.1 Types of Exceptions Triggered by Instructions
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal
slot instructions, as shown in table 5.8.
Table 5.8 Types of Exceptions Triggered by Instructions
Type Source Instruction Comment

Trap instructions TRAPA —
Illegal slot Undefined code placed Delayed branch instructions: JMP, JSR,
instructions immediately after a delayed BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
branch instruction (delay slot) BRAF
and instructions that rewrite Instructions that rewrite the PC: JMP, JSR,
the PC BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
General illegal Undefined code anywhere —
instructions besides in a delay slot
5.5.2 Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU
operates as follows:

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
table that corresponds to the vector number specified in the TRAPA instruction. That address
is jumped to and the program starts executing. The jump that occurs is not a delayed branch.
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5.5.3 Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, illegal slot exception
processing starts up when that undefined code is decoded. Illegal slot exception processing also
starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The
processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as
follows:

2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump that occurs is not a delayed branch.
5.5.4 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The
CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of
illegal slot instructions, however, the program counter value stored is the start address of the
undefined code.
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5.6 When Exception Sources Are Not Accepted

When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in
table 5.9. When this happens, it will be accepted when an instruction that can accept the exception
is decoded.
Table 5.9 Generation of Exception Sources Immediately after a Delayed Branch

Instruction or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence Address Error Interrupt
Immediately after a delayed branch instruction*
1
Not accepted Not accepted
Immediately after an interrupt-disabled instruction*
2
Accepted Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
5.6.1 Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction located immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts

are not accepted. Address errors are accepted.
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5.7 Stack Status after Exception Processing Ends

The status of the stack after exception processing ends is as shown in table 5.10.
Table 5.10 Types of Stack Status After Exception Processing Ends
Types Stack Status

Address error
SP Address of instruction 32 bits

after executed instruction
SR 32 bits
Trap instruction
Address of instruction
SP after TRAPA instruction 32 bits
SR 32 bits
General illegal instruction
SP Start address of illegal

instruction 32 bits
SR 32 bits
Interrupt
Address of instruction
SP after executed instruction 32 bits
SR 32 bits
Illegal slot instruction

Jump destination address
SP of delay branch instruction 32 bits
SR 32 bits
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5.8 Notes on Use
5.8.1 Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will
occur when the stack is accessed during exception processing.
5.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error
will occur when the stack is accessed during exception processing.
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing
When the stack pointer is not a multiple of four, an address error will occur during stacking of the
exception processing (interrupts, etc.) and address error exception processing will start up as soon
as the first exception processing is ended. Address errors will then also occur in the stacking for
this address error exception processing. To ensure that address error exception processing does not
go into an endless loop, no address errors are accepted at that point. This allows program control
to be shifted to the address error exception service routine and enables error processing.
When an address error occurs during exception processing stacking, the stacking bus cycle (write)
is executed. During stacking of the status register (SR) and program counter (PC), the SP is –4 for
both, so the value of SP will not be a multiple of four after the stacking either. The address value
output during stacking is the SP value, so the address where the error occurred is itself output.
This means the write data stacked will be undefined.
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Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be
used by the user to order the priorities in which the interrupt requests are processed.
6.1.1 Features
The INTC has the following features:
• 16 levels of interrupt priority: By setting the eight interrupt-priority level registers, the
priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for
different request sources.
• NMI noise canceler function: NMI input level bits indicate the NMI pin status. By reading
these bits with the interrupt exception service routine, the pin status can be confirmed, enabling
it to be used as a noise canceler.
• Notification of interrupt occurrence can be reported externally (IRQOUT pin). For example, it
is possible to request bus rights if an external bus master is informed that a peripheral module
interrupt has occurred when the LSI has released the bus rights.
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6.1.2 Block Diagram
Figure 6.1 is a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
Input CPU/ Priority
IRQ3 control DMAC ranking
IRQ4 request judg- Com-
IRQ5 judgment parator
Interrupt
IRQ6 ment request
IRQ7
SR
(Interrupt request) I3 I2 I1 I0
UBC
(Interrupt request)
DMAC CPU
(Interrupt request)
ATU
(Interrupt request)
CMT
(Interrupt request)
SCI
(Interrupt request)
A/D
(Interrupt request)
WDT
DTER
ICR IPR DTC
ISR
IPRA–IPRH
Internal bus
Bus
Module bus
interface
INTC
UBC: User break controller ICR: Interrupt control register
DMAC: Direct memory access controller ISR: IRQ ststus register
CMT: Compare match timer DTER: DTC enable register
SCI: Serial communication interface IPRA–IPRH: Interrupt priority level setting
A/D: A/D converter registers A to H
WDT: Watchdog timer SR: Status register
Figure 6.1 INTC Block Diagram
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Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name Abbreviation I/O Function

Non-maskable interrupt input pin NMI I Input of non-maskable interrupt
request signal
Interrupt request input pins IRQ0–IRQ7 I Input of maskable interrupt request
signals
Interrupt request output pin IRQOUT O Output of notification signal when an
interrupt has occurred
6.1.4 Register Configuration
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts
and control external interrupt input signal detection.
Table 6.2 Register Configuration
Name Abbr. R/W Initial Value Address Access Sizes

Interrupt priority register A IPRA R/W H'0000 H'FFFF8348 8, 16, 32
Interrupt priority register B IPRB R/W H'0000 H'FFFF834A 8, 16, 32
Interrupt priority register C IPRC R/W H'0000 H'FFFF834C 8, 16, 32
Interrupt priority register D IPRD R/W H'0000 H'FFFF834E 8, 16, 32
Interrupt priority register E IPRE R/W H'0000 H'FFFF8350 8, 16, 32
Interrupt priority register F IPRF R/W H'0000 H'FFFF8352 8, 16, 32
Interrupt priority register G IPRG R/W H'0000 H'FFFF8354 8, 16, 32
Interrupt priority register H IPRH R/W H'0000 H'FFFF8356 8, 16, 32
Interrupt control register ICR R/W *1 H'FFFF8358 8, 16, 32
R(W)*
2
IRQ status register ISR H'0000 H'FFFF835A 8, 16, 32
Notes: Two access cycles are required for byte access and word access, and four cycles for
longword access.
1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.
2. Only 0 can be written, in order to clear flags.
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6.2 Interrupt Sources

There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules.
Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the
highest). Giving an interrupt a priority level of 0 masks it.
6.2.1 NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by
edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either
the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15.
6.2.2 User Break Interrupt
A user break interrupt has a priority of level 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15. For more information about the user break interrupt,
see Section 7, User Break Controller.
6.2.3 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0–IRQ7. Set the IRQ sense select bits
(IRQ0S–IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge
detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt
priority registers A and B (IPRA–IPRB).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F–IRQ7F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request
detection results are maintained until the interrupt request is accepted. Confirmation that IRQ
interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F–IRQ7F) of the
IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection
results can be withdrawn.
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In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt.
6.2.4 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules:
• Direct memory access controller (DMAC)

• Advanced timer unit (ATU)
• Compare match timer (CMT)
• A/D converter (A/D)
• Serial communications interface (SCI)
• Watchdog timer (WDT)
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers C–H (IPRC–
IPRH).
On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3–I0)
in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that
was accepted.
6.2.5 Interrupt Exception Vectors and Priority Rankings
Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. See table 5.4, Calculating Exception Processing Vector Table Addresses.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A–H (IPRA–IPRH). The ranking
of interrupt sources for IPRC–IPRH, however, must be the order listed under Priority within IPR
Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ
interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or
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more interrupt sources and interrupts from those sources occur simultaneously, their priority order
is the default priority order indicated at the right in table 6.3.
Table 6.3 Interrupt Exception Processing Vectors and Priorities
Interrupt Vector
Interrupt Priority
Vector Table Priority Corre- within IPR
Vector Address (Initial sponding Setting Default
Interrupt Source No. Offset Value) IPR (Bits) Range Priority
NMI 11 H'0000002C to 16 — — High
H'0000002F ↑
User 12 H'00000030 to 15 — —
break H'00000033
IRQ0 64 H'00000100 to 0 to 15 (0) IPRA —
H'00000103 (15–12)
IRQ1 65 H'00000104 to 0 to 15 (0) IPRA —
H'00000107 (11–8)
IRQ2 66 H'00000108 to 0 to 15 (0) IPRA —
H'0000010B (7–4)
IRQ3 67 H'0000010C to 0 to 15 (0) IPRA —
H'0000010F (3–0)
IRQ4 68 H'00000110 to 0 to 15 (0) IPRB —
H'00000113 (15–12)
IRQ5 69 H'00000114 to 0 to 15 (0) IPRB —
H'00000117 (11–8)
IRQ6 70 H'00000118 to 0 to 15 (0) IPRB —
H'0000011B (7–4)
IRQ7 71 H'0000011C to 0 to 15 (0) IPRB —
H'0000011F (3–0)
DMAC0 DEI0 72 H'00000120 to 0 to 15 (0) IPRC High
H'00000123 (15–12) ↑
DMAC1 DEI1 74 H'00000128 to 0 to 15 (0) ↓
H'0000012B Low
DMAC2 DEI2 76 H'00000130 to 0 to 15 (0) IPRC High
H'00000133 (11–8) ↑
DMAC3 DEI3 78 H'00000138 to 0 to 15 (0) ↓ ↓
H'0000013B Low Low
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Interrupt Vector
Interrupt Priority
ATU0 ATU01 ITV 80 H'00000140 to 0 to 15 (0) IPRC — High
H'00000143 (7–4) ↑
ATU02 ICI0A 84 H'00000150 to 0 to 15 (0) IPRC ↑ 1
H'00000153 (3–0)
ICI0B 85 H'00000154 to 2
H'00000157
ICI0C 86 H'00000158 to 3
H'0000015B
ICI0D 87 H'0000015C to ↓ 4
H'0000015F
ATU03 OVIO 88 H'00000160 to 0 to 15 (0) IPRD —
H'00000163 (15–12)
ATU1 ATU11 IMI1A 92 H'00000170 to 0 to 15 (0) IPRD ↑ 1
H'00000173 (11–8)
IMI1B 93 H'00000174 to 2
H'00000177
IMI1C 94 H'00000178 to ↓ 3
H'0000017B
ATU12 IMI1D 96 H'0000180 to 0 to 15 (0) IPRD ↑ 1
H'00000183 (7–4)
IMI1E 97 H'00000184 to 2
H'00000187
IMI1F 98 H'00000188 to ↓ 3
H'0000018B
ATU13 OV11 100 H'00000190 to 0 to 15 (0) IPRD —
H'00000193 (3–0)
ATU2 IMI2A 104 H'000001A0 to 0 to 15 (0) IPRE ↑ 1
H'000001A3 (15–12)
IMI2B 105 H'000001A4 to 2
H'000001A7
↓
OV12 106 H'000001A8 to ↓ 3 Low
H'000001AB
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Interrupt Vector
Interrupt Priority
ATU3 ATU31 IMI3A 108 H'000001B0 to 0 to 15 (0) IPRE ↑ 1 High
H'000001B3 (11–8) ↑
IMI3B 109 H'000001B4 to 2
H'000001B7
IMI3C 110 H'000001B8 to 3
H'000001BB
IMI3D 111 H'000001BC to ↓ 4
H'000001BF
ATU32 OV13 112 H'000001C0 to 0 to 15 (0) IPRE —
H'000001C3 (7–4)
ATU4 ATU41 IMI4A 116 H'000001D0 to 0 to 15 (0) IPRE ↑ 1
H'000001D3 (3–0)
IMI4B 117 H'000001D4 to 2
H'000001D7
IMI4C 118 H'000001D8 to 3
H'000001DB
IMI4D 119 H'000001DC to ↓ 4
H'000001DF
ATU42 OV14 120 H'000001E0 to 0 to 15 (0) IPRF —
H'000001E3 (15–12)
ATU5 IMI5A 124 H'000001F0 to 0 to 15 (0) IPRF ↑ 1
H'000001F3 (11–8)
IMI5B 125 H'000001F4 to 2
H'000001F7
OV15 126 H'000001F8 to ↓ 3
H'000001FB
ATU6 CMI6 128 H'00000200 to 0 to 15 (0) IPRF ↑ 1
H'00000203 (7–4)
ATU7 CMI7 129 H'00000204 to 2
H'00000207
ATU8 CMI8 130 H'00000208 to 3
H'0000020B
↓
ATU9 CMI9 131 H'0000020C to ↓ 4 Low
H'0000020F
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Interrupt Vector
Interrupt Priority
ATU10 ATU101 OSI10A 132 H'00000210 to 0 to 15 (0) IPRF ↑ 1 High
H'00000213 (3–0) ↑
OSI10B 133 H'00000214 to 2
H'00000217
OSI10C 134 H'00000218 to ↓ 3
H'0000021B
ATU102 OSI10D 136 H'00000220 to 0 to 15 (0) IPRG ↑ 1
H'00000223 (15–12)
OSI10E 137 H'00000224 to 2
H'00000227
OSI10F 138 H'00000228 to ↓ 3
H'0000022B
ATU103 OSI10G 140 H'00000230 to 0 to 15 (0) IPRG ↑ 1
H'00000233 (11–8)
OSI10H 141 H'00000234 to ↓ 2
H'00000237
CMT0 CMTI0 144 H'00000240 to 0 to 15 (0) IPRG ↑ 1
H'00000243 (7–4)
A/D0 ADI0 145 H'00000244 to ↓ 2
H'00000247
CMT1 CMT11 148 H'00000250 to 0 to 15 (0) IPRG ↑ 1
H'00000253 (3–0)
A/D1 ADI1 149 H'00000254 to ↓ 2
H'00000257
SCI0 ERI0 152 H'00000260 to 0 to 15 (0) IPRH ↑ 1
H'00000263 (15–12)
RXI0 153 H'00000264 to 2
H'00000267
TXI0 154 H'00000268 to 3
H'0000026B
↓
TEI0 155 H'0000026C to ↓ 4 Low
H'0000026F
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Interrupt Vector
Interrupt Priority
SCI1 ERI1 156 H'00000270 to 0 to 15 (0) IPRH ↑ 1 High
H'00000273 (11–8) ↑
RXI1 157 H'00000274 to 2
H'00000277
TXI1 158 H'00000278 to 3
H'0000027B
TEI1 159 H'0000027C to ↓ 4
H'0000027F
SCI2 ERI2 160 H'00000280 to 0 to 15 (0) IPRH ↑ 1
H'00000283 (7–4)
RXI2 161 H'00000284 to 2
H'00000287
TXI2 162 H'00000288 to 3
H'0000028B
TEI2 163 H'0000028C to ↓ 4
H'0000028F
↓
WDT ITI 164 H'00000290 to 0 to 15 (0) IPRH — Low
H'00000293 (3–0)
6.3 Description of Registers
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)
Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in
table 6.4.
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Bit: 15 14 13 12 11 10 9 8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Table 6.4 Interrupt Request Sources and IPRA–IPRH
Bits
Register 15–12 11–8 7–4 3–0
Interrupt priority register A IRQ0 IRQ1 IRQ2 IRQ3
Interrupt priority register B IRQ4 IRQ5 IRQ6 IRQ7
Interrupt priority register C DMAC0, 1 DMAC2, 3 ATU01 ATU02
Interrupt priority register D ATU03 ATU11 ATU12 ATU13
Interrupt priority register E ATU2 ATU31 ATU32 ATU41
Interrupt priority register F ATU42 ATU5 ATU6–9 ATU101
Interrupt priority register G ATU102 ATU103 CMT0, A/D0 CMT1, A/D1
Interrupt priority register H SCI0 SCI1 SCI2 WDT
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4 and 3–0. Interrupt
priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If
multiple on-chip peripheral modules are assigned to same bit (DMAC0 and DMAC1, DMAC2
and DMAC3, ATU6 to ATU9, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules
are set to the same priority rank.
IPRA–IPRH are initialized to H'0000 by a power-on reset. They are not initialized in standby
mode.
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6.3.2 Interrupt Control Register (ICR)
The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input
pin NMI and IRQ0 –IRQ7 and indicates the input signal level to the NMI pin. A power-on reset
and hardware standby mode initialize ICR but the software standby mode does not.
Bit: 15 14 13 12 11 10 9 8
NMIL — — — — — — NMIE
Initial value: * 0 0 0 0 0 0 0
R/W: R R R R R R R R/W
Bit: 7 6 5 4 3 2 1 0
IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S
Note: * When NMI input is high: 1; when NMI input is low: 0
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL Description

0 NMI input level is low
1 NMI input level is high
Bits 14 to 9—Reserved: These bits always read as 0. The write value should always be 0.
Bit 8—NMI Edge Select (NMIE)
Bit 8: NMIE Description

0 Interrupt request is detected on falling edge of NMI input (initial value)
1 Interrupt request is detected on rising edge of NMI input
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Bits 7 to 0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7
interrupt request detection mode.
Bits 7-0: IRQ0S–IRQ7S Description

0 Interrupt request is detected on low level of IRQ input (initial value)
1 Interrupt request is detected on falling edge of IRQ input
6.3.3 IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input
pins IRQ0–IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1.
A power-on reset initializes ISR but the standby mode does not.
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
R/W: R R R R R R R R
Bit: 7 6 5 4 3 2 1 0
IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F
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Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt
request status.
Bits 7-0:
IRQ0F–IRQ7F Detection Setting Description
0 Level detection No IRQn interrupt request exists.
Clear conditions: When IRQn input is high level
Edge detection No IRQn interrupt request was detected. (initial value)
Clear conditions:
1. When a 0 is written after reading IRQnF = 1 status
2. When IRQn interrupt exception processing has been
executed
1 Level detection An IRQn interrupt request exists.
Set conditions: When IRQn input is low level
Edge detection An IRQn interrupt request was detected.
Set conditions: When a falling edge occurs at an IRQn
input
IRQnS
(0: level, 1: edge) ISR.IRQnF
level
selector
IRQ pin detection CPU

interrupt
edge request
S Q
detection
RESIRQn R
(IRQn interrupt reception/writing a 0 to IRQnF after reading an IRQnF = 1)
Figure 6.2 IRQ0 – IRQ7 Interrupt Control
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6.4 Interrupt Operation
6.4.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
following the priority levels set in interrupt priority level setting registers A–H (IPRA–IPRH).
Lower-priority interrupts are ignored. They are held pending until interrupt requests designated
as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by
accessing the IRQ status register (ISR). See section 6.2.3, IRQ Interrupts, for details. Interrupts
held pending due to edge detection are cleared by a power-on reset or a manual reset. If two of
these interrupts have the same priority level or if multiple interrupts occur within a single
module, the interrupt with the highest default priority or the highest priority within its IPR
setting range (as indicated in table 6.3) is selected.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3–I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is ignored. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
next instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing (figure 6.5).
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in
the status register (SR).
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the point when the CPU starts interrupt exception
processing instead of instruction execution as noted in (5) above. However, if the interrupt
controller accepts an interrupt with a higher priority than one it is in the midst of accepting, the
IRQOUT pin will remain low level.
9. The CPU reads the start address of the exception service routine from the exception vector
table for the accepted interrupt, jumps to that address, and starts executing the program there.
This jump is not a delay branch.
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Program
execution state
No
Interrupt?
Yes
No
NMI?
Yes No
User break?
Yes Level 15 No
interrupt?
IRQOUT = low level*1
Yes
Level 14 No
Save SR to stack interrupt?
Yes I3 to I0 ≤ No
level 14? Yes Level 1
Save PC to stack interrupt?
No Yes I3 to I0 ≤
Copy accept-interrupt level 13? Yes
level to I3 to I0
No Yes I3 to I0 =
IRQOUT = high level*2 level 0?
Reads exception No
vector table
Branches to exception
service routine
I3 to I0: Interrupt mask bits of status register

Notes: 1. IRQOUT is the same signal as the interrupt request signal to the CPU (see
figure 6.1). Thus, it is output when there is a higher priority interrupt request
than the one in the I3 to I0 bits of the SR.
2. When the accepted interrupt is sensed by edge, the IRQOUT pin becomes
high level at the point when the CPU starts interrupt exception processing
instead of instruction execution (before SR is saved to the stack).
If the interrupt controller has accepted another interrupt with a higher priority
and has output an interrupt request to the CPU, the IRQOUT pin will remain
low level.
Figure 6.3 Interrupt Sequence Flowchart
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6.4.2 Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address
4n–8 PC*1 32 bits SP*2
4n–4 SR 32 bits
4n
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executing instruction
2. Always be certain that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
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6.5 Interrupt Response Time

Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is
accepted.
Table 6.5 Interrupt Response Time
Number of States
NMI, Peripheral
Item Module IRQ Notes
DMAC active judgment 0 or 1 1 1 state required for interrupt
signals for which DMAC
activation is possible
Compare identified inter- 2 3
rupt priority with SR mask
level
Wait for completion of X (≥ 0) The longest sequence is for
sequence currently being interrupt or address-error
executed by CPU exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Time from start of interrupt 5 + m1 + m2 + m3 Performs the PC and SR
exception processing until saves and vector address
fetch of first instruction of fetch.
exception service routine
starts
Interrupt Total: 7 + m1 + m2 + m3 8 + m1 + m2 + m3
response Minimum: 10 11 0.50 to 0.55 µs at 20 MHz
time
Maximum: 12 + 2 (m1 + m2 + 12 + 2 (m1 + m2 + 0.95 µs at 20 MHz*
m3) + m4 m3) + m4
Note: m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* When m1 = m2 = m3 = m4 = 1
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Interrupt acceptance
5 + m1 + m2 + m3
1 3 3 m1 m2 1 m3 1
IRQ
Instruction (instruction F D E E M M E M E E
replaced by interrupt
exception processing)
Overrun fetch F
Interrupt service routine
F D E
start instruction
F: Instruction fetch (instruction fetched from memory where program is stored).

D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed
according to the results of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
6.6 Data Transfer with Interrupt Request Signals

The following data transfers can be done using interrupt request signals:
• Activate DMAC only, without generating CPU interrupt
Among interrupt sources, those designated as DMAC activating sources are masked and not input
to the INTC. The masking condition is listed below:
Mask condition = DME • (DE0 • source selection 0 + DE1 × source selection 1 + DE2 •
source selection 2 + DE3 • source selection 3)
Figure 6.6 is a block diagram of interrupt controller.
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interrupt source
DMAC
Interrupt request flag
(generated by DMAC)
clear
interrupt source (not designated as DMAC

activating sources)
interrupt request
Figure 6.6 Block Diagram of Interrupt Controller
6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources
1. Either do not select the DMAC as a source, or clear the DME bit to 0.
2. Activating sources are applied to the CPU when interrupts occur.
3. The CPU clears interrupt sources with its interrupt processing routine and performs the
necessary processing.
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources
1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources are masked
regardless of the interrupt priority level register settings.
2. Activating sources are applied to the DMAC when interrupts occur.
3. The DMAC clears activating sources at the time of data transfer.
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Section 7 User Break Controller (UBC)
7.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. Break
conditions are set in the UBC and a user break interrupt is generated according to the conditions of
the bus cycle generated by the CPU, DMAC, or DTC. This function makes it easy to design an
effective self-monitoring debugger, enabling the chip to easily debug programs without using a
large in-circuit emulator.
7.1.1 Features
The features of the user break controller are:
• Break compare conditions can be set:

 Address
 CPU cycle/DMA cycle
 Instruction fetch or data access
 Read or write
 Operand size: byte/word/longword
• User break interrupt generated upon satisfying break conditions. A user-designed user break
interrupt exception processing routine can be run.
• Select either to break in the CPU instruction fetch cycle before the instruction is executed or
after.
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7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the UBC.
Bus
Module bus
interface
Internal bus
UBBR UBAMRH UBARH
UBAMRL UBARL
Break condition comparator
User break
interrupt Interrupt request
generating
circuit
UBC
Interrupt controller
UBARH, UBARL: User break address registers H, L

UBAMRH, UBAMRL: User break address mask registers H, L
UBBR: User break bus cycle register
Figure 7.1 User Break Controller Block Diagram
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The UBC has the five registers shown in table 7.1. Break conditions are established using these
registers.
Initial Access
Name Abbr. R/W Value Address* Size
User break address register H UBARH R/W H'0000 H'FFFF8600 8, 16, 32
User break address register L UBARL R/W H'0000 H'FFFF8602 8, 16, 32
User break address mask register H UBAMRH R/W H'0000 H'FFFF8604 8, 16, 32
User break address mask register L UBAMRL R/W H'0000 H'FFFF8606 8, 16, 32
User break bus cycle register UBBR R/W H'0000 H'FFFF8608 8, 16, 32
Note: * In register access, three cycles are required for byte access and word access, and six
cycles for longword access.
7.2 Register Descriptions
7.2.1 User Break Address Register (UBAR)
UBARH:
Bit: 15 14 13 12 11 10 9 8
UBARH UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24
Bit: 7 6 5 4 3 2 1 0
UBARH UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16
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UBARL:
Bit: 15 14 13 12 11 10 9 8
UBARL UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8
Bit: 7 6 5 4 3 2 1 0
UBARL UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0
The user break address register (UBAR) consists of user break address register H (UBARH) and
user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH
stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the
lower bits (bits 15 to 0). UBARH and UBARL are initialized by a power on reset to H'0000. They
are not initialized in software standby mode.
UBARH Bits 15 to 0—User Break Address 31 to 16 (UBA31 to UBA16): These bits store the
upper bit values (bits 31 to 16) of the address of the break condition.
UBARL Bits 15 to 0—User Break Address 15 to 0 (UBA15 to UBA0): These bits store the
lower bit values (bits 15 to 0) of the address of the break condition.
7.2.2 User Break Address Mask Register (UBAMR)
UBAMRH:
Bit: 15 14 13 12 11 10 9 8
UBAMRH UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
Bit: 7 6 5 4 3 2 1 0
UBAMRH UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16
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UBAMRL:
Bit: 15 14 13 12 11 10 9 8
UBAMRL UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8
Bit: 7 6 5 4 3 2 1 0
UBAMRL UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0
The user break address mask register (UBAMR) consists of user break address mask register H
(UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH designates whether to mask any of the break address bits
established in the UBARH, and UBAMRL designates whether to mask any of the break address
bits established in the UBARL. UBAMRH and UBAMRL are initialized by a power on reset to
H'0000. They are not initialized in software standby mode.
UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits
designate whether to mask any of the break address 31 to 16 bits (UBA31 to UBA16) established
in the UBARH.
UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits
designate whether to mask any of the break address 15 to 0 bits (UBA15 to UBA0) established in
the UBARL.
Bits 15–0: UBMn Description

0 Break address UBAn is included in the break conditions (initial value)
1 Break address UBAn is not included in the break conditions
Note: n = 31 to 0
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7.2.3 User Break Bus Cycle Register (UBBR)
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0
User break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from
among the following four break conditions:
1. CPU cycle/DMA cycle

2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
UBBR is initialized by a power on reset to H'0000. It is not initialized in software standby mode.
Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break
conditions for CPU cycles or peripheral cycles (DMA cycles).
Bit 7: CP1 Bit 6: CP0 Description

0 0 No user break interrupt occurs (initial value)
1 Break on CPU cycles
1 0 Break on peripheral cycles
1 Break on both CPU and peripheral cycles
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Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to
break on instruction fetch and/or data access cycles.
Bit 5: ID1 Bit 4: ID0 Description

1 Break on instruction fetch cycles
1 0 Break on data access cycles
1 Break on both instruction fetch and data access cycles
Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read
and/or write cycles.
Bit 3: RW1 Bit 2: RW0 Description

1 Break on read cycles
1 0 Break on write cycles
1 Break on both read and write cycles
Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break
condition.
Bit 1: SZ1 Bit 0: SZ0 Description

0 0 Operand size is not a break condition (initial value)
1 Break on byte access
1 0 Break on word access
1 Break on longword access
Note: When breaking on an instruction fetch, set the SZ0 bit to 0. All instructions are considered
to be word-size accesses (even when there are instructions in on-chip memory and 2
instruction fetches are done simultaneously in 1 bus cycle).
Operand size is word for instructions or determined by the operand size specified for the
CPU/DMAC data access. It is not determined by the bus width of the space being
accessed.
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7.3 Operation
7.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break interrupt exception processing is described
below:
1. The user break addresses are set in the user break address register (UBAR), the desired masked
bits in the addresses are set in the user break address mask register (UBAMR) and the breaking
bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three
groups of the UBBR’s CPU cycle/peripheral cycle select bits (CP1, CP0), instruction
fetch/data access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no
user break interrupt is generated), no user break interrupt will be generated even if all other
conditions are in agreement. When using user break interrupts, always be certain to establish
bit conditions for all of these three groups.
2. The UBC uses the method shown in figure 7.2 to judge whether set conditions have been
fulfilled. When the set conditions are satisfied, the UBC sends a user break interrupt request
signal to the interrupt controller (INTC).
3. The interrupt controller checks the accepted user break interrupt request signal’s priority level.
The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level
in bits I3–I0 in the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user
break interrupt cannot be accepted but it is held pending until user break interrupt exception
processing can be carried out. Consequently, user break interrupts within NMI exception
service routines cannot be accepted, since the I3–I0 bit level is 15. However, if the I3–I0 bit
level is changed to 14 or lower at the start of the NMI exception service routine, user break
interrupts become acceptable thereafter. Section 6, Interrupt Controller, describes the handling
of priority levels in greater detail.
4. The INTC sends the user break interrupt request signal to the CPU, which begins user break
interrupt exception processing upon receipt. See Section 6.4, Interrupt Operation, for details on
interrupt exception processing.
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UBARH/UBARL UBAMRH/UBAMRL
32
32
Internal address 32
bits 31–0 32 32
CP1 CP0
CPU cycle
DMA cycle
ID1 ID0
Instruction fetch User

break
interrupt
Data access
RW1 RW0
Read cycle
Write cycle
SZ1 SZ0
Byte size
Word size
Longword size
Figure 7.2 Break Condition Judgment Method
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7.3.2 Break on On-Chip Memory Instruction Fetch Cycle
On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle.
Therefore, 2 instructions can be retrieved in 1 bus cycle when fetching instructions from on-chip
memory. At such times, only 1 bus cycle is generated, but by setting the start addresses of both
instructions in the user break address register (UBAR) it is possible to cause independent breaks.
In other words, when wanting to effect a break using the latter of two addresses retrieved in 1 bus
cycle, set the start address of that instruction in UBAR. The break will occur after execution of the
former instruction.
7.3.3 Program Counter (PC) Values Saved
Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the
stack in user break interrupt exception processing is the address that matches the break condition.
The user break interrupt is generated before the fetched instruction is executed. If a break
condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction
(delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user
break interrupt is not accepted immediately, but the break condition establishing instruction is
executed. The user break interrupt is accepted after execution of the instruction that has accepted
the interrupt. In this case, the PC value saved is the start address of the instruction that will be
executed after the instruction that has accepted the interrupt.
Break on Data Access (CPU/Peripheral): The program counter (PC) value is the top address of
the next instruction after the last instruction executed before the user break exception processing
started. When data access (CPU/peripheral) is set as a break condition, the place where the break
will occur cannot be specified exactly. The break will occur at the instruction fetched close to
where the data access that is to receive the break occurs.
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7.4 Use Examples
7.4.1 Break on CPU Instruction Fetch Cycle
1. Register settings: UBARH = H'0000

UBARL = H'0404
UBBR = H'0054
Conditions set: Address: H'00000404
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)
A user break interrupt will occur before the instruction at address H'00000404. If it is possible for
the instruction at H'00000402 to accept an interrupt, the user break exception processing will be
executed after execution of that instruction. The instruction at H'00000404 is not executed. The
PC value saved is H'00000404.

UBARL = H'389C
UBBR = H'0058
Conditions set: Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.

UBARL = H'0147
UBBR = H'0054
Bus cycle: CPU, instruction fetch, read
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be done after address error
exception processing.
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7.4.2 Break on CPU Data Access Cycle

UBARL = H'3456
UBBR = H'006A
Bus cycle: CPU, data access, write, word
A user break interrupt occurs when word data is written into address H'00123456.
2. Register settings: UBARH = H'00A8

UBARL = H'0391
UBBR = H'0066
Conditions set: Address: H'00A80391
Bus cycle: CPU, data access, read, word
A user break interrupt does not occur because the word access was performed on an even address.
7.4.3 Break on DMA/DTC Cycle

UBARL = H'BCDC
UBBR = H'00A7
Conditions set: Address: H'0076BCDC
Bus cycle: DMA, data access, read, longword
A user break interrupt occurs when longword data is read from address H'0076BCDC.

UBARL = H'45C8
UBBR = H'0094
Conditions set: Address: H'002345C8
Bus cycle: DMA, instruction fetch, read
A user break interrupt does not occur because no instruction fetch is performed in the DMA/CTC
cycle.
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7.5 Cautions on Use
7.5.1 On-Chip Memory Instruction Fetch
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
7.5.2 Instruction Fetch at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF

TRAPA instruction, branch taken: TRAPA
Instruction fetch cycles: Conditional branch fetch → Next-instruction overrun fetch
→ Next-instruction overrun fetch → Branch destination fetch
Instruction execution: Conditional branch instruction execution → Branch destination
instruction execution
2. When branching with a delayed conditional instruction: BT/S and BF/S instructions
Instruction fetch order: Corresponding instruction fetch → next instruction fetch (delay
slot) → overrun fetch of instruction after next → branch destination instruction fetch
Instruction execution order: Corresponding instruction execution → delay slot instruction
execution → branch destination instruction execution
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
However, because the instruction that is the object of the break first breaks after a definite
instruction fetch and execution, the kind of overrun fetch instructions noted above do not
become objects of a break. If data access breaks are also included with instruction fetch breaks
as break conditions, a break occurs because the instruction overrun fetch is also regarded as
becoming a data break.
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7.5.3 Contention between User Break and Exception Handling
If a user break is set for the fetch of a particular instruction, and exception handling with higher
priority than a user break is in contention and is accepted in the decode stage for that instruction
(or the next instruction), user break exception handling may not be performed after completion of
the higher-priority exception handling routine (on return by RTE).
7.5.4 Break at Non-Delay Branch Instruction Jump Destination
When a branch instruction with no delay slot (including exception handling) jumps to the jump
destination instruction on execution of the branch, a user break will not be generated even if a user
break condition has been set for the first jump destination instruction fetch.
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Section 8 Bus State Controller (BSC)
8.1 Overview
The bus state controller (BSC) divides up the address spaces and outputs control for various types
of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI without
external circuitry.
8.1.1 Features
The BSC has the following features:
• Address space is divided into four spaces

 A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum linear
4-Mbyte for on-chip ROM ineffective mode for address space CS0
 A maximum linear 4 Mbytes for each of the address spaces CS1–CS3
 Bus width can be selected for each space (8 or 16 bits)
 Wait states can be inserted by software for each space
 Wait state insertion with WAIT pin in external memory space access
 Outputs control signals for each space according to the type of memory connected
• On-chip ROM and RAM interfaces
 On-chip RAM access of 32 bits in 1 state
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8.1.2 Block Diagram
Figure 8.1 shows the BSC block diagram.
Internal bus
Bus interface
On-chip
memory RAMER
control unit
WCR1
Wait
WAIT
Module bus
control unit
WCR2
BCR1
Area
CS0–CS3
control unit
BCR2
RD
Memory
control unit
WRH, WRL
BSC
WCR1: Wait control register 1 BCR1: Bus control register 1

WCR2: Wait control register 2 BCR2: Bus control register 2
RAMER: RAM emulation register
Figure 8.1 BSC Block Diagram
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Table 8.1 shows the bus state controller pin configuration.
Signal I/O Description

A21–A0 O Address output
D15–D0 I/O 16-bit data bus.
CS0–CS3 O Chip select, indicating the area being accessed
RD O Strobe that indicates the read cycle for ordinary space/multiplex I/O.
WRH O Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
WRL O Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
WAIT I Wait state request signal
BREQ I Bus release request input
BACK O Bus use enable output
Note: When an 8-bit bus width is selected for external space, WRL is enabled.
When a 16-bit bus width is selected for external space, WRH and WRL are enabled.
The BSC has eight registers. These registers are used to control wait states, bus width, and
interfaces with memories like ROM and SRAM, as well as refresh control. The register
configurations are listed in table 8.2.
All registers are 16 bits. All BSC registers are all initialized by a power-on reset, but are not by a
manual reset. Values are maintained in standby mode.
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Name Abbr. R/W Initial Value Address Access Size

Bus control register 1 BCR1 R/W H'000F H'FFFF8620 8, 16, 32
Bus control register 2 BCR2 R/W H'FFFF H'FFFF8622 8, 16, 32
Wait state control register 1 WCR1 R/W H'FFFF H'FFFF8624 8, 16, 32
Wait state control register 2 WCR2 R/W H'000F H'FFFF8626 8, 16, 32
RAM emulation register RAMER R/W H'0000 H'FFFF8628 8, 16, 32
Notes: 1. When using a longword access to write to RAMER , always write 0 in the lower word
(address H'FFFF8630). Operation cannot be guaranteed if a non-zero value is written.
2. In register access, three cycles are required for byte access and word access, and six
cycles for longword access.
8.1.5 Address Map
Figure 8.2 shows the address format used by the SH7050 series.
A31–A24 A23, A22 A21 A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS0 to CS3 space when 00000000 (H'00)
DRAM space when 00000001 (H'01)
Reserved (do not access) when 00000010 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 8.2 Address Format
This LSI uses 32-bit addresses:
• A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the
corresponding areas when bits A31 to A24 are 00000000.
• A21 to A0 are output externally.
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Table 8.3 and table 8.4 show address map.
Table 8.3 Address Map (128 kB ROM/6 kB RAM Version)
• On-chip ROM effective mode
Address Space Memory Size Bus Width

H'0000 0000 to H'0001 FFFF On-chip ROM On-chip ROM 128 kB 32bit
H'0002 0000 to H'001F FFFF Reserved Reserved
8, 16 bit *
1
H'0020 0000 to H'003F FFFF CS0 space External space 2 MB
8, 16 bit *
1
8, 16 bit *
1
H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB
8, 16 bit *
1
H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB
H'0100 0000 to H'FFFF 7FFF Reserved Reserved
H'FFFF 8000 to H'FFFF 87FF On-chip peripheral On-chip peripheral 2 kB 8, 16 bit
module module
H'FFFF 8800 to H'FFFF E7FF Reserved Reserved
H'FFFF E800 to H'FFFF FFFF On-chip RAM On-chip RAM 6 kB 32 bit
• On-chip ROM ineffective mode

8, 16 bit *
2
8, 16 bit *
1
8, 16 bit *
1
8, 16 bit *
1
module module
H'FFFF 8800 to H'FFFF E7FF Reserved Reserved
H'FFFF E800 to H'FFFF FFFF On-chip RAM On-chip RAM 6 kB 32 bit
Notes: 1. Selected by on-chip register settings.
2. Selected by the mode pin.
Do not access reserved spaces. Operation cannot be guaranteed if they are accessed.
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Table 8.4 Address Map (256 kB ROM/10 kB RAM Version)
• On-chip ROM effective mode

H'0000 0000 to H'0003 FFFF On-chip ROM On-chip ROM 256 kB 32 bit
H'0004 0000 to H'001F FFFF Reserved Reserved
8, 16 bit *
1
8, 16 bit *
1
8, 16 bit *
1
8, 16 bit *
1
module module
H'FFFF 8800 to H'FFFF D7FF Reserved Reserved
H'FFFF D800 to H'FFFF FFFF On-chip RAM On-chip RAM 10 kB 32 bit
• On-chip ROM ineffective mode

8, 16 bit *
2
8, 16 bit *
1
8, 16 bit *
1
8, 16 bit *
1
module module
H'FFFF 8800 to H'FFFF D7FF Reserved Reserved
H'FFFF D800 to H'FFFF FFFF On-chip RAM On-chip RAM 10 kB 32 bit
Notes: 1. Selected by on-chip register settings.
2. Selected by the mode pin.
Do not access reserved spaces. Operation cannot be guaranteed if they are accessed.
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8.2 Description of Registers
8.2.1 Bus Control Register 1 (BCR1)
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
— — — — A3SZ A2SZ A1SZ A0SZ
R/W: R R R R R/W R/W R/W R/W
BCR1 is a 16-bit read/write register that specifies the bus size of the CS spaces.
Write bits 15–0 of BCR1 during the initialization stage after a power-on reset, and do not change
the values thereafter. In on-chip ROM effective mode, do not access any of the CS spaces until
after completion of register initialization. In on-chip ROM ineffective mode, do not access any CS
space other than CS0 until after completion of register initialization.
BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bits 15–4—Reserved: These bits always read as 0. The write value should always be 0.
Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 3: A3SZ Description

0 Byte (8 bit) size
1 Word (16 bit) size (initial value)
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0 Byte (8 bit) size

0 Byte (8 bit) size
Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting

0 Byte (8 bit) size
Note: A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode,
the CS0 space bus size is specified by the mode pin.
8.2.2 Bus Control Register 2 (BCR2)
Bit: 15 14 13 12 11 10 9 8
IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00
Bit: 7 6 5 4 3 2 1 0
CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert
extension of each CS space.
BCR2 is initialized by a power-on reset and in hardware standby mode to H'FFFF. It is not
initialized by software standby mode.
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Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00):
These bits specify idle cycles inserted between consecutive accesses when the second one is to a
different CS area after a read. Idles are used to prevent data conflict between ROM (and other
memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even
when access is to the same area, idle cycles must be inserted when a read access is followed
immediately by a write access. The idle cycles to be inserted comply with the area specification of
the previous access. Refer to section 10.6, Waits between Access Cycles, for details.
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between
cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00
specify the idle between cycles for CS0 space.
Bit 15: IW31 Bit 14: IW30 Description

0 0 No idle cycle after accessing CS3 space
1 Inserts one idle cycle
1 0 Inserts two idle cycles
1 Inserts three idle cycles (initial value)



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Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by once
negating the CSn signal when doing consecutive accesses of the same CS space. When a write
immediately follows a read, the number of idle cycles inserted is the larger of the two values
specified by IW and CW. Refer to section 8.4, Waits between Access Cycles, for details.
CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access
idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies
the continuous access idles for CS0 space.
Bit 7: CW3 Description

0 No CS3 space continuous access idle cycles
1 One CS3 space continuous access idle cycle (initial value)



Bits 3–0—CS CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle
extension specification is for making insertions to prevent extension of the RD signal or WRx
signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one
cycle before and after each bus cycle, which simplifies interfaces with external devices and also
has the effect of extending write data hold time. Refer to section 8.3.3 CS Assert Period Extension
for details.
SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert
extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and
SW0 specifies the CS assert extension for CS0 space access.
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Bit 3: SW3 Description

0 No CS3 space CS assert extension
1 CS3 space CS assert extension (initial value)



8.2.3 Wait Control Register 1 (WCR1)
Bit: 15 14 13 12 11 10 9 8
W33 W32 W31 W30 W23 W22 W21 W20
Bit: 7 6 5 4 3 2 1 0
W13 W12 W11 W10 W03 W02 W01 W00
WCR1 is a 16-bit read/write register that specifies the number of wait cycles (0–15) for each CS
space.
WCR1 is initialized by a power-on reset and in hardware standby mode to H'FFFF. It is not
Bits 15–12—CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of
waits for CS3 space access.
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Bit 15: Bit 14: Bit 13: Bit 12:

W33 W32 W31 W30 Description
0 0 0 0 No wait (external wait input disabled)
0 0 0 1 1 wait external wait input enabled
⋅⋅⋅
1 1 1 1 15 wait external wait input enabled (initial value)
Bit 11: Bit 10: Bit 9: Bit 8:

⋅⋅⋅

⋅⋅⋅

⋅⋅⋅
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8.2.4 Wait Control Register 2 (WCR2)
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
— — — — DSW3 DSW2 DSW1 DSW0
WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space
and CS space for DMA single address mode transfers.
Do not perform any DMA single address transfers before WCR2 is set.
WCR2 is initialized by a power-on reset and in hardware standby mode to H'000F. It is not
Bits 3–0—CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,
DSW1, DSW0): Specifies the number of waits for CS space access (0–15) during DMA single
address mode accesses. These bits are independent of the W bits of the WCR1.

DSW3 DSW2 DSW1 DSW0 Description
0 0 0 1 1 wait (external wait input enabled)
⋅⋅⋅
1 1 1 1 15 wait (external wait input enabled) (initial value)
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8.2.5 RAM Emulation Register (RAMER)
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
— — — — — RAMS RAM1 RAM0
R/W: R R R R R R/W R/W R/W
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been
modified. Operation cannot be guaranteed if such an access is made.
Bits 15 to 3—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if
1 is written.
Bit 2—RAM Select (RAMS): Used together with bits 1 and 0 to designate the RAM area (table
8.5 and table 8.6).
When 1 is written to this bit, all flash memory blocks are write/erase-protected.
This bit is ignored in modes with no on-chip ROM.
Bits 1 and 0—RAM Area Specification (RAM1, RAM0): These bits are used together with the
RAMS bit to designate the RAM area (tables 8.5 and 8.6).
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Table 8.5 RAM Area Setting Method (128 kB ROM/6 kB RAM Version)
RAM Area Bit 2: RAMS Bit 1: RAM1 Bit 0: RAM0

H'FFFF E800 to H'FFFF EBFF 0 * *
H'0001 F000 to H'0001 F3FF 1 0 0
H'0001 F400 to H'0001 F7FF 1 0 1
H'0001 F800 to H'0001 FBFF 1 1 0
H'0001 FC00 to H'0001 FFFF 1 1 1
*: Don’t care
Table 8.6 RAM Area Setting Method (256 kB ROM/10 kB RAM Version)
RAM Area Bit 2: RAMS Bit 1: RAM1 Bit 0: RAM0

H'FFFF D800 to H'FFFF DBFF 0 * *
H'0003 F000 to H'0003 F3FF 1 0 0
H'0003 F400 to H'0003 F7FF 1 0 1
H'0003 F800 to H'0003 FBFF 1 1 0
H'0003 FC00 to H'0003 FFFF 1 1 1
*: Don’t care
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8.3 Accessing Ordinary Space

A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM
direct connections.
8.3.1 Basic Timing
Figure 8.3 shows the basic timing of ordinary space access. Ordinary access bus cycles are
performed in 2 states.
T1 T2
CK
Address
CSn
RD
Read
Data
WRx
Write
Data
Figure 8.3 Basic Timing of Ordinary Space Access
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8.3.2 Wait State Control
The number of wait states inserted into ordinary space access states can be controlled using the
WCR settings (figure 8.4).
T1 TW T2
CK
Address
CSn
RD
Read
Data
WRx
Write
Data
Figure 8.4 Wait Timing of Ordinary Space Access (Software Wait Only)
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When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when Tw state shifts to T2 state. When using external waits, use
a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise.
T1 TW TW TW0 T2
CK
Address
CSn
RD
Read
Data
WRx
Write
Data
WAIT
Figure 8.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2
State + WAIT Signal)
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8.3.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period
beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. Th and Tf
cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these
cycles; RD and WRx signals are not. Further, data is extended up to the Tf cycle, which is
effective for gate arrays and the like, which have slower write operations.
Th T1 T2 Tf
CK
Address
CSn
RD
Read
Data
WRx
Write
Data
Figure 8.6 CS Assert Period Extension Function
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8.4 Waits between Access Cycles

When a read from a slow device is completed, data buffers may not go off in time to prevent data
conflicts with the next access. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the CSn signal once.
8.4.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read
cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of
the BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles,
only the number of empty cycles remaining beyond the specified number of idle cycles are
inserted.
Figure 8.7 shows an example of idles between cycles. In this example, 1 idle between CSn space
cycles has been specified, so when a CSm space write immediately follows a CSn space read
cycle, 1 idle cycle is inserted.
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T1 T2 Tidle T1 T2
CK
Address
CSn
CSm
RD
WRx
Data
CSn space read Idle cycle CSm space write
Figure 8.7 Idle Cycle Insertion Example
IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read
other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20
specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1
space read, and IW01 and IW00, the number after a CS0 space read.
DIW specifies the number of idle cycles required, after a DRAM space read either to read other
external spaces (CS space), or for this LSI, to do write accesses.
0 to 3 cycles can be specified for CS space, and 0 to 1 cycle for DRAM space.
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8.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles
designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the
number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits.
When idle cycles already exist between access cycles, waits are not inserted. Figure 8.8 shows an
example. A continuous access idle is specified for CSn space, and CSn space is consecutively
write accessed.
T1 T2 Tidle T1 T2
CK
Address
CSn
RD
WRx
Data
CSn space access Idle cycle CSn space access
Figure 8.8 Same Space Consecutive Access Idle Cycle Insertion Example
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8.5 Bus Arbitration

The SH7050 series has a bus arbitration function that, when a bus release request is received from
an external device, releases the bus to that device. It also has two internal bus masters, the CPU
and the DMAC, DTC. The priority ranking for determining bus right transfer between these bus
masters is:
Bus right request from external device > DMAC > CPU
Therefore, an external device that generates a bus request is given priority even if the request is
made during a DMAC burst transfer.
A bus request by an external device should be input at the BREQ pin. The signal indicating that
the bus has been released is output from the BACK pin.
Figure 8.9 shows the bus right release procedure.
SH7050 series External device
BREQ = Low
BREQ accepted Bus right request
Strobe pin:
high-level output
Address, data, BACK confirmation

strobe pin:
high impedance
BACK = Low
Bus right release
response
Bus right release status Bus right acquisition
Figure 8.9 Bus Right Release Procedure
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8.6 Memory Connection Examples

Figures 8.10–8.13 show examples of the memory connections.
32k × 8 bit
SH705x ROM
CSn CE
RD OE
A0–A14 A0–A14
D0–D7 I/O0–I/O7
Figure 8.10 8-Bit Data Bus Width ROM Connection
256k × 16 bit
SH705x ROM
CSn CE
RD OE
A0
A1–A18 A0–A17
D0–D15 I/O0–I/O15
Figure 8.11 16-Bit Data Bus Width ROM Connection
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128k × 8 bit
SH705x SRAM
CSn CE
RD OE
A0–A16 A0–A16
WRL WE
D0–D7 I/O0–I/O7
Figure 8.12 8-Bit Data Bus Width SRAM Connection
128k × 8 bit
SH705x SRAM
CSn CS
RD OE
A0
A1ÐA17 A0ÐA16
WRH WE
D8–D15 I/O0–I/O7
WRL
D0–D7
CS
OE
A0–A16
WE
I/O0–I/O7
Figure 8.13 16-Bit Data Bus Width SRAM Connection
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Section 9 Direct Memory Access Controller (DMAC)
9.1 Overview
The SH7050 series includes an on-chip four-channel direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (transfer request acknowledge signal), external memories, memory-
mapped external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and
UBC). Using the DMAC reduces the burden on the CPU and increases operating efficiency of the
LSI as a whole.
9.1.1 Features
The DMAC has the following features:
• Four channels
• Four GB of address space in the architecture
• Byte, word, or longword selectable data transfer unit
• 16 MB (6,777,216 maximum) transfers
• Single or dual address mode. Dual address mode can be direct or indirect address transfer.
 Single address mode: Either the transfer source or transfer destination (peripheral device) is
accessed by a DACK signal while the other is accessed by address. One transfer unit of
data is transferred in each bus cycle.
 Dual address mode: Both the transfer source and transfer destination are accessed by
address. Dual address mode can be direct or indirect address transfer.
• Direct access: Values set in a DMAC internal register indicate the accessed address for
both the transfer source and transfer destination. Two bus cycles are required for one
data transfer.
• Indirect access: The value stored at the location pointed to by the address set in the
DMAC internal transfer source register is used as the address. Operation is otherwise
the same as direct access. This function can only be set for channel 3.
• Channel function: Transfer modes that can be set are different for each channel. (Dual address
mode indirect access can only be set for channel 1. Only direct access is possible for the other
channels).
 Channel 0: Single or dual address mode. External requests are accepted.
 Channel 1: Single or dual address mode. External requests are accepted.
 Channel 2: Dual address mode only. Source address reload function operates every fourth
transfer.
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 Channel 3: Dual address mode only. Direct address transfer mode and indirect address
transfer mode selectable.
• Reload function: Enables automatic reloading of the value set in the first source address
register every fourth DMA transfer. This function can be executed on channel 2 only.
• Transfer requests: There are three DMAC transfer activation requests, as indicated below.
 External request: From two DREQ pins. DREQ can be detected either by falling edge or by
low level. External requests can only be received on channels 0 or 1.
 Requests from on-chip peripheral modules: Transfer requests from on-chip modules such
as SCI or A/D. These can be received by all channels.
 Auto-request: The transfer request is generated automatically within the DMAC.
• Selectable bus modes: Cycle-steal mode or burst mode
• Two types of DMAC channel priority ranking:
 Fixed priority mode: Always fixed
 Round robin mode: Sets the lowest priority level for the channel that received the execution
request last
• CPU can be interrupted when the specified number of data transfers are complete.
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9.1.2 Block Diagram
Figure 9.1 is a block diagram of the DMAC.
DMAC module
Circuit
On-chip ROM SARn
control
Register DARn
On-chip RAM
control
On-chip Peripheral bus DMATCRn
Internal bus
peripheral
module Activation
control
CHCRn
DMAOR
DREQ0, DREQ1
ATU Request
SCI0–SCI2 priority
A/D converter 0, 1 control
DEIn
DACK0, DACK1
DRAK0, DRAK1
External
ROM Bus interface
External
RAM
External I/O SARn: DMAC source address register

(memory DARn: DMAC destination address register
mapped)
DMATCRn: DMAC transfer count register
Bus state CHCRn: DMAC channel control register
External I/O controller DMAOR: DMAC operation register
(with n: 0, 1, 2, 3
acknowledge)
Figure 9.1 DMAC Block Diagram
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Table 9.1 shows the DMAC pins.
Table 9.1 DMAC Pin Configuration
Channel Name Symbol I/O Function

0 DMA transfer request DREQ0 I DMA transfer request input from
external device to channel 0
DMA transfer request DACK0 O DMA transfer strobe output from
acknowledge channel 0 to external device
DREQ0 acceptance DRAK0 O Sampling receive acknowledge output
confirmation for DMA transfer request input from
external source
1 DMA transfer request DREQ1 I DMA transfer request input from
external device to channel 1
DMA transfer request DACK1 O DMA transfer strobe output from
acknowledge channel 1 to external device
DREQ1 acceptance DRAK1 O Sampling receive acknowledge output
confirmation for DMA transfer request input from
external source
Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has
four control registers. One other control register is shared by all channels. There are two channel 0
dedicated registers, ISAR and IDAR, which preserve different initial transfer source and
destination addresses than those of the SAR0 and DAR0. There is also an IAR used by the indirect
address mode.
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Table 9.2 DMAC Registers
Chan- Abbrevi- Initial Register Access

nel Name ation R/W Value Address Size Size
16, 32*
2
0 DMA source address SAR0 R/W Undefined H'FFFF86C0 32 bit
register 0
16, 32*
2
DMA destination DAR0 R/W Undefined H'FFFF86C4 32 bit
address register 0
32*
2
DMA transfer count DMATCR0 R/W Undefined H'FFFF86C8 32 bit
register 0
R/W* 16, 32*
1 2
DMA channel control CHCR0 H'00000000 H'FFFF86CC 32 bit
register 0
16, 32*
2
1 DMA source address SAR1 R/W Undefined H'FFFF86D0 32 bit
register 1
16, 32*
2
DMA destination DAR1 R/W Undefined H'FFFF86D4 32 bit
address register 1
32*
3
DMA transfer count DMATCR1 R/W Undefined H'FFFF86D8 32 bit
register 1
R/W* 16, 32*
1 2
DMA channel control CHCR1 H'00000000 H'FFFF86DC 32 bit
register 1
16, 32*
2
2 DMA source address SAR2 R/W Undefined H'FFFF86E0 32 bit
register 2
16, 32*
2
DMA destination DAR2 R/W Undefined H'FFFF86E4 32 bit
address register 2
32*
3
DMA transfer count DMATCR2 R/W Undefined H'FFFF86E8 32 bit
register 2
R/W* 16, 32*
1 2
DMA channel control CHCR2 H'00000000 H'FFFF86EC 32 bit
register 2
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Chan- Abbrevi- Initial Register Access

nel Name ation R/W Value Address Size Size
16, 32*
2
3 DMA source address SAR3 R/W Undefined H'FFFF86F0 32 bit
register 3
16, 32*
2
DMA destination DAR3 R/W Undefined H'FFFF86F4 32 bit
address register 3
32*
3
DMA transfer count DMATCR3 R/W Undefined H'FFFF86F8 32 bit
register 3
R/W* 16, 32*
1 2
DMA channel control CHCR3 H'00000000 H'FFFF86FC 32 bit
register 3
R/W* H'0000 8, 16*
1 4
Shared DMA operation DMAOR H'FFFF86B0 16 bit
register
Notes: Registers are accessed in three cycles when using word access and six cycles when using
longword access.
Do not attempt to access an empty address.
1. Write 0 after reading 1 in bit 1 of CHCR0–CHCR3 and in bits 1 and 2 of the DMAOR to
clear flags. No other writes are allowed.
2. For 16-bit access of SAR0–SAR3, DAR0–DAR3, and CHCR0–CHCR3, the 16-bit value
on the side not accessed is held.
3. DMATCR has a 24-bit configuration: bits 0–23. Writing to the upper 8 bits (bits 24–31)
is invalid, and these bits always read 0.
4. Do not make 32-bit access for DMAOR.
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. These registers have a count function, and during a DMA
transfer, they indicate the next source address. In single-address mode, SAR values are ignored
when a device with DACK has been specified as the transfer source.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The initial value after power-on resets and in software standby mode is undefined.
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Bit: 31 30 29 28 27 26 25 24
Initial value: — — — — — — — —
Bit: 23 22 21 … … 2 1 0
… …
Initial value: — — — … … — — —
R/W: R/W R/W R/W … … R/W R/W R/W
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next destination address. In single-address mode, DAR values are
ignored when a device with DACK has been specified as the transfer destination.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The value after power-on resets and in standby mode is undefined.
Bit: 31 30 29 28 27 26 25 24
Bit: 23 22 21 … … 2 1 0
… …
Initial value: — — — … … — — —
R/W: R/W R/W R/W … … R/W R/W R/W
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9.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that
specify the transfer count for the channel (byte count, word count, or longword count). Specifying
a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216
transfers.
The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0.
The value after power-on resets and in standby mode is undefined.
Always write 0 to the upper 8 bits of a DMATCR.
Bit: 31 30 29 28 27 26 25 24
— — — — — — — —
Bit: 23 22 21 20 19 18 17 16
Bit: 15 14 13 12 11 10 9 8
Bit: 7 6 5 4 3 2 1 0
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9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the
operation and transmission of each channel is designated. Bits 31–21 and bit 7 should always read
0. The written value should also be 0. They are initialized to 0 by a power-on reset and in standby
mode.
Bit: 31 30 29 28 27 26 25 24
— — — — — — — —
Bit: 23 22 21 20 19 18 17 16
— — — DI RO RL AM AL
R/W: R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Bit: 7 6 5 4 3 2 1 0
— DS TM TS1 TS0 IE TE DE
R/W: R R/W R/W R/W R/W R/W R/(W)* R/W
Notes: 1. TE bit: Allows only 0 write after reading 1.
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
Bit 20—Direct/Indirect (DI): Specifies either direct address mode operation or indirect address
mode operation for channel 3 source address. This bit is valid only in CHCR3. It always reads 0
for CHCR0–CHCR2, and cannot be modified.
Bit 20: DI Description

0 Direct access mode operation for channel 3 (initial value)
1 Indirect access mode operation for channel 3
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Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial value
during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for CHCR0,
CHCR1, and CHCR3, and cannot be modified.
Bit 19: RO Description

0 Does not reload source address (initial value)
1 Reloads source address
Bit 18—Request Check Level (RL): Selects whether to output DRAK notifying external device
of DREQ received, with active high or active low. This bit is valid only for CHCR0 and CHCR1.
It always reads 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 18: RL Description

0 Output DRAK with active high (initial value)
1 Output DRAK with active low
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether to output DACK in
the data write cycle or data read cycle. In single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid only for CHCR0 and CHCR1. It always reads
as 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 17: AM Description

0 Outputs DACK during read cycle (initial value)
1 Outputs DACK during write cycle
Bit 16—Acknowledge Level (AL): Specifies whether to set DACK (acknowledge) signal output
to active high or active low. This bit is valid only with CHCR0 and CHCR1. It always reads as 0
for CHCR2 and CHCR3, and cannot be modified.
Bit 16: AL Description

0 Active high output (initial value)
1 Active low output
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Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify
increment/decrement of the DMA transfer source address. These bit specifications are ignored
when transferring data from an external device to address space in single address mode.
Bit 15: DM1 Bit 14: DM0 Description

0 0 Destination address fixed (initial value)
0 1 Destination address incremented (+1 during 8-bit transfer, +2
during 16-bit transfer, +4 during 32-bit transfer)
1 0 Destination address decremented (–1 during 8-bit transfer, –2
during 16-bit transfer, –4 during 32-bit transfer)
1 1 Setting prohibited
Bits 13 and 12—Source Address Mode 1, 0 (SM1 and SM0): These bits specify
increment/decrement of the DMA transfer source address. These bit specifications are ignored
when transferring data from an external device to address space in single address mode.
Bit 13: SM1 Bit 12: SM0 Description

0 0 Source address fixed (initial value)
0 1 Source address incremented (+1 during 8-bit transfer, +2
during 16-bit transfer, +4 during 32-bit transfer)
1 0 Source address decremented (–1 during 8-bit transfer, –2
during 16-bit transfer, –4 during 32-bit transfer)
1 1 Setting prohibited
When the transfer source is specified at an indirect address, specify in source address register 3
(SAR3) the actual storage address of the data you want to transfer as the data storage address
(indirect address).
During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this
case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size
specified by TS1 and TS0.
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Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source.

RS3 RS2 RS1 RS0 Description
0 0 0 0 External request, dual address mode (initial value)
0 0 0 1 Prohibited
0 0 1 0 External request, single address mode. External address
space → external device.
0 0 1 1 External request, single address mode. External device →
external address space.
0 1 0 0 Auto-request
0 1 0 1 Prohibited
0 1 1 0 ATU, compare-match 6 (CMI6)
0 1 1 1 ATU, input capture 0B (ICI0B)
1 0 0 0 SCI0 transmission
1 0 0 1 SCI0 reception
1 1 1 0 On-chip A/D0
1 1 1 1 On-chip A/D1
Note: External request designations are valid only for channels 0 and 1. No transfer request
sources can be set for channels 2 or 3.
DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode
Bit 6—DREQ
to either low-level detection or falling-edge detection. This bit is valid only with CHCR0 and
CHCR1. For CHCR2 and CHCR3, this bit always reads as 0 and cannot be modified.
Even with channels 0 and 1, when specifying an on-chip peripheral module or autorequest as the
transfer request source, this bit setting is ignored. The sampling method is fixed at falling-edge
detection in cases other than auto-request.
Bit 6: DS Description
0 Low-level detection (initial value)
1 Falling-edge detection
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Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer.
Bit 5: TM Description
0 Cycle steal mode (initial value)
1 Burst mode
Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer.
Bit 4: TS1 Bit 3: TS0 Description

0 0 Specifies byte size (8 bits) (initial value)
0 1 Specifies word size (16 bits)
1 0 Specifies longword size (32 bits)
1 1 Prohibited
Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the
number of data transfers specified in the DMATCR (when TE = 1).
Bit 2: IE Description
0 Interrupt request not generated after DMATCR-specified transfer count
(initial value)
1 Interrupt request enabled on completion of DMATCR specified number
of transfers
Bit 1—Transfer End (TE): This bit is set to 1 after the number of data transfers specified by the
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing
of the DE bit or DME bit of the DMAOR) the TE is not set to 1. With this bit set to 1, data transfer
is disabled even if the DE bit is set to 1.
Bit 1: TE Description
0 DMATCR-specified transfer count not ended (initial value)
Clear condition: 0 write after TE = 1 read, Power-on reset, standby
mode
1 DMATCR specified number of transfers completed
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Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel.
Bit 0: DE Description
0 Operation of the corresponding channel disabled (initial value)
1 Operation of the corresponding channel enabled
Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings).
With an external request or on-chip module request, when a transfer request occurs after this bit is
set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended.
If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or
AE bit of the DMAOR is 1, transfer enable mode is not entered.
9.2.5 DMAC Operation Register (DMAOR)
The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC. Bits
15–10 and bits 7–3 of this register always read as 0 and cannot be modified.
Register values are initialized to 0 by a power-on reset and in software standby mode.
Bit: 15 14 13 12 11 10 9 8
— — — — — — PR1 PR0
R/W: R R R R R R R/W R/W
Bit: 7 6 5 4 3 2 1 0
— — — — — AE NMIF DME
R/W: R R R R R R/(W)* R/(W)* R
Note: * 0 write only is valid after 1 is read at the AE and NMIF bits.
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Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of
channels for execution when transfer requests are made for several channels simultaneously.
Bit 9: PR1 Bit 8: PR0 Description

0 0 CH0 > CH1 > CH2 > CH3 (initial value)
0 1 CH0 > CH2 > CH3 > CH1
1 0 CH2 > CH0 > CH1 > CH3
1 1 Round robin mode
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU
cannot write a 1 to the AE bit. Clearing is effected by 0 write after 1 read.
Bit 2: AE Description
0 No address error, DMA transfer enabled (initial value)
Clearing condition: Write AE = 0 after reading AE = 1
1 Address error, DMA transfer disabled
Setting condition: Address error due to DMAC
Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the
DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels
are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by 0 write after 1
read.
Bit 1: NMIF Description

0 No NMI interrupt, DMA transfer enabled (initial value)
Clearing condition: Write NMIF = 0 after reading NMIF = 1
1 NMI has occurred, DMC transfer prohibited
Set condition: NMI interrupt occurrence
Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are
suspended.
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Even when the DME bit is set, when the TE bit of the CHCR is 1, or its DE bit is 0, transfer is
disabled in the case of an NMI of the DMAOR or when AE = 1.
Bit 0: DME Description

0 Disable operation on all channels (initial value)
1 Enable operation on all channels
9.3 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. Transfer can be in either the single address mode or the dual address
mode, and dual address mode can be either direct or indirect address transfer mode. The bus mode
can be either burst or cycle steal.
9.3.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation
register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according
to the following procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,

AE = 0).
2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer
unit of data (determined by TS0 and TS1 setting). For an auto-request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus
mode.
3. When the specified number of transfers have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the
DMAOR are changed to 0.
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Figure 9.2 is a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and No

NMIF, AE, TE = 0?
Yes
Transfer request No *2
occurs?*1
Bus mode,
Yes *3 transfer request mode,
DREQ detection selection
Transfer (1 transfer unit); system
DMATCR – 1 → DMATCR, SAR and DAR
updated
Does
No No
DMATCR = 0? NMIF = 1, AE = 1,
DE = 0, or DME
= 0?
Yes Yes
DEI interrupt request (when IE = 1) Transfer aborted
Does
NMIF = 1, AE = 1, No
DE = 0, or DME
= 0?
Yes
Transfer ends Normal end
Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal
mode.
3. DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
Figure 9.2 DMAC Transfer Flowchart
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9.3.2 DMA Transfer Requests
DMA transfer requests are usually generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto-request, external request, and
on-chip peripheral module request. The request mode is selected in the RS3–RS0 bits of the DMA
channel control registers 0–3 (CHCR0–CHCR3).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR0–CHCR3 and the DME bit of the
DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0–CHCR3 and the
NMIF and AE bits of DMAOR are all 0).
External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an
external device. Choose one of the modes shown in table 9.3 according to the application system.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,
AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by
either the falling edge or low level of the signal input with the DS bit of CHCR0–CHCR3 (DS = 0
is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be
the data transfer source or destination.
Table 9.3 Selecting External Request Modes with the RS Bits
RS3 RS2 RS1 RS0 Address Mode Source Destination

0 0 0 0 Dual address Any* Any*
mode
0 0 1 0 Single address External memory or External device with
mode memory-mapped DACK
external device
0 0 1 1 Single address External device with External memory or
mode DACK memory-mapped
external device
Note: * External memory, memory-mapped external device, on-chip memory, on-chip
peripheral module (excluding DMAC, DTC, BSC, UBC).
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On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.4,
there are ten transfer request signals: five from the multifunction timer pulse unit (MTU), which
are compare match or input capture interrupts; the receive data full interrupts (RxI) and transmit
data empty interrupts (TxI) of the two serial communication interfaces (SCI); and the A/D
conversion end interrupt (ADI) of the A/D converter. When DMA transfers are enabled (DE = 1,
DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request
signal.
The transfer request source need not be the data transfer source or transfer destination. However,
when the transfer request is set by RxI (transfer request because SCI’s receive data is full), the
transfer source must be the SCI’s receive data register (RDR). When the transfer request is set by
TxI (transfer request because SCI’s transmit data is empty), the transfer destination must be the
SCI’s transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the
data transfer destination must be the A/D converter register.
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Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits
DMAC Transfer DMAC Transfer Transfer Transfer

RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode
0 1 1 0 ATU Compare-match Don’t care* Don’t care* Burst/cycle
6 generation steal
1 ATU Input capture B * *
Don’t care Don’t care Burst/cycle
generation steal
1 0 0 0 SCI0 transmit TXI0 (SCI0 Don’t care* TDR0 Burst/cycle
block transmit-data- steal
empty transfer
request)
1 SCI0 receive RXI0 (SCI0 RDR0 Don’t care* Burst/cycle
block receive-data-full steal
transfer request)
1 0 SCI1 transmit TXI1 (SCI1 Don’t care* TDR1 Burst/cycle
empty transfer
request)
transfer request)
1 0 0 SCI2 transmit TXI2 (SCI2 Don’t care* TDR2 Burst/cycle
empty transfer
request)
transfer request)
1 0 A/D converter ADI (A/D ADDR0 Don’t care* Burst/cycle
conversion end steal
interrupt)
1 A/D converter ADI (A/D ADDR1 Don’t care* Burst/cycle
conversion end steal
interrupt)
ATU: Advanced timer unit
SCI0, SCI1, SCI2: Serial communication interface channels 0–2
ADDR0, ADDR1: A/D converter channel 0 and 1 A/D registers
Note: * External memory, memory-mapped external device, on-chip memory, on-chip
peripheral module (excluding DMAC, BSC, and UBC)
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In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt
enable bit for each module, and output an interrupt signal.
When an on-chip peripheral module’s interrupt request signal is used as a DMA transfer request
signal, interrupts for the CPU are not generated.
When a DMA transfer is conducted corresponding with one of the transfer request signals in table
9.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in
burst mode with the last transfer.
9.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order, either in a fixed mode or in round robin
mode. These modes are selected by priority bits PR1 and PR0 in the DMA operation register
(DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed.
The following priority orders are available for fixed mode:
• CH0 > CH1 > CH2 > CH3

• CH0 > CH2 > CH3 > CH1
• CH2 > CH0 > CH1 > CH3
These are selected by settings of the PR1 and PR0 bits of the DMA operation register (DMAOR).
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word
or long word) ends on a given channel, that channel receives the lowest priority level (figure 9.3).
The priority level in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3.
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Transfer on channel 0
Initial priority setting CH0 > CH1 > CH2 > CH3 Channel 1 is given the lowest
priority.
Priority after transfer CH1 > CH2 > CH3 > CH0
Initial priority setting CH0 > CH1 > CH2 > CH3 When channel 1 is given the
lowest priority, the priority
of channel 0, which was
above channel 1, is also shifted
simultaneously.
Initial priority setting CH0 > CH1 > CH2 > CH3 When channel 2 receives the
lowest priority, the priorities
of channel 0 and 1, which
were above channel 2, are also
shifted simultaneously. Immedi-
Priority after transfer CH3 > CH0 > CH1 > CH2 ately thereafter, if there is a transfer
request for channel 1 only, channel
1 is given the lowest priority,
Priority after transfer and the priorities of channels 3
due to issue of a transfer CH2 > CH3 > CH0 > CH1 and 0 are simultaneously
request for channel 1 shifted down.
only.
Initial priority setting CH0 > CH1 > CH2 > CH3 No change in priority.
Figure 9.3 Round Robin Mode
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Figure 9.4 shows the example of changes in priority levels when transfer requests are issued
simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on
channel 0. The DMAC operates in the following manner under these circumstances:
1. Transfer requests are issued simultaneously for channels 0 and 3.

2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are
on transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer
comes first (channel 3 is on transfer standby).
6. When the channel 1 transfer ends, channel 1 shifts to the lowest priority level.
7. Channel 3 transfer begins.
8. When the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving
channel 3 the lowest priority.
Transfer request Channel waiting DMAC operation Channel priority
Issued for
channels 0 and 3 Channel 0 0>1>2>3
3 transfer begins
Issued for channel 1
Change of
priority
1.3 Channel 0 1>2>3>0
transfer ends
Channel 1
transfer begins
Change of
priority
3 Channel 1 2>3>0>1
transfer ends
Channel 3
transfer begins
None Change of
priority
Channel 3 0>1>2>3
transfer ends
Figure 9.4 Example of Changes in Priority in Round Robin Mode
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9.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode, in
which either the transfer source or destination is accessed using an acknowledge signal, or dual
address mode, in which both the transfer source and destination addresses are output. The dual
address mode consists of a direct address mode, in which the output address value is the object of
a direct data transfer, and an indirect address mode, in which the output address value is not the
object of the data transfer, but the value stored at the output address becomes the transfer object
address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus
modes: cycle-steal mode and burst mode.
Table 9.5 Supported DMA Transfers
Transfer Destination
Memory-
External Mapped On-Chip
Transfer Device with External External On-Chip Peripheral
Source DACK Memory Device Memory Module
External Not available Single address Single address Not available Not available
device with mode mode
DACK
External Single address Dual address Dual address Dual address Dual address
memory mode mode mode mode mode
Memory- Single address Dual address Dual address Dual address Dual address
mapped mode mode mode mode mode
external
device
On-chip Not available Dual address Dual address Dual address Dual address
memory mode mode mode mode
On-chip Not available Dual address Dual address Dual address Dual address
peripheral mode mode mode mode
module
Note: The dual address mode includes direct address mode and indirect address mode.
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9.3.5 Address Modes
Single Address Mode: In the single address mode, both the transfer source and destination are
external; one (selectable) is accessed by a DACK signal while the other is accessed by an address.
In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 9.5 shows a transfer between an external memory
and an external device with DACK in which the external device outputs data to the data bus while
that data is written in external memory in the same bus cycle.
External address bus External data bus

SuperH microcomputer
External
DMAC memory
External device
with DACK
DACK
DREQ
: Data flow
Figure 9.5 Data Flow in Single Address Mode
Two types of transfers are possible in the single address mode: (a) transfers between external
devices with DACK and memory-mapped external devices, and (b) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 9.6 shows the DMA transfer timing for the single address mode.
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CK
A21–A0 Address output to external memory space
CSn
Data that is output from the external
D15–D0
device with DACK
DACK DACK signal to external devices with
DACK (active low)
WRH
WR signal to external memory space
WRL
a. External device with DACK to external memory space
CK
A21–A0 Address output to external memory space
CSn
D15–D0 Data that is output from external memory space
RD RD signal to external memory space
DACK DACK signal to external device with DACK

(active low)
b. External memory space to external device with DACK
Figure 9.6 Example of DMA Transfer Timing in the Single Address Mode
9.3.6 Dual Address Mode
Dual address mode is used for access of both the transfer source and destination by address.
Transfer source and destination can be accessed either internally or externally. Dual address mode
is subdivided into two other modes: direct address transfer mode and indirect address transfer
mode.
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Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 9.7, data is read from one of the memories by the DMAC during
a read cycle, then written to the other external memory during the subsequent write cycle. Figure
9.8 shows the timing for this operation.
1st bus cycle
DMAC
SAR Memory
Address bus
Data bus
DAR
Transfer source
module
Transfer destination
Data buffer
module
1st bus cycle
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
2nd bus cycle
DMAC
SAR Memory
Address bus
Data bus
DAR
Transfer source
module
Data buffer
module
2nd bus cycle

The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Figure 9.7 Direct Address Operation during Dual Address Mode
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CK
Transfer source Transfer destination

A21–A0
address address
CSn
D15–D0
RD
WRH, WRL
DACK
Data read cycle Data write cycle
(1st cycle) (2nd cycle)
Note: Transfer between external memories with DACK are output during read
cycle.
Figure 9.8 Direct Address Transfer Timing in Dual Address Mode
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Indirect Address Transfer Mode: In this mode the memory address storing the data you actually
want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore,
in indirect address transfer mode, the DMAC internal transfer source address register value is read
first. This value is stored once in the DMAC. Next, the read value is output as the address, and the
value stored at that address is again stored in the DMAC. Finally, the subsequent read value is
written to the address specified by the transfer destination address register, ending one cycle of
DMAC transfer.
In indirect address mode (figure 9.9), transfer destination, transfer source, and indirect address
storage destination are all 16-bit external memory locations, and transfer in this example is
conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 9.10.
In indirect address mode, one NOP cycle (figure 9.10) is required until the data read as the indirect
address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles
each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole
operation.
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2nd bus cycle DMAC
SAR3 Memory
Address bus
DAR3
Data bus
Transfer source
Temporary module
buffer
Data
module
buffer
The SAR value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.
3rd bus cycle DMAC
SAR3 Memory
DAR3 Address bus Transfer source
Data bus
Temporary module
buffer
Data Transfer destination
buffer module
The value in the temporary buffer is taken as the address, and data is read from the
transfer source module to the data buffer.
4th bus cycle DMAC
SAR3 Memory
Address bus
DAR3
Transfer source
Data bus
Temporary module
buffer
Data
module
buffer
The DAR3 value is taken as the address, and the value in the data buffer is written to the
transfer destination module.
Note: Memory, transfer source, and transfer destination modules are shown here.
In practice, connection can be made anywhere there is address space.
Figure 9.9 Dual Address Mode and Indirect Address Operation
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External memory space → External memory space

(External memory space has 16-bit width)
CK
Transfer Transfer Transfer

A21–A0 source source Indirect destination
NOP
address (H) address (L) address address
CSn
Indirect Indirect Transfer Transfer

D15–D0 address (H) address (L) data data
Internal
address Transfer source Indirect
address ∗1
NOP
bus address
Internal
Transfer source address ∗2
Transfer Transfer
data bus data data
DMAC
indirect Indirect
address address
buffer
DMAC Transfer
data data
buffer
RD
WRH,
WRL
Address read cycle NOP Data Data

cycle read cycle write cycle
(1st) (2nd) (3rd) (4th)
Notes: 1. The internal address bus is controlled by the port and does not change.
2. DMAC does not fetch value until 32-bit data is read from the internal data
bus.
Figure 9.10 Dual Address Mode and Indirect Address Transfer Timing Example 1
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Figure 9.11 shows an example of timing in indirect address mode when transfer source and
indirect address storage locations are in internal memory, the transfer destination is an on-chip
peripheral module with 2-cycle access space, and transfer data is 8-bit.
Since the indirect address storage destination and the transfer source are in internal memory, these
can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write
cycles are required. One NOP cycle is required until the data read as the indirect address is output
to the address bus.
Internal memory space → Internal memory space
CK
Internal Transfer Transfer
address Indirect
source NOP destination
bus address
address address
Internal
Indirect Transfer
data NOP Transfer data
address data
bus
DMAC
indirect Indirect
address address
buffer
DMAC
data Transfer data
buffer
Address NOP Data

Data write cycle (4th)
read cycle cycle read cycle
(1st) (2nd) (3rd)
Figure 9.11 Dual Address Mode and Indirect Address Transfer Timing Example 2
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9.3.7 Bus Modes
Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes:
cycle steal and burst.
Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each
one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request
occurs, the bus rights are obtained from the other bus master and a transfer is performed for one
transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is
repeated until the transfer end conditions are satisfied.
The cycle steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.12 shows an example of DMA transfer timing in the cycle steal mode.
Transfer conditions are dual address mode and DREQ level detection.
DREQ
Bus control returned to CPU
Bus cycle CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
Read Write Read Write
Figure 9.12 DMA Transfer Timing Example in the Cycle-Steal Mode
Burst Mode: Once the bus right is obtained, the transfer is performed continuously until the
transfer end condition is satisfied. In the external request mode with low level detection of the
DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master
after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the
transfer end conditions have not been satisfied.
Figure 9.13 shows an example of DMA transfer timing in the burst mode. Transfer conditions are
single address mode and DREQ level detection.
DREQ
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 9.13 DMA Transfer Timing Example in the Burst Mode
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9.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 9.6 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 9.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Bus*
6
Address Request Transfer Usable
Mode Transfer Category Mode Mode Size (Bits) Channels
Single External device with DACK and External B/C 8/16/32 0,1
external memory
External device with DACK and External B/C 8/16/32 0, 1
memory-mapped external device
Any* 0–3*
1 5
Dual External memory and external memory B/C 8/16/32
Any* 0–3*
1 5
External memory and memory-mapped B/C 8/16/32
external device
Any* 0–3*
1 5
Memory-mapped external device and B/C 8/16/32
memory-mapped external device
Any* 0–3*
1 5
External memory and on-chip memory B/C 8/16/32
Any* B/C* 8/16/32* 0–3*
2 3 4 5
External memory and on-chip
peripheral module
Any* 0–3*
1 5
Memory-mapped external device and B/C 8/16/32
on-chip memory
Any* B/C* 8/16/32* 0–3*
2 3 4 5
Memory-mapped external device and
on-chip peripheral module
Any* 0–3*
1 5
On-chip memory and on-chip memory B/C 8/16/32
Any* B/C* 8/16/32* 0–3*
2 3 4 5
On-chip memory and on-chip
peripheral module
Any* B/C* 8/16/32* 0–3*
2 3 4 5
On-chip peripheral module and on-
chip peripheral module
Notes: 1. External request, auto-request or on-chip peripheral module request enabled. However,
in the case of on-chip peripheral module request, it is not possible to specify the SCI or
A/D converter for the transfer request source.
2. External request, auto-request or on-chip peripheral module request possible. However,
if transfer request source is also the SCI or A/D converter, the transfer source or
transfer destination must be the SCI or A/D converter.
3. When the transfer request source is the SCI, only cycle steal mode is possible.
4. Access size permitted by register of on-chip peripheral module that is the transfer
source or transfer destination.
5. When the transfer request is an external request, channels 0 and 1 only can be used.
6. B: Burst, C: Cycle steal
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9.3.9 Bus Mode and Channel Priority Order
When a given channel is transferring in burst mode, and a transfer request is issued to channel 0,
which has a higher priority ranking, transfer on channel 0 begins immediately. If the priority level
setting is fixed mode (CH0 > CH1), channel 1 transfer is continued after transfer on channel 0 are
completely ended, whether the channel 0 setting is cycle steal mode or burst mode.
When the priority level setting is for round robin mode, transfer on channel 1 begins after transfer
of one transfer unit on channel 0, whether channel 0 is set to cycle steal mode or burst mode.
Thereafter, bus right alternates in the order: channel 1 > channel 0 > channel 1 > channel 0.
Whether the priority level setting is for fixed mode or round robin mode, since channel 1 is set to
burst mode, the bus right is not given to the CPU. An example of round robin mode is shown in
figure 9.14.
DMAC DMAC DMAC DMAC DMAC DMAC DMAC

CPU CPU
ch1 ch1 ch0 ch1 ch0 ch1 ch1
ch0 ch1 ch0
DMAC ch1 DMAC ch0 and ch1 DMAC ch1

CPU burst mode round-robin mode burst mode CPU
Priority: Round-robin mode

ch0: Cycle-steal mode
ch1: Burst mode
Figure 9.14 Bus Handling when Multiple Channels Are Operating
9.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. The bus cycle in the dual address mode is controlled by wait state control register 1
(WCR1) while the single address mode bus cycle is controlled by wait state control register 2
(WCR2). For details, see section 8.3.2, Wait State Control.
DREQ Pin Sampling Timing and DRAK Signal: In external request mode, the DREQ pin is
sampled by either falling edge or low-level detection. When a DREQ input is detected, a DMAC
bus cycle is issued and DMA transfer effected, at the earliest, after three states. However, in burst
mode when single address operation is specified, a dummy cycle is inserted for the first bus cycle.
In this case, the actual data transfer starts from the second bus cycle. Data is transferred
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continuously from the second bus cycle. The dummy cycle is not counted in the number of
transfer cycles, so there is no need to recognize the dummy cycle when setting the TCR.
DREQ sampling from the second time begins from the start of the transfer one bus cycle prior to
the DMAC transfer generated by the previous sampling.
DRAK is output once for the first DREQ sampling, irrespective of transfer mode or DREQ
detection method. In burst mode, using edge detection, DREQ is sampled for the first cycle only,
so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be
ascertained, and this facilitates handshake operations of transfer requests with the DMAC.
Cycle Steal Mode Operations: In cycle steal mode, DREQ sampling timing is the same
irrespective of dual or single address mode, or whether edge or low-level DREQ detection is used.
For example, DMAC transfer begins (figure 9.15), at the earliest, three cycles from the first
sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the
start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3)
transfer). At this point, if DREQ detection has not occurred, sampling is executed every cycle
thereafter.
As in figure 9.16, whatever cycle the CPU transfer cycle is, the next sampling begins from the
start of the transfer one bus cycle before the DMAC transfer begins.
Figure 9.15 shows an example of output during DACK read and figure 9.16 an example of output
during DACK write.
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CPU(5) DMAC(R) DMAC(W)

2nd sampling
1st sampling
CPU(2)
CPU(1)
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.15 Cycle Steal, Dual Address and Level Detection (Fastest Operation)
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1st sampling 2nd sampling
CK
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DREQ
DRAK
Bus DMAC
CPU CPU CPU DMAC(R) DMAC(W) CPU (R)

cycle
DACK
Note: With cycle-steal and dual address operation, sampling timing is the same
whether DREQ detection is by level or by edge.
Figure 9.16 Cycle Steal, Dual Address and Level Detection (Normal Operation)
Figures 9.17 and 9.18 show cycle steal mode and single address mode. In this case, transfer begins
at earliest three cycles after the first DREQ sampling. The second sampling begins from the start
of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode,
the DACK signal is output during the DMAC transfer period.
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DMAC
CPU
DMAC
CPU
DMAC
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.17 Cycle Steal, Single Address and Level Detection (Fastest Operation)
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CPU
DMAC
CPU
DMAC
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.18 Cycle Steal, Single Address and Level Detection (Normal Operation)
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Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with
dual address and level detection is virtually the same as that of cycle steal mode.
For example, DMAC transfer begins (figure 9.19), at the earliest, three cycles after the timing of
the first sampling. The second sampling also begins from the start of the transfer one bus cycle
before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued,
DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC
transfer” may be a DMAC transfer.
In burst mode, the DACK output period is thesame as that of cycle steal mode. Figure 9.20 shows
the normal operation of this burst mode.
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DMAC(R)
CPU
DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W)
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.19 Burst Mode, Dual Address and Level Detection (Fastest Operation)
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DMAC(R)
DMAC(R) DMAC(W)
DMAC(W)
DMAC(R)
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.20 Burst Mode, Dual Address and Level Detection (Normal Operation)
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Burst Mode, Single Address, and Level Detection: DREQ sampling timing in burst mode with
single address and level detection is shown in figures 9.21 and 9.22.
In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle,
at the earliest, three cycles after timing of the first sampling. Data during this period is undefined,
and the DACK signal is not output. Nor is the number of DMAC transfers counted. The actual
DMAC transfer begins after one dummy bus cycle output.
The dummy cycle is not counted either at the start of the second sampling (transfer one bus cycle
before the start of the first DMAC transfer). Therefore, the second sampling is not conducted from
the bus cycle starting the dummy cycle, but from the start of the CPU(3) bus cycle.
Thereafter, as long the DREQ is continuously sampled, no dummy cycle is inserted. DREQ
sampling timing during this period begins from the start of the transfer one bus cycle before the
start of DMAC transfer, in the same way as with cycle steal mode.
As with the four samplings in figure 9.21, once DMAC transfer is interrupted, a dummy cycle is
again inserted at the start as soon as DMAC transfer is resumed.
The DACK output period in burst mode is the same as in cycle steal mode.
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CPU(4) Dummy
DMAC
4th sampling
DMAC
3rd sampling
DMAC
2nd sampling
CPU(2) CPU(3) Dummy

1st sampling
CPU(1)
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.21 Burst Mode, Single Address and Level Detection (Fastest Operation)
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DMAC
DMAC
DMAC
Dummy
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.22 Burst Mode, Single Address and Level Detection (Normal Operation)
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Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge
detection, DREQ sampling is conducted only on the first cycle.
In figure 9.23, DMAC transfer begins, at the earliest, three cycles after the timing of the first
sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the
TCR. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first
cycle only.
When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput
an edge request. The remaining transfer restarts after the first DRAK output.
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DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W)

CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.23 Burst Mode, Dual Address and Edge Detection
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Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge
detection, DREQ sampling is conducted only on the first cycle. In figure 9.24, a dummy cycle is
inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data
is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. Thereafter,
DMAC transfer continues until the data transfer count set in the TCR has ended. DREQ sampling
is not conducted during this period. Therefore, DRAK is output on the first cycle only.
When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput
an edge request. DRAK is output once, and the remaining transfer restarts after output of one
dummy cycle.
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DMAC
DMAC
DMAC
DMAC
Dummy
CPU
CPU
CPU
CK
DREQ
DRAK
cycle
DACK
Bus
Figure 9.24 Burst Mode, Single Address and Edge Detection
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9.3.11 Source Address Reload Function
Channel 2 has a source address reload function. This returns to the first value set in the source
address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 9.25
illustrates this operation. Figure 9.26 is a timing chart for reload ON mode, with burst mode,
autorequest, 16-bit transfer data size, SAR2 increment, and DAR2 fixed mode.
DMAC
DMAC control block

RO bit = 1
CHCR2
Transfer Count signal

DMATCR2
request
Address bus
Reload signal SAR2
Reload control
(initial value)
Reload
signal
SAR2
4th count
Figure 9.25 Source Address Reload Function
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CK
Internal
SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 DAR2
address bus
Internal
SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data SAR2 data
data bus
1st channel 2 2nd channel 2 3rd channel 2 4th channel 2 5th channel 2
transfer transfer transfer transfer transfer
SAR2 output SAR2+2 output SAR2+4 output SAR2+6 output SAR2 output
DAR2 output DAR2 output DAR2 output DAR2 output DAR2 output
After SAR2+6 output, SAR2 is reloaded Bus right is returned one time in four
Figure 9.26 Source Address Reload Function Timing Chart
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every
single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore,
when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2.
Operation will not be guaranteed if any other value is set. Also, the counter which counts the
occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR
or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and
setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in
software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset.
Consequently, when one of these sources occurs, there is a mixture of initialized counters and
uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in
this state. Therefore, when one of the above sources, other than TE setting, occurs during use of
the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before re-
execution.
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9.3.12 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and for all channels
ending together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (TCR) is 0, or when the DE bit of the
channel’s CHCR is cleared to 0.
• When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt
enable) bit has been set, a DMAC interrupt (DEI) is requested of the CPU.
• When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or when the DME
bit in the DMAOR is cleared to 0.
• When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address
error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their
transfers. The DMAC obtains the bus rights, and if these flags are set to 1 during execution of
a transfer, DMAC halts operation when the transfer processing currently being executed ends,
and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bits
are set to 1 during a transfer, the DMA source address register (SAR), designation address
register (DAR), and transfer count register (TCR) are all updated. The TE bit is not set. To
resume the transfers after NMI interrupt or address error processing, clear the appropriate flag
bit to 0. To avoid restarting a transfer on a particular channel, clear its DE bit to 0.
When the processing of a one unit transfer is complete. In a dual address mode direct address
transfer, even if an address error occurs or the NMI flag is set during read processing, the
transfer will not be halted until after completion of the following write processing. In such a
case, SAR, DAR, and TCR values are updated. In the same manner, the transfer is not halted in
dual address mode indirect address transfers until after the final write processing has ended.
• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR aborts the
transfers on all channels. The TE bit is not set.
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9.3.13 DMAC Access from CPU
The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus
master and accesses the DMAC, a minimum of three basic clock (CLK) cycles are required for
one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the
DMAC is completed in one bus cycle, a longword-size access is automatically divided into two
word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are
executed consecutively; a different bus cycle is never inserted between the two word accesses.
This applies to both write accesses and read accesses.
9.4 Examples of Use
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, on-chip serial communication interface channel 0 (SCI0) received data is
transferred to external memory using the DMAC channel 3.
Table 9.7 indicates the transfer conditions and the setting values of each of the registers.
Table 9.7 Transfer Conditions and Register Set Values for Transfer between On-chip SCI
and External Memory
Transfer Conditions Register Value

Transfer source: RDR0 of on-chip SCI0 SAR0 H'FFFF81A5
Transfer destination: external memory DAR0 H'00400000
Transfer count: 64 times DMATCR0 H'00000040
Transfer source address: fixed CHCR0 H'00004905
Transfer destination address: incremented
Transfer request source: SCI0 (RDR0)
Bus mode: cycle steal
Transfer unit: byte
Interrupt request generation at end of transfer
Channel priority ranking: 0 > 1 > 2 > 3 DMAOR H'0001
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9.4.2 Example of DMA Transfer between External RAM and External Device with
DACK
In this example, an external request, serial address mode transfer with external memory as the
transfer source and an external device with DACK as the transfer destination is executed using
DMAC channel 1.
Table 9.8 Transfer Conditions and Register Set Values for Transfer between External
RAM and External Device with DACK

Transfer source: external RAM SAR1 H'00400000
Transfer destination: external device with DACK DAR1 (access by DACK)
Transfer count: 32 times DMATCR1 H'00000020
Transfer source address: decremented CHCR1 H'00002269
Transfer destination address: (setting ineffective)
Transfer request source: external pin (DREQ1) edge
detection
Bus mode: burst
Transfer unit: word
No interrupt request generation at end of transfer
9.4.3 Example of DMA Transfer between A/D Converter and Internal Memory (Address
Reload On)
In this example, the on-chip A/D converter channel 0 is the transfer source and internal memory is
the transfer destination, and the address reload function is on.
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Table 9.9 Transfer Conditions and Register Set Values for Transfer between A/D
Converter and Internal Memory

Transfer source: on-chip A/D converter ch1 (AD1) SAR2 H'FFFF85F0
Transfer destination: internal memory DAR2 H'FFFFE800
Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080
Transfer source address: incremented CHCR2 H'00085F21
Transfer destination address: incremented
Transfer request source: A/D converter (AD1)
Bus mode: burst
Transfer unit: byte
Interrupt request generation at end of transfer
When address reload is on, the SAR value returns to its initially established value every four
transfers. In the above example, when a transfer request is input from the A/D converter, the byte
size data is first read in from the H'FFFF85F0 register of AD1 and that data is written to the
internal address H'FFFFE800. Because a byte size transfer was performed, the SAR and DAR
values at this point are H'FFFF85F1 and H'FFFFE801, respectively. Also, because this is a burst
transfer, the bus rights remain secured, so continuous data transfer is possible.
When four transfers are completed, if the address reload is off, execution continues with the fifth
and sixth transfers and the SAR value continues to increment from H'FFFF85F3 to H'FFFF85F4 to
H'FFFF85F5 and so on. However, when the address reload is on, the DMAC transfer is halted
upon completion of the fourth one and the bus right request signal to the CPU is cleared. At this
time, the value stored in SAR is not H'FFFF85F3 to H'FFFF85F4, but H'FFFF85F3 to
H'FFFF85F0, a return to the initially established address. The DAR value always continues to be
decremented regardless of whether the address reload is on or off.
The DMAC internal status, due to the above operation after completion of the fourth transfer, is
indicated in Table 9.10 for both address reload on and off.
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Table 9.10 DMAC Internal Status
Item Address Reload On Address Reload Off

SAR H'FFFF83F0 H'FFFF83F4
DAR H'00400004 H'00400004
DMATCR H'0000007C H'0000007C
Bus rights Released Maintained
DMAC operation Halted Processing continues
Interrupts Not issued Not issued
Transfer request source flag clear Executed Not executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
they are executed regardless of whether the address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where
abnormal operation will result if it is executed in cycle steal mode.
4. Designate a multiple of four for the TCR value when using the address reload function.
There are cases where abnormal operation will result if anything else is designated.
To execute transfers after the fifth one when the address reload is on, make the transfer request
source issue another transfer request signal.
9.4.4 Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On)
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 sending side is the transfer destination.
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Table 9.11 Transfer Conditions and Register Set Values for Transfer between External
Memory and SCI1 Sending Side

Transfer source: external memory SAR3 H'00400000
Value stored in address H'00400000 — H'00450000
Value stored in address H'00450000 — H'55
Transfer destination: on-chip SCI TDR1 DAR3 H'FFFF81B3
Transfer count: 10 times DMATCR3 H'0000000A
Transfer source address: incremented CHCR3 H'00011801
Transfer destination address: fixed
Transfer request source: SCI1 (TDR1)
Bus mode: cycle steal
Transfer unit: byte
Interrupt request not generated at end of transfer
When indirect address mode is on, the data stored in the address established in SAR is not used as
the transfer source data. In the case of indirect addressing, the value stored in the SAR address is
read, then that value is used as the address and the data read from that address is used as the
transfer source data, then that data is stored in the address designated by the DAR.
In the table 9.11 example, when a transfer request from the TDR1 of SCI1 is generated, a read of
the address located at H'00400000, which is the value set in SAR3, is performed first. The data
H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000
value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is
stored in the H'00450000 address. It then writes the value H'55 to the address H'FFFF81B3
designated by DAR3 to complete one indirect address transfer.
With indirect addressing, the first executed data read from the address established in SAR3 always
results in a longword size transfer regardless of the TS0, TS1 bit designations for transfer data
size. However, the transfer source address fixed and increment or decrement designations are as
according to the SM0, SM1 bits. Consequently, despite the fact that the transfer data size
designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The
write operation is exactly the same as an ordinary dual address transfer write operation.
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9.5 Cautions on Use

1. Access is possible regardless of the DMA channel control register (CHCR0 to CHCR3) data
size. Other than the DMA operation register (DMAOR) accessing in byte (8 bit) or word (16
bit) units, access all registers in word (16 bit) or longword (32 bit) units.
2. When rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (set the DE
bit to 0 before doing rewrites with a CHCR byte address).
3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is
not operating.
4. Set the DME bit of the DMAOR to 0 and make certain that any DMAC received transfer
request processing has been completed before entering standby mode.
5. Do not access the DMAC, DTC, BSC, or UBC on-chip peripheral modules from the DMAC.
6. When activating the DMAC, do the CHCR or DMAOR setting as the final step. There are
instances where abnormal operation will result if any other registers are established last.
7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write a 0 to
the TCR, even when executing the maximum number of transfers on the same channel. There
are instances where abnormal operation will result if this is not done.
8. Designate burst mode as the transfer mode when using the address reload function. There are
instances where abnormal operation will result in cycle steal mode.
9. Designate a multiple of four for the TCR value when using the address reload function. There
are instances where abnormal operation will result if anything else is designated.
10. When detecting external requests by falling edge, maintain the external request pin at high
level when performing the DMAC establishment.
11. When operating in single address mode, establish an external address as the address. There are
instances where abnormal operation will result if an internal address is established.
12. Do not access DMAC register empty addresses (H'FFFF86B2 to H'FFFF86BF). Operation
cannot be guaranteed when empty addresses are accessed.
13. If DMAC transfer is aborted by NMI or AE setting, or DME or DE2 clearing, during DMAC
execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made
before reexecuting the transfer. The DMAC will not operate correctly if this is not done.
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Section 10 Advanced Timer Unit (ATU)
10.1 Overview
The SH7050 series has an on-chip advanced timer unit (ATU) with one 32-bit timer channel and
nine 16-bit timer channels.
10.1.1 Features
ATU features are summarized below.

• Capability to process up to 34 pulse inputs and outputs
• Prescaler
 Input clock to channel 0 scaled in 1 stage, input clock to channels 1 to 9 scaled in 2 stages
 1/1 to 1/32 clock scaling possible in initial stage for all channels
 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 10
 External clock TCLKA, TCLKB selection also possible for channels 1 to 5
• Channel 0 has four 32-bit input capture lines, allowing the following operations:
 Rising-edge, falling-edge, or both-edge detection selectable
 Channel 1 compare-match can be used as capture signal (TRG1A) (ICR0A, ICR0D only)
 Interrupt can be generated by trigger input
 Interval interrupt generation function generates four interval interrupts as selected
• Channels 1 and 2 have a total of eight 16-bit input capture/output compare registers and one
dedicated input capture register. The 16-bit output compare registers can also be selected for
channel 10 one-shot pulse offset.
 Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle
output
 Input capture function: Rising-edge, falling-edge, or both-edge detection
OSBR trigger source is channel 0 capture set to 1 (TRG0A)
 Eight counter overflow interrupts/compare-match interrupts/capture interrupts can be
generated (channel 1/A–F, channel 2/A, B)
 Compare-match signal (TRG1A) can be sent from channel 1 to channel 0 as a trigger
 Compare-match signal can be sent from channel 2 to the advanced pulse controller (APC)
• Channels 3 to 5 have a total of ten 16-bit input capture/output compare/PWM registers (ten
inputs/outputs when using input capture/output compare, seven outputs when using PWM),
allowing the following operations:
 Selection of input capture, output compare, PWM mode
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 Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle

output
 Input capture function: Rising-edge, falling-edge, or both-edge detection
 Ten compare-match interrupts/capture interrupts (channel 3/A–D, channel 4/A–D, channel
5/A, B) and three counter overflow interrupts can be generated
• Channels 6 to 9 have four PWM outputs, allowing the following operations:
 Any cycle and duty from 0 to 100% can be set
 Duty buffer register, with transfer to duty register every cycle
 Interrupts can be generated every cycle
• Channel 10 has eight 16-bit down-counters for one-shot pulse output, allowing the following
operations:
 One-shot pulse generation by down-counter
 Down-counter can be rewritten during count
 Interrupt can be generated at end of down-count
 Offset one-shot pulse function available
• High-speed access to internal 16-bit bus
 High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and
capture registers
• 44 interrupt sources
 Four input capture and one overflow interrupt request for channel 0
 Four interval interrupt requests
 Eight dual input capture/compare-match interrupt requests and two counter overflow
interrupt requests for channels 1 and 2
 Ten dual input capture/compare-match interrupt requests and three overflow interrupt
requests for channels 3 to 5
 Four cycle interrupts for channels 6 to 9
 Eight underflow interrupts for channel 10
• Direct memory access controller (DMAC) activation
 The DMAC can be activated by a channel 0 input capture interrupt (ICI0B)
 The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt
(CMI6)
• A/D converter activation
 The A/D converter can be activated by detection of 1 in bits 10 to 13 of the channel 0 free-
running counter (TCNT0)
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Table 10.1 lists the functions of the ATU.
Table 10.1 ATU Functions

Channel Channel Channel Channels Channels Channel
Item 0 1 2 3–5 6–9 10
Counter Clock φ–φ/32 (φ–φ/32) × (φ–φ/32) × (φ–φ/32) × (φ–φ/32) × (φ–φ/32) ×
configura- sources (1/2n) (1/2n) (1/2n) (1/2n) (1/2n)
tion (n = 0–5) (n = 0–5) (n = 0–5) (n = 0–5) (n = 0–5)
TCLKA, TCLKA, TCLKA,
TCLKB TCLKB TCLKB
Counters TCNT0H, TCNT1 TCNT2 TCNT3, TCNT6, DCNT10A,
TCNT0L TCNT4, TCNT7, DCNT10B,
TCNT5 TCNT8, DCNT10C,
TCNT9 DCNT10D,
DCNT10E,
DCNT10F,
DCNT10G,
DCNT10H
Register General — GR1A, GR2A, GR3A–3D, — —
configu- registers GR1B, GR2B GR4A–4D,
ration GR1C, GR5A,
GR1D, GR5B
GR1E,
GR1F
Dedicated ICR0AH, OSBR — — — —
input ICR0AL,
capture ICR0BH,
ICR0BL,
ICR0CH,
ICR0CL,
ICR0DH,
ICR0DL
PWM — — — — CYLR6–9, —
output DTR6–9,
BFR6–9
Input pins TIA0, — — — — —
TIB0,
TIC0,
TID0
I/O pins — TIOA1, TIOA2, TIOA3– — —
TIOB1, TIOB2 TIOD3,
TIOAC, TIOA4–
TIOD1, TIOD4,
TIOE1, TIOA5,
TIOF1 TIOB5
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Item 0 1 2 3–5 6–9 10
Output pins — — — — TO6–TO9 TOA10,
TOB10,
TOC10,
TOD10,
TOE10,
TOF10,
TOG10,
TOH10
Counter clearing — — — O O —
function
Interrupt sources 9 sources 7 sources 3 sources 13 sources 1 source 8 sources
• Input • Dual input • Dual input • Dual input each (total • Underflow
4 sources)
capture 0A capture/ capture/ capture/ OSF10A
• Input compare- compare- compare- • Cycle OSF10B
match 1A match 2A match compare- OSF10C
capture 0B
• Dual input • Dual input 3A–5A match OSF10D
• Input (CMI6– OSF10E
capture/ capture/ • Dual input
capture 0C CMI9) OSF10F
compare- compare- capture/
• Input match 1B match 2B compare- OSF10G
capture 0D match OSF10H
• Dual input • Overflow 2
• Overflow 0 capture/ 3B–5B
• Interval 0* compare- • Dual input
* match 1C capture/
• Interval 1 compare-
• Dual input
• Interval 2* match
capture/
• Interval 3* compare- 3C–4C
match 1D • Dual input
(* Same
vector) • Dual input capture/
capture/ compare-
match
compare-
match 1E 3D–4D
• Overflow
• Dual input
capture/ 3–5
compare-
match 1F
• Overflow 1
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Item 0 1 2 3–5 6–9 10
Inter-channel and Trigger Trigger Trigger — Output of Trigger
inter-module output of output of output of activation output of
connection signals input compare- compare- compare- channel 1 &
capture match match match 2 compare-
signal to signal to signal to signal to match
channel 1 channel 10 channel 10 DMAC signals to
Trigger one-shot one-shot one-shot
output of pulse pulse pulse output
compare- output output down-
match down- down- counter
signal to counter counter
channel 1 Trigger Compare-
A/D output of match
converter compare- signal
activation match output to
signal signal to APC
output channel 0 (advanced
pulse
Output of controller)
activation
input
capture
signal to
DMAC
O: Available
—: Not available
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10.1.2 Block Diagrams
Overall block Diagram ATU Block Diagram: Figure 10.1 shows an overall block diagram of
the ATU.
Interrupts
TCLKA
I/O interrupt
Clock selection
TCLKB IC/OC control Inter-module
control connection
signals
External pins
Counter and register control,
and comparator
Inter-module
address bus
16-bit timer channel 10


Prescaler
TSTR
Bus interface
........
Inter-module
Module data bus data bus
Legend:
TSTR: Timer start register (16 bits)
Interrupts:
ITV0–ITV3, OV10–OV15, IC10A –IC10D, IMI1A–IMI1F, IMI2A, IMI2B, IMI3A–IMI3D,
IMI4A–IMI4D, IMI5A, IMI5B, CMI6–CMI9, OSI10A–OSI10H
External pins:
TIA0–TID0, TIOA1–TIOF1, TIOA2, TIOIB2, TIOA3–TIOD3, TIOA4–TIOD3, TIOA5, TIOB5,
TO6–TO9, TOA10–TOH10
Inter-module connection signals:
Signals to A/D converter, signals to direct memory access controller (DMAC),
signals to advanced pulse controller (APC)
Figure 10.1 Overall Block Diagram of ATU
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Block Diagram of Channel 0: Figure 10.2 shows a block diagram of ATU channel 0.
OVI0
ITV
TSTR Clock ICI0A
TGSR control IRQER control
selection ICI0B
ICI0C
ICI0D
TIA0
Control logic TIB0
φ/m
TIC0
1 ≤ m ≤ 32 TID0
TRG1A
TCNT0H
TCNT0L
ICR0CH
ICR0CH
ICR0DH
ICR0AH
ICR0BH
TIOR0A
ICR0DL
ICR0AL
ICR0BL
TSRAH
TSRAL
ITVRR
TIERA
TGSR
Module data bus
Legend:
TIOR0A: Timer I/O control register 0A (8 bits)
TGSR: Trigger selection register (8 bits)
TSRA: Timer status register A (8 bits)
TIERA: Timer interrupt enable register A (8 bits)
ITVRR: Interval interrupt request register (8 bits)
TCNT0: Free-running counter 0 (16 bits)
ICR0: Input capture register 0 (16 bits)
Interrupts:
OVI0: Overflow interrupt 0
ITV: Interval interrupt
ICI0: Input capture interrupt 0
Inter-channel connection signal:
TRG1A: Channel 1/GR1A compare-match signal
Figure 10.2 Block Diagram of Channel 0
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OVI1
IMIA
IMIB
IMIC
TSTR Clock selection Comparator IMID
IMIE
IMIF
TIOA1
TCLKA TIOB1
TCLKB TIOC1
TIOD1
TIOE1
φ/(m·2n) Control logic TIOF1
1 ≤ m ≤ 32 TRG0A
0≤n≤5 TRG1A
OFF1A–1F
TIOR1C
TIOR1A
TIOR1B
TCNT1
TIERB
OSBR
GR1C
GR1D
GR1A
GR1B
GR1E
TSRB
GR1F
TCR1
Module data bus
Legend:
TSTR: Timer start register (16 bits) TIERB: Timer interrupt enable register B (8 bits)
TCR1: Timer control register 1 (8 bits) TCNT1: Free-running counter 1 (16 bits)
TIOR1: Timer I/O control register 1 (8 bits) GR1: General register 1 (16 bits)
TSRB: Timer status register B (8 bits) OSBR: Offset base register (16 bits)
Interrupts:
IMI1: Input capture/compare-match interrupt 1
Inter-channel connection signals:
OFF1: Offset compare-match signal
TRG0A: Channel 0/ICR0A input signal
TRG1A: Channel 1/GR1A compare-match signal
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APCHIGH
APCLOW
TSTR
Clock selection Comparator OVI2
IMI2A
TCLKA IMI2B
TCLKB
TIOA2
TIOB2
φ/(m·2n) Control logic
1 ≤ m ≤ 32 OFF2A–2B
0≤n≤5
TIOR2A
TCNT2
TIERC
TSRC
GR2A
GR2B
TCR2
Module data bus
Legend:
TCR2: Timer control register 2 (8 bits)
TIOR2A: Timer I/O control register 2 (8 bits)
TSRC: Timer status register C (8 bits)
TIERC: Timer interrupt enable register C (8 bits)
GR2: General register 2 (16 bits)
Interrupts:
OFF2: Offset compare-match signal
Inter-module connection signals:
APCHIGH: GR2B compare-match signal
APCLOW: GR2A compare-match signal
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Block Diagram of Channels 3 and 4: Figure 10.5 shows a block diagram of ATU channels 3 and
4.
TSTR OVI3/4
IMI3A/4A
Clock selection Comparator IMI3B/4B
IMI3C/4C
TCLKA IMI3D/4D
TCLKB
TIOA3/4
TIOB3/4
φ/(m·2n) Control logic
TIOC3/4
TIOD3/4
1 ≤ m ≤ 32
0≤n≤5
TIOR3A/4A
TIOR3B/4B
TIERDH/L*
TSRDH/L*
GR3C/4C
GR3D/4D
GR3A/4A
GR3B/4B
TCNT3/4
TCR3/4
TMDR*
Module data bus
Legend:
TMDR: Timer mode register (8 bits)
TCR: Timer control register (8 bits)
TIOR: Timer I/O control register (8 bits)
TSRD: Timer status register D (8 bits)
TIERD: Timer interrupt enable register D (8 bits)
TCNT: Free-running counter (16 bits)
GR: General register (16 bits)
Interrupts:
OVI: Overflow interrupt
IMI: Input capture/compare-match interrupt
Note: * TMDR is used by channels 3 to 5.

TSRDH and TIERDH are used by channel 3.
TSRDL and TIERDL are used by channels 4 and 5.
Figure 10.5 Block Diagram of Channels 3 and 4
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TSTR
Clock selection Comparator OVI5
IMI5A
TCLKA IMI5B
TCLKB
TIOA5
φ/(m·2n) Control logic TIOB5
1 ≤ m ≤ 32
0≤n≤5
CTIOR5A
TIERDL*
TSRDL*
TMDR*
TCNT5
GR5A
GR5B
TCR5
Module data bus
Legend:
TMDR: Timer mode register (8 bits)
TIOR5A: Timer I/O control register 5A (8 bits)
TSRDL: Timer status register DL (8 bits)
TIERDL: Timer interrupt enable register DL (8 bits)
GR5: General register 5 (16 bits)
Interrupts:
Note: * TMDR is used by channels 3 to 5.

TSRDH and TIERDH are used by channels 4 and 5.
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Block Diagram of Channels 6 to 9: Figure 10.7 shows a block diagram of ATU channels 6 to 9.
TSTR Clock selection Comparator CMI6–9
φ/(m·2n) Control logic TO6–9
1 ≤ m ≤ 32
0≤n≤5
TCNT6–9
CYLR6–9
TCR6–9
DTR6–9
BFR6–9
TIERE
TSRE
Module data bus
Legend:
TCR: Timer control register (8 bits)
TSRE: Timer status register E (8 bits)
TIERE: Timer interrupt enable register E (8 bits)
TCNT: Free-running counter (16 bits)
CYLR: Cycle register (16 bits)
BFR: Buffer register (16 bits)
DTR: Duty register (16 bits)
Interrupt:
CMI: Cycle compare-match interrupt
Figure 10.7 Block Diagram of Channels 6 to 9
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OSI10A–H
OFF1A–F
OFF2A–B Clock selection Comparator TOA10
TOB10
TOC10
TOD10
TOE10
φ/(m·2n) Control logic TOF10
TOG10
1 ≤ m ≤ 32 TOH10
0≤n≤5
DCNT10G
DCNT10C
DCNT10D
DCNT10H
DCNT10A
DCNT10B
DCNT10E
DCNT10F
TCR10
TIERF
TCNR
DSTR
TSRF
Module data bus
Legend:
TIERF: Timer interrupt enable register F (8 bits)
TSRF: Timer status register F (8 bits)
DSTR: Down-count start register (8 bits)
TCNR: Timer connection register (8 bits)
DCNT10: Down-counter 10 (16 bits)
Interrupt:
OSI10: One-shot pulse interrupt 10
OFF: Offset compare-match signal
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10.1.3 Inter-Channel and Inter-Module Signal Connection Diagram
Channel 10.9 shows the connections between channels and between modules in the ATU.
DMAC activation
(input capture)
Channel 0 TRG0A
Trigger output
MUX
TIA0 ICR0AH ICR0AL (synchronous capture)
TCNT0 TIB0 ICR0BH ICR0BL
Internal CLK TCNT0H TCNT0L TIC0 ICR0CH ICR0CL
MUX
TID0 ICR0DH ICR0DL
A/D converter activation

(“1” detection)
Channel 1 TRG1A
TIOA1 GR1A
Internal CLK TIOB1 GR1B Trigger output
MUX
TCLKA TCNT1 TIOC1 GR1C (compare-match)

TCLKB TIOD1 GR1D
TIOE1 GR1E
TIOF1 GR1F
OSBR
Trigger input
Internal CLK
MUX
TCLKA TCNT2 TIOA2 GR2A

TCLKB TIOB2 GR2B
Channel 2
Compare-match signal
transmission to advanced
pulse controller (APC)
DMAC
CYLR6 activation
Internal CLK TCNT6 TO6 DTR6 (compare-
BFR6 match)
Channel 6
Channel 10 Offset compare-

match signal
Down-counters
TOA10 OFF1A
DCNT10A
OFF1B
TOB10 DCNT10B
OFF1C
TOC10 DCNT10C
OFF1D
TOD10 DCNT10D
TOE10 OFF1E
DCNT10E
TOF10 DCNT10F OFF1F
TOG10 DCNT10G OFF2A
TOH10 OFF2B
DCNT10H
Figure 10.9 Inter-Channel and Inter-Module Signal Connection Diagram
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10.1.4 Prescaler Diagram
Figure 10.10 shows the first and second prescaler stages in the ATU. The output of the first
prescaler stage is input to channel 0. Either the output of the second prescaler stage or an external
clock can be input to channels 1 to 10, and an additional external clock (TCLKA or TCLKB) can
be input to channels 1 to 5.
φ/m (1 ≤ m ≤ 32) can be set as the output of the first prescaler stage (φ'), the setting being made in
prescaler control register 1 (PSCR1).
φ/2 (0 ≤ n ≤ 5) can be set as the output of the second prescaler stage (φ"), the setting being made
n
in the timer control register (TCR).
First prescaler Second prescaler

stage setting stage setting
register register
Input clock φ'
φ PSCR1 Channel 0
φ" or
φ' = ø/m TCR1
external clock
Channel 1
1 ≤ m ≤ 32
TCR2 φ" or Channel 2
external clock
external clock
external clock
external clock
φ"
TCR6 Channel 6
φ"
TCR7 Channel 7
Settable prescaler values φ"

TCR8 Channel 8
φ"
φ' = φ/m (1 ≤ m ≤ 32) TCR9 Channel 9
φ"
φ" = φ'/2n (0 ≤ n ≤ 5) TCR10 Channel 10
or external clock
DCNT10A–DCNT10F
φ" = φ'/2n (0 ≤ n ≤ 5) Channel 10
DCNT10G, DCNT10H
Figure 10.10 Prescaler Diagram
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Table 10.2 shows the pin configuration of the ATU. When these external pin functions are used,
the pin function controller (PFC) should also be set in accordance with the ATU settings. For
details, see section 16, Pin Function Controller.
Table 10.2 ATU Pins
Channel Name Abbreviation I/O Function

Common Clock input A TCLKA Input External clock A input pin
Clock input B TCLKB Input External clock B input pin
0 Input capture A0 TIA0 Input ICR0A input capture input pin
Input capture B0 TIB0 Input ICR0B input capture input pin
Input capture C0 TIC0 Input ICR0C input capture input pin
Input capture D0 TID0 Input ICR0D input capture input pin
1 Input capture/output TIOA1 Input/ GR1A output compare output/GR1A
compare A1 output input capture input
Input capture/output TIOB1 Input/ GR1B output compare output/GR1B
compare B1 output input capture input
Input capture/output TIOC1 Input/ GR1C output compare output/GR1C
compare C1 output input capture input
Input capture/output TIOD1 Input/ GR1D output compare output/GR1D
compare D1 output input capture input
Input capture/output TIOE1 Input/ GR1E output compare output/GR1E
compare E1 output input capture input
Input capture/output TIOF1 Input/ GR1F output compare output/GR1F
compare F1 output input capture input
compare A2 output input capture input
compare A3 output input capture input/PWM output pin
(PWM mode)
compare B3 output input capture input/PWM output pin
(PWM mode)
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Channel Name Abbreviation I/O Function

3 Input capture/output TIOC3 Input/ GR3C output compare output/GR3C
compare C3 output input capture input/PWM output pin
(PWM mode)
(PWM mode)
compare B4 output input capture input/PWM output pin
(PWM mode)
Input capture/output TIOC4 Input/ GR4C output compare output/GR4C
compare C4 output input capture input/PWM output pin
(PWM mode)
(PWM mode)
6 Output compare 6 TO6 Output Channel 6 PWM output pin
10 One-shot pulse A10 TOA10 Output One-shot pulse output pin
One-shot pulse B10 TOB10 Output One-shot pulse output pin
One-shot pulse C10 TOC10 Output One-shot pulse output pin
One-shot pulse D10 TOD10 Output One-shot pulse output pin
One-shot pulse E10 TOE10 Output One-shot pulse output pin
One-shot pulse F10 TOF10 Output One-shot pulse output pin
One-shot pulse G10 TOG10 Output One-shot pulse output pin
One-shot pulse H10 TOH10 Output One-shot pulse output pin
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10.1.6 Register and Counter Configuration
Table 3 summarizes the ATU registers.
Table 10.3 ATU Registers
Abbrevia- Initial
Channel Name tion R/W Value Address Access Size
Common Prescaler register 1 PSCR1 R/W H'00 H'FFFF82E9 8 bits
Timer start register TSTR R/W H'0000 H'FFFF82EA 16 bits
0 Trigger selection register TGSR R/W H'00 H'FFFF8280 8 bits
Timer I/O control register 0A TIOR0A R/W H'00 H'FFFF8281 8 bits
Interval interrupt request ITVRR R/W H'00 H'FFFF8282 8 bits
register
R/(W)* H'00
1
Timer status register AH TSRAH H'FFFF8283 8 bits
Timer interrupt enable TIERA R/W H'00 H'FFFF8284 8 bits
register A
R/(W)* H'00
1
Timer status register AL TSRAL H'FFFF8285 8 bits
Free-running counter 0H TCNT0H R/W H'0000 H'FFFF8288 32 bits
Free-running counter 0L TCNT0L R/W H'0000
Input capture register 0AH ICR0AH R H'0000 H'FFFF828C 32 bits
Input capture register 0AL ICR0AL R H'0000
Input capture register 0BH ICR0BH R H'0000 H'FFFF8290 32 bits
Input capture register 0BL ICR0BL R H'0000
Input capture register 0CH ICR0CH R H'0000 H'FFFF8294 32 bits
Input capture register 0CL ICR0CL R H'0000
Input capture register 0DH ICR0DH R H'0000 H'FFFF8298 32 bits
Input capture register 0DL ICR0DL R H'0000
1 Timer control register 1 TCR1 R/W H'00 H'FFFF82C0 8 bits 16 bits
Timer I/O control register 1A TIOR1A R/W H'00 H'FFFF82C1 8 bits
Timer I/O control register 1B TIOR1B R/W H'00 H'FFFF82C2 8 bits 16 bits
Timer I/O control register 1C TIOR1C R/W H'00 H'FFFF82C3 8 bits
Timer interrupt enable TIERB R/W H'00 H'FFFF82C4 8 bits
register B
R/(W)* H'00
1
Timer status register B TSRB H'FFFF82C5 8 bits
Free-running counter 1 TCNT1 R/W H'0000 H'FFFF82D0 16 bits
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Abbrevia- Initial
1 General register 1A GR1A R/W H'FFFF H'FFFF82D2 16 bits
General register 1B GR1B R/W H'FFFF H'FFFF82D4 16 bits
General register 1C GR1C R/W H'FFFF H'FFFF82D6 16 bits
General register 1D GR1D R/W H'FFFF H'FFFF82D8 16 bits
General register 1E GR1E R/W H'FFFF H'FFFF82DA 16 bits
General register 1F GR1F R/W H'FFFF H'FFFF82DC 16 bits
Offset base register OSBR R H'0000 H'FFFF82DE 16 bits
2 Timer control register 2 TCR2 R/W H'00 H'FFFF82C6 8 bits 16 bits
Timer I/O control register 2A TIOR2A R/W H'00 H'FFFF82C7 8 bits
Timer interrupt enable TIERC R/W H'00 H'FFFF82C8 8 bits
register C
R/(W)* H'00
1
Timer status register C TSRC H'FFFF82C9 8 bits
Free-running counter 2 TCNT2 R/W H'0000 H'FFFF82CA 16 bits
General register 2A GR2A R/W H'FFFF H'FFFF82CC 16 bits
General register 2B GR2B R/W H'FFFF H'FFFF82CE 16 bits
3–5 Timer mode register TMDR R/W H'00 H'FFFF8200 8 bits
Timer interrupt enable TIERDH R/W H'00 H'FFFF8202 8 bits
register DH
R/(W)* H'00
1
Timer status register DH TSRDH H'FFFF8203 8 bits
Timer interrupt enable TIERDL R/W H'00 H'FFFF8204 8 bits
register DL
R/(W)* H'00
1
Timer status register DL TSRDL H'FFFF8205 8 bits
3 Timer I/O control register 3A TIOR3A R/W H'00 H'FFFF8208 8 bits 16 bits
Timer I/O control register 3B TIOR3B R/W H'00 H'FFFF8209 8 bits
Free-running counter 3 TCNT3 R/W H'0000 H'FFFF820E 16 bits
General register 3A GR3A R/W H'FFFF H'FFFF8210 16 bits
General register 3B GR3B R/W H'FFFF H'FFFF8212 16 bits
General register 3C GR3C R/W H'FFFF H'FFFF8214 16 bits
General register 3D GR3D R/W H'FFFF H'FFFF8216 16 bits
Timer control register 3 TCR3 R/W H'00 H'FFFF8206 8 bits 16 bits
4 Timer control register 4 TCR4 R/W H'00 H'FFFF8207 8 bits
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Abbrevia- Initial
4 Timer I/O control register 4A TIOR4A R/W H'00 H'FFFF820A 8 bits 16 bits
Timer I/O control register 4B TIOR4B R/W H'00 H'FFFF820B 8 bits
Free-running counter 4 TCNT4 R/W H'0000 H'FFFF8218 16 bits
General register 4A GR4A R/W H'FFFF H'FFFF821A 16 bits
General register 4B GR4B R/W H'FFFF H'FFFF821C 16 bits
General register 4C GR4C R/W H'FFFF H'FFFF821E 16 bits
General register 4D GR4D R/W H'FFFF H'FFFF8220 16 bits
5 Timer control register 5 TCR5 R/W H'00 H'FFFF820C 8 bits 16 bits
Timer I/O control register 5A TIOR5A R/W H'00 H'FFFF820D 8 bits
Free-running counter 5 TCNT5 R/W H'0000 H'FFFF8222 16 bits
General register 5A GR5A R/W H'FFFF H'FFFF8224 16 bits
General register 5B GR5B R/W H'FFFF H'FFFF8226 16 bits
6–9 Timer interrupt enable TIERE R/W H'00 H'FFFF8240 8 bits
register E
R/(W)* H'00
1
Timer status register E TSRE H'FFFF8241 8 bits
6 Free-running counter 6 TCNT6 R/W H'0001 H'FFFF8246 16 bits
Cycle register 6 CYLR6 R/W H'FFFF H'FFFF8248 16 bits
Buffer register 6 BFR6 R/W H'FFFF H'FFFF824A 16 bits
Duty register 6 DTR6 R/W H'FFFF H'FFFF824C 16 bits
Free-running counter 7 TCNT7 R/W H'0001 H'FFFF824E 16 bits
Buffer register 7 BFR7 R/W H'FFFF H'FFFF8252 16 bits
Duty register 7 DTR7 R/W H'FFFF H'FFFF8254 16 bits
8 Free-running counter 8 TCNT8 R/W H'0001 H'FFFF8256 16 bits
Buffer register 8 BFR8 R/W H'FFFF H'FFFF825A 16 bits
Duty register 8 DTR8 R/W H'FFFF H'FFFF825C 16 bits
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REJ09B0273-0500
Abbrevia- Initial
9 Free-running counter 9 TCNT9 R/W H'0001 H'FFFF825E 16 bits
Buffer register 9 BFR9 R/W H'FFFF H'FFFF8262 16 bits
Duty register 9 DTR9 R/W H'FFFF H'FFFF8264 16 bits
10 Timer control register 10 TCR10 R/W H'00 H'FFFF82E0 8 bits 16 bits
Timer connection register TCNR R/W H'00 H'FFFF82E1 8 bits
Timer interrupt enable TIERF R/W H'00 H'FFFF82E2 8 bits
register F
R/(W)* H'00
1
Timer status register F TSRF H'FFFF82E3 8 bits
R/(W)* H'00
2
Down-count start register DSTR H'FFFF82E5 8 bits
Down-counter 10A DCNT10A R/W H'FFFF H'FFFF82F0 16 bits
Down-counter 10B DCNT10B R/W H'FFFF H'FFFF82F2 16 bits
Down-counter 10C DCNT10C R/W H'FFFF H'FFFF82F4 16 bits
Down-counter 10D DCNT10D R/W H'FFFF H'FFFF82F6 16 bits
Down-counter 10E DCNT10E R/W H'FFFF H'FFFF82F8 16 bits
Down-counter 10F DCNT10F R/W H'FFFF H'FFFF82FA 16 bits
Down-counter 10G DCNT10G R/W H'FFFF H'FFFF82FC 16 bits
Down-counter 10H DCNT10H R/W H'FFFF H'FFFF82FE 16 bits
Notes: 1. Only 0 can be written after reading 1, to clear flags.
2. Only 1 can be written, to set flags.
8-bit registers, and 16-bit registers and counters, are accessed in two cycles, but since the
data bus is 16 bits wide, 32-bit registers and counters are accessed in four cycles.
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10.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) is a 16-bit register. The ATU has one TSTR register.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — STR9 STR8 STR7 STR6 STR5 STR4 STR3 STR2 STR1 STR0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TSTR is a 16-bit readable/writable register that starts and stops the free-running counter (TCNT)
in channels 0 to 9.
TSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 15 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 9—Counter Start 9 (STR9): Starts and stops free-running counter 9 (TCNT9).
Bit 9:
STR7 Description
0 TCNT9 is halted (Initial value)
1 TCNT9 counts
Bit 8:
STR8 Description
1 TCNT8 counts
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Bit 7:
STR7 Description
1 TCNT7 counts
Bit 6: Description
STR6
1 TCNT6 counts
Bit 5:
STR5 Description
1 TCNT5 counts
Bit 4:
STR4 Description
1 TCNT4 counts
Bit 3:
STR3 Description
1 TCNT3 counts
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Bit 2:
STR2 Description
1 TCNT2 counts
Bit 1:
STR1 Description
1 TCNT1 counts
Bit 0:
STR0 Description
1 TCNT0 counts
10.2.2 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an 8-bit register. The ATU has one TDR register.
Bit: 7 6 5 4 3 2 1 0
— — — — — T5PWN T4PWN T3PWN
TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in
input capture/output compare mode or PWM mode.
TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Bit 2—PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output
compare mode or PWM mode.
Bit 2:
T5PWM Description
0 Channel 5 operates in input capture/output compare mode (Initial value)
1 Channel 5 operates in PWM mode
When bit T5PWM is set to 1 to select PWM mode, pin TIOA5 becomes a PWM output pin,
general register 5B (GR5B) functions as a cycle register, and general register 5A (GR5A) as a
duty register.
Bit 1:
T4PWM Description
When bit T4PWM is set to 1 to select PWM mode, pins TIOA4 to TIOC4 become PWM output
pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A to 4C
(GR4A to GR4C) as duty registers.
Bit 0:
T3PWM Description
When bit T3PWM is set to 1 to select PWM mode, pins TIOA3 to TIOC3 become PWM output
pins, general register 3D (GR3D) functions as a cycle register, and general registers 3A to 3C
(GR3A to GR3C) as duty registers.
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10.2.3 Prescaler Register 1 (PSCR1)
Prescaler register 1 (PSCR1) is an 8-bit register. The ATU has one PSCR1 register.
Bit: 7 6 5 4 3 2 1 0
— — — PSCE PSCD PSCC PSCB PSCA
PSCR1 is an 8-bit readable/writable register that enables the first-stage counter clock φ' input to
each free-running counter (TCNT0 to TCNT9) and down-counter (DCNT10A to DCNT10H) to be
set to any value from φ/1 to φ/32.
Input counter clock φ' is determined by setting PSCA to PSCE: φ' is φ/1 when the set value is
H'00, and φ/32 when H'1F.
PSCR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
The internal clock φ' set with this register can undergo further second-stage scaling to create clock
φ" for channels 1 to 10, the setting being made in the timer control register (TCR).
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10.2.4 Timer Control Registers (TCR)
The timer control registers (TCR) are 8-bit registers. The ATU has ten TCR registers. one for each
channel.
Channel Abbreviation Function
1 TCR1 Internal clock/external clock selection
2 TCR2 When internal clock is selected: Further scaling of clock φ' scaled
with PSCR1, to create φ"
3 TCR3
When external clock is selected: Selection of 2 external clocks,
4 TCR4
selection of input edge
5 TCR5
6 TCR6 Further scaling of clock φ' scaled with PSCR1, to create φ"
7 TCR7 (internal clock only)
8 TCR8
9 TCR9
10 TCR10 Further scaling of clock φ' scaled with PSCR1, to create φ"
(internal clock only)
Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external
clock is used for channels 1 to 5.
When an internal clock is selected, TCR selects the value of φ" further scaled from clock φ' scaled
with prescaler register 1 (PSCR1). Scaled clock φ" can be selected, for channels 1 to 10 only, from
φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32 (only φ' is available for channel 0). Edge detection is performed
on the rising edge.
When an external clock is selected (channels 1 to 5 only), TCR selects whether TCLKA or
TCLKB is used, and also performs edge selection.
Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Timer Control Registers 1 to 5 (TCR1 to TCR5)
Bit: 7 6 5 4 3 2 1 0
— — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0
R/W: R R R/W R/W R R/W R/W R/W
Bits 7 and 6—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 5 and 4—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock is used.
Bit 5: Bit 4:
CKEG1 CKEG0 Description
0 0 Rising edges counted (Initial value)
1 Falling edges counted
1 0 Both rising and falling edges counted
1 External clock count disabled
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 2 to 0—Clock Select 2 to 0 (CKSEL2 to CKSEL0): These bits select whether an internal
clock or external clock is used.
When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and
φ'/32.
When an external clock is selected, either TCLKA or TCLKB is selected.
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Bit 2: Bit 1: Bit 0:

CKSEL2 CKSEL1 CKSEL0 Description
0 0 0 Internal clock φ": counting on φ' (Initial value)
1 Internal clock φ": counting on φ'/2
1 0 Internal clock φ": counting on φ'/4
1 0 0 Internal clock φ": counting on φ'/16
1 0 External clock: counting on TCLKA pin input
1 External clock: counting on TCLKB pin input
Timer Control Registers 6 to 9 (TCR6 to TCR9)
Bit: 7 6 5 4 3 2 1 0
— — — — — CKSEL2 CKSEL1 CKSEL0
Bits 2 to 0—Clock Select 2 to 0 (CKSEL2 to CKSEL0): These bits select clock φ", scaled from
the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32.

CKSEL2 CKSEL1 CKSEL0 Description
1 0 Cannot be set
1 Cannot be set
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Timer Control Register 10 (TCR10)
Bit: 7 6 5 4 3 2 1 0
— CKSEL CKSEL CKSEL — CKSEL CKSEL CKSEL
2A 1A 0A 2B 1B 0B
R/W: R R/W R/W R/W R R/W R/W R/W
Bits 6 to 4—Clock Select 2A to 0A (CKSEL2A to CKSEL0A): These bits select clock φ",
scaled from the internal clock source, for DCNT10A to DCNT10F in channel 10, from φ', φ'/2,
φ'/4, φ'/8, φ'/16, and φ'/32. DCNT10A to DCNT10F all count on the same synchronous clock.

CKSEL2A CKSEL1A CKSEL0A Description
1 0 Cannot be set
1 Cannot be set
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Bits 2 to 0—Clock Select 2B to 0B (CKSEL2B to CKSEL0B): These bits select clock φ", scaled
from the internal clock source, for DCNT10G and DCNT10H in channel 10, from φ', φ'/2, φ'/4,
φ'/8, φ'/16, and φ'/32. DCNT10G and DCNT10H count on the same synchronous clock.

CKSEL2B CKSEL1B CKSEL0B Description
1 0 Cannot be set
1 Cannot be set
10.2.5 Timer I/O Control Registers (TIOR)
The timer I/O control registers (TIOR) are 8-bit registers. The ATU has ten TIOR registers, one
for channel 0, three for channel 1, one for channel 2, two each for channels 3 and 4, and one for
channel 5.

0 TIOR0A ICR0 and OSBR edge detection setting
1 TIOR1A, GR1 and GR2 input capture/compare-match switching, edge
TIOR1B, detection/output value setting
TIOR1C
2 TIOR2A
3 TIOR3A, GR3 to GR5 input capture/compare-match switching, edge
TIOR3B detection/output value setting, TCNT3 to TCNT5 clear
4 TIOR4A, enable/disable setting
TIOR4B
5 TIOR5A
Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input
capture registers and general registers.
For dedicated input capture registers (ICR), TIOR performs edge detection setting.
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For general registers (GR), TIOR selects use as an input capture register or output compare
register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or
disabling of free-running counter (TCNT) clearing.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Timer I/O Control Register 0A (TIOR0A)
Timer I/O control register 0A (TIOR0A) is an 8-bit register. Channel 1 has one TIOR register.
Bit: 7 6 5 4 3 2 1 0
IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0
TIOR0A specifies edge detection for input capture registers ICR0A to ICR0D.
Bits 7 and 6—I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select input capture
register 0D (ICR0D) edge detection.
Bit 7: Bit 6:
IO0D1 IO0D0 Description
0 0 Input capture disabled (Initial value)
1 Input capture in ICR0D on rising edge
1 0 Input capture in ICR0D on falling edge
1 Input capture in ICR0D on both rising and falling edges
Bits 5 and 4—I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select input capture
register 0C (ICR0C) edge detection.
Bit 5: Bit 4:
IO0C1 IO0C0 Description
1 Input capture in ICR0C on rising edge
1 0 Input capture in ICR0C on falling edge
1 Input capture in ICR0C on both rising and falling edges
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Bits 3 and 2—I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select input capture
register 0B (ICR0B) edge detection.
Bit 3: Bit 2:
IO0B1 IO0B0 Description
1 Input capture in ICR0B on rising edge
1 0 Input capture in ICR0B on falling edge
1 Input capture in ICR0B on both rising and falling edges
Bits 1 and 0—I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select input capture
register 0A (ICR0A) and offset base register (OSBR) edge detection.
Bit 1: Bit 0:
IO0A1 IO0A0 Description
1 Input capture in ICR0A on rising edge
1 0 Input capture in ICR0A on falling edge
1 Input capture in ICR0A on both rising and falling edges
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Timer I/O Control Registers 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A)
Timer I/O control register 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A) are 8-bit registers.
There are four TIOR registers, three for timer 1 and one for timer 2.
TIOR1A
Bit: 7 6 5 4 3 2 1 0
— IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0
TIOR1B
Bit: 7 6 5 4 3 2 1 0
— IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0
TIOR1C
Bit: 7 6 5 4 3 2 1 0
— IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0
Registers TIOR0A to TIOR1C specify whether general registers GR1A to GR1F are used as input
capture or compare-match registers, and also perform edge detection and output value setting.
standby mode.
TIOR2A
Bit: 7 6 5 4 3 2 1 0
— IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0
TIOR2A specifies whether general registers GR2A and GR2B are used as input capture or
compare-match registers, and also performs edge detection and output value setting.
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TIOR2A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 2B2 to 2B0 (IO1B2 to IO1B0,
IO1D2 to IO1D0, IOF12 to IO1F0, IO2B2 to IO2B0): These bits select the general register
(GR) function.

IOxx2 IOxx1 IOxx0 Description
0 0 0 GR is an output 0 output regardless of compare-match
compare register (Initial value)
1 0 output on GR compare-match
1 0 1 output on GR compare-match
1 Toggle output on GR compare-match
1 0 0 GR is input capture Input capture disabled
1 register Input capture in GR on rising edge
1 0 Input capture in GR on falling edge
1 Input capture in GR on both rising and
falling edges
Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 2A2 to 2A0 (IO1A2 to IO1A0,
IO1C2 to IO1C0, IO1E2 to IO1E0, IO2A2 to IO2A0): These bits select the general register
(GR) function.
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falling edges
Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A (TIOR3A, TO0R3B, TIOR4A, TIOR4B,
TIOR5A)
Timer I/O control registers 3A, 3B, 4A, 4B, and 5A (TIOR3A, TO0R3B, TIOR4A, TIOR4B,
TIOR5A) are 8-bit registers. There are five TIOR registers, two each for channels 3 and 4, and one
for channel 5.
TIOR3A
Bit: 7 6 5 4 3 2 1 0
CCI3B IO3B2 IO3B1 IO3B0 CCI3A IO3A2 IO3A1 IO3A0
TIOR3B
Bit: 7 6 5 4 3 2 1 0
CCI3D IO3D2 IO3D1 IO3D0 CCI3C IO3C2 IO3C1 IO3C0
TIOR3A and TIOR3B are 8-bit readable/writable registers. When bit 0 of TMDR is 0, they
specify whether general registers GR3A to GR3D are used as input capture or compare-match
registers, and also perform edge detection and output value setting. Also, when bit 0 of TMDR is
0, they select enabling or disabling of free-running counter (TCNT3) clearing.
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standby mode.
TIOR4A
Bit: 7 6 5 4 3 2 1 0
TIOR4B
Bit: 7 6 5 4 3 2 1 0
CCI4D IO4D2 IO4D1 IO4D0 CCI4C IO4C2 IO4C1 IO4C0
TIOR4A and TIOR4B are 8-bit readable/writable registers. When bit 1 of TMDR is 0, they
specify whether general registers GR4A to GR4D are used as input capture or compare-match
registers, and also perform edge detection and output value setting. Also, when bit 1 of TMDR is
0, they select enabling or disabling of free-running counter (TCNT4) clearing.
standby mode.
TIOR5A
Bit: 7 6 5 4 3 2 1 0
TIOR5A is an 8-bit readable/writable register. When bit 2 of TMDR is 0, it specifies whether

general registers GR5A and GR5B are used as input capture or compare-match registers, and also
performs edge detection and output value setting. Also, when bit 2 of TMDR is 0, TIOR5A selects
enabling or disabling of free-running counter (TCNT5) clearing.
TIOR5A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Bit 7—Clear Counter Enable Flag 3B, 3D, 4B, 4D, 5B (CCI3B, CCI3D, CCI4B, CCI4D,
CCI5B): These bits select enabling or disabling of free-running counter (TCNT) clearing.
Bit 7:
CCIxx Description
0 TCNT clearing disabled (Initial value)
1 TCNT cleared on GR compare-match
TCNT is cleared on compare-match only when GR is functioning as an output compare register.
Bits 6 to 4—I/O Control 3B2 to 3B0, 3D2 to 3D0, 4B2 to 4B0, 4D2 to 4D0, 5B2 to 5B0 (IO3B2
to IO3B0, IO3D2 to IO3D0, IO4B2 to IO4B0, IO4D2 to IO4D0, IO5B2 to IO5B0): These bits
select the general register (GR) function.

falling edges
Bit 3—Clear Counter Enable Flag 3A, 3C, 4A, 4C, 5A (CCI3A, CCI3C, CCI4A, CCI4C,
CCI5A): These bits select enabling or disabling of free-running counter (TCNT) clearing.
Bit 3:
CCIxx Description
0 TCNT clearing disabled (Initial value)
1 TCNT cleared on GR compare-match
TCNT is cleared on compare-match only when GR is functioning as an output compare register.
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Bits 2 to 0—I/O Control 3A2 to 3A0, 3C2 to 3C0, 4A2 to 4A0, 4C2 to 4C0, 5A2 to 5A0
(IO3A2 to IO3A0, IO3C2 to IO3C0, IO4A2 to IO4A0, IO4C2 to IO4C0, IO5A2 to IO5A0):
These bits select the general register (GR) function.

falling edges
10.2.6 Trigger Selection Register (TGSR)
The trigger selection register (TGSR) is an 8-bit register. The ATU has one TGSR register.
Bit: 7 6 5 4 3 2 1 0
— — — — — TRG0D — TRG0A
R/W: R R R R R R/W R R/W
TGSR is an 8-bit readable/writable register that selects an input pin (TIOA, TIOD) or the
compare-match output signal (TGR1A) from the channel 1 general register (GR1A) as the channel
0 input capture register (ICR0A, ICR0D) input trigger.
TGSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Bit 2—ICR0D Input Trigger (TRG0D): Selects whether a pin (TIOD) or the channel 1
compare-match signal (TRG1A) is to be used as the channel 0 input capture register (ICR0D)
input trigger.
Bit 2:
TRG0D Description
0 Input pin (TIOD) used as input trigger (Initial value)
1 Channel 1 compare-match signal (TRG1A) used as input trigger
Bit 0—ICR0A Input Trigger (TRG0A): Selects whether a pin (TIOA) or the channel 1
compare-match signal (TRG1A) is to be used as the channel 0 input capture register (ICR0A)
input trigger.
Bit 0:
TRG0A Description
0 Input pin (TIOA) used as input trigger (Initial value)
1 Channel 1 compare-match signal (TRG1A) used as input trigger
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10.2.7 Timer Status Registers (TSR)
The timer status registers (TSR) are 8-bit registers. The ATU has eight TSR registers: two for
channel 0, one each for channels 1 and 2, two for channels 3 to 5, one for channels 6 to 9, and one
for channel 10.

0 TSRAH, TSRAL Indicates input capture, interval interrupt, and overflow status.
1 TSRB Indicates input capture, compare-match, and overflow status
2 TSRC
3 TSRDH, TSRDL Indicates input capture, compare-match, and overflow status.
4
5
6 TSRE Indicates cycle register compare-match status
7
8
9
10 TSRF Indicates down-counter underflow status.
The TSR registers are 8-bit readable/writable registers containing flags that indicate free-running
counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, general register
input capture or compare-match, channel 6 to 9 compare-matches, down-counter underflow.
Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is
enabled by the corresponding bit in the timer interrupt enable register (TIER).
Each TSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Timer Status Registers AH and AL (TSRAH, TSRAL)
TSRAH indicates the status of channel 0 interval interrupts.
Bit: 7 6 5 4 3 2 1 0
— — — — IIF3 IIF2 IIF1 IIF0
R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
Bit 3—Interval Interrupt Flag (IIF3): Status flag that indicates the generation of an interval
interrupt.
Bit 3:
IIF3 Description
0 [Clearing condition] (Initial value)
When IIF3 is read while set to 1, then 0 is written in IIF3
1 [Setting condition]
When 1 is generated by AND of ITVE3 in ITVRR and bit 13 of TCNT0L
interrupt.
Bit 2:
IIF2 Description
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interrupt.
Bit 1:
IIF1 Description
interrupt.
Bit 0:
IIF0 Description
TSRAL indicates the status of channel 0 input capture and overflow.
Bit: 7 6 5 4 3 2 1 0
— — — OVF0 ICF0D ICF0C ICF0B ICF0A
R/W: R R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit 4—Overflow Flag (OVF0): Status flag that indicates TCNT0 overflow.
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Bit 4:
OVF0 Description
When OVF0 is read while set to 1, then 0 is written in OVF0
When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000)
Bit 3—Input Capture Flag (ICF0D): Status flag that indicates ICR0D input capture.
Bit 3:
ICF0D Description
When ICF0D is read while set to 1, then 0 is written in ICF0D
When the TCNT0 value is transferred to the input capture register (ICR0D) by an input
capture signal
Bit 2—Input Capture Flag (ICF0C): Status flag that indicates ICR0C input capture.
Bit 2:
ICF0C Description
When ICF0C is read while set to 1, then 0 is written in ICF0C
When the TCNT0 value is transferred to the input capture register (ICR0C) by an input
capture signal
Bit 1—Input Capture Flag (ICF0B): Status flag that indicates ICR0B input capture.
Bit 1:
ICF0B Description
When ICF0B is read while set to 1, then 0 is written in ICF0B
When the TCNT0 value is transferred to the input capture register (ICR0B) by an input
capture signal
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Bit 0—Input Capture Flag (ICF0A): Status flag that indicates ICR0A input capture.
Bit 0:
ICF0A Description
When ICF0A is read while set to 1, then 0 is written in ICF0A
When the TCNT0 value is transferred to the input capture register (ICR0A) by an input
capture signal
Timer Status Register B (TSRB)
TSRB indicates the status of channel 1 input capture, compare-match, and overflow.
Bit: 7 6 5 4 3 2 1 0
— OVF1 IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A
R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit 6:
OVF1 Description
0 [Clearing condition]) (Initial value)
When the TCNT1 value overflows (from H'FFFF to H'0000)
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Bit 5—Input Capture/Compare-Match Flag (IMF1F): Status flag that indicates GR1F input
capture or compare-match.
Bit 5:
IMF1F Description
When IMF1F is read while set to 1, then 0 is written in IMF1F
1 [Setting conditions]
• When the TCNT1 value is transferred to GR1F by an input capture signal while
GR1F is functioning as an input capture register
• When TCNT1 = GR1F while GR1F is functioning as an output compare register
Bit 4—Input Capture/Compare-Match Flag (IMF1E): Status flag that indicates GR1E input
Bit 4:
IMF1E Description
When IMF1E is read while set to 1, then 0 is written in IMF1E
• When the TCNT1 value is transferred to GR1E by an input capture signal while
GR1E is functioning as an input capture register
• When TCNT1 = GR1E while GR1E is functioning as an output compare register
Bit 3—Input Capture/Compare-Match Flag (IMF1D): Status flag that indicates GR1D input
Bit 3:
IMF1D Description
When IMF1D is read while set to 1, then 0 is written in IMF1D
• When the TCNT1 value is transferred to GR1D by an input capture signal while
GR1D is functioning as an input capture register
• When TCNT1 = GR1D while GR1D is functioning as an output compare register
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Bit 2—Input Capture/Compare-Match Flag (IMF1C): Status flag that indicates GR1C input
Bit 2:
IMF1C Description
When IMF1C is read while set to 1, then 0 is written in IMF1C
• When the TCNT1 value is transferred to GR1C by an input capture signal while
GR1C is functioning as an input capture register
• When TCNT1 = GR1C while GR1C is functioning as an output compare register
Bit 1—Input Capture/Compare-Match Flag (IMF1B): Status flag that indicates GR1B input
Bit 1:
IMF1B Description
When IMF1B is read while set to 1, then 0 is written in IMF1B
• When the TCNT1 value is transferred to GR1B by an input capture signal while
GR1B is functioning as an input capture register
• When TCNT1 = GR1B while GR1B is functioning as an output compare register
Bit 0—Input Capture/Compare-Match Flag (IMF1A): Status flag that indicates GR1A input
Bit 0:
IMF1A Description
When IMF1A is read while set to 1, then 0 is written in IMF1A
• When the TCNT1 value is transferred to GR1A by an input capture signal while
GR1A is functioning as an input capture register
• When TCNT1 = GR1A while GR1A is functioning as an output compare register
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Timer Status Register C (TSRC)
TSRC indicates the status of channel 2 input capture, compare-match, and overflow.
Bit: 7 6 5 4 3 2 1 0
— — — — — OVF2 IMF2B IMF2A
R/W: R R R R R R/(W)* R/(W)* R/(W)*
Bit 2:
OVF2 Description
Bit 1:
IMF2B Description
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Bit 0:
IMF2A Description
Timer Status Registers DH and DL (TSRDH, TSRDL)
TSRDH indicates the status of channel 3 input capture, compare-match, and overflow.
Bit: 7 6 5 4 3 2 1 0
— — — OVF3 IMF3D IMF3C IMF3B IMF3A
Bit 4:
OVF3 Description
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Bit 3:
IMF3D Description
Bit 2:
IMF3C Description
Bit 1:
IMF3B Description
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Bit 0:
IMF3A Description
TSRDL indicates the status of channel 4 and 5 input capture, compare-match, and overflow.
Bit: 7 6 5 4 3 2 1 0
OVF4 IMF4D IMF4C IMF4B IMF4A OVF5 IMF5B IMF5A
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit 7:
OVF4 Description
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Bit 6:
IMF4D Description
Bit 5:
IMF4C Description
Bit 4:
IMF4B Description
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Bit 3:
IMF4A Description
Bit 2:
OVF5 Description
Bit 1:
IMF5B Description
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Bit 0:
IMF5A Description
Timer Status Register E (TSRE)
TSRE indicates the status of channel 6 to 9 cycle register compare-matches.
Bit: 7 6 5 4 3 2 1 0
— CMF6 — CMF7 — CMF8 — CMF9
R/W: R R/(W)* R R/(W)* R R/(W)* R R/(W)*
Bit 6—Cycle Register Compare-Match Flag (CMF6): Status flag that indicates CYLR6
compare-match.
Bit 6:
CMF6 Description
0 [Clearing conditions] (Initial value)
• When CMF6 is read while set to 1, then 0 is written in CMF6
• When cleared by the DMAC after data transfer when used as a
DMAC activation source
When TCNT6 = CYLR6
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compare-match.
Bit 4:
CMF7 Description
When CMF7 is read while set to 1, then 0 is written in CMF7
When TCNT7 = CYLR7
compare-match.
Bit 2:
CMF8 Description
When TCNT8 = CYLR8
compare-match.
Bit 0:
CMF9 Description
When TCNT9 = CYLR9
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Timer Status Register F (TSRF)
TSRF indicates the channel 10 one-shot pulse status.
Bit: 7 6 5 4 3 2 1 0
OSF10H OSF10G OSF10F OSF10E OSF10D OSF10C OSF10B OSF10A
Bit 7—One-Shot Pulse Flag (OSF10H): Status flag that indicates a DCNT10H one-shot pulse.
Bit 7:
OSF10H Description
When OSF10H is read while set to 1, then 0 is written in OSF10H
When the down-counter (DCNT10H) value underflows
Bit 6—One-Shot Pulse Flag (OSF10G): Status flag that indicates a DCNT10G one-shot pulse.
Bit 6:
OSF10G Description
When OSF10G is read while set to 1, then 0 is written in OSF10G
When the down-counter (DCNT10G) value underflows
Bit 5—One-Shot Pulse Flag (OSF10F): Status flag that indicates a DCNT10F one-shot pulse.
Bit 5:
OSF10F Description
When OSF10F is read while set to 1, then 0 is written in OSF10F
When the down-counter (DCNT10F) value underflows
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Bit 4—One-Shot Pulse Flag (OSF10E): Status flag that indicates a DCNT10E one-shot pulse.
Bit 4:
OSF10E Description
When OSF10E is read while set to 1, then 0 is written in OSF10E
When the down-counter (DCNT10E) value underflows
Bit 3—One-Shot Pulse Flag (OSF10D): Status flag that indicates a DCNT10D one-shot pulse.
Bit 3:
OSF10D Description
When OSF10D is read while set to 1, then 0 is written in OSF10D
When the down-counter (DCNT10D) value underflows
Bit 2—One-Shot Pulse Flag (OSF10C): Status flag that indicates a DCNT10C one-shot pulse.
Bit 2:
OSF10C Description
When OSF10C is read while set to 1, then 0 is written in OSF10C
When the down-counter (DCNT10C) value underflows
Bit 1—One-Shot Pulse Flag (OSF10B): Status flag that indicates a DCNT10B one-shot pulse.
Bit 1:
OSF10B Description
When OSF10B is read while set to 1, then 0 is written in OSF10B
When the down-counter (DCNT10B) value underflows
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Bit 0—One-Shot Pulse Flag (OSF10A): Status flag that indicates a DCNT10A one-shot pulse.
Bit 0:
OSF10A Description
When OSF10A is read while set to 1, then 0 is written in OSF10A
When the down-counter (DCNT10A) value underflows
10.2.8 Timer Interrupt Enable Registers (TIER)
The timer interrupt enable registers (TIER) are 8-bit registers. The ATU has seven TIER registers:
one each for channels 0, 1, and 2, two for channels 3 to 5, one for channels 6 to 9, and one for
channel 10.

0 TIERA Controls input capture, compare-match, and interval interrupt
request enabling/disabling.
1 TIERB Controls input capture, compare-match, and overflow interrupt
2 TIERC request enabling/disabling.
3 TIERDH, Controls input capture, compare-match, and overflow interrupt

4 TIERDL request enabling/disabling.
5
6 TIERE Controls cycle register compare-match interrupt request
7 enabling/disabling.
8
9
10 TIERF Controls underflow interrupt request enabling/disabling.
The TIER registers are 8-bit readable/writable registers that control enabling/disabling of free-
running counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests,
interval interrupt requests, general register and dedicated input capture register input
capture/compare-match interrupt requests, channel 6 to 9 compare-match interrupt requests, and
down-counter (DCNT) underflow interrupt requests.
Each TIER is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Timer Interrupt Enable Register A (TIERA)
TIERA controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bit: 7 6 5 4 3 2 1 0
— — — OVE0 ICE0D ICE0C ICE0B ICE0A
Bit 4—Overflow Interrupt Enable (OVE0): Enables or disables OVI0 requests when the
overflow flag (OVF0) in TSR is set to 1.
Bit 4:
OVE0 Description
0 OVI0 interrupt requested by OVF0 is disabled (Initial value)
1 OVI0 interrupt requested by OVF0 is enabled
Bit 3—Input Capture Interrupt Enable (ICE0D): Enables or disables ICI0D requests when the
input capture flag (ICF0D) in TSR is set to 1.
Bit 3:
ICE0D Description
0 ICI0D interrupt requested by ICF0D is disabled (Initial value)
1 ICI0D interrupt requested by ICF0D is enabled
Bit 2—Input Capture Interrupt Enable (ICE0C): Enables or disables ICI0C requests when the
input capture flag (ICF0C) in TSR is set to 1.
Bit 2:
ICE0C Description
0 ICI0C interrupt requested by ICF0C is disabled (Initial value)
1 ICI0C interrupt requested by ICF0C is enabled
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Bit 1—Input Capture Interrupt Enable (ICE0B): Enables or disables ICI0B requests when the
input capture flag (ICF0B) in TSR is set to 1.
Bit 1:
ICE0B Description
0 ICI0B interrupt requested by ICF0B is disabled (Initial value)
1 ICI0B interrupt requested by ICF0B is enabled
Bit 0—Input Capture Interrupt Enable (ICE0A): Enables or disables ICI0A requests when the
input capture flag (ICF0A) in TSR is set to 1.
Bit 0:
ICE0A Description
0 ICI0A interrupt requested by ICF0A is disabled (Initial value)
1 ICI0A interrupt requested by ICF0A is enabled
Timer Interrupt Enable Register B (TIERB)
TIERB controls enabling/disabling of channel 1 input capture, compare-match, and overflow

interrupt requests.
Bit: 7 6 5 4 3 2 1 0
— OVE1 IME1F IME1E IME1D IME1C IME1B IME1A
R/W: R R/W R/W R/W R/W R/W R/W R/W
Bit 6—Overflow Interrupt Enable (OVE1): Enables or disables interrupt requests by OVF1 in
TSR when OVF1 is set to 1.
Bit 6:
OVE1 Description
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Bit 5—Input Capture/Compare-Match Interrupt Enable (IME1F): Enables or disables

interrupt requests by IMF1F in TSR when IMF1F is set to 1.
Bit 5:
IME1F Description
0 IMI1F interrupt requested by IMF1F is disabled (Initial value)
1 IMI1F interrupt requested by IMF1F is enabled
Bit 4—Input Capture/Compare-Match Interrupt Enable (IME1E): Enables or disables

interrupt requests by IMF1E in TSR when IMF1E is set to 1.
Bit 4:
IME1E Description
0 IMI1E interrupt requested by IMF1E is disabled (Initial value)
1 IMI1E interrupt requested by IMF1E is enabled
Bit 3—Input Capture/Compare-Match Interrupt Enable (IME1D): Enables or disables

interrupt requests by IMF1D in TSR when IMF1D is set to 1.
Bit 3:
IME1D Description
0 IMI1D interrupt requested by IMF1D is disabled (Initial value)
1 IMI1D interrupt requested by IMF1D is enabled
Bit 2—Input Capture/Compare-Match Interrupt Enable (IME1C): Enables or disables

interrupt requests by IMF1C in TSR when IMF1C is set to 1.
Bit 2:
IME1C Description
0 IMI1C interrupt requested by IMF1C is disabled (Initial value)
1 IMI1C interrupt requested by IMF1C is enabled
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Bit 1—Input Capture/Compare-Match Interrupt Enable (IME1B): Enables or disables

interrupt requests by IMF1B in TSR when IMF1B is set to 1.
Bit 1:
IME1B Description
0 IMI1B interrupt requested by IMF1B is disabled (Initial value)
1 IMI1B interrupt requested by IMF1B is enabled
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME1A): Enables or disables

interrupt requests by IMF1A in TSR when IMF1A is set to 1.
Bit 0:
IME1A Description
0 IMI1A interrupt requested by IMF1A is disabled (Initial value)
1 IMI1A interrupt requested by IMF1A is enabled
Timer Interrupt Enable Register C (TIERC)
TIERC controls enabling/disabling of channel 2 input capture, compare-match, and overflow

interrupt requests.
Bit: 7 6 5 4 3 2 1 0
— — — — — OVE2 IME2B IME2A
Bit 2:
OVE2 Description
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Bit 1:
IME2B Description

Bit 0:
IME2A Description
Timer Interrupt Enable Registers DH and DL (TIERDH, TIERDL)
TIERDH controls enabling/disabling of channel 3 input capture, compare-match, and overflow

interrupt requests.
Bit: 7 6 5 4 3 2 1 0
— — — OVE3 IME3D IME3C IME3B IME3A
Bit 4:
OVE3 Description
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Bit 3:
IME3D Description

Bit 2:
IME3C Description

Bit 1:
IME3B Description

Bit 0:
IME3A Description
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TIERDL controls enabling/disabling of channel 4 and 5 input capture, compare-match, and

overflow interrupt requests.
Bit: 7 6 5 4 3 2 1 0
OVE4 IME4D IME4C IME4B IME4A OVE5 IME5B IME5A
Bit 7:
OVE4 Description

Bit 6:
IME4D Description

Bit 5:
IME4C Description
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Bit 4:
IME4B Description

Bit 3:
IME4A Description
Bit 2:
OVE5 Description

Bit 1:
IME5B Description
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Bit 0:
IME5A Description
Timer Interrupt Enable Register E (TIERE)
TIERE controls enabling/disabling of channel 6 to 9 cycle register compare interrupt requests.
Bit: 7 6 5 4 3 2 1 0
— CME6 — CME7 — CME8 — CME9
R/W: R R/W R R/W R R/W R R/W
Bit 6—Cycle Register Compare-Match Interrupt Enable (CME6): Enables or disables

interrupt requests by CMF6 in TSR when CMF6 is set to 1.
Bit 6:
CME6 Description
0 CMI6 interrupt requested by CMF6 is disabled (Initial value)
1 CMI6 interrupt requested by CMF6 is enabled

Bit 4:
OME7 Description
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Bit 2:
CME8 Description

Bit 0:
CME9 Description
Timer Interrupt Enable Register F (TIERF)
TIERF controls enabling/disabling of channel 10 one-shot pulse interrupt requests.
Bit: 7 6 5 4 3 2 1 0
OSE10H OSE10G OSE10F OSE10E OSE10D OSE10C OSE10B OSE10A
Bit 7—One-Shot Pulse Interrupt Enable (OSE10H): Enables or disables interrupt requests by
OSF10H in TSR when OSF10H is set to 1.
Bit 7:
OSE10H Description
0 OSI10H interrupt requested by OSF10H is disabled (Initial value)
1 OSI10H interrupt requested by OSF10H is enabled
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Bit 6—One-Shot Pulse Interrupt Enable (OSE10G): Enables or disables interrupt requests by
OSF10G in TSR when OSF10G is set to 1.
Bit 6:
OSE10G Description
0 OSI10G interrupt requested by OSF10G is disabled (Initial value)
1 OSI10G interrupt requested by OSF10G is enabled
Bit 5—One-Shot Pulse Interrupt Enable (OSE10F): Enables or disables interrupt requests by
OSF10F in TSR when OSF10F is set to 1.
Bit 5:
OSE10F Description
0 OSI10F interrupt requested by OSF10F is disabled (Initial value)
1 OSI10F interrupt requested by OSF10F is enabled
Bit 4—One-Shot Pulse Interrupt Enable (OSE10E): Enables or disables interrupt requests by
OSF10E in TSR when OSF10E is set to 1.
Bit 4:
OSE10E Description
0 OSI10E interrupt requested by OSF10E is disabled (Initial value)
1 OSI10E interrupt requested by OSF10E is enabled
Bit 3—One-Shot Pulse Interrupt Enable (OSE10D): Enables or disables interrupt requests by
OSF10D in TSR when OSF10D is set to 1.
Bit 3:
OSE10D Description
0 OSI10D interrupt requested by OSF10D is disabled (Initial value)
1 OSI10D interrupt requested by OSF10D is enabled
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Bit 2—One-Shot Pulse Interrupt Enable (OSE10C): Enables or disables interrupt requests by
OSF10C in TSR when OSF10C is set to 1.
Bit 2:
OSE10C Description
0 OSI10C interrupt requested by OSF10C is disabled (Initial value)
1 OSI10C interrupt requested by OSF10C is enabled
Bit 1—One-Shot Pulse Interrupt Enable (OSE10B): Enables or disables interrupt requests by
OSF10B in TSR when OSF10B is set to 1.
Bit 1:
OSE10B Description
0 OSI10B interrupt requested by OSF10B is disabled (Initial value)
1 OSI10B interrupt requested by OSF10B is enabled
Bit 0—One-Shot Pulse Interrupt Enable (OSE10A): Enables or disables interrupt requests by
OSF10A in TSR when OSF10A is set to 1.
Bit 0:
OSE10A Description
0 OSI10A interrupt requested by OSF10A is disabled (Initial value)
1 OSI10A interrupt requested by OSF10A is enabled
10.2.9 Interval Interrupt Request Register (ITVRR)
The interval interrupt request register (ITVRR) is an 8-bit register. The ATU has one ITVRR
register in channel 0.
Bit: 7 6 5 4 3 2 1 0
ITVAD3 ITVAD2 ITVAD1 ITVAD0 ITVE3 ITVE2 ITVE1 ITVE0
ITVRR is an 8-bit readable/writable register used for channel 0 interval interrupt bit setting.
ITVRR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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Bit 7—A/D Converter Interval Activation Bit 3 (ITVAD3): A/D converter activation setting bit
corresponding to bit 13 in free running counter 0L (TCNT0L). The rise of bit 13 in TCNT0L is
ANDed with ITVAD3, and the result is output to the A/D converter as an activation signal.
Bit 7:
ITVAD3 Description
0 A/D converter activation by ATU is disabled (Initial value)
1 A/D converter activation by ATU is enabled
corresponding to bit 12 in TCNT0L. The rise of bit 12 in TCNT0L is ANDed with ITVAD2, and
the result is output to the A/D converter as an activation signal.
Bit 6:
ITVAD2 Description
Bit 5:
ITVAD1 Description
Bit 4:
ITVAD0 Description
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Bit 3—Interval Interrupt Bit 3 (ITVE3): Interrupt controller (INTC) interval interrupt setting
bit corresponding to bit 13 in TCNT0L. The rise of bit 13 in TCNT0L is ANDed with ITVE3, the
result is stored in IIF3 in the timer status register (TSRAH), and an interrupt request is sent to
INTC.
Bit 3:
ITVE3 Description
0 ATU interval interrupt generation is disabled (Initial value)
1 Generation of interval interrupt to INTC is enabled
Bit 2—Interval Interrupt Bit 2 (ITVE2): INTC interval interrupt setting bit corresponding to bit
12 in TCNT0L. The rise of bit 12 in TCNT0L is ANDed with ITVE2, the result is stored in IIF2 in
TSRAH, and an interrupt request is sent to INTC.
Bit 2:
ITVE2 Description
Bit 1
ITVE1 Description
Bit 0:
ITVE0 Description
For details, see section 10.3.7, Interval Timer Operation.
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10.2.10 Down-Count Start Register (DSTR)
The down-count start register (DSTR) is an 8-bit register. The ATU has one DSTR register in
channel 10.
Bit: 7 6 5 4 3 2 1 0
DST10H DST10G DST10F DST10E DST10D DST10C DST10B DST10A
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only 1 can be written.
DSTR is an 8-bit readable/writable register that starts and stops the channel 10 down-counter
(DCNT).
When the one-shot pulse function is used, a value of 1 can be set in a DST10 bit at any time by the
user program. The DST10 bits are cleared to 0 automatically when the DCNT value underflows.
When the offset one-shot pulse function is used, a DST10 bit is automatically set to 1 when a
compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general
register (GR) while the corresponding timer connection register (TCNR) bit is set to 1. The bit is
automatically cleared to 0 when the DCNT value underflows. A value of 1 can be set in a DST10
bit at any time by the user program.
DSTR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse
Function.
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Bit 7—Down-Count Start Flag 10H (DST10H): Starts and stops down-counter 10H
(DCNT10H).
Bit 7:
DST10H Description
0 DCNT10H is halted (Initial value)
[Clearing condition]
When the DCNT10H value underflows
1 DCNT10H counts
[Setting conditions]
One-shot pulse function: Set by user program
Offset one-shot pulse function: Set on GR2B compare-match, or by user program
Bit 6—Down-Count Start Flag 10G (DST10G): Starts and stops down-counter 10G
(DCNT10G).
Bit 6:
DST10G Description
0 DCNT10G is halted (Initial value)
When the DCNT10G value underflows
1 DCNT10G counts
Offset one-shot pulse function: Set on GR2A compare-match, or by user program
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Bit 5—Down-Count Start Flag 10F (DST10F): Starts and stops down-counter 10F (DCNT10F).
Bit 5:
DST10F Description
0 DCNT10F is halted (Initial value)
When the DCNT10F value underflows
1 DCNT10F counts
Offset one-shot pulse function: Set on GR1F compare-match, or by user program
Bit 4—Down-Count Start Flag 10E (DST10E): Starts and stops down-counter 10E (DCNT10E).
Bit 4:
DST10E Description
0 DCNT10E is halted (Initial value)
When the DCNT10E value underflows
1 DCNT10E counts
Offset one-shot pulse function: Set on GR1E compare-match, or by user program
Bit 3—Down-Count Start Flag 10D (DST10D): Starts and stops down-counter 10D
(DCNT10D).
Bit 3:
DST10D Description
0 DCNT10D is halted (Initial value)
When the DCNT10D value underflows
1 DCNT10D counts
Offset one-shot pulse function: Set on GR1D compare-match, or by user program
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Bit 2—Down-Count Start Flag 10C (DST10C): Starts and stops down-counter 10C
(DCNT10C).
Bit 2:
DST10C Description
0 DCNT10C is halted (Initial value)
When the DCNT10C value underflows
1 DCNT10C counts
Offset one-shot pulse function: Set on GR1C compare-match, or by user program
Bit 1—Down-Count Start Flag 10B (DST10B): Starts and stops down-counter 10B
(DCNT10B).
Bit 1:
DST10B Description
0 DCNT10B is halted (Initial value)
When the DCNT10B value underflows
1 DCNT10B counts
Offset one-shot pulse function: Set on GR1B compare-match, or by user program
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Bit 0—Down-Count Start Flag 10A (DST10A): Starts and stops down-counter 10A
(DCNT10A).
Bit 0:
DST10A Description
0 DCNT10A is halted (Initial value)
When the DCNT10A value underflows
1 DCNT10A counts
Offset one-shot pulse function: Set on GR1A compare-match, or by user program
10.2.11 Timer Connection Register (TCNR)
The timer connection register (TCNR) is an 8-bit register. The ATU has one TCNR register in
channel 10.
Bit: 7 6 5 4 3 2 1 0
CN10H CN10G CN10F CN10E CN10D CN10C CN10B CN10A
TCNR is an 8-bit readable/writable register that enables or disables connection between the
channel 10 down-counter start register (DSTR) and channel 1 and 2 compare-match signals.
TCNR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Function.
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Bit 7—Connection Flag 10H (CN10H): Enables or disables connection between DST10H and
channel 2 compare-match signal OFF2B.
Bit 7:
CN10H Description
0 Connection between DST10H and OFF2B is disabled (Initial value)
1 Connection between DST10H and OFF2B is enabled
Bit 6—Connection Flag 10G (CN10G): Enables or disables connection between DST10G and
channel 2 compare-match signal OFF2A.
Bit 6:
CN10G Description
0 Connection between DST10G and OFF2A is disabled (Initial value)
1 Connection between DST10G and OFF2A is enabled
Bit 5—Connection Flag 10F (CN10F): Enables or disables connection between DST10F and
channel 1 compare-match signal OFF1F.
Bit 5:
CN10F Description
0 Connection between DST10F and OFF1F is disabled (Initial value)
1 Connection between DST10F and OFF1F is enabled
Bit 4—Connection Flag 10E (CN10E): Enables or disables connection between DST10E and
channel 1 compare-match signal OFF1E.
Bit 4:
CN10E Description
0 Connection between DST10E and OFF1E is disabled (Initial value)
1 Connection between DST10E and OFF1E is enabled
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Bit 3—Connection Flag 10D (CN10D): Enables or disables connection between DST10D and
channel 1 compare-match signal OFF1D.
Bit 3:
CN10D Description
0 Connection between DST10D and OFF1D is disabled (Initial value)
1 Connection between DST10D and OFF1D is enabled
Bit 2—Connection Flag 10C (CN10C): Enables or disables connection between DST10C and
channel 1 compare-match signal OFF1C.
Bit 2:
CN10C Description
0 Connection between DST10C and OFF1C is disabled (Initial value)
1 Connection between DST10C and OFF1C is enabled
Bit 1—Connection Flag 10B (CN10B): Enables or disables connection between DST10B and
channel 1 compare-match signal OFF1B.
Bit 1:
CN10B Description
0 Connection between DST10B and OFF1B is disabled (Initial value)
1 Connection between DST10B and OFF1B is enabled
Bit 0—Connection Flag 10A (CN10A): Enables or disables connection between DST10A and
channel 1 compare-match signal OFF1A.
Bit 0:
CN10A Description
0 Connection between DST10A and OFF1A is disabled (Initial value)
1 Connection between DST10A and OFF1A is enabled
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10.2.12 Free-Running Counters (TCNT)
The free-running counters (TCNT) are 32- or 16-bit up-counters. The ATU has ten TCNT
counters: one 32-bit TCNT in channel 0, and one 16-bit TCNT in each of channels 1 to 9.
Channel Abbreviation Description

0 TCNT0H, 32-bit up-counter (initial value H'00000000)
TCNT0L
1 TCNT1 16-bit up-counters (initial value H'0000)
2 TCNT2
3 TCNT3
4 TCNT4
5 TCNT5
6 TCNT6 16-bit up-counters (initial value H'0001)
7 TCNT7
8 TCNT8
9 TCNT9
Free-Running Counter 0H, L (TCNT0H, TCNT0L): Free-running counter 0 (comprising

TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. The
input clock is selected with prescaler register 1 (PSCR1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the
timer status register (TSR) is set to 1.
TCNT0 is connected to the CPU via an internal 16-bit bus, and can only be accessed by a
longword read or write. Word reads or writes cannot be used..
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TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and
software standby mode.
Free-Running Counters 1 to 5 (TCNT1 to TCNT5): Free-running counters 1 to 5 (TCNT1 to

TCNT5) are 16-bit readable/writable registers that count on an input clock. The input clock is
selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TCNT3 to TCNT5 can be cleared to H'0000 by a compare-match with the corresponding general
register (GR) or input capture (counter clear function).
When one of counters TCNT1 to TCNT5 overflows (from H'FFFF to H'0000), the overflow flag
(OVF) for the corresponding channel in the timer status register (TSR) is set to 1.
TCNT1 to TCNT5 are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
TCNT1 to TCNT5 are initialized to H'0000 by a power-on reset, and in hardware standby mode
and software standby mode.
Free-Running Counters 6 to 9 (TCNT6 to TCNT9): Free-running counters 6 to 9 (TCNT6 to

TCNT9) are 16-bit readable/writable registers that count on an input clock. The input clock is
selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TCNT6 to TCNT9 are connected to the CPU via an internal 16-bit bus, and can only be accessed
TCNT6 to TCNT9 are initialized to H'0001 by a power-on reset, and in hardware standby mode
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10.2.13 Input Capture Registers (ICR)
The input capture registers (ICR) are 32-bit registers. The ATU has four 32-bit ICR registers in
channel 0.

0 ICR0AH, ICR0AL, Dedicated input capture registers
ICR0BH, ICR0BL,
ICR0CH, ICR0CL,
ICR0DH, ICR0DL
Input capture registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The ICR registers are 32-bit read-only registers used exclusively for input capture.
These dedicated input capture registers store the TCNT0 value on detection of an input capture
signal from an external source. The corresponding TSR bit is set to 1 at this time. The input
capture signal edge to be detected is specified by timer I/O control register TIOR0A.
ICR0A and ICR0D can detect an external input capture (TIA0) or the channel 1 general register
(GR1A) compare-match signal (TRG1A) as an input capture signal.
The ICR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a longword read. Word reads cannot be used.
The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby
mode and software standby mode.
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10.2.14 General Registers (GR)
The general registers (GR) are 16-bit registers. The ATU has 18 general registers: six in channel 1,
two in channel 2, four each in channels 3 and 4, and two in channel 5.

1 GR1A, GR1B, Dual-purpose input capture and output compare registers
GR1C, GR1D,
GR1E, GR1F
2 GR2A, GR2B
3 GR3A, GR3B,
GR3C, GR3D
4 GR4A, GR4B,
GR4C, GR4D
5 GR5A, GR5B
General Registers 1A to 1F (GR1A to GR1F)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The GR registers are 16-bit readable/writable registers with both input capture and output compare
functions. Function switching is performed by means of the timer I/O control registers (TIOR).
When a general register is used for input capture, it stores the TCNT value on detection of an input
capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time.
The input capture signal edge to be detected is specified by the corresponding TIOR.
When a general register is used for output compare, the GR value and free-running counter
(TCNT) value are constantly compared, and when both values match, the IMF bit in the timer
status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR.
The GR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed by
a word read or write.
The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and
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General Registers 2A and 2B (GR2A and GR2B)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Channel 2 compare-match signals can be transmitted to the advanced pulse controller (APC). For
details, see section 11, Advanced Pulse Controller (APC).
General Registers 3A to 3D, 4A to 4D, 5A, and 5B (GR3A to GR3D, GR4A to GR4D, GR5A,
GR5B)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10.2.15 Down-Counters (DCNT)
The DCNT registers are 16-bit down-counters. The ATU has eight DCNT counters in channel 10.
Channel Abbreviation Description

10 DCNT10A, DCNT10B, Down-counter
DCNT10C, DCNT10D,
DCNT10E, DCNT10F,
DCNT10G, DCNT10H
Down-Counters 10A to 10H (DCNT10A to DCNT10H): Down-counters 10A to 10H

(DCNT10A to DCNT10H) are 16-bit readable/writable registers that count on an input clock. The
input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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When the one-shot pulse function is used, DCNT starts counting down when the corresponding
DSTR bit is set to 1 by the user program after the DCNT value has been set. When the DCNT
value underflows, the corresponding DSTR bit and DCNT are automatically cleared to 0, and the
count is stopped. At the same time, the corresponding channel 10 timer status register F (TSRF)
status flag is set to 1.
When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general
register (GR) when the corresponding timer connection register (TCNR) bit is 1, the
corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count
is started. When the DCNT value underflows, the corresponding DSTR bit and DCNT are
automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel
10 TSRF status flag is set to 1.
The DCNT counters are connected to the CPU via an internal 16-bit bus, and can only be accessed
The DCNT counters are initialized to H'0000 by a power-on reset, and in hardware standby mode
Function.
10.2.16 Offset Base Register (OSBR)
The offset base register (OSBR) is a 16-bit register. The ATU has one OSBR register in channel 1.

1 OSBR Dedicated input capture register with signal from channel 0
ICR0A as input trigger
Offset Base Register (OSBR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OSBR is a 16-bit read-only register used exclusively for input capture. OSBR uses the channel 0
ICR0A input capture register input as its trigger signal (TRG0A), and stores the TCNT1 value on
detection of the edge selected with bits 0 and 1 of TIORA.
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OSBR is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word
read.
OSBR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
For details, see sections 10.3.4, Input Capture Function.
10.2.17 Cycle Registers (CYLR)
The cycle registers (CYLR) are 16-bit registers. The ATU has four cycle registers, one each for
channels 6 to 9.

6 CYLR6 Cycle registers
7 CYLR7
8 CYLR8
9 CYLR9
Cycle Registers (CYLR6 to CYLR9)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage.
The CYLR value is constantly compared with the corresponding free-running counter (TCNT6 to
TCNT9) value, and when the two values match, the corresponding timer start register (TSR) bit
(CMF6 to CMF9) is set to 1, and the free-running counter (TCNT6 to TCNT9) is cleared. At the
same time, the buffer register (BFR) value is transferred to the duty register (DTR).
The CYLR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
For details of the CYLR, BFR, and DTR registers, see sections 10.3.9, PWM Timer Function.
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10.2.18 Buffer Registers (BFR)
The buffer registers (BFR) are 16-bit registers. The ATU has four buffer registers, one each for
channels 6 to 9.

6 BFR6 Buffer registers
7 BFR7
8 BFR8
9 BFR9
Buffer Registers (BFR6 to BFR9)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The BFR registers are 16-bit readable/writable registers that store the value to be transferred to the
duty register (DTR) in the event of a cycle register (CYLR) compare-match.
The BFR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
The BFR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
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10.2.19 Duty Registers (DTR)
The duty registers (DTR) are 16-bit registers. The ATU has four duty registers, one each for
channels 6 to 9.

6 DTR6 Duty registers
7 DTR7
8 DTR8
9 DTR9
Duty Registers (DTR6 to DTR9)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The DTR registers are 16-bit readable/writable registers used for PWM duty storage.
The DTR value is constantly compared with the corresponding free-running counter (TCNT6 to
TCNT9) value, and when the two values match, the corresponding channel output pin (TO6 to
TO9) goes to 0 output.
The DTR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
The DTR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
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10.3 Operation
10.3.1 Overview
The ATU has eleven timers of seven kinds in channels 0 to 10. It also has a built-in prescaler that
generates input clocks, and it is possible to generate or select internal clocks of the required
frequency independently of circuitry outside the ATU.
The operation of each channel and the prescaler is outlined below.
Channel 0 (32-Bit Dedicated Input Capture Timer): Channel 0 has a 32-bit free-running
counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-
counter that performs free-running operation. The four input capture registers (ICR0A to ICR0D)
can be used for input capture with input from the corresponding external signal input pin (TIA0 to
TID0) or output compare-match trigger input from channel 1 GR1A. Input pin (TIA0 to TID0) and
GR1A output compare-match trigger selection can be made by setting the trigger selection register
(TGSR).
Channel 0 also has an interval interrupt request register (ITVRR). When 1 is set in ITVE0 to
ITVE3 in ITVRR, an interval timer function can be used whereby an interrupt request can be sent
to the CPU when the corresponding bit (of bits 10 to 13) in TCNT0 changes to 1.
Channels 1 and 2: ATU channel 1 has a 16-bit free-running counter (TCNT1) and six 16-bit
general registers (GR1A to GR1F). TCNT1 is an up-counter that performs free-running operation.
The six general registers (GR1A to GR1F) can be used as input capture or output compare-match
registers using the corresponding external signal I/O pin (TIOA0 to TIOF0). Use as a one-shot
pulse offset function is also possible in combination with ATU channel 10 described below.
Channel 2 has a 16-bit free-running counter (TCNT2) and two 16-bit general registers (GR2A and
GR2B). Channel 2 can perform the same kind of operations as channel 1, the only difference being
in the number of general registers.
In addition, channel 1 has a 16-bit dedicated input capture register (OSBR) (not provided in
channel 2). The TIA0 external pin for input to channel 0 can also be used as the OSBR trigger
input, enabling use of a twin-capture function.
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Channels 3, 4, and 5: ATU channels 3 and 4 each have a 16-bit free-running counter (TCNT3,
TCNT4) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D). TCNT3 and
TCNT4 are up-counters that perform free-running operation. The four general registers (GR3A to
GR3D, GR4A to GR4D) each have corresponding external signal I/O pins (TIOA3 to TIOD3,
TIOA4 to TIOD4, TIOA5, TIOB5), and can be used as input capture or output compare-match
registers.
With channels 3 and 4, GR3D and GR4D are automatically designated as cycle registers by setting
PWM mode in the timer mode register (TMDR). In PWM mode, the counter is automatically
cleared by an output compare-match when the GR3D/GR4D value matches the TCNT3/TCNT4
value. Therefore, channels 3 and 4 can each be used as 3-channel PWM timers, with GR3A to
GR3C or GR4A to GR4C as the duty registers, and GR3D or GR4D as the cycle register.
Channel 5 has a 16-bit counter (TCNT5) and two 16-bit general registers (GR5A and GR5B).
Channel 5 can perform the same kind of operations as channel 3, the only difference being in the
number of general registers. In PWM mode, GR5A is designated as the duty register and GR5B as
the cycle register.
Channels 6, 7, 8, and 9 (Dedicated PWM Timers): ATU channels 6 to 9 each have a 16-bit free-
running counter (TCNT6 to TCNT9), 16-bit cycle register (CYLR6 to CYLR9), 16-bit duty
register DTR6 to DTR9), and buffer register (BFR6 to BFR9). Each of channels 6 to 9 also has an
external output pin (TO6 to TO9), and can be used as a buffered PWM timer. TCNT6 to TCNT9
are up-counters, and 0 is output to the corresponding external output pin when the TCNT value
matches the DTR value (when DTR ≠ H'0000). When the TCNT value matches the CYLR value
(when DTR ≠ H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and
the BFR value is transferred to DTR. Thus, the configuration of channels 6 to 9 enables them to
perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to
use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence.
The relationship between the pins and registers is shown in table 10.4.
When DTR ≥ CYLR, 1 is output continuously to the external output pin, giving a duty of 100%.
When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%.
Channel 10: ATU channel 10 has eight 16-bit down-counters (DCNT10A to DCNT10H), and
corresponding external output pins (TOA10 to TOH10). One-shot pulse output can be performed
by setting the DCNT value, starting DCNT operation in the user program and outputting 1 to the
external output pin, then halting the count operation when DCNT underflows, and outputting 0 to
the external output pin.
By coupling the operation with the channel 1 or channel 2 output compare function, offset one-
shot pulse output can be performed, whereby a one-shot pulse is generated by starting DCNT
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operation in response to a compare-match signal and outputting 1 to the external output pin, then
halting the count operation when DCNT underflows, and outputting 0.
Prescaler: The ATU has a dedicated prescaler with a 2-stage configuration. The first prescaler
stage includes a 5-bit prescaler register (PSCR1) that allows any scaling factor from 1 to 1/32 to
be specified. The first prescaler stage supplies a clock (φ') scaled from the φ clock second
prescaler stage and to channel 0. The second prescaler stage further scales the φ' clock supplied by
the first stage by a factor of the reciprocal of a power of 2 (the power being between 0 and 5) to
create six different clocks (φ") to be supplied to channels 1 to 10.
In channels 1 to 9, one of the six clocks (φ") created by scaling in the second prescaler stage can
be selected for use. In channel 10, two of the φ" clocks can be selected, with one clock input for
DCNT10A to DCNT10F, and the other for DCNT10G and DCNT10H.
10.3.2 Free-Running Count Operation and Cyclic Count Operation
The ATU channel 0 to 5 free-running counters (TCNT) are all designated as free-running counters
immediately after a reset, and start counting up as free-running counters when the corresponding
TSTR bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000;
channels 1 to 5: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1.
If the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time,
an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from
H'00000000 or H'0000.
If the timer start register (TSTR) value is cleared to 0 during the count, only the corresponding
free-running counter (TCNT) stops counting, and initialization of all TCNT counters and ATU
registers is not performed. The value at the point at which the TSTR value is cleared to 0
continues to be output externally.
Free-running counter operation is shown in figure 10.11.
(For channel 0: H'00000000 to H'FFFFFFFF)

H'FFFF
H'0000
Time
STR bit
in TSTR
OVF
Figure 10.11 Free-Running Counter Operation
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The ATU channel 6 to 9 counters (TCNT) all perform cyclic count operations unconditionally.
ATU channel 3 to 5 free-running counters (TCNT) perform synchronous count operation when 1
is set in bits T3PWM to T5PWM in the timer mode register (TMDR). These free-running counters
also perform synchronous count operation if the corresponding CCI bit in the timer I/O control
register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0. The relevant TCNT counter is
cleared by a compare-match of TCNT with GR3D or GR4D in channel 3 or 4, GR5B in channel 5,
or CYLR in channels 6 to 9 (counter clear function). In this way, cyclic counting is performed.
TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1
after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5B, or
CYLR value, the corresponding IMF3D, IMF4D, or IMF5B bit in timer status register D (TSRD)
(or the CMF bit in TSRE for channels 6 to 9) is set to 1, and TCNT is cleared to H'0000 (H'0001
for channels 6 to 9). If the corresponding TIER bit is set to 1 at this time, an interrupt request is
sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001
for channels 6 to 9).
Cyclic counter operation is shown in figure 10.12.
Counter cleared on compare-match
GR3D, GR4D,
GR5B, CYLR
H'0000
(channels 6 to 9: H'0001) Time
STR bit
in TSTR
IMF3D, IMF4D,
IMF5B, CMF
Figure 10.12 Cyclic Counter Operation
10.3.3 Output Compare-Match Function
In ATU channels 1 to 5, waveform output is performed by means of output compare-matches at

the corresponding external pin (TIOA1 to TIOF1, TIOA2, TIOB2, TIOA3 to TIOD3, TIO4A to
TIOD4, TIOA5, TIOB5) by making an output compare-match specification for the timer I/O
control registers (TIOR0 to TIOR5). A free-running counter (TCNT) starts counting up when 1 is
set in the timer status register (TSTR). When the desired number is set beforehand in a general
register (GR1A to GR1F, GR2A, GR2B, GR3A to GR3D, GR4A to GR4D, GR5A, GR5B), and
the counter value matches the corresponding general register, a waveform is output from the
corresponding external pin.
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External output value selection and counter clear function (channels 3 to 5 only) specification can
be performed with the timer I/O control register (TIOR). 1 output, 0 output, or toggle output can
be selected as the external output value. When the counter clear function is specified, the relevant
TCNT is cleared to H'0000 by a compare-match between the corresponding general register and
TCNT. If the appropriate interrupt enable register (TIER) setting is made, an interrupt request will
be sent to the CPU when an output compare-match occurs.
An example of free-running counter and output compare-match operation is shown in figure

10.13.
In the example in figure 10.13, ATU channel 1 is activated, and external output is performed with
1 output specified in the event of GR1A output compare-match, 0 output in the event of GR1B
output compare-match, and toggle output in the event of GR1C output compare-match.
Counter value
TCNT1
H'FFFF
GR1A
GR1B
GR1C
H'0000
Time
No change
No change
TIOA1
(1 output)
No change
TIOB1
(0 output)
TIOC1
(toggle output)
Figure 10.13 Example of Output Compare-Match Operation
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10.3.4 Input Capture Function
In ATU channels 0 to 5, when input capture is specified for the timer I/O control register (TIOR),
an input capture trigger signal is input from the corresponding external pin (TIA0 to TID0, TIOA1
to TIOF1, TIOA2, TIOB2, TIOA3 to TIOD3, TIO4A to TIOD4, TIOA5, TIOB5). A free-running
counter (TCNT) starts counting up when 1 is set in the timer start register (TSTR). When a trigger
signal is input from one of the above external pins, the counter value is transferred to the
corresponding register (ICR0AH/L to ICR0DH/L, OSBR, GR1A to GR1F, GR2A, GR2B, GR3A
to GR3D, GR4A to GR4D, GR5A, GR5B).
The detected edge of the external trigger input data can be selected by making a setting in the
timer I/O control register (TIOR). Rising-edge, falling-edge, or both-edge detection can be
selected. A CPU interrupt request can be issued if the appropriate setting is made in the interrupt
enable register (TIER).
An example of free-running counter and input capture operation is shown in figure 10.14.
In the example in figure 10.14, ATU channel 1 is activated, and input capture operation is
performed with rising-edge detection specified for TIOA1 and both-edge detection for TIOB1.
Counter value
TCNT1 H'FFFF
Data 1
Data 2
Data 3
Data 4
H'0000
(32 bits in case of channel 0) Time
STR1
TIOA1
TIOB1
GR1A H'FFFF Data 1 Data 2

(32 bits in case of channel 0)
GR1B
H'FFFF Data 3 Data 4
(32 bits in case of channel 0)
Figure 10.14 Example of Input Capture Operation
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10.3.5 One-Shot Pulse Function
ATU channel 10 has eight down-counters (DCNT10A to DCNT10H) and corresponding external
pins (TOA10 to TOH10) which can be used as one-shot pulse output pins.
To generate a one-shot pulse, the one-shot pulse width is set in the down-counter (DCNT), and the
corresponding down-count start register (DSTR) bit (DST10A to DST10H) is set to 1 by the user
program to start the down-count using the clock specified in the timer control register (TCR).
When the down-count starts, 1 is output to the corresponding external pin (TOA10 to TOH10). If
the DCNT value is 0, however, the external pin remains at 0 even if DST is set to 1; in this case, a
one-shot pulse is not generated, but an interrupt is requested. When the DCNT value underflows,
DCNT and the relevant DST bit are automatically cleared to 0, and DCNT stops counting. At the
same time, 0 is output to the corresponding external pin.
By making the appropriate setting in timer interrupt enable register F (TIERF), an interrupt request
can be sent to the CPU when the corresponding down-counter (DCNT10A to DCNT10H) reaches
0.
It is possible to forcibly output 0 to the output pin during the down-count by clearing DCNT to 0
(since DST cannot be cleared to 0 by the user program). In this case, DCNT and the relevant DST
bit are automatically cleared to 0 when the DCNT value underflows, and DCNT stops counting.
At the same time, 0 is output to the corresponding external pin.
An example of one-shot pulse operation is shown in figure 10.15.
In the example in figure 10.15, one-shot pulse widths dataA and dataB are set for DCNT10A by
the user program, and one-shot pulse output is performed by writing 1 to DST10A.
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H'FFFF
Down-count value
Data B DCNT10A
Data A
H'0000
Time
Write to DCNT10A (Data A) DST10A= ‘1’ (Data B) DST10A = ‘1’
and DST10A by
user program
DST10A
Automatically
cleared to 0
TOA10 One-shot One-shot pulse
pulse
Figure 10.15 Example of One-Shot Pulse Operation
10.3.6 Offset One-Shot Pulse Function
The ATU channel 10 down-counters (DCNT) can be coupled with compare-matches between the
channel 1 and 2 free-running counters (TCNT) and general registers (GR) by setting bits CN10A
to CN10H to 1 in the timer connection register (TCNR). At the same time, the external pins
(TOA10 to TOH10) corresponding to the eight channel 10 down-counters, DCNT10A to
DCNT10H, can be used as offset one-shot pulse output pins.
Setting 1 in timer start register (TSTR) bit STR1 or STR2 starts the up-count by TCNT1 or
TCNT2 in channel 1 or 2. When TCNT1 or TCNT2 matches the general register (GR!A to GR1F,
GR2A, GR2B) value, the down-count start register (DSTR) bit corresponding to bit CN10A to
CN10H in TCNR corresponding to GR automatically changes to 1, and the down-count is started.
When the down-count starts, 1 is output to the corresponding external pin (TOA10 to TOH10). If
the DCNT value is 0, however, the external pin remains at 0 even if DST is set to 1; in this case, a
one-shot pulse is not generated, but an interrupt is requested. When the DCNT value underflows,
DCNT and the relevant DST bit are automatically cleared to 0, and DCNT stops counting. At the
same time, 0 is output to the corresponding external pin. As long as a count value is set in DCNT
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from the CPU before the next match with the general register, one-shot pulses can be output
consecutively. DSTR cannot be rewritten while the offset one-shot pulse function is being used.
By making the appropriate setting in timer interrupt enable register F (TIERF), an interrupt request
can be sent to the CPU one clock cycle after the corresponding down-counter (DCNT10A to
DCNT10H) reaches 0.
It is possible to forcibly output 0 to the output pin during the down-count by clearing DCNT to 0
(since DST cannot be cleared to 0 by the user program). In this case, DCNT and the relevant DST
bit are automatically cleared to 0 when the DCNT value underflows, and DCNT stops counting.
At the same time, 0 is output to the corresponding external pin.
An example of offset one-shot pulse operation is shown in figure 10.16.
In the example in figure 10.16, the ATU channel 1 free-running counter is started, and offset one-
shot pulse output is performed by means of GR1A output compare-match and the DCNT10A
channel 10 down-counter corresponding to GR1A.
Counter value
TCNT1
H'FFFF
GR1A
H'0000
Time
Write to GR1A
Write to DCNT10A (dataA) (dataB)

by user program
H'FFFF
data B
data A
Down-count value
DCNT10A
H'0000
Offset Offset
One- One-shot
TOA10 shot pulse
pulse
Figure 10.16 Example of Offset One-Shot Pulse Operation
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10.3.7 Interval Timer Operation
The 8 bits of the interval interrupt request register (ITVRR) are connected to bits 10 to 13 of
TCNT0L in the channel 0 32-bit free-running counter (TCNT0H, TCNT0L). The upper 4 bits
(ITVAD3 to ITVAD0) are used to start A/D converter sampling, and the lower 4 bits (ITVE3 to
ITVE0) generate signals to the interrupt controller (INTC).
For A/D converter activation, an edge sensor is provided for bits 10 to 13 of TCNT0L, and A/D
channel 0 sampling is started when the corresponding bit in TCNT0L changes to 1 as a result of
setting 1 in one of the upper 4 bits (ITVAD3 to ITVAD0) of ITVRR.
For generation of interrupt signals to the INTC, after detection of bits 10 to 13 of TCNT0L by the
edge sensor, when the corresponding bit in TCNT0L changes to 1 as a result of setting 1 in one of
the lower 4 bits (ITVE3 to ITVE0) of ITVRR after detection of bits 10 to 13 of TCNT0L by the
edge sensor, the corresponding flag (IIF0 to IIF3) in timer status register TSRAH is set to 1 and an
interrupt request is sent to INTC. The above four interrupt sources have only one interrupt vector
address, and therefore when more than one of bits ITVE3 to ITVE0 in ITVRR is specified, control
branches to the same vector when any TCNT0 bit corresponding to one of the specified bits
changes to 1.
To suppress interrupts to INTC, or to prevent A/D sampling from being started, all ITVRR bits
should be cleared to 0.
A schematic diagram of the interval timer is shown in figure 10.17.
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ATU
13 12 11 10 bit TCNT0L
(32 bit FRT)
Edge sensor
Upper 4 bits Lower 4 bits

of ITVRR of ITVRR
TRSAH
(status flags)
A/D converter INTC

activation signal
Figure 10.17 Schematic Diagram of Interval Timer
An example of TCNT0 and bit detection operation is shown in figure 10.18.
In the example in figure 10.18, free-running counter 0 (TCNT0) is started by setting 1 in ITVE1 in
ITVRR.
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H'FFFFFFFF
Counter value
H'FFFFF800
TCNT0
H'00002800
H'00001800
H'00000800
H'00000000
Time
CPU 0 write
to IIF1by user
program
Interrupt status
flag (IIF1)
Figure 10.18 Example of Interval Timer Operation
10.3.8 Twin-Capture Function
The ATU’s channel 0 ICR0A and channel 1 OSBR can be made to perform input capture in
response to the same trigger by means of a setting in timer I/O control register TIOR0A. When the
ATU channel 0 counter (TCNT0) and channel 1 counter (TCNT1) are started by a setting in the
timer status register (TSR), and a trigger signal is input from the ICR0A input capture input pin
(TIA0), the TCNT0 value can be transferred to ICR0A, and the TCNT1 value to OSBR. Rising-
edge, falling-edge, or both-edge detection can be selected for the TIA0 trigger input pin.
By making the appropriate setting in the timer interrupt enable register (TIER), an interrupt
request can be sent to the CPU when input capture occurs.
An example of twin-capture operation is shown in figure 10.19.
In the example in figure 10.19, twin-capture is started using a both-edge detection specification.
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TIA0
H'FFFFFFFF
Channel 0
counter Data X1
value Data X2
TCNT0
H'00000000
Time
H'FFFF
Channel 1 Data Y1
counter
value
TCNT1 Data Y2
H'0000
Time
ICR0AH/L Data X1 Data X2
OSBR Data Y1 Data Y2
Figure 10.19 Example of Twin-Capture Operation
10.3.9 PWM Timer Function
PWM mode is set unconditionally for ATU channels 6 to 9, and also by setting 1 in the
corresponding bit (T3PWM to T5PWM) of the ATU channel 3 to 5 timer mode registers (TMDR),
enabling the counters to be used as PWM timers.
In ATU channels 6 to 9, when the free-running counter (TCNT) is started, 0 is output to the
external pin if the corresponding duty register (DTR6 to DTR9) value is 0, and 1 is output to the
external pin if the DTR6 to DTR9 value is 1. When the TCNT count matches the DTR6 to DTR9
value after the up-count is started, 0 is output to the corresponding external pin (unless 100% duty
has been set, in which case 1 is output). When the continuing TCNT up-count matches the cycle
register (CYLR) value, 1 is output to the corresponding external pin (unless 0% duty has been set,
in which case 0 is output). At the same time, the counter is cleared. 0% duty is specified by setting
DTR to H'0000, and 100% duty by setting DTR ≥ CYLR.
The relationship between pins and registers is shown in table 10.4. Details of the buffer function
for ATU channels 6 to 9 are given in section 10.3.10, Buffer Function.
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An example of channel 6 to 9 PWM operation is shown in figure 10.20.
In the example in figure 10.20, H'F000 is set in CYLR6 to CYLR8, H'F000 in DTR6, H'7000 in
DTR7, and H'0000 in DTR8, ATU channels 6 to 8 are activated simultaneously, and waveform
output (100%, 50%, 0%) is generated on external pins TO6 to TO8.
Counter value
TCNT6 to TCNT8
H'FFFF
CYLR6–8,
DTR6 (H'F000)
DTR7 (H'7000)
DTR8 (H'0000)
Time
No change No change
TO6
TO7
No change No change No change
TO8 (‘0’)
Figure 10.20 Example of PWM Waveform Output Operation
In ATU channels 3 to 5, when PWM mode is set, corresponding general register GR3D, GR4D,
and GR5B function as cycle registers, and GR3A to GR3C, GR4A to GR4C, and GR5A, as duty
registers. At the same time, external pins TIOA3 to TIOC3, TIOA4 to TIOC4, and TIOA5
function as PWM waveform output pins. In channels 3 and 4, there are four duty registers for one
cycle register, and the cycle is the same for all the corresponding output pins.
In PWM mode, output of a 0% duty waveform cannot be set for ATU channels 3 to 5. If 0% duty
is required, channels 6 to 9 should be used. Although constant 1 output is performed if 100% duty
is set (GR3A, B, C ≥ GR3D, GR4A, B, C ≥ GR4D or GR5A ≥ GR5B), use of channels 6 to 9 is
also recommended if 100% duty is to be set.
An example of channel 3 to 5 PWM operation is shown in figure 10.21.
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In the example in figure 10.21, H'F000 is set in GR3D, H'F000 in GR3A, H'7000 in GR3B, and
H'0000 in GR3C, ATU channel 3 is activated, and waveform output is generated on external pins
TIOA3 to TIOD3.
Counter value
TCNT3
H'FFFF
GR3D,
GR3A (H'F000)
GR3B (H'7000)
GR3C (H'0000)
Time
No change No change
TIOA3
TIOB3
TIOC3
Figure 10.21 Example of PWM Waveform Output Operation
10.3.10 Buffer Function
ATU channels 6 to 9 each have a free-running counter (TCNT6 to TCNT9), cycle register
(CYLR6 to CYLR9), duty register (DTR6 to DTR9), and buffer register (BFR6 to BFR9). PWM
waveform output by means of counter matches with the cycle register and duty register is
performed as described in section 10.3.9, PWM Timer Function. However, channels 6 to 9 also
include a buffer function, whereby the corresponding buffer register value is transferred to the
duty register on a match between the cycle register and counter. If the corresponding bit in timer
interrupt enable register E (TIERE) is set to 1, an interrupt request can be sent to the CPU when
the cycle register value and counter value match.
An example of buffered PWM operation is shown in figure 10.22.
In the example in figure 10.22, H'4000 is set in BFR6, H'A000 in DTR6, and H'F000 in CYLR6,
and after the PWM operation is started, the BFR6 value is changed to H'B000 and H'7000 during
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the operation, so that a waveform with varying duty cycles is output continuously on external pin
TO6.
Counter value Duty register value

TCNT6 DTR6
H'FFFF
CYLR6 (H'F000)
DTR6 (H'A000)
BFR6 (H'4000)
H'0000
Time
STR6
BFR6 H'4000 H'B000 H'7000 H'7000
DTR6 H'A000 H'4000 H'B000 H'7000
TO6
Figure 10.22 Example of Buffered PWM Waveform Output Operation
10.3.11 One-Shot Pulse Function Pulse Output Timing
There is a maximum delay of one DCNT input clock count clock cycle between setting of the
down-count start flag (DST) and the start of the DCNT down-count. One-shot pulse output also
varies by a delay of one CK state, but there is no error in the one-shot pulse output pulse width.
Figure 10.23 shows an example with a pulse width setting of H'0005.
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CK
1 written
to DST
Internal write signal
DCNT start delay
Down-count start
flag DST
DCNT input clock
DCNT H'0005 H'0004 H'0003 H'0002 H'0001 H'0000 H'0000
One-shot pulse
output
1 state 1 state
Figure 10.23 One-Shot Pulse Function Pulse Output Timing
10.3.12 Offset One-Shot Pulse Function Pulse Output Timing
There is a delay of one CK state between the occurrence of a compare-match between the channel
1 or 2 free-running counter (TCNT) and a general register (GR), and setting of the channel 10
down-count start flag (DST) is set. In addition, there is a maximum delay of one DCNT input
clock count clock cycle between setting of the DST flag and the start of the DCNT count. One-
shot pulse output varies by a further delay of one CK state, but there is no error in the one-shot
pulse output pulse width.
Figure 10.24 shows an example with an offset width setting of H'0100, and a pulse width setting
of H'0003.
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1 state
CK
TCNT input clock
TCNT H'0100 H'0101 H'0102 H'0103
GR H'0100
Compare-match
signal
Down-count start
flag DST DCNT start
delay
DCNT input clock
DCNT H'0003 H'0002 H'0001 H'0000 H'0000
One-shot pulse
output
1 state 1 state
Figure 10.24 Offset One-Shot Pulse Function Pulse Output Timing
10.3.13 Channel 3 to 5 PWM Output Waveform Actual Cycle and Actual Duty
In channel 3 to 5 PWM mode, the actual cycle corresponding to the cycle register value is one
TCNT input clock cycle greater than the cycle register value, and the actual cycle corresponding to
the duty register value is one TCNT input clock cycle greater than the duty register value. This
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phenomenon is due to the fact that the value is H'0000 when the free-running counter (TCNT3 to
TCNT5) is cleared.
The timing in this case is shown in figure 10.25. In this example, H'0005 is set as the cycle register
value and H'0000 as the duty register value, the actual cycle value is H'0006, and the actual duty
value is H'0001.
Actual cycle
TCNT 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003
TCNT input clock
(duty)
(cycle)
Counter clear signal
Actual duty
PWM output
Figure 10.25 Channel 3 to 5 PWM Output Waveform and Counter Operation
10.3.14 Channel 3 to 5 PWM Output Waveform Settings and Interrupt Handling Times
Since channels 3 to 5 have no function for rewriting a general register (GR) simultaneously with
compare-match occurrence (buffer function) in PWM mode or when the counter clear function is
set, it may not be possible to generate waveform output with a resolution that exceeds the time
required to rewrite GR after a compare-match.
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The timing in this case is shown in figure 10.26. In this example, channel 5 is set to PWM mode,
H'00FE is set in GR5A and H'00FF in GR5B, and free-running counter 5 (TCNT5) is started.
When H'0000 (0% duty) is set in GR5A in the interrupt handling routine after a compare-match
with GR5B, a 0% duty waveform cannot be output immediately since the TCNT5 value is already
H'0002, and so 1 continues to be output until the subsequent compare-match with GR5A.
TCNT5 00FA 00FB 00FC 00FD 00FE 00FF 0000 0001 0002 00FE 00FF 0000 0001 0002 0003
TCNT input clock
Time from compare-match

to GR5A rewrite
GR5A 00FF 0000
GR5B 00FF
Interrupt status flag
GR5A write signal

generated in interrupt
handling routine
PWM output
Period during which

PWM output is 1 although
duty value is 0
Figure 10.26 Channel 5 Waveform when Duty Changes from 100% to 0%
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10.3.15 PWM Output Operation at Start of Channel 3 to 5 Counter
In channel 3 to 5 PWM mode, free-running counter (TCNT3 to TCNT5) PWM output is not 1 in
the first cycle when the counter is started. However, the interrupt status flag is set to 1 when there
is a match with the duty register value in the first cycle.
The timing in this case is shown in figure 10.27. In this example, H'0003 is set as the duty register
value, and H'0005 as the cycle register value.
Cycle
TCNT 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003
TCNT input clock
Counter start signal
Duty
PWM output
1st cycle 2nd cycle 3rd cycle
Figure 10.27 Channel 3 to 5 PWM Output Waveform
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10.3.16 PWM Output Operation at Start of Channel 6 to 9 Counter
In channels 6 to 9, the maximum TCNT input clock error occurs between the cycle register value
or duty register value and the actual output waveform in the waveform of the first cycle when the
free-running counter starts (there is no error in the waveform in the second and subsequent cycles).
This is because the counter start signal from the CPU cannot be determined in synchronization
with the TCNT input clock timing. To output a waveform with no error in the waveform of the
first cycle, the initial value of the duty register (DTR) should be set to H'0000 (in this case,
however, the interrupt status flag will be set when 1 is first output).
The timing in this case is shown in figure 10.28. In this example, H'0003 is set as the duty register
value, and H'0005 as the cycle register value.
Cycle
TCNT 0001 0002 0003 0004 0005 0001 0002 0003 0004 0005 0001 0002 0003 0004
TCNT input clock
Counter start signal
Duty
PWM output
Error with respect

to counter start
1st cycle 2nd cycle 3rd cycle
Figure 10.28 Channel 6 to 9 PWM Output Waveform
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10.3.17 Timing of Buffer Register (BFR) Write and Transfer by Buffer Function
In channels 6 to 9, if the BFR value is transferred to the duty register (DTR) by a compare-match
with the cycle register (CYLR) in the T2 state during a write cycle from the CPU to the buffer
register (BFR), the value prior to the CPU write to BFR is transferred to DTR.
The timing in this case is shown in figure 10.29. In this example, a CYLR compare-match and a
write of H'AAAA to BFR occur simultaneously when the BFR value is H'5555.
BFR write cycle

T1 T2
CK
Address BFR address
H'AAAA
written
Internal write signal to BFR
BFR H'5555 H'AAAA
DTR H'5555
Figure 10.29 Contention between Buffer Register (BFR) Write and Transfer by Buffer
Function
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10.4 Interrupts
The ATU has 44 interrupt sources of five kinds: input capture interrupts, compare-match
interrupts, overflow interrupts, underflow interrupts, and interval interrupts.
10.4.1 Status Flag Setting Timing
IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the
IMF bit (ICF bit in case of channel 0) is set to 1 in the timer status register (TSR), and the TCNT
value is simultaneously transferred to the corresponding GR (ICR in the case of channel 0).
The timing in this case is shown in figure 10.30.
In the example in figure 10.30, a signal is input from an external pin, and input capture is
performed on detection of a rising edge.
CK
tTICS (input capture input setup time)
Input capture input
Internal input capture

signal
TCNT N
GR (ICR) N

IMF (ICF)
Interrupt request signal

IMI (ICI)
Figure 10.30 IMF (ICF) Setting Timing in Input Capture
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IMF (ICF) Setting Timing in Compare-Match: The IMF bit (CMF bit in case of channels 6 to
9) is set to 1 in the timer status register (TSR) by the compare-match signal generated when the
general register (GR) or cycle register (CYLR) value matches the timer counter (TCNT) value.
The compare-match signal is generated in the last state of the match (when the matched TCNT
count value is updated).
CK
TCNT input clock
TCNT N N+1
GR(CYLR) N

IMF (CMF)

IMI (CMI)
Figure 10.31 IMF (CMF) Setting Timing in Compare-Match
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OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from
H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR).
CK
TCNT input clock
TCNT H'FFFF H'0000
Overflow signal

OVF

OVI
Figure 10.32 OVF Setting Timing in Overflow
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OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to
H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when
the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is
H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input.
CK
DCNT input clock
DCNT H'0001 H'0000 H'0000
Underflow signal

OSF

OSI
Figure 10.33 OSF Setting Timing in Underflow
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Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10–13
in free-running counter TCNT0L with bit ITVE0–ITVE3 in the interval interrupt request register
(ITVRR), the IIF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 10.34. TCNT0 value N in the figure is the counter value
when TCNT0L bit 10–13 changes to 1. (For example, N = H'00000400 in the case of bit 10,
H'00000800 in the case of bit 11, etc.)
CK
TCNT input clock
TCNT0 N–1 N
Internal interval signal

IIF
Figure 10.34 Timing of IIF Setting Timing by Interval Timer
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10.4.2 Interrupt Status Flag Clearing
Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag
after reading it while set to 1.
The procedure and timing in this case are shown in figure 10.35.
TSR write cycle

T1 T2
Start
CK
Read 1 from TSR

Address TSR address
Write 0 to TSR Internal write

signal

IMF, ICF, CMF,
Interrupt status
OVF, OSF, IIF
flag cleared
Interrupt request
signal
Figure 10.35 Procedure and Timing for Clearing by CPU Program
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Clearing by DMAC: The interrupt status flag (ICF0B, CMF6) is cleared automatically during
data transfer when the DMAC is activated by input capture (ICR0B) or compare-match (CYLR6).
The procedure and timing in this case are shown in figure 10.36.
CK
Start
Clear request signal
from DMAC
Activate DMAC Interrupt status

flag clear signal

ICF0B, CMF6
Interrupt status
flag cleared during
data transfer Interrupt request
signal
Figure 10.36 Procedure and Timing for Clearing by DMAC
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10.5 CPU Interface
10.5.1 Registers Requiring 32-Bit Access
Free-running counter 0 (TCNT0) and input capture registers 0A to 0D (ICR0A to ICR0D) are 32-
bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or
write (read only, in the case of ICR0A to ICR0D) is automatically divided into two 16-bit
accesses.
Figure 10.37 shows a read from TCNT0, and figure 10.38 a write to TCNT0.
When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal
data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer
register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer
register is output to the internal data bus.
When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer
register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time,
the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write.
The above method performs simultaneous reading and simultaneous writing of 32-bit data,
preventing contention with an up-count.
1st read operation

Internal data bus
H Module data bus H
Bus
CPU interface TCNT0H
L
Internal
TCNT0L
buffer register
Module data
bus
Internal data bus 2nd read operation

L
Bus Module data
CPU TCNT0H
interface bus
L Internal
TCNT0L
buffer register
Figure 10.37 Read from TCNT0
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1st write operation

Internal data bus
H Bus H Internal buffer
CPU interface TCNT0H
register
Module data
bus TCNT0L
Internal data bus 2nd write operation Module

L L data bus
Bus Internal buffer H
CPU TCNT0H
interface register
TCNT0L
Module data bus
Figure 10.38 Write to TCNT0
Free-running counters 1 to 9 (TCNT1 to TCNT9), the general registers (GR), down-counters

(DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty
registers (DTR), and timer start register (TSTR) are 16-bit registers. These registers are connected
to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of
OSBR) a word at a time.
Figure 10.39 shows the operation when performing a word read or write access to TCNT1.
Internal data bus Module data bus

Bus
CPU TCNT1
interface
Figure 10.39 TCNT1 Read/Write Operation
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10.5.3 8-Bit or 16-Bit Accessible Registers
The timer control register (TCR), timer I/O control registers 1 to 5 (TIOR1 to TIOR5), and the
timer connection register (TCNR) are 8-bit registers. These registers are connected to the upper 8
bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time.
In addition, a pair of 8-bit registers for which only the least significant bit of the address is
different, such as timer I/O control register 4A (TIOR4A) and timer I/O control register 4B
(TIOR4B), can be read or written in combination a word at a time.
Figures 10.40 and 10.41 show the operation when performing individual byte read or write
accesses to TIOR4A and TIOR4B. Figure 10.42 shows the operation when performing a word
read or write access to TIOR4A and TIOR4B simultaneously.

Bus TIOR4A
CPU
interface TIOR4B
Only upper 8 bits used Only upper 8 bits used
Figure 10.40 Byte Read/Write Access to TIOR4A

Bus TIOR4A
CPU
interface TIOR4B
Only lower 8 bits used Only lower 8 bits used
Figure 10.41 Byte Read/Write Access to TIOR4B

Bus TIOR4A
CPU
interface TIOR4B
Figure 10.42 Word Read/Write Access to TIOR4A and TIOR4B
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The timer mode register (TMOR), prescaler register 1 (PSCR1), timer I/O control register 0
(TIOR0), the trigger selection register (TGSR), interval interrupt request register (ITVRR), timer
status register (TSR), timer interrupt enable register (TIER), and down-count start register (DSTR)
are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the internal
16-bit data bus, and can be read or written a byte at a time.
Figures 10.43 and 10.44 show the operation when performing individual byte read or write
accesses to TGSR and TIOR0A.

Bus TGSR
CPU
interface
Only upper 8 bits used Only upper 8 bits used
Figure 10.43 Byte Read/Write Access to TGSR

Bus
CPU
interface TIOR0A
Only lower 8 bits used Only lower 8 bits used
Figure 10.44 Byte Read/Write Access to TIORA
10.6 Sample Setup Procedures

Sample setup procedures for activating the various ATU functions are shown below.
Sample Setup Procedure for Input Capture: An example of the setup procedure for input
capture is shown in figure 10.45.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1).

For channels 1 to 5, also select the second-stage counter clock φ" with the CKSEL bit in the
timer control register (TCR). When selecting an external clock, also select the external clock
edge type with the CKEG bit in TCR.
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
port for signal input as the input capture trigger, to ATU input capture input.
3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the
timer I/O control register (TIOR).
If necessary, an interrupt request can be sent to the CPU on input capture by making the
appropriate setting in the interrupt enable register (TIER).
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4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT) for the relevant channel.
Note: When channel 0 input capture (ICR0A) occurs, the TCNT1 value is always transferred to
the offset base register (OSBR), irrespective of channel 1 free-running counter (TCNT1)
activation.
For details, see section 10.3.8, Twin-Capture Function.
Start
Select counter clock 1
Set port-ATU connection 2
Set input waveform edge

3
detection
Start counter 4
Input capture operation
Figure 10.45 Sample Setup Procedure for Input Capture
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Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of

the setup procedure for waveform output by output compare-match is shown in figure 10.46.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1), and select the second-stage
counter clock φ" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, also select the external clock edge type with the CKEG bit in TCR.
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute for the port.
3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control
register (TIOR). If necessary, an interrupt request can be sent to the CPU on output compare-
match by making the appropriate setting in the interrupt enable register (TIER).
4. Set the timing for compare-match generation in the ATU general register (GR) corresponding
to the port set in 2.
counter (TCNT). Waveform output is performed from the relevant port when the TCNT value
and GR value match.
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Start
Select waveform output

3
mode
Set output timing 4
Start counter 5
Waveform output
Figure 10.46 Sample Setup Procedure for Waveform Output by Output Compare-Match
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Sample Setup Procedure for ATU Channel 0 Input Capture Triggered by Channel 1
Compare-Match: An example of the setup procedure for ATU channel 0 input capture triggered
by channel 1 compare-match is shown in figure 10.47.
1. Set the channel 1 timer I/O control register (TIOR1A) to output compare-match, and set the
timing for compare-match generation in the channel 1 general register (GR1A).
2. Set bits TRG1A and TRG1D to 1 in the trigger selection register (TGSR).
3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 free-
running counter (TCNT1). On compare-match between TCNT1 and GR1A, the compare-
match signal is transmitted to channel 0 as the channel 0 TIA0 and TID0 input capture signal.
Start
Set compare-match 1
Set TGSR 2
Start counter 3
Signal transmission
Figure 10.47 Sample Setup Procedure for Compare-Match Signal Transmission
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Sample Setup Procedure for One-Shot pulse Output: An example of the setup procedure for
one-shot pulse output is shown in figure 10.48.
counter clock φ" with the CKSEL bit in timer control register TCR10.
2. Set the port C control register (PCCR) corresponding to the waveform output port to ATU one-
shot pulse output. Also set the corresponding bit to 1 in the port C IO register (PCIOR) to
specify the output attribute.
3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2).
If necessary, an interrupt request can be sent to the CPU when the down-counter underflows by
making the appropriate setting in the interrupt enable register (TIERF).
4. Set the corresponding bit (DST10A to DST10H) to 1 in the down-count start register (DSTR)
to start the down-counter (DCNT).
Start
Set pulse width 3
Start down-count 4
One-shot pulse output
Figure 10.48 Sample Setup Procedure for One-Shot Pulse Output
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Sample Setup Procedure for Offset One-Shot Pulse Output: An example of the setup
procedure for offset one-shot pulse output is shown in figure 10.49.
counter clock φ" with the CKSEL bit in the timer control register (TCR1, TCR2, TCR10).
2. Set the port C control register (PCCR) corresponding to the waveform output port to ATU one-
shot pulse output. Also set the corresponding bit to 1 in the port C IO register (PCIOR) to
specify the output attribute.
3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2).
If necessary, an interrupt request can be sent to the CPU when the down-counter underflows by
making the appropriate setting in the interrupt enable register (TIERF).
4. Set the offset width in the channel 1 or 2 general register (GR1A–GR1F, GR2A, GR2B)
connected to the down-counter (DCNT) corresponding to the port set in (2).
5. Set the CN10A–CN10H bit in the timer connection register (TCNR) corresponding to the port
set in (2) to 1.
6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-
running counter (TCNT1, TCNT2). When the TCNT value and GR value match, the
corresponding DCNT starts counting down, and one-shot pulse output is performed.
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Start
Set pulse width 3
Set offset width 4
Set offset operation 5
Start count 6
Offset one-shot pulse output
Figure 10.49 Sample Setup Procedure for Offset One-Shot Pulse Output
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Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for
interval timer operation is shown in figure 10.50.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1).

2. Set the ITVE0–ITVE3 bit to be used in the interval interrupt request register (ITVRR) to 1. An
interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the
channel 0 free-running counter (TCNT0).
To start A/D converter sampling, set the ITVAD0–ITVAD3 bit to be used in ITVRR to 1.
3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0.
Note: TCNT0 bit 10 corresponds to ITVE0 and ITVAD0, bit 11 to ITVE1 and ITVAD1, bit 12
to ITVE2 and ITVAD2, and bit 13 to ITVE3 and ITVAD3.
Start
Set interval 2
Start counter 3
Interrupt request to CPU

or start of A/D0 sampling
Figure 10.50 Sample Setup Procedure for Interval Timer Operation
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Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the
setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 10.51.
counter clock φ" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, at the same time select the external clock edge type with the CKEG bit in TCR.
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute.
3. Set bit T3PWM–T5PWM in the timer mode register (TMDR) to PWM mode. When PWM
mode is set, the TIOD3. TIOD4, and TIOD5 pins go to 0 output irrespective of the timer I/O
control register (TIOR) contents.
4. The GR3A–GR3C, GR4A–GR4C, and GR5A ATU general registers are used as duty registers
(DTR), and the GR3D, GR4D, and GR5B ATU general registers as cycle registers (CYLR).
Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1
output timing in CYLR.
counter (TCNT) for the relevant channel.
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Start
Set PWM timer 3
Set GR 4
Start count 5
PWM waveform output
Figure 10.51 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5)
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Sample Setup Procedure for PWM Timer Operation (Channels 6 to 9): An example of the
setup procedure for PWM timer operation (channels 6 to 9 ) is shown in figure 10.52.
counter clock φ" with the CKSEL bit in the timer control register (TCR6–TCR9).
2. Set the port B control register (PBCR) corresponding to the waveform output port to ATU
PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify
the output attribute.
3. Set PWM waveform output 1 output timing in the cycle register (CYLR6–CYLR9), and set the
PWM waveform output 0 output timing in the buffer register (BFR6–BFR9) and duty register
(DTR6–DTR9). If necessary, an interrupt request can be sent to the CPU on a compare-match
between the CYLR value and the free-running counter (TCNT) value by making the
appropriate setting in the interrupt enable register (TIERE).
4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for
the relevant channel.
Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR
setting. For details, see section 10.3.10, Buffer Function.
2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is
specified by setting buffer register (BFR) ≥ cycle register (CYLR).
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Start
Set CYLR, BFR, DTR 3
Start count 4
PWM waveform output
Figure 10.52 Sample Setup Procedure for PWM Timer Operation (Channels 6 to 9)
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10.7 Usage Notes

Note that the kinds of operation and contention described below occur during ATU operation.
Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 9 free-
running counters (TCNT3 to TCNT9), if a compare-match occurs in the T2 state of a CPU write
cycle when clearing is enabled, the write to TCNT has priority and clearing is not performed.
The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform
output to an external destination are performed in the same way as for a normal compare-match.
T1 T2
CK
Address TCNT address
TCNT CPU write value
External output signal

(1 output)
Figure 10.53 Contention between TCNT Write and Clear
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Contention between GR Write and Data Transfer by Input Capture: If input capture occurs
in the T2 state of a CPU write cycle for a channel 1 to 5 general register (GR1A to GR1F, GR2A,
GR2B, GR3A to GR3D, GR4A to GR4D, GR5A, GR5B), the write to TCNT has priority and the
data transfer to GR is not performed.
Writing of 1 to the interrupt status flag due to input capture is performed in the same way as for
normal input capture.
T1 T2
CK
Address GR address
Internal input capture signal
GR CPU write value
Figure 10.54 Contention between GR Write and Data Transfer by Input Capture
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Contention between TCNT Write and Increment: If a write to a channel 0 to 9 free-running

counter (TCNT0 to TCNT9) is performed while that counter is counting up, the write to the
counter has priority and the counter is not incremented.
The timing in this case is shown in figure 10.55. In this example, the CPU writes H'5555 at the
point at which TCNT is to be incremented from H'1001 to H'1002.
T1 T2
CK
TCNT input clock
5555
TCNT 1001 (CPU write value) 5556
Figure 10.55 Contention between TCNT Write and Increment
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Contention between TCNT Write and Counter Clearing by Overflow: With channel 3 to 5
free-running counters (TCNT3 to TCNT5), if overflow occurs in the T2 state of a CPU write cycle
when clearing is enabled, the write to TCNT has priority and the counter is not cleared to H'0000.
Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as
for normal overflow.
The timing in this case is shown in figure 10.56. In this example, H'5555 is written at the point at
which TCNT overflows.
T1 T2
CK
TCNT input clock
Overflow signal
5555
TCNT FFFF (CPU write value) 5556

(OVF)
Figure 10.56 Contention between TCNT Write and Overflow
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Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If
an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an
interrupt status flag 0 write cycle by the CPU, setting of the interrupt status flag to 1 by that event
has priority and the interrupt status flag is not cleared.
TSR write cycle

T1 T2
CK
Address TSR address
0 written
to TSR
TCNT N N+1
GR N

Remains unchanged at 1
IMF
Figure 10.57 Contention between Interrupt Status Flag Setting by Compare-Match and
Clearing
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Contention between DTR Write and BFR Value transfer by Buffer Function: Do not write to
the duty register (DTR) when the free-running counter (TCNT) has been started in channels 6 to 9.
If there is contention between transfer of the buffer register (BFR) value to the corresponding
DTR due to a cycle register compare-match, and a write to DTR by the CPU, the OR of the BFR
value and CPU write value is written to DTR.
Figure 10.58 shows an example in which contention arises when the BFR value is H'AAAA and
the value to be written to DTR is H'5555.
CK
Address DTR address
H'5555
Internal write signal written
to DTR
BFR H'AAAA
DTR H'FFFF
(OR of H'5555 and
H'AAAA)
Figure 10.58 Contention between DTR Write and BFR Value Transfer by Buffer Function
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Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input
Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt
status flag (ICF0B, CMF6) is set by input capture (ICR0B) or compare-match (CYLR6), clearing
by the DMAC has priority and the interrupt status flag is not set.
The width of the DMAC clear request signal is normally two states, the same as an ATU access
cycle, and clearing is performed in two states. If a bus wait, or a bus request from off-chip, occurs
while the DMAC clear request signal is being output, the DMAC clear request signal width will be
N states (N ≥ 3).
The timing in this case is shown in figure 10.59
a. When the input capture/compare-match signal precedes the interrupt status flag
clear signal by 1/2 state
CK
DMAC clear request

signal

clear signal
1/2 state
Input capture/
compare-match signal

ICF0B, CMF6
b. When the input capture/compare-match signal follows the interrupt status flag
clear signal by 1/2 state, and contention arises
CK
DMAC clear request

signal

clear signal
Input capture/
compare-match signal

ICF0B, CMF6
Figure 10.59 Contention between Interrupt Status Flag Clearing by DMAC and Setting by
Input Capture/Compare-Match
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Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing

H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by
setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped.
However, the OSF bit in the timer status register (TSR) is set when DCNT underflows.
Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0
immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following
the H'0000 write.
CK
DCNT input clock
DCNT N H'0000 H'0000
H'0000
written
Internal write signal to DCNT
DSTR
TSR
Port output
(one-shot pulse)
Figure 10.60 Halting of a Down-Counter by the CPU
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Starting a Count with a Down-Counter Value of H'0000: A one-shot pulse will not be output if
the down-count start register (DSTR) is set and the down-counter (DCNT) count started from the
CPU, or the timer connection register (TCNR) is set and DCNT is started by a channel 1 or
channel 2 compare-match, when the DCNT value is H'0000. However, the OSF bit in the timer
status register (TSR) will be set to 1.
CK
DCNT input clock
DCNT H'0000 H'0000

1 written
to DST
Internal write signal bit in
DSTR
DSTR
TSR
Remains unchanged at 0
Port output
(one-shot pulse)
Figure 10.61 Starting a Count with a Down-Counter Value of H'0000
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Input Capture Operation when Free-Running Counter is Halted: In channel 0 or channels 1

to 5, if input capture setting is performed and a trigger signal is input from the input pin, the
TCNT value will be transferred to the corresponding general register (GR) or input capture
register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and
the IMF or ICF bit will be set in the timer status register (TSR).
CK
Timer status register

TSR
Internal input capture

signal
TCNT N
GR (ICR) N

IMF (ICF)
Figure 10.62 Input Capture Operation before Free-Running Counter is Started
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Contention between DCNT Write and Counter Clearing by Underflow: With the channel 10
down-counters (DCNT10A to DCNT10H), if the count is halted due to underflow occurring in the
T2 state of a down-counter write cycle by the CPU, retention of the H'0000 value has priority and
the write to DCNT by the CPU is not performed. Writing of 1 to the interrupt status flag (OSF)
when the underflow occurs is performed in the same way as for normal underflow.
The timing in this case is shown in figure 10.63. In this example, a write of H'5555 to DCNT is
attempted at the same time as DCNT underflows.
T1 T2
CK
DCNT input clock
Address DCNT address
Write data 5555
Underflow signal
H'0000 retained when DCNT halts

DCNT 0001 0000 0000

(OSF)
Figure 10.63 Contention between DCNT Write and Underflow
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Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow
occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU,
clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1.
STR write cycle

T1 T2
CK
Address DSTR address
1 written
to DSTR
DCNT 0001 0000 0000
Underflow signal
Down-count start
register
Figure 10.64 Contention between DSTR Bit Setting by CPU and Clearing by Underflow
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Timing of Prescaler Register (PSCR1), Timer Control Register (TCR), and Timer Mode
Register (TMDR) Setting: Settings in the prescaler register (PSCR1), timer control register
(TCR), and timer mode register (TMDR) should be made before the counter is started. Operation
is not guaranteed if these registers are modified while the counter is running.
Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the
CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is
written without first reading the flag.
Setting H'0000 in Free-Running Counters 6 to 9 (TCNT6 to TCNT9): If H'0000 is written to a

channel 6 to 9 free-running counter (TCNT6 to TCNT9), and the counter is started, the interval up
to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a
maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-
matches, the correct waveform will be output for the CYLR and DTR values.
Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register
(TSTR) value is set to 0 during counter operation, only incrementing of the corresponding free-
running counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other
ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will
continue to be output.
TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in free-
running counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register
(ITVRR) when that TCNT0 bit is 0, TCNT0 bit 10, 11, 12, or 13 will be detected as having
changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be
started.
Automatic TSR Clearing by DMAC Activation by the ATU: When the DMAC is activated by
the ATU, automatic clearing of TSR will not be performed unless an address in the ATU’s I/O
space (H'FFFF8200 to H'FFFF82FF) is set as either the DMAC data transfer source address or
destination address. If it is wished to set an address outside the ATU’s I/O space for both transfer
source and destination, the corresponding bit should be written with 0 after being read while set to
1 from within the interrupt handling routine.
Interrupt Status Flag Setting/Resetting: With TSRF, a 0 write to a bit is invalid only if
duplicate events have occurred for the same bit before writing 0 after reading 1 to clear a specific
bit. (The duplicate events are accepted.) In order to perform the 0 write, another 1 read is
necessary. Also, with TSRA to TSRE, events are not accepted even if duplicate events have
occurred for the same bit before a 0 write following a 1 read is performed.
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External Output Value in Software Standby Mode: In software standby mode, the ATU
register and external output values are cleared to 0. However, while the TIOA to TIOF1, TIOA,
and TIOB2 external output values are cleared to 0 immediately after software standby mode is
exited, other external output values and all registers are cleared to 0 immediately before a
transition to software standby mode.
Software standby mode
CK
TIOA–F1,
TIOA, B2
Other external
outputs
Figure 10.65 External Output Value Transition Points in Relation to Software Standby
Mode
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10.8 Advanced Timer Unit Registers And Pins

Table 10.4 ATU Registers and Pins
Channel
Register Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel
Name 0 1 2 3 4 5 6 7 8 9 10
TSTR (16) TSTR TSTR TSTR TSTR TSTR TSTR TSTR TSTR TSTR TSTR —
TMDR (8) — — — TMDR TMDR TMDR — — — — —
TCR (8) — TCR1 TCR2 TCR3 TCR4 TCR5 TCR6 TCR7 TCR8 TCR9 TCR10
PSCR1 (8) PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1
TIOR (8) TIOR0A TIOR1A TIOR2A TIOR3A TIOR4A TIOR5A — — — — —
to TIOR3B TIOR4B
TIOR1C
TGSR (8) TGSR — — — — — — — — — —
TSR (8) TSRAH, TSRB TSRC TSRDH TSRDH TSRDH TSRE TSRE TSRE TSRE TSRF
TSRAL TSRDL TSRDL TSRDL
TIER (8) TIERA TIERB TIERC TIERDH TIERDH TIERDH TIERE TIERE TIERE TIERE TIERF
TIERDL TIERDL TIERDL
ITVRR (8) ITVRR — — — — — — — — — —
DSTR (8) — — — — — — — — — — DSTR
TCNDR (8) — — — — — — — — — — TCNR
TCNT (16) TCNT0H, TCNT1 TCNT2 TCNT3 TCNT4 TCNT5 TCNT6 TCNT7 TCNT8 TCNT9 —
TCNT0L
ICR (16) ICR0AH, — — — — — — — — — —
ICR0AL
to
ICR0DH,
ICR0DL
GR (16) — GR1A GR2A GR3A GR4A GR5A — — — — —
to GR2B to to GR5B
GR1F GR3D GR4D
DCNT (16) — — — — — — — — — — DCNT10A
to
DCNT10
H
OSBR (16) — OSBR — — — — — — — — —
CYLR (16) — — — — — — CYLR6 CYLR7 CYLR8 CYLR9 —
BFR (16) — — — — — — BFR6 BFR7 BFR8 BFR9 —
DTR (16) — — — — — — DTR6 DTR7 DTR8 DTR9 —
Pins* TIA0 TIOA1 TIOA2 TIOA3 TIOA4 TIOA5 TO6 TO7 TO8 TO9 TOA10
to to TIOB2 to to TIOB5 to
TID0 TIOF1, TIOD3 TIOD4 TOH10
TCLKA, TCLKA TCLKA TCLKA TCLKA
TCLKB TCLKB TCLKB TCLKB TCLKB
Note: * Pin functions should be set as described in section 16, Pin Function Controller (PFC).
The function of dual input/output pins (e.g. TIOA1) can also be set as described in
section 17, I/O Ports.
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Section 11 Advanced Pulse Controller (APC)
11.1 Overview
The SH7050 series has an on-chip advanced pulse controller (APC) that can generate a maximum
of eight pulse outputs, using the advanced timer unit (ATU) as the time base.
11.1.1 Features
The features of the APC are summarized below.
• Maximum eight pulse outputs

The pulse output pins can be selected from among eight pins. Multiple settings are possible.
• Output trigger provided by advanced timer unit (ATU) channel 2
Pulse 0 output and 1 output is performed using the compare-match signal generated by the
ATU channel 2 compare-match register as the trigger.
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11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the advanced pulse controller.
ATU
Internal/external clock
Compare-
match signal
TCNT2 GR2A
Compare-
Compare match
signal
GR2B
Set
Reset PULS7
Bit 7 Bit 15
Set
Reset PULS6
Bit 6 Bit 14
POPCR (pulse output port setting register)
Set
Reset PULS5
Bit 5 Bit 13
Set
Reset PULS4
Bit 4 Bit 12
Set
Reset PULS3
Bit 3 Bit 11
Set
Reset PULS2
Bit 2 Bit 10
Set
Reset PULS1
Bit 1 Bit 9
Set
Reset PULS0
Bit 0 Bit 8
APC
Legend:
POPCR: Pulse output port control register
Figure 11.1 Advanced Pulse Controller Block Diagram
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Table 11.1 summarizes the advanced pulse controller’s output pins.
Table 11.1 Advanced Pulse Controller Pins
Pin Name I/O Function

PULS0 Output APC pulse output 0
Table 11.2 summarizes the advanced pulse controller’s register.
Table 11.2 Advanced Pulse Controller Register
Name Abbreviation R/W Initial Value Address Access Size

Pulse output port control POPCR R/W H'0000 H'FFFF83C0 8, 16
register
Note: Register access requires 2 cycles.
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11.2.1 Pulse Output Port Control Register (POPCR)
The pulse output port control register (POPCR) is a 16-bit readable/writable register.
POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0 PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0
ROE ROE ROE ROE ROE ROE ROE ROE SOE SOE SOE SOE SOE SOE SOE SOE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These

bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 15 to 8:
PULS7 to 0ROE Description
0 0 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
1 0 output to APC pulse output pin (PULS7–PULS0) is enabled
When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match
between the GR2B and TCNT2 values.
Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits
enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 7 to 0:
PULS7 to 0SOE Description
0 1 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
1 1 output to APC pulse output pin (PULS7–PULS0) is enabled
When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match
between the GR2A and TCNT2 values.
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11.3 Operation
11.3.1 Overview
APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin
function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control
register (POPCR).
When general register 2A (GR2A) in the advanced timer unit (ATU) subsequently generates a
compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general
register 2B (GR2B) generates a compare-match signal, 0 is output from the pins set to 1 by bits 15
to 8 in POPCR.
0 is output from the output-enabled state until the first compare-match occurs.
The advanced pulse controller output operation is shown in figure 11.2.
CR Upper 8 bits
of POPCR
GR2B
Compare-match
signal
Reset signal
Port function
selection
APC output pins Set signal
(PULS0 to PULS7)
Compare-match
signal
GR2A
Lower 8 bits
of POPCR
Figure 11.2 Advanced Pulse Controller Output Operation
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11.3.2 Advanced Pulse Controller Output Operation
Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 11.3
shows an example of the setting procedure for advanced pulse controller output operation.
1. Set general registers GR2A and GR2B as output compare registers with the timer I/O control
register (TIOR).
2. Set the pulse rise point with GR2A and the pulse fall point with GR2B.
3. Select the timer counter 2 (TCNT2) counter clock with the timer prescale register (PSCR).
TCNT2 can only be cleared by an overflow.
4. Enable the respective interrupts with the timer interrupt enable register (TIER).
5. Set the pins for 1 output and 0 output with POPCR.
6. Set the control register for the port to be used by the APC to the APC output pin function.
7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 2 (TCNT2).
8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse
output time.
9. Each time a compare-match interrupt is generated, update the POPCR value and set the next
pin for pulse output.
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APC output operation
GR function selection 1
GR setting 2
ATU settings
Count operation setting 3
Interrupt request setting 4
APC setting Rise/fall port setting 5
Port setting Port output setting 6
ATU setting Start count 7
No
Compare-match?
Yes
ATU setting GR setting 8
APC setting Rise/fall port setting 9
Figure 11.3 Example of Setting Procedure for Advanced Pulse Controller Output
Operation
Example of Advanced Pulse Controller Output Operation: Figure 11.4 shows an example of
advanced pulse controller output operation.
1. Set ATU registers GR2A and GR2B (to be used for output trigger generation) as output
compare registers. Set the rise point in GR2A and the fall point in GR2B, and enable the
respective compare-match interrupts.
2. Write H'0101 to POPCR.
3. Start ATU timer 2. When a GR2A compare-match occurs, 1 is output from the PULS0 pin.
When a GR2B compare-match occurs, 0 is output from the PULS0 pin.
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4. Pulse output widths and output pins can be continually changed by successively rewriting
GR2A, GR2B, and POPCR in response to compare-match interrupts.
5. By setting POPCR to a value such as H'E0E0, pulses can be output from up to 8 pins in
response to a single compare-match.
Cleared on overflow
TCNT value Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
Rewritten
GR2B
GR2A
H'0000
POPCR 0101 0202 0404 0808 1010 E0E0
PULS0
PULS1
PULS2
PULS3
PULS4
PULS5
PULS6
PULS7
Figure 11.4 Example of Advanced Pulse Controller Output Operation
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11.4 Usage Notes

Contention between Compare-Match Signals: If the same value is set for both GR2A and
GR2B, and 0 output and 1 output are both enabled for the same pin by the POPCR settings, 0
output has priority on pins PULS0 to PULS7 when compare-matches occur.
TCNT value
H'FFFF
H'8000
GR2A H'8000
GR2B H'8000
POPCR H'0101
PULS0 pin
Pin output is 0
Figure 11.5 Example of Compare-Match Contention
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Section 12 Watchdog Timer (WDT)
12.1 Overview
The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system
encounters a problem (crashes, for example) and the timer counter overflows without being
rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT
can simultaneously generate an internal reset signal for the entire chip.
When the watchdog function is not needed, the WDT can be used as an interval timer. In the
interval timer operation, an interval timer interrupt is generated at each counter overflow. The
WDT is also used in recovering from the standby mode.
12.1.1 Features
• Works in watchdog timer mode or interval timer mode.

• Outputs WDTOVF in the watchdog timer mode. When the counter overflows in the watchdog
timer mode, overflow signal WDTOVF is output externally. You can select whether to reset
the chip internally when this happens. Either the power-on reset or manual reset signal can be
selected as the internal reset signal.
• Generates interrupts in the interval timer mode. When the counter overflows, it generates an
interval timer interrupt.
• Clears standby mode.
• Works with eight counter input clocks.
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Figure 12.1 is the block diagram of the WDT.
Overflow φ/2
ITI
(interrupt Interrupt φ/64
signal) control φ/128
Clock Clock φ/256
select φ/512
φ/1024
WDTOVF Reset φ/4096
Internal control φ/8192
reset signal* Internal
clock sources
Internal data bus

RSTCSR TCNT TCSR
Bus
Module bus interface
WDT
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
Note: The internal reset signal can be generated by setting the register.
The type of reset can be selected (power-on or manual).
Figure 12.1 WDT Block Diagram
Table 12.1 shows the pin configuration.
Pin Abbreviation I/O Function

Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in the
watchdog timer mode
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Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 12.2 WDT Registers
Address
Write* Read*
1 2
Name Abbreviation R/W Initial Value
R/(W)*
3
Timer control/status TCSR H'18 H'FFFF8610 H'FFFF8610
register
Timer counter TCNT R/W H'00 H'FFFF8611
R/(W)*
3
Reset control/status RSTCSR H'1F H'FFFF8612 H'FFFF8613
register
Notes: In register access, three cycles are required for both byte access and word access.
1. Write by word transfer. It cannot be written in byte or longword.
2. Read by byte transfer. It cannot be read in word or longword.
3. Only 0 can be written in bit 7 to clear the flag.
12.2.1 Timer Counter (TCNT)
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is
more difficult to write to. See section 12.2.4, Register Access, for details.) When the timer enable
bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts
counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the
TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer
overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode
selected in the WT/IT bit of the TCSR.
The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not
initialized in the standby mode.
Bit: 7 6 5 4 3 2 1 0
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12.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from
other registers in that it is more difficult to write to. See section 12.2.4, Register Access, for
details.) TCSR performs selection of the timer counter (TCNT) input clock and mode.
Bits 7 to 5 are initialized to 000 by a power-on reset, in hardware standby mode and software
standby mode. Bits 2 to 0 are initialized to 000 by a power-on reset and in hardware standby
mode, but retain their values in the software standby mode.
Bit: 7 6 5 4 3 2 1 0
OVF WT/IT TME — — CKS2 CKS1 CKS0
R/W: R/(W)* R/W R/W R R R/W R/W R/W
Note: * Only 0 can be written in bit 7 to clear the flag.
Bit 7—Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in the
interval timer mode. It is not set in the watchdog timer mode.
Bit 7: OVF Description

0 No overflow of TCNT in interval timer mode (initial value)
Cleared by reading OVF, then writing 0 in OVF
1 TCNT overflow in the interval timer mode
Bit 6—Timer Mode Select (WT/IT IT):

IT Selects whether to use the WDT as a watchdog timer or
interval timer. When the TCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
IT
Bit 6: WT/IT Description
0 Interval timer mode: interval timer interrupt request to the CPU when
TCNT overflows (initial value)
1 Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. (Section 12.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in the watchdog
timer mode.)
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Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME Description

0 Timer disabled: TCNT is initialized to H'00 and count-up stops (initial
value)
1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
Bits 4 and 3—Reserved: These bits always read as 1. The write value should always be 1.
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the
system clock (φ).
Description
Overflow Interval*
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source φ = 20 MHz)
(φ
0 0 0 φ/2 (initial value) 25.6 µs
0 0 1 φ/64 819.2 µs
0 1 0 φ/128 1.6 ms
0 1 1 φ/256 3.3 ms
1 0 0 φ/512 6.6 ms
1 0 1 φ/1024 13.1 ms
1 1 0 φ/4096 52.4 ms
1 1 1 φ/8192 104.9 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
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12.2.3 Reset Control/Status Register (RSTCSR)
The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers
in that it is more difficult to write. See section 12.2.4, Register Access, for details.) It controls
output of the internal reset signal generated by timer counter (TCNT) overflow and selects the
internal reset signal type. RSTCR is initialized to H'1F by input of a reset signal from the RES pin,
but is not initialized by the internal reset signal generated by the overflow of the WDT. It is
initialized to H'1F in hardware standby mode and software standby mode.
Bit: 7 6 5 4 3 2 1 0
WOVF RSTE — — — — — —
R/W: R/(W)* R/W R R R R R R
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed
(H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode.
Bit 7: WOVF Description

0 No TCNT overflow in watchdog timer mode (initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
1 Set by TCNT overflow in watchdog timer mode
Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT overflows
in the watchdog timer mode.
Bit 6: RSTE Description

0 Not reset when TCNT overflows (initial value). LSI not reset internally,
but TCNT and TCSR reset within WDT.
1 Reset when TCNT overflows
Bit 5, 4—Reserved: These bits always read as 0. The write value should always be 0.
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12.2.4 Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they
are more difficult to write to. The procedures for writing and reading these registers are given
below.
Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
The TCNT and TCSR both have the same write address. The write data must be contained in the
lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the
TCSR) (figure 12.2). This transfers the write data from the lower byte to the TCNT or TCSR.
Writing to the TCNT

15 8 7 0
Address: H'FFFF8610 H'5A Write data
Writing to the TCSR

15 8 7 0
Address: H'FFFF8610 H'A5 Write data
Figure 12.2 Writing to the TCNT and TCSR
Writing to the RSTCSR: The RSTCSR must be written by a word access to address
H'FFFF8612. It cannot be written by byte transfer instructions.
Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are
different, as shown in figure 12.3.
To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower
byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the
RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The
values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.
The WOVF bit is not affected.
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Writing 0 to the WOVF bit

15 8 7 0
Address: H'FFFF8612 H'A5 H'00
Writing to the RSTE bit

15 8 7 0
Address: H'FFFF8612 H'5A Write data
Figure 12.3 Writing to the RSTCSR
Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like
other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR,
H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR.
12.3 Operation
12.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software
must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. No TCNT overflows will occur while the system is operating normally, but if the
TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF
signal is output externally (figure 12.4). The WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 128 φ clock cycles.
If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit. The internal reset signal is output for 512 φ clock cycles.
When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit is cleared to 0.
The following are not initialized a WDT reset signal:
• PFC (Pin Function Controller) function register

• I/O port register
Initializing is only possible by external power-on reset.
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TCNT
value
Overflow
H'FF
H'00 Time
WT/IT = 1 H'00 written WOVF = 1 WT/IT = 1 H'00 written

TME = 1 in TCNT TME = 1 in TCNT
WDTOVF and
internal reset generated
WDTOVF
signal
128 φ clocks
Internal
reset signal*
512 φ clocks
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 12.4 Operation in the Watchdog Timer Mode
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12.3.2 Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer
interrupt (ITI) is generated each time the timer counter overflows. This function can be used to
generate interval timer interrupts at regular intervals (figure 12.5).
TCNT value
Overflow Overflow Overflow Overflow
H'FF
H'00 Time
WT/IT = 0 ITI ITI ITI ITI

TME = 1
ITI: Interval timer interrupt request generation
Figure 12.5 Operation in the Interval Timer Mode
12.3.3 Clearing the Standby Mode
The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When
using the standby mode, set the WDT as described below.
Before Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop
the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby
mode while the TME bit is set to 1. Set bits CKS2 to CKS0 so that the counter overflow interval is
equal to or longer than the oscillation settling time. See section 22.3, AC Characteristics, for the
oscillation settling time.
Recovery from the Standby Mode: When an NMI request signal is received in standby mode,
the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected
by bits CKS2 to CKS0 before the standby mode was entered. When the TCNT overflows (changes
from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the
entire chip and the standby mode ends.
For details on the standby mode, see section 21, Power-Down States.
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12.3.4 Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and
an interval timer interrupt is simultaneously requested (figure 12.6).
CK
TCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 12.6 Timing of Setting the OVF
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1
and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 12.7).
CK
TCNT H'FF H'00
Overflow signal
(internal signal)
WOVF
Figure 12.7 Timing of Setting the WOVF Bit
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12.4 Notes on Use
12.4.1 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to the
TCNT, the write takes priority and the timer counter is not incremented (figure 12.8).
TCNT write cycle
T1 T2 T3
CK
Internal
write signal
TCNT
input clock
TCNT N M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
12.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may
increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
12.4.3 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
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12.4.4 System Reset With WDTOVF
If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly.
Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system
with the WDTOVF signal, use the circuit shown in figure 12.9.
SH7050 series
Reset input RES
Reset signal to
entire system WDTOVF
Figure 12.9 Example of a System Reset Circuit with a WDTOVF Signal
12.4.5 Internal Reset With the Watchdog Timer
If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a
TCNT overflow occurs, but the TCNT and TCSR in the WDT will reset.
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Section 13 Serial Communication Interface (SCI)
13.1 Overview
The SH7050 series has a serial communication interface (SCI) with three independent channels,
both of which possess the same functions.
The SCI supports both asynchronous and clock synchronous serial communication. It also has a
multiprocessor communication function for serial communication among two or more processors.
13.1.1 Features
• Select asynchronous or clock synchronous as the serial communications mode.

• Asynchronous mode: Serial data communications are synched by start-stop in character units.
The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an
asynchronous communication interface adapter (ACIA), or any other chip that employs a
standard asynchronous serial communication. It can also communicate with two or more other
processors using the multiprocessor communication function. There are twelve selectable
serial data communication formats.
 Data length: seven or eight bits
 Stop bit length: one or two bits
 Parity: even, odd, or none
 Multiprocessor bit: one or none
 Receive error detection: parity, overrun, and framing errors
 Break detection: by reading the RxD level directly when a framing error occurs
• Clocked synchronous mode: Serial data communication is synchronized with a clock signal.
The SCI can communicate with other chips having a clock synchronous communication
function. There is one serial data communication format.
 Data length: eight bits
 Receive error detection: overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates.
• Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin
(external).
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• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full
interrupts can start the direct memory access controller (DMAC)/data transfer controller
(DTC) to transfer data.
Figure 13.1 shows a block diagram of the SCI.
Bus interface
Internal
Module data bus
data bus
RDR TDR SSR BRR
SCR
φ
RxD RSR TSR SMR Baud rate φ/4
generator φ/16
Transmit/ φ/64
receive control
TxD
Parity Clock
generation
Parity check
External clock
SCK
TEI
TxI
RxI
ERI
SCI
RSR : Receive shift register SMR : Serial mode register

RDR: Receive data register SCR : Serial control register
TSR : Transmit shift register SSR : Serial status register
TDR : Transmit data register BRR : Bit rate register
Figure 13.1 SCI Block Diagram
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Table 13.1 summarizes the SCI pins by channel.
Table 13.1 SCI Pins
Channel Pin Name Abbreviation Input/Output Function

0 Serial clock pin SCK0 Input/output SCI0 clock input/output
Receive data pin RxD0 Input SCI0 receive data input
Transmit data pin TxD0 Output SCI0 transmit data output
Table 13.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
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Table 13.2 Registers
Initial Access
Address*
2
Channel Name Abbreviation R/W Value Size
0 Serial mode register SMR0 R/W H'00 H'FFFF81A0 8, 16
Bit rate register BRR0 R/W H'FF H'FFFF81A1 8, 16
Serial control register SCR0 R/W H'00 H'FFFF81A2 8, 16
Transmit data register TDR0 R/W H'FF H'FFFF81A3 8, 16
R/(W) *
1
Serial status register SSR0 H'84 H'FFFF81A4 8, 16
Receive data register RDR0 R H'00 H'FFFF81A5 8, 16
1 Serial mode register SMR1 R/W H'00 H'FFFF81B0 8, 16
Bit rate register BRR1 R/W H'FF H'FFFF81B1 8, 16
Serial control register SCR1 R/W H'00 H'FFFF81B2 8, 16
Transmit data register TDR1 R/W H'FF H'FFFF81B3 8, 16
R/(W) *
1
Serial status register SSR1 H'84 H'FFFF81B4 8, 16
Receive data register RDR1 R H'00 H'FFFF81B5 8, 16
2 Serial mode register SMR2 R/W H'00 H'FFFF81C0 8, 16
Bit rate register BRR2 R/W H'FF H'FFFF81C1 8, 16
Serial control register SCR2 R/W H'00 H'FFFF81C2 8, 16
Transmit data register TDR2 R/W H'FF H'FFFF81C3 8, 16
Serial status register SSR2 R/(W) * 1
H'84 H'FFFF81C4 8, 16
Receive data register RDR2 R H'00 H'FFFF81C5 8, 16
Notes: In register access, two cycles are required for byte access, and four cycles for word
access.
1. The only value that can be written is a 0 to clear the flags.
2. Do not access empty addresses.
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13.2.1 Receive Shift Register (RSR)
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the
RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte
has been received, it is automatically transferred to the RDR.
The CPU cannot read or write the RSR directly.
Bit: 7 6 5 4 3 2 1 0
R/W: — — — — — — — —
13.2.2 Receive Data Register (RDR)
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset, in
hardware standby mode and software standby mode.
Bit: 7 6 5 4 3 2 1 0
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13.2.3 Transmit Shift Register (TSR)
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR.
The CPU cannot read or write the TSR directly.
Bit: 7 6 5 4 3 2 1 0
R/W: — — — — — — — —
13.2.4 Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the
TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset,
in hardware standby mode and software standby mode.
Bit: 7 6 5 4 3 2 1 0
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13.2.5 Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset,
in hardware standby mode and software standby mode.
Bit: 7 6 5 4 3 2 1 0
C/A CHR PE O/E STOP MP CKS1 CKS0
A): Selects whether the SCI operates in the asynchronous or

Bit 7—Communication Mode (C/A
clock synchronous mode.
A
Bit 7: C/A Description
0 Asynchronous mode (initial value)
1 Clocked synchronous mode
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the
clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR Description

0 Eight-bit data (initial value)
1 Seven-bit data. (When 7-bit data is selected, the MSB (bit 7) of the
transmit data register is not transmitted.)
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Bit 5: PE Description
0 Parity bit not added or checked (initial value)
1 Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
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Bit 4—Parity Mode (O/E E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set
to 1 to enable parity addition and check. The O/E setting is ignored in the clock synchronous
mode, or in the asynchronous mode when parity addition and check is disabled.
E
Bit 4: O/E Description
0 Even parity (initial value). If even parity is selected, the parity bit is
added to transmit data to make an even number of 1s in the transmitted
character and parity bit combined. Receive data is checked to see if it
has an even number of 1s in the received character and parity bit
combined.
1 Odd parity. If odd parity is selected, the parity bit is added to transmit
data to make an odd number of 1s in the transmitted character and
parity bit combined. Receive data is checked to see if it has an odd
number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the
asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock
synchronous mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP Description

0 One stop bit (initial value). In transmitting, a single bit of 1 is added at
the end of each transmitted character.
1 Two stop bits. In transmitting, two bits of 1 are added at the end of each
transmitted character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit
setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. For
the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication.
Bit 2: MP Description
0 Multiprocessor function disabled (initial value)
1 Multiprocessor format selected
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Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available; φ, φ/4, φ/16, or φ/64.
For further information on the clock source, bit rate register settings, and baud rate, see section
13.2.8, Bit Rate Register.
Bit 1: CKS1 Bit 0: CKS0 Description

0 0 φ (initial value)
1 φ/4
1 0 φ/16
1 φ/64
13.2.6 Serial Control Register (SCR)
The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized
to H'00 by a power-on reset, in hardware standby mode and software standby mode. Manual reset
does not initialize SCR.
Bit: 7 6 5 4 3 2 1 0
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TxI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 7: TIE Description

0 Transmit-data-empty interrupt request (TxI) is disabled (initial value).
The TxI interrupt request can be cleared by reading TDRE after it has
been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.
1 Transmit-data-empty interrupt request (TxI) is enabled
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Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI)
requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to
1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables receive-
error interrupt (ERI) requests.
Bit 6: RIE Description

0 Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are disabled (initial value). RxI and ERI interrupt requests can
be cleared by reading the RDRF flag or error flag (FER, PER, or ORER)
after it has been set to 1, then clearing the flag to 0, or by clearing RIE
to 0.
1 Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are enabled.
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE Description
0 Transmitter disabled (initial value). The transmit data register empty bit
(TDRE) in the serial status register (SSR) is locked at 1.
1 Transmitter enabled. Serial transmission starts when the transmit data
register empty (TDRE) bit in the serial status register (SSR) is cleared
to 0 after writing of transmit data into the TDR. Select the transmit
format in the SMR before setting TE to 1.
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE Description
0 Receiver disabled (initial value). Clearing RE to 0 does not affect the
receive flags (RDRF, FER, PER, ORER). These flags retain their
previous values.
1 Receiver enabled. Serial reception starts when a start bit is detected in
the asynchronous mode, or synchronous clock input is detected in the
clock synchronous mode. Select the receive format in the SMR before
setting RE to 1.
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Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in
the clock synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE Description

0 Multiprocessor interrupts are disabled (normal receive operation) (initial
value). MPIE is cleared when the MPIE bit is cleared to 0, or the
multiprocessor bit (MPB) is set to 1 in receive data.
1 Multiprocessor interrupts are enabled. Receive-data-full interrupt
requests (RxI), receive-error interrupt requests (ERI), and setting of the
RDRF, FER, and ORER status flags in the serial status register (SSR)
are disabled until data with the multiprocessor bit set to 1 is received.
The SCI does not transfer receive data from the RSR to the RDR, does
not detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in
the SCR are set to 1), and allows the FER and ORER bits to be set.
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE Description

0 Transmit-end interrupt (TEI) requests are disabled* (initial value)
1 Transmit-end interrupt (TEI) requests are enabled.*
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source
and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and
CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin
function by using the pin function controller (PFC).
The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an
external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode
register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock
source, see table 13.10 in section 13.3, Operation.
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Bit 1: Bit 0:
Description*
1
CKE1 CKE0
0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input
signal is ignored) or output pin (output level is
undefined) *
2
Clock synchronous mode Internal clock, SCK pin used for synchronous
clock output*
2
Internal clock, SCK pin used for clock output*

3
0 1 Asynchronous mode
Clock synchronous mode Internal clock, SCK pin used for synchronous
clock output
External clock, SCK pin used for clock input*
4
Clock synchronous mode External clock, SCK pin used for synchronous
clock input
External clock, SCK pin used for clock input*
4
Clock synchronous mode External clock, SCK pin used for synchronous
clock input
Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to
select the SCK function for this pin, as well as the I/O direction.
2. Initial value.
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
13.2.7 Serial Status Register (SSR)
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a power-on reset, in hardware standby mode and software standby mode.
Manual reset does not initialize SSR.
Bit: 7 6 5 4 3 2 1 0
TDRE RDRF ORER FER PER TEND MPB MPBT
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Note: * The only value that can be written is a 0 to clear the flag.
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Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the TDR into the TSR and new serial transmit data can be written in the TDR.
Bit 7: TDRE Description

0 TDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE or the DMAC writes data in TDR
1 TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when the chip is power-on reset or enters standby mode, the
TE bit in the serial control register (SCR) is cleared to 0, or TDR contents are
loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data.
Bit 6: RDRF Description

0 RDR does not contain valid received data (initial value)
RDRF is cleared to 0 when the chip is power-on reset or enters standby mode,
software reads RDRF after it has been set to 1, then writes 0 in RDRF, or the
DMAC reads data from RDR
1 RDR contains valid received data
RDRF is set to 1 when serial data is received normally and transferred from RSR
to RDR
Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the
received data is lost.
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Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER Description

0 Receiving is in progress or has ended normally (initial value). Clearing the RE bit
to 0 in the serial control register does not affect the ORER bit, which retains its
previous value.
ORER is cleared to 0 when the chip is power-on reset or enters standby mode or
software reads ORER after it has been set to 1, then writes 0 in ORER
1 A receive overrun error occurred. RDR continues to hold the data received
before the overrun error, so subsequent receive data is lost. Serial receiving
cannot continue while ORER is set to 1. In the clock synchronous mode, serial
transmitting is disabled.
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in the asynchronous mode.
Bit 4: FER Description

to 0 in the serial control register does not affect the FER bit, which retains its
previous value.
FER is cleared to 0 when the chip is power-on reset or enters standby mode or
software reads FER after it has been set to 1, then writes 0 in FER
1 A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked to see if it is a 1. The second stop bit is not checked. When a
framing error occurs, the SCI transfers the receive data into the RDR but does
not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock
synchronous mode, serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0
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Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a
parity error in the asynchronous mode.
Bit 3: PER Description

to 0 in the serial control register does not affect the PER bit, which retains its
previous value.
PER is cleared to 0 when the chip is power-on reset or enters standby mode or
software reads PER after it has been set to 1, then writes 0 in PER
1 A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into the RDR but does not set RDRF. Serial receiving cannot
continue while PER is set to 1. In the clock synchronous mode, serial
transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR)
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a read-only
bit and cannot be written.
Bit 2: TEND Description

0 Transmission is in progress
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or the DMAC writes data in TDR
1 End of transmission (initial value)
TEND is set to 1 when the chip is power-on reset or enters standby mode, TE is
cleared to 0 in the serial control register (SCR), or TDRE is 1 when the last bit of
a one-byte serial character is transmitted.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a
read-only bit and cannot be written.
Bit 1: MPB Description

0 Multiprocessor bit value in receive data is 0 (initial value). If RE is cleared to 0
when a multiprocessor format is selected, the MPB retains its previous value.
1 Multiprocessor bit value in receive data is 1
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Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT Description

0 Multiprocessor bit value in transmit data is 0 (initial value)
1 Multiprocessor bit value in transmit data is 1
13.2.8 Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset,
in hardware standby mode and software standby mode. Each channel has independent baud rate
generator control, so different values can be set in the two channels.
Bit: 7 6 5 4 3 2 1 0
Table 13.3 lists examples of BRR settings in the asynchronous mode; table 13.4 lists examples of
BBR settings in the clock synchronous mode.
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The BRR setting is calculated as follows:
Asynchronous mode:
φ
N= × 106 − 1
64 × 22n−1 ×B
Synchronous mode:
φ
N= × 106 − 1
8× 22n−1 ×B
B: Bit rate (bit/s)

N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the following table for the clock sources and value of n.)
SMR Settings
n Clock Source CKS1 CKS2
0 φ 0 0
1 φ/4 0 1
2 φ/16 1 0
3 φ/64 1 1
The bit rate error in asynchronous mode is calculated as follows:
φ × 106
Error (%) = − 1 × 100
(N + 1) × B × 64 × 22n−1
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Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
4 4.9152 6
Bit Rate
(Bits/s) n N Error (%) n N Error (%) n N Error (%)
110 2 70 0.03 2 86 0.31 2 106 –0.44
150 1 207 0.16 1 255 0.00 2 77 0.16
300 1 103 0.16 1 127 0.00 1 155 0.16
600 0 207 0.16 0 255 0.00 1 77 0.16
1200 0 103 0.16 0 127 0.00 0 155 0.16
2400 0 51 0.16 0 63 0.00 0 77 0.16
4800 0 25 0.16 0 31 0.00 0 38 0.16
9600 0 12 0.16 0 15 0.00 0 19 –2.34
14400 0 8 –3.55 0 10 –3.03 0 12 0.16
19200 0 6 –6.99 0 7 0.00 0 9 –2.34
28800 0 3 8.51 0 4 6.67 0 6 –6.99
31250 0 3 0.00 0 4 –1.70 0 5 0.00
38400 0 2 8.51 0 3 0.00 0 4 –2.34
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φ (MHz)
7.3728 8 9.8304
Bit Rate
110 2 130 –0.07 2 141 0.03 2 174 0.26
150 2 95 0.00 2 103 0.16 2 127 0.00
300 1 191 0.00 1 207 0.16 1 255 0.00
600 1 95 0.00 1 103 0.16 1 127 0.00
1200 0 191 0.00 0 207 0.16 0 255 0.00
2400 0 95 0.00 0 103 0.16 0 127 0.00
4800 0 47 0.00 0 51 0.16 0 63 0.00
9600 0 23 0.00 0 25 0.16 0 31 0.00
14400 0 15 0.00 0 16 2.12 0 20 1.59
19200 0 11 0.00 0 12 0.16 0 15 0.00
28800 0 7 0.00 0 8 –3.55 0 10 –3.03
31250 0 6 0.54 0 7 0.00 0 9 –1.70
38400 0 5 0.00 0 6 –6.99 0 7 0.00
φ (MHz)
10 11.0592 12
Bit Rate
110 2 177 –0.25 2 195 0.19 2 212 0.03
150 2 129 0.16 2 143 0.00 2 155 0.16
300 2 64 0.16 2 71 0.00 2 77 0.16
600 1 129 0.16 1 143 0.00 1 155 0.16
1200 1 64 0.16 1 71 0.00 1 77 0.16
2400 0 129 0.16 0 143 0.00 0 155 0.16
4800 0 64 0.16 0 71 0.00 0 77 0.16
9600 0 32 –1.36 0 35 0.00 0 38 0.16
14400 0 21 –1.36 0 23 0.00 0 25 0.16
19200 0 15 1.73 0 19 0.00 0 19 –2.34
28800 0 10 –1.36 0 11 0.00 0 12 0.16
31250 0 9 0.00 0 10 0.54 0 11 0.00
38400 0 7 1.73 0 8 0.00 0 9 –2.34
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φ (MHz)
12.288 14 14.7456
Bit Rate
110 2 217 0.08 2 248 –0.17 3 64 0.70
150 2 159 0.00 2 181 0.16 2 191 0.00
300 2 79 0.00 2 90 0.16 2 95 0.00
600 1 159 0.00 1 181 0.16 1 191 0.00
1200 1 79 0.00 1 90 0.16 1 95 0.00
2400 0 159 0.00 0 181 0.16 0 191 0.00
4800 0 79 0.00 0 90 0.16 0 95 0.00
9600 0 39 0.00 0 45 –0.93 0 47 0.00
14400 0 26 –1.23 0 29 1.27 0 31 0.00
19200 0 19 0.00 0 22 –0.93 0 23 0.00
28800 0 12 2.56 0 14 1.27 0 15 0.00
31250 0 11 2.40 0 13 0.00 0 14 –1.70
38400 0 9 0.00 0 10 3.57 0 11 0.00
φ (MHz)
16 17.2032 18
Bit Rate
110 3 70 0.03 3 75 0.48 3 79 –0.12
150 2 207 0.16 2 223 0.00 2 233 0.16
300 2 103 0.16 2 111 0.00 2 116 0.16
600 1 207 0.16 1 223 0.00 1 233 0.16
1200 1 103 0.16 1 111 0.00 1 116 0.16
2400 0 207 0.16 0 223 0.00 0 233 0.16
4800 0 103 0.16 0 111 0.00 0 116 0.16
9600 0 51 0.16 0 55 0.00 0 58 –0.69
14400 0 34 –0.79 0 36 0.90 0 38 0.16
19200 0 25 0.16 0 27 0.00 0 28 1.02
28800 0 16 2.12 0 18 –1.75 0 19 –2.34
31250 0 15 0.00 0 16 1.20 0 17 0.00
38400 0 12 0.16 0 13 0.00 0 14 –2.34
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φ (MHz)
18.432 19.6608 20
Bit Rate
110 3 81 –0.22 3 86 0.31 3 88 –0.25
150 2 239 0.00 2 255 0.00 3 64 0.16
300 2 119 0.00 2 127 0.00 2 129 0.16
600 1 239 0.00 1 255 0.00 2 64 0.16
1200 1 119 0.00 1 127 0.00 1 129 0.16
2400 0 239 0.00 0 255 0.00 1 64 0.16
4800 0 119 0.00 0 127 0.00 0 129 0.16
9600 0 59 0.00 0 63 0.00 0 64 0.16
14400 0 39 0.00 0 42 –0.78 0 42 0.94
19200 0 29 0.00 0 31 0.00 0 32 –1.36
28800 0 19 0.00 0 20 1.59 0 21 –1.36
31250 0 17 2.40 0 19 –1.70 0 19 0.00
38400 0 14 0.00 0 15 0.00 0 15 1.73
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Table 13.4 Bit Rates and BRR Settings in Clocked Synchronous Mode
φ (MHz)
4 8 10 12
Bit Rate
(Bits/s) n N n N n N n N
110 3 141 3 212 3 212 3 212
250 2 249 3 124 3 155 3 187
500 2 124 2 249 3 77 3 93
1k 1 249 2 124 2 155 2 187
2.5k 1 99 1 199 1 249 2 74
5k 0 199 1 99 1 124 1 149
10k 0 99 0 199 0 249 1 74
25k 0 39 0 79 0 99 0 119
50k 0 19 0 39 0 49 0 59
100k 0 9 0 19 0 24 0 29
250k 0 3 0 7 0 9 0 11
500k 0 1 0 3 0 4 0 5
1M 0 1 — — 0 2
2.5M 0 0* 0 0*
5M
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φ (MHz)
16 20
Bit Rate
(Bits/s) n N n N
110 3 212 3 212
250 3 249 3 249
500 3 124 3 155
1k 2 249 3 77
2.5k 2 99 2 124
5k 1 199 2 249
10k 1 99 1 124
25k 0 159 1 199
50k 0 79 0 99
100k 0 39 0 49
250k 0 15 0 19
500k 0 7 0 9
1M 0 3 0 4
2.5M — — 0 1
5M 0 0*
Note: * Settings with an error of 1% or less are recommended.
Legend:
Blank: No setting available
—: Setting possible, but error occurs
Table 13.5 indicates the maximum bit rates in the asynchronous mode when the baud rate
generator is being used for various frequencies. Tables 13.6 and 13.7 show the maximum rates for
external clock input.
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Table 13.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)
Settings
φ (MHz) Maximum Bit Rate (Bits/s) n N
4 125000 0 0
4.9152 153600 0 0
6 187500 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
11.0592 345600 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
18.432 576000 0 0
19.6608 614400 0 0
20 625000 0 0
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Table 13.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s)

4 1.0000 62500
4.9152 1.2288 76800
6 1.5000 93750
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
11.0592 2.7648 172800
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
18.432 4.6080 288000
19.6608 4.9152 307200
20 5.0000 312500
Table 13.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s)

4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
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13.3 Operation
13.3.1 Overview
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission
format are selected in the serial mode register (SMR), as shown in table 13.8. The SCI clock
source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits
in the serial control register (SCR), as shown in table 13.9.
Asynchronous Mode:
• Data length is selectable: seven or eight bits.

• Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits).
These selections determine the transmit/receive format and character length.
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors
(ORER), and the break state.
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and can output a clock with a frequency matching the bit rate.
 When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Clock Synchronous Mode:
• The communication format has a fixed 8-bit data length.

• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and outputs a synchronous clock signal to external devices.
 When an external clock is selected, the SCI operates on the input synchronous clock. The
on-chip baud rate generator is not used.
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Table 13.8 Serial Mode Register Settings and SCI Communication Formats
SMR Settings SCI Communication Format

Mode Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit
C/AA CHR PE MP STOP Length Bit cessor Bit Length
Asynchronous 0 0 0 0 0 8-bit Not set Not set 1 bit
1 2 bits
1 0 Set 1 bit
1 2 bits
1 0 0 7-bit Not set 1 bit
1 2 bits
1 0 Set 1 bit
1 2 bits
Asynchronous 0 * 1 0 8-bit Not set Set 1 bit
(multiprocessor * 1 2 bits
format)
1 * 0 7-bit 1 bit
* 1 2 bits
Clock 1 * * * * 8-bit Not set None
synchronous
Note: Asterisks (*) in the table indicate don’t-care bits.
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings SCI Transmit/Receive Clock

Mode Bit 7 Bit 1 Bit 0
Clock Source SCK Pin Function*
C/AA CKE1 CKE0
Asynchronous 0 0 0 Internal SCI does not use the SCK pin
1 Outputs a clock with frequency
matching the bit rate
1 0 External Inputs a clock with frequency 16 times
1 the bit rate
Clock synch- 1 0 0 Internal Outputs the synchronous clock

ronous 1
1 0 External Inputs the synchronous clock
1
Note: * Select the function in combination with the pin function controller (PFC).
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13.3.2 Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends
with a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the marking (high) state. The
SCI monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start
bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
Idling (marking state)

1 (LSB) (MSB) 1
Serial 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
data
Start Parity Stop
bit bit bit
Transmit/receive data
1 bit 7 or 8 bits 1 or 1 or
no bit 2 bits
One unit of communication data (characters or frames)
Figure 13.2 Data Format in Asynchronous Communication (Example: 8-bit Data with
Parity and Two Stop Bits)
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Transmit/Receive Formats: Table 13.10 shows the 12 communication formats that can be
selected in the asynchronous mode. The format is selected by settings in the serial mode register
(SMR).
Table 13.10 Serial Communication Formats (Asynchronous Mode)
SMR Bits Serial Transmit/Receive Format and Frame Length

CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12
0 0 0 0 START 8-Bit data STOP
0 0 0 1 START 8-Bit data STOP STOP
0 1 0 0 START 8-Bit data P STOP
0 1 0 1 START 8-Bit data P STOP STOP
1 0 0 0 START 7-Bit data STOP
1 0 0 1 START 7-Bit data STOP STOP
1 1 0 0 START 7-Bit data P STOP
1 1 0 1 START 7-Bit data P STOP STOP
0 — 1 0 START 8-Bit data MPB STOP
0 — 1 1 START 8-Bit data MPB STOP STOP
1 — 1 0 START 7-Bit data MPB STOP
1 — 1 1 START 7-Bit data MPB STOP STOP
—: Don’t care bits.

Note: START: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control
register (SCR) (table 13.9).
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When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 13.3 Output Clock and Communication Data Phase Relationship (Asynchronous
Mode)
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in the serial control register (SCR), then initialize the SCI as follows.
When changing the operation mode or communication format, always clear the TE and RE bits to
0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the
transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER,
and ORER flags and receive data register (RDR), which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 13.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps
correspond to the numbers in the flowchart):
1. Select the communication format in the serial mode register (SMR).

2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
clock is used.
3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE
and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts
immediately after the setting is made to SCR.
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE
or RE enables the SCI to use the TxD or RxD pin. The initial states are the marking transmit
state, and the idle receive state (waiting for a start bit).
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Initialize
Clear TE and RE bits to 0 in SCR
Select transmit/receive format in SMR 1
Set value to BRR 2
Set CKE1 and CKE0 bits in SCR 3

(TE and RE bits are 0)
No
1-bit interval elapsed?
Yes
Set TE or RE to 1 in SCR; Set RIE,
4
TIE, TEIE, and MPIE as necessary
End
Figure 13.4 Sample Flowchart for SCI Initialization
Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for
transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart):
1. SCI initialization: Set the TxD pin using the PFC.

2. SCI status check and transmit data write: Read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE
to 0.
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) in order to write data in TDR, the TDRE bit is
checked and cleared automatically.
4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0,
then clear the TE to 0 in SCR and use the PFC to establish the TxD pin as an output port.
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Initialize 1
Start transmitting
Read TDRE bit in SSR 2
No
TDRE = 1?
Yes
Write transmission data to TDR

and clear TDRE bit in SSR to 0
3
No
All data transmitted?
Yes
Read TEND bit in SSR
No
TEND = 1?
Yes
No
Output break signal?
4
Yes
Set DR = 0
Clear TE bit in SCR to 0;

select theTxD pin as an
output port with the PFC
End transmission
Figure 13.5 Sample Flowchart for Transmitting Serial Data
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In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the
SCI requests a transmit-data-empty interrupt (TxI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Marking: output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then
continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR
is set to 1, a transmit-end interrupt (TEI) is requested.
Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode.
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Start Parity Stop Start Parity Stop

1 bit Data bit bit Data bit bit 1
bit
Serial Idle
0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
data (marking
state)
TDRE
TEND
TxI TxI interrupt TxI TEI interrupt request

interrupt handler writes request
request data in TDR
and clears
TDRE to 0
1 frame
Example: 8-bit data with parity and one stop bit
Figure 13.6 SCI Transmit Operation in Asynchronous Mode
Receiving Serial Data (Asynchronous Mode): Figures 13.7 and 13.8 show a sample flowchart
for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart).
1. SCI initialization: Set the RxD pin using the PFC.

2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,
and FER bits of the SSR to identify the error. After executing the necessary error handling,
clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain
set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the
stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RxI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
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Initialization 1
Start reception
Read ORER, PER, and

FER bits in SSR
PER, FER, Yes

ORER = 1? 2
No Error handling
Read the RDRF bit in SSR 3
No
RDRF = 1?
Yes
Read reception data of RDR and
4
clear RDRF bit in SSR to 0
No
All data received?
Yes
Clear the RE bit of SCR to 0
End reception
Figure 13.7 Sample Flowchart for Receiving Serial Data (1)
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Start of error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and FER

to 0 in SSR
End
Figure 13.8 Sample Flowchart for Receiving Serial Data (2)
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In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
internally and starts receiving.
2. Receive data is shifted into the RSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
checks:
a. Parity check. The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in the SMR.
b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR into the
RDR.
If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the
RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.11.
Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF
bit is not set to 1, so be sure to clear the error flags.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also
set to 1, the SCI requests a receive-error interrupt (ERI).
Figure 13.9 shows an example of SCI receive operation in the asynchronous mode.
Table 13.11 Receive Error Conditions and SCI Operation
Receive Error Abbreviation Condition Data Transfer

Overrun error ORER Receiving of next data ends while Receive data not loaded
RDRF is still set to 1 in SSR from RSR into RDR
Framing error FER Stop bit is 0 Receive data loaded from
RSR into RDR
Parity error PER Parity of receive data differs from Receive data loaded from
even/odd parity setting in SMR RSR into RDR
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Example: 8-bit data with parity and one stop bit
Start Parity Stop Start Parity Stop

1 bit Data bit bit bit Data bit bit 1
Serial 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle
data (marking
state)
TDRF
FER RxI interrupt request
1 frame RxI interrupt Framing error

handler reads generates
data in RDR and ERI interrupt
clears RDRF to 0. request.
Figure 13.9 SCI Receive Operation
13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line for sending and receiving data. The processors communicate in the
asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.10 shows the example of communication among processors using the multiprocessor
format.
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Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.9.
Clock: See the description in the asynchronous mode section.
Example: Sending data H'AA to receiving processor A
Transmitting
processor
Serial communication line
Receiving Receiving Receiving Receiving

processor A processor B processor C processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial
H'01 H'AA
data
(MPB = 1) (MPB = 0)
ID-transmit cycle: Data-transmit cycle:

receiving processor address data sent to receiving
processor specified by ID
MPB: Multiprocessor bit
Figure 13.10 Communication Among Processors Using Multiprocessor Format
Transmitting Multiprocessor Serial Data: Figure 13.11 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the
numbers in the flowchart):
1. SCI initialization: Set the TxD pin using the PFC.

TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it
reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is checked and
cleared automatically.
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4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then
clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
Initialization 1
Start transmission
No
TDRE = 1?
Yes
Write transmit data in TDR
and set MPBT in SSR
Clear TDRE bit to 0
No 3
Yes
Read TEND bit in SSR
No
TEND = 1?
Yes
No
Output break signal? 4
Yes
Set DR = 0
Clear TE bit in SCR to 0;

select theTxD pin function as
an output port with the PFC
End transmission
Figure 13.11 Sample Flowchart for Transmitting Multiprocessor Serial Data
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In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits are output, LSB first.
c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Marking: output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE)
in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Figure 13.12 shows an example of SCI receive operation in the multiprocessor format.
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Example: 8-bit data with multiprocessor bit and one stop bit
Multiprocessor Multiprocessor
bit bit
Start Stop Start Stop
1 bit Data bit bit Data bit 1
Serial Idle
0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
data (marking
state)
TDRE
TEND
TxI TxI interrupt TxI TEI

interrupt handler writes interrupt interrupt
request data in TDR and request request
clears TDRE to 0
1 frame
Figure 13.12 SCI Multiprocessor Transmit Operation
Receiving Multiprocessor Serial Data: Figure 13.13 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.

2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.
3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that
RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
bits in SSR to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data
from the receive data register (RDR).
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Initialization 1
Start reception
Set MPIE bit in SCR to 1 2
Read ORER and FER bits of SSR
FER = 1? Yes
or ORER =1?
No
Read RDRF bit in SSR 3
No
RDRF = 1?
Yes
Read receive data from RDR
No
Is ID the station’s ID
Yes
Read ORER and FER bits in SSR
FER = 1? Yes
or ORER =1?
No
Read RDRF bit of SSR 5
No
RDRF = 1?
Yes
4
No
All data received? Error processing
Yes
Clear RE bit in SCR to 0
End reception
Figure 13.13 Sample Flowchart for Receiving Multiprocessor Serial Data
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Start error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling Clear RE bit in SCR to 0
Clear ORER and FER

bits in SSR to 0
End
Figure 13.13 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
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Figures 13.14 and 13.15 show examples of SCI receive operation using a multiprocessor format.
Start Data Stop Start Data Stop

1 bit (ID1) MPB bit bit (data 1) MPB bit 1
Serial
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 Idling
data
(marking)
MPB
MPIE
RDRF
RDR
ID1
value
RxI interrupt request RxI interrupt handler Not station’s No RxI interrupt,
(multiprocessor reads data in RDR ID, so MPIE is RDR maintains
interrupt), MPIE = 0 and clears RDRF to 0 set to 1 again state
Figure 13.14 SCI Receive Operation (ID Does Not Match)
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Example: Own ID matches data, 8-bit data with multiprocessor bit and one stop bit
Start Data Stop Start Data Stop

1 bit (ID2) MPB bit bit (data 2) MPB bit 1
Serial Idling
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1
data (marking)
MPB
MPIE
RDRF
RDR
value ID1 ID2 Data2
RxI interrupt request RxI interrupt handler Station’s ID, so receiving MPIE
(multiprocessor reads data in RDR continues, with data bit is again
interrupt), MPIE = 0 and clears RDRF to 0 received by the RxI set to 1
interrupt processing routine
Figure 13.15 Example of SCI Receive Operation (ID Matches)
13.3.4 Clock Synchronous Operation
In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full duplex communication is possible while
sharing the same clock. The transmitter and receiver are also double buffered, so continuous
transmitting or receiving is possible by reading or writing data while transmitting or receiving is in
progress.
Figure 13.16 shows the general format in clock synchronous serial communication.
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Transfer direction
One unit (character or frame) of communication data
* *
Synchroni-
zation clock
LSB MSB
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Note: * High except in continuous transmitting or receiving.
Figure 13.16 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first)
to the MSB (last). After output of the MSB, the communication line remains in the state of the
MSB. In the clock synchronous mode, the SCI transmits or receives data by synchronizing with
the falling edge of the synchronization clock.
Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control
register (SCR). See table 13.9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state.
Note: An overrun error occurs only during the receive operation, and the sync clock is output
until the RE bit is cleared to 0. When you want to perform a receive operation in one-
character units, select external clock for the clock source.
SCI Initialization (Clock Synchronous Mode): Before transmitting or receiving, software must
clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows.
When changing the mode or communication format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
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shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.17 is a sample flowchart for initializing the SCI.
1. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
clock is used.
2. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE,
and RE cleared to 0.
3. Select the communication format in the serial mode register (SMR).
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
serial control register (SCR) to 1. When selecting the simultaneous transmission and receiving,
set TE and RE bits to 1 simultaneously. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD
pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings.
Start of initialization
Clear TE and RE bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE, CKE1,

and CKE0 bits in SCR 1
(TE and RE are 0)
Select transmit/receive
format in SMR 2
Set value in BRR 3

Wait
No
1-bit interval elapsed?
Yes
Set TE and RE to 1 in SCR;
Set RIE, TIE, TEIE, and MPIE bits 4
End
Figure 13.17 Sample Flowchart for SCI Initialization
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Transmitting Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
1. SCI initialization: Set the TxD pin function with the PFC.
2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write
transmit data in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that
data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is
activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE
flag is checked and cleared automatically.
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Initialize 1
Start transmitting
Read TDRE flag in SSR 2
No
TDRE = 1?
Yes
Write transmit data in TDR and

clear TDRE flag to 0 in SSR
No
3
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
Clear TE bit to 0 in SCR
End
Figure 13.18 Sample Flowchart for Serial Transmitting
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Figure 13.19 shows an example of SCI transmit operation.
Transmit direction
Synchroni-
zation clock
LSB MSB
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDRE
TEND
TxI TxI interrupt TxI TEI

request handler writes request request
data in TDR and
clears TDRE to 0
1 frame
Figure 13.19 Example of SCI Transmit Operation
SCI serial transmission operates as follows.
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
that the transmit data register (TDR) contains new data and loads this data from the TDR into
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data are
output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
data from the TDR into the TSR, then begins serial transmission of the next frame. If TDRE is
1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then holds the transmit data
pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to
1, a transmit-end interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK pin is held in the high state.
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Receiving Serial Data (Clock Synchronous Mode): Figure 13.20 shows a sample flowchart for
receiving serial data. When switching from the asynchronous mode to the clock synchronous
mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF
bit will not be set and both transmitting and receiving will be disabled.
The procedure for receiving serial data is listed below:

2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF
4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the frame MSB (bit 7)
of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RxI)
to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
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Initialization 1
Start reception
Read the ORER bit of SSR
Yes
ORER = 1? 2
No Error processing
No
RDRF = 1?
Yes

4
and clear RDRF bit of SSR to 0
No
All data received?
Yes
Clear RE bit of SCR to 0
End reception
Figure 13.20 Sample Flowchart for Serial Receiving
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Error handling
Overrun error processing
Clear ORER bit of SSR to 0
End
Figure 13.20 Sample Flowchart for Serial Receiving (cont)
Figure 13.21 shows an example of the SCI receive operation.
Transfer direction
Synchroni-
zation clock
Serial
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
data
RDRF
ORER
RxI request Read data with RxI RxI request

interrupt processing ERI interrupt
routine and clear request generated
RDRF bit to 0 by overrun error
1 frame
Figure 13.21 Example of SCI Receive Operation
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the
data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the
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RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If
the check does not pass (receive error), the SCI operates as indicated in table 13.11 and no
further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set
to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to
clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCR, the SCI requests a receive-data-full interrupt (RxI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a
receive-error interrupt (ERI).
Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure
13.22 shows a sample flowchart for transmitting and receiving serial data simultaneously. The
procedure is as follows (the steps correspond to the numbers in the flowchart):
1. SCI initialization: Set the TxD and RxD pins using the PFC.
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to
0. The TxI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.
3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF
5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF
to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to
check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0
before the MSB (bit 7) of the current frame is transmitted. When the DMAC or the DTC is
started by a transmit-data-empty interrupt request (TxI) to write data in TDR, the TDRE bit is
checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt
(RxI) to read RDR, the RDRF bit is cleared automatically.
Note: When selecting the transmission or receiving mode to the simultaneous transmission and
receiving mode, clear TE and RE bits to zero once, then set both of them to 1
simultaneously.
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Initialization 1
Start transmitting/receive
No
TDRE = 1?
Yes
Write transmission data in TDR
and clear TDRE bit of SSR to 0
Read ORER bit of SSR
Yes
ORER = 1? 3
No Error handling
No
RDRF = 1?
Yes
Read receive data of RDR,
and clear RDRF bit of SSR to 0 5
All
No
data transmitted/and
received
Yes
Clear TE and RE bits of SCR to 0
End transmission/reception
Figure 13.22 Sample Flowchart for Serial Transmission
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13.4 SCI Interrupt Sources and the DMAC

The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full
(RxI), and transmit-data-empty (TxI). Table 13.12 lists the interrupt sources and indicates their
priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial
control register (SCR). Each interrupt request is sent separately to the interrupt controller.
TxI is requested when the TDRE bit in the SSR is set to 1. TxI can start the direct memory access
controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes
data in the transmit data register (TDR).
RxI is requested when the RDRF bit in the SSR is set to 1. RxI can start the DMAC to transfer
data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR).
ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the
DMAC.
TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC. Where the
TxI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the
transmit operation is complete.
Table 13.12 SCI Interrupt Sources
Interrupt Source Description DMAC Activation Priority

ERI Receive error (ORER, PER, or FER) No High
RxI Receive data full (RDRF) Yes
TxI Transmit data empty (TDRE) Yes
TEI Transmit end (TEND) No Low
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13.5 Notes on Use

Sections 13.5.1 through 13.5.9 provide information for using the SCI.
13.5.1 TDR Write and TDRE Flags
The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data
from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can
be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is
0, however, the old data stored in TDR will be lost because the data has not yet been transferred to
the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1.
13.5.2 Simultaneous Multiple Receive Errors
Table 13.13 indicates the state of the SSR status flags when multiple receive errors occur
simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the
RDR, so receive data is lost.
Table 13.13 SSR Status Flags and Transfer of Receive Data
Receive Data
SSR Status Flags
Transfer
Receive Error Status RDRF ORER FER PER RSR → RDR
Overrun error 1 1 0 0 X
Framing error 0 0 1 0 O
Parity error 0 0 0 1 O
Overrun error + framing error 1 1 1 0 X
Overrun error + parity error 1 1 0 1 X
Framing error + parity error 0 0 1 1 O
Overrun error + framing error + parity 1 1 1 1 X
error
Note: O = Receive data is transferred from RSR to RDR.
X = Receive data is not transferred from RSR to RDR.
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13.5.3 Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the
parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so
if the FER bit is cleared to 0, it will be set to 1 again.
13.5.4 Sending a Break Signal
The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port
data register (DR) and pin function controller (PFC) control register (CR). These conditions allow
break signals to be sent. The DR value is substituted for the marking status until the PFC is set.
Consequently, the output port is set to initially output a 1. To send a break in serial transmission,
first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is
cleared to 0, the transmission section is initialized regardless of the present transmission status.
13.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only)
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting
even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit.
Note that clearing RE to 0 does not clear the receive error flags.
13.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode
In the asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples
on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure
13.23).
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16 clocks
8 clocks
Internal 0 78 15 0 78 15 0 5
base clock
–7.5 clocks +7.5 clocks
Receive
data (RxD) Start bit D0 D1
Synchronization
sampling timing
Data
sampling timing
Figure 13.23 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in the asynchronous mode can therefore be expressed as:
D − 0.5
M= (
0.5 −
1
2N
) − (L − 0.5) F −
N
(1 + F) × 100%
M : Receive margin (%)

N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0–1.0)
L : Frame length (L = 9–12)
F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
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13.5.7 Constraints on DMAC Use
• When using an external clock source for the synchronization clock, update the TDR with the
DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit
clock is input in the first four system clocks after the TDR is written, an error may occur
(figure 13.24).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source.
SCK
t
TDRE
D0 D1 D2 D3 D4 D5 D6 D7
Note: During external clock operation, an error may occur if t is 4φ or less.
Figure 13.24 Example of Clock Synchronous Transmission with DMAC
13.5.8 Cautions for Clock Synchronous External Clock Mode
• Set TE = RE = 1 only when the external clock SCK is 1.

• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
13.5.9 Caution for Clock Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7
bit SCK output, but it cannot be copied to RDR.
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Section 14 A/D Converter
14.1 Overview
The SH7050 series includes a 10-bit successive-approximation A/D converter., with software
selection of up to 16 analog input channels.
The A/D converter is composed of two independent modules, A/D0 and A/D1. A/D0 comprises
three groups, while A/D1 comprises a single group.
Module Analog Groups Channels

A/D0 Analog group 0 AN0–AN3
Analog group 1 AN4–AN7
Analog group 2 AN8–AN11
A/D1 Analog group 3 AN12–AN15
14.1.1 Features
The features of the A/D converter are summarized below.
• 10-bit resolution
16 input channels (A/D0: 12 channels, A/D1: 4 channels)
• High-speed conversion
Conversion time: minimum 6.7 µs per channel (when φ = 20 MHz)
• Two conversion modes
 Single mode: A/D conversion on one channel
 Scan mode:
Continuous conversion on 1 to 12 channels (A/D0)
Continuous conversion on 1 to 4 channels (A/D1)
• Sixteen 10-bit A/D data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Two sample-and-hold circuits
A sample-and-hold circuit is built into each A/D converter module (AD/0 and AD/1),
simplifying the configuration of external analog input circuitry.
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• A/D conversion interrupts and DMA function supported

An A/D conversion interrupt request (ADI) can be sent to the CPU at the end of A/D
conversion (ADI0: A/D0 interrupt request; ADI1: A/D1 interrupt request). Also, the DMAC
can be activated by an ADI interrupt request.
• Two kinds of conversion activation
 Software or external trigger (pin, ATU) can be selected (A/D0)
 Software or external trigger (pin) can be selected (A/D1)
• Analog conversion voltage range can be set
The analog conversion voltage range can be set with the AVref pin.
• ADEND output
Conversion timing can be monitored with the ADEND output pin when using channel 15 in
scan mode.
Figure 14.1 shows a block diagram of the A/D converter.
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A/D0
Module data bus
Bus interface
Internal
data bus
approximation
Successive-
ADTRGR
AVCC
ADCSR0
register
ADCR0
AVref 10-bit D/A ADDR0–11
AVSS
AN0
AN1
Analog multiplexer
AN2
AN3 Sample-and-
AN4 hold circuit +
AN5 A/D conversion
AN6 – control circuit
AN7 Comparator
AN8
AN9
AN10
AN11
ADI0
ATU trigger
interrupt
ADTRG signal
A/D1
Module data bus
Bus interface
Internal
approximation
data bus
Successive-
ADCSR1
register
ADCR1
10-bit D/A ADDR
12–15
ADEND
AN12
Analog multiplexer
Sample-and-
AN13 hold circuit +
– A/D conversion
AN14 control circuit
Comparator
AN15
ADI1
Legend: interrupt
ADCR0, ADCR1: A/D control registers 0 and 1 signal
ADCSR0, ADCSR1: A/D control/status registers 0 and 1
ADDR0 to ADDR15: A/D data registers 0 to 15
ADTRGR: A/D trigger register
Figure 14.1 A/D Converter Block Diagram
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Table 14.1 summarizes the A/D converter’s input pins. There are 16 analog input pins, AN0 to
AN15. The 12 pins AN0 to AN11 are A/D0 analog inputs, divided into three groups: AN0 to AN3
(group 0), AN4 to AN7 (group 1), and AN8 to AN11 (group 2). The four pins AN12 to AN15 are
A/D1 analog inputs, comprising analog input group 3.
The ADTRG pin is used to provide A/D conversion start timing from off-chip. When a low-level
pulse is applied to this pin, the A/D converter starts conversion. This pin is shared by A/D0 and
A/D1.
The ADEND pin is an output used to monitor conversion timing when channel 15 is used in scan
mode.
The AVCC and AVSS pins are power supply voltage pins for the analog section in the A/D
converter. The AVref pin is the A/D converter reference voltage pin. These pins are also shared by
A/D0 and A/D1.
To maintain chip reliability, ensure that AVCC = VCC ±10% and AVSS = VSS during normal
operation, and never leave the AVCC and AVSS pins open, even when the A/D converter is not
being used.
The voltage applied to the analog input pins should be in the range AVSS ≤ ANn ≤ AVref.
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Table 14.1 A/D Converter Pins
Pin Name Abbreviation I/O Function

Analog power supply pin AVCC Input Analog section power supply
Analog ground pin AVSS Input Analog section ground and reference voltage
Analog reference power AVref Input Analog section reference voltage
supply pin
Analog input pin 0 AN0 Input A/D0 analog inputs 0 to 3 (analog group 0)
Analog input pin 1 AN1 Input
A/D conversion trigger ADTRG Input A/D conversion trigger input
input pin
ADEND output pin ADEND Output A/D1 channel 15 conversion timing monitor
output
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Table 14.2 summarizes the A/D converter’s registers.
Table 14.2 A/D Converter Registers
Initial Access
Size*
1
Name Abbreviation R/W Value Address
A/D data register 0 (H/L) ADDR0 (H/L) R H'0000 H'FFFF85D0 8, 16
A/D data register 5 (H/L) ADDR5 (H/L) R H'0000 H'FFFF85DA 8, 16
A/D data register 6 (H/L) ADDR6 (H/L) R H'0000 H'FFFF85DC 8, 16
A/D data register 7 (H/L) ADDR7 (H/L) R H'0000 H'FFFF85DE 8, 16
A/D data register 8 (H/L) ADDR8 (H/L) R H'0000 H'FFFF85E0 8, 16
A/D data register 12 (H/L) ADDR12 (H/L) R H'0000 H'FFFF85F0 8, 16
R/(W)*
2
A/D control/status register 0 ADCSR0 H'00 H'FFFF85E8 8, 16
A/D control register 0 ADCR0 R/W H'1F H'FFFF85E9 8, 16
R/(W)*
2
A/D control/status register 1 ADCSR1 H'00 H'FFFF85F8 8, 16
A/D control register 1 ADCR1 R/W H'7F H'FFFF85F9 8, 16
A/D trigger register ADTRGR R/W H'FF H'FFFF83B8 8
Notes: Register accesses consist of 3 cycles for byte access and 6 cycles for word access.
1. A 16-bit access must be made on a word boundary.
2. Only 0 can be written in bit 7, to clear the flag.
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14.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15)
A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit read-only registers that store the
results of A/D conversion. There are 16 registers, corresponding to analog inputs 0 to 15 (AN0 to
AN15).
The ADDR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode
Bit: 7 6 5 4 3 2 1 0
ADDRnH
AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2
(upper byte)
Bit: 7 6 5 4 3 2 1 0
ADDRnL
AD1 AD0 — — — — — —
(lower byte)
(n = 0 to 15)
The A/D converter converts analog input to a 10-bit digital value. The upper 8 bits of this data are
stored in the upper byte of the ADDR corresponding to the selected channel, and the lower 2 bits
in the lower byte of that ADDR. Only the most significant 2 bits of the ADDR lower byte data are
valid.
Table 14.3 shows correspondence between the analog input channels and A/D data registers.
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Table 14.3 Analog Input Channels and A/D Data Registers
Analog Analog Analog Analog

Input A/D Data Input A/D Data Input A/D Data Input A/D Data
Channel Register Channel Register Channel Register Channel Register
AN0 ADDR0 AN4 ADDR4 AN8 ADDR8 AN12 ADDR12
14.2.2 A/D Control/Status Register 0 (ADCSR0)
A/D control/status register 0 (ADCSR0) is an 8-bit readable/writable register whose functions

include selection of the A/D conversion mode for A/D0.
ADCSR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7 6 5 4 3 2 1 0
ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0
R/W: R/(W)* R/W R/W R/W R/W R/W R/W R/W
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7:
ADF Description
0 Indicates that A/D0 is performing A/D conversion, or is in the idle state. (Initial value)
[Clearing conditions]
• When ADF is read while set to 1, then 0 is written in ADF
• When the DMAC is activated by ADI0
1 Indicates that A/D0 has finished A/D conversion, and the digital value has been
transferred to ADDR.
• Single mode: When A/D conversion ends
• Scan mode: When all A/D conversions end within one selected analog group
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The operation of the A/D converter after ADF is set to 1 differs between single mode and scan
mode.
In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the
A/D converter enters the idle state. In scan mode, after all conversions end within one selected
analog group, ADF is set to 1 and conversion is continued. For example, in the case of 12-channel
scanning, ADF is set to 1 immediately after the end of conversion for AN0 to AN3 (group 0)
It is not possible to write 1 to ADF.
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI).
To prevent incorrect operation, ensure that the ADST bit in A/D control register 0 (ADCR0) is
cleared to 0 before switching the operating mode.
Bit 6:
ADIE Description
0 A/D interrupt (ADI0) is disabled (Initial value)
1 A/D interrupt (ADI0) is enabled
When A/D conversion ends and the ADF bit in ADCSR0 is set to 1, an A/D0 A/D interrupt
(ADI0) will be generated If the ADIE bit is 1. ADI0 is cleared by clearing ADF or ADIE to 0.
Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode
from single mode, 4-channel scan mode, 8-channel scan mode, and 12-channel scan mode.
cleared to 0 before switching the operating mode.
Bit 5: Bit 4:
ADM1 ADM0 Description
0 0 Single mode (Initial value)
1 4-channel scan mode (analog group 0/1/2)
1 0 8-channel scan mode (analog groups 0 and 1)
1 12-channel scan mode (analog groups 0, 1, and 2)
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When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after
A/D conversion has been performed once on the analog channels selected with bits CH3 to CH0 in
ADCSR.
When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion
is performed continuously on a number of channels. The channels on which A/D conversion is to
be performed in scan mode are set with bits CH3 to CH0 in ADCSR0. In 4-channel scan mode,
conversion is performed continuously on the channels in one of analog groups 0 (AN0 to AN3), 1
(AN4 to AN7), or 2 (AN8 to AN11).
When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode,
conversion is performed continuously on the 8 channels in analog groups 0 (AN0 to AN3) and 1
(AN4 to AN7)
When ADM1 and ADM0 are set to 11, 12-channel scan mode is set. In 12-channel scan mode,
conversion is performed continuously on the 12 channels in analog groups 0 (AN0 to AN3), 1
(AN4 to AN7), and 2 (AN8 to AN11).
For details of the operation in single mode and scan mode, see section 14.4, Operation.
Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and
ADM0 bits, select the analog input channels.
cleared to 0 before changing the analog input channel selection.
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Analog Input Channels

CH3 CH2 CH1 CH0 Single Mode 4-Channel Scan Mode
0 0 0 0 AN0 (Initial value) AN0
1 AN1 AN0, AN1
1 0 AN2 AN0–AN2
1 AN3 AN0–AN3
1 0 0 AN4 AN4
1 AN5 AN4, AN5
1 0 AN6 AN4–AN6
1 AN7 AN4–AN7
0*
1
1 0 0 AN8 AN8
1 AN9 AN8, AN9
1 0 AN10 AN8–AN10
1 AN11 AN8–AN11

CH3 CH2 CH1 CH0 8-Channel Scan Mode 12-Channel Scan Mode
0 0 0 0 AN0, AN4 AN0, AN4, AN8
1 AN0, AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8, AN9
1 0 AN0–AN2, AN4–AN6 AN0–AN2, AN4–AN6, AN8–AN10
1 AN0–AN7 AN0–AN11
1 0 0 AN0, AN4 AN0, AN4, AN8
1 AN0, AN1, AN4, AN5 AN0, AN1, AN4, AN5, AN8, AN9
1 0 AN0–AN2, AN4–AN6 AN0–AN2, AN4–AN6, AN8–AN10
1 AN0–AN7 AN0–AN11
0* Reserved*
1 2
1 0 0 AN0, AN4, AN8
1 AN0, AN1, AN4, AN5, AN8, AN9
1 0 AN0–AN2, AN4–AN6, AN8–AN10
1 AN0–AN11
Notes: 1. Must be cleared to 0.
2. These modes are provided for future expansion, and cannot be used at present.
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14.2.3 A/D Control Register 0 (ADCR0)
A/D control register 0 (ADCR0) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR0 is initialized to H'1F by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 4 to 0 of ADCR0 are reserved. These bits cannot be written to, and always return 1 if read.
Bit: 7 6 5 4 3 2 1 0
TRGE CKS ADST — — — — —
R/W: R/W R/W R/W R R R R R
Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external
input or the ATU.
Bit 7:
TRGE Description
0 A/D conversion triggering by external input or ATU is disabled (Initial value)
1 A/D conversion triggering by external input or ATU is enabled
For details of external or ATU trigger selection, see section 14.2.6, A/D Trigger Register.
When ATU triggering is selected, clear bit 7 of the ADTRGR register to 0.
When external triggering is selected, upon input of a low-level pulse to the ADTRG pin after
TRGE has been set to 1, the A/D converter detects the falling edge of the pulse, and sets the
ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the
ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit
is cleared to 0.
When external triggering is used, the low-level pulse input to the ADTRG pin must be at least 1.5
φ clock cycles in width. For details, see section 14.4.4, External Triggering of A/D Conversion.
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Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a
maximum of 266 states when CKS is 0, and a maximum of 134 states when 1. To prevent
incorrect operation, ensure that the ADST bit in A/D control register 0 (ADCR0) is cleared to 0
before changing the A/D conversion time. For details, see section 14.4.3, Analog Input Setting and
A/D Conversion Time.
Bit 6:
CKS Description
0 Conversion time = 266 states (maximum) (Initial value)
1 Conversion time = 134 states (maximum)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST
is set to 1, and stopped when ADST is cleared to 0.
Bit 5:
ADST Description
0 A/D conversion is stopped (Initial value)
1 A/D conversion is being executed
• Single mode: Automatically cleared to 0 when A/D conversion ends
• Scan mode: Cleared by writing 0 in ADST after confirming that ADF in ADCSR0
is 1
Note that the operation of the ADST bit differs between single mode and scan mode.
In single mode and scan mode, ADST is automatically cleared to 0 when A/D conversion ends on
one channel. However, in scan mode, when all conversions have ended for the selected analog
inputs, ADST remains set to 1 in order to start A/D conversion again for all the channels.
Therefore, the ADST bit must be cleared to 0, stopping A/D conversion, before changing the
conversion time or the analog input channel selection.
Ensure that the ADST bit in ADCR0 is cleared to 0 before switching the operating mode.
Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D
interrupt enabling (bit ADIE in ADCSR0), the A/D conversion time (bit CKS in ADCR0), the
operating mode (bits ADM1 and ADM0 in ADSCR), or the analog input channel selection (bits
CH3 to CH0 in ADCSR0). The A/D data register contents will not be guaranteed if these changes
are made while the A/D converter is operating (ADST is set to 1).
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14.2.4 A/D Control/Status Register 1 (ADCSR1)
A/D control/status register 0 (ADCSR1) is an 8-bit readable/writable register whose functions

include selection of the A/D conversion mode for A/D1.
ADCSR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7 6 5 4 3 2 1 0
ADF ADIE ADST SCAN CKS — CH1 CH0
R/W: R/(W)* R/W R/W R/W R/W R R/W R/W
Bit 7—A/D End Flag (ADF): Same as ADF in ADCSR0.
Bit 6—A/D Interrupt Enable (ADIE): Same as ADIE in ADCSR0.
Bit 5—A/D Start (ADST): Same as ADST in ADCR0.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode for A/D1. To prevent incorrect
operation, ensure that the ADST bit is cleared to 0 before switching the operating mode.
Bit 4:
SCAN Description
0 Single mode (Initial value)
1 Scan mode
For details of the operation in single mode and scan mode, see section 14.4, Operation.
Bit 3—Clock Select (CKS): Same as CKS in ADCR0.
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Bits 1 and 0—Channel Select 1 and 0 (CH1 and CH0): These bits, together with the SCAN bit,
select the analog input channels.
To prevent incorrect operation, ensure that the ADST bit in A/D control/status register 1
(ADCSR1) is cleared to 0 before changing the analog input channel selection.

Bit 1: Bit 0:
CH3 CH0 Single Mode Scan Mode
0 0 AN12 (Initial value) AN12
1 AN13 AN12, 13
1 0 AN14 AN12–14
1 AN15 AN12–15
14.2.5 A/D Control Register 1 (ADCR1)
A/D control register 1 (ADCR1) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR1 is initialized to H'7F by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7 6 5 4 3 2 1 0
TRGE — — — — — — —
R/W: R/W R R R R R R R
Bit 7—Trigger Enable (TRGE): Same as TRGE in ADCR0.
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14.2.6 A/D Trigger Register (ADTRGR)
The A/D trigger register (ADTRGR) is an 8-bit readable/writable register that selects the A/D0
trigger. Either external pin (ADTRG) or ATU (ATU interval timer interrupt) triggering can be
selected.
ADTRGR is initialized to H'FF by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7 6 5 4 3 2 1 0
EXTRG — — — — — — —
Bit 7—Trigger Enable (EXTRG): Selects external pin input (ADTRG) or the ATU interval
timer interrupt.
Bit 7:
EXTRGA Description
0 A/D conversion is triggered by the ATU channel 0 interval timer interrupt
1 A/D conversion is triggered by external pin input (ADTRG) (Initial value)
In order to select external triggering or ATU triggering, the TGRE bit in ADCR0 must be set to 1.
For details, see section 14.2.3, A/D Control Register 0.
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14.3 CPU Interface

A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit registers, but they are connected to the
CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately.
To prevent the data being changed between the reads of the upper and lower bytes of an A/D data
register, the lower byte is read via a temporary register (TEMP). The upper byte can be read
directly.
Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte
value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When performing byte-size reads on an A/D data register, always read the upper byte before the
lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect
data may be obtained. If a word-size read is performed on an A/D data register, reading is
performed in upper byte, lower byte order automatically.
Figure 14.2 shows the data flow for access to an A/D data register.
Upper-byte read
Bus Module data bus

CPU
(H'AA) interface
TEMP
(H'40)
ADDRnH ADDRnL
(H'AA) (H'40)
Lower-byte read
Bus Module data bus

CPU
(H'40) interface
TEMP
(H'40)
ADDRnH ADDRnL
(H'AA) (H'40)
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
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14.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode. In single mode, conversion is performed once on
one specified channel, then ends. In scan mode, A/D conversion continues on one or more
specified channels until the ADST bit is cleared to 0.
14.4.1 Single Mode
Single mode, should be selected when only one A/D conversion on one channel is required. Single
mode is selected for A/D0 by setting the ADM1 and ADM0 bits in A/D control/status register 0
(ADSCR0) to 00, and for A/D1 by clearing the SCAN mode bit in ADCSR1 to 0. When the
ADST bit (in ADCR0 for A/D0, or in ADCSR1 for A/D1) is set to 1, A/D conversion is started in
single mode.
The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends.
When conversion ends, the ADF flag in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1,
an ADI interrupt is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 in
ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared automatically.
An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion
is performed in single mode is described next. Figure 14.3 shows a timing diagram for this
example.
1. Single mode is selected (ADM1 = ADM0 = 0), input channel AN1 is selected (CH3 = CH2 =
CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2. When A/D conversion is completed, the result is transferred to ADDR1. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine is started.
5. The routine reads ADF set to 1, then writes 0 in ADF.
6. The routine reads and processes the conversion result (ADDR1).
7. Execution of the A/D interrupt handling routine ends. After this, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
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Set*
ADIE
A/D conver- Set* Set*

sion starts
ADST
Clear* Clear*
ADF
State of channel 0 Idle

(AN0)
State of channel 1 Idle Idle Idle

A/D con- A/D con-
(AN1)
version (1) version (2)

(AN2)

(AN3)
ADDR0
Read conversion Read conversion
result result
ADDR1 A/D conversion result (1) A/D conversion result (2)
ADDR2
ADDR3
Note: * Vertical arrows ( ) indicate instructions executed by software.
Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
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14.4.2 Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode
is selected for A/D0 by setting the ADM1 and ADM0 bits in A/D control/status register 0
(ADSCR0) to 01 (4-channel scan mode), 10 8-channel scan mode), or 11 (12-channel scan mode),
and for A/D1 by setting the SCAN bit in A/D control/status register 1 (ADCSR1) to 1. When the
ADST bit is set to 1, A/D conversion is started in scan mode.
In scan mode, A/D conversion is performed in low-to-high analog input channel number order
(AN0, AN1 ... AN15). The ADST bit remains set to 1 until written with 0 by software.
When all conversions are completed within one selected analog group, the ADF flag in ADCSR is
set to 1 and A/D conversion us repeated. When ADF is set to 1, if the ADIE bit in ADCSR is also
1, an ADI interrupt (ADI0 or ADI1) is requested. To clear the ADF flag, first read ADF when set
to 1, then write 0 in ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared
automatically.
An example of the operation when analog input channels 0 to 2 and 4 to 6 (AN0 to AN2 and AN4
to AN6) are selected and A/D conversion is performed in 8-channel scan mode is described in
Figure 14.4. Figure 14.6 shows a timing diagram for this example.
1. 8-channel scan mode is selected (ADM1 = 1, ADM0 = 0), input channels AN0 to AN2 and
AN4 to AN6 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is
started.
2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0.
Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion is completed for all the channels (AN0 to AN2) in one selected analog group
(analog group 0), the ADF flag is set to 1. If the ADIE bit is also 1, an ADI interrupt is
requested.
5. Conversion of the fourth channel (AN4) starts automatically.
6. Conversion proceeds in the same way through the sixth channel (AN6)
7. Steps 2 to 6 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts
again from the first channel (AN0).
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Continuous A/D conversion

Set*1
ADST Clear*1
Clear*1
ADF
State of channel 0
Idle A/D Idle A/D Idle
(AN0) conver- conver-
sion (1) sion (7)
State of channel 1
sion (2) sion (8)
State of channel 2
sion (3) sion (9)
State of channel 3
Idle
(AN3)
State of channel 4
sion (4) sion (10) *2
State of channel 5
sion (5) sion (11)
tate of channel 6
Idle A/D Idle
(AN6) conver-
sion (6)
State of channel 7
Idle
(AN7)
ADDR3
ADDR5 A/D conversion result (5)
ADDR6 A/D conversion result (6)
ADDR7
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.

2. Data currently being converted is ignored.
Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 and
AN4 to AN6 Selected)
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14.4.3 Analog Input Setting and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit in A/D0 and A/D1. The A/D converter
samples the analog input at time tD (A/D conversion start delay time) after the ADST bit is set to 1,
then starts conversion. Figure 14.5 shows the A/D conversion timing.
The A/D conversion time (tCONV) includes tD and the analog input sampling time (tSPL). The length of
tD is not fixed, since it includes the time required for synchronization of the A/D conversion
operation. The total conversion time therefore varies within the ranges shown in table 14.4.
In scan mode, the tCONV values given in table 14.4 apply to the first conversion. In the second and
subsequent conversions, tCONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
Table 14.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max Unit
A/D conversion start tD 10 — 17 6 — 9 States
delay time
Input sampling time tSPL — 64 — — 32 —
(A/D0)
Input sampling time tSPL — 64 — — 32 —
(A/D1)
A/D conversion time tCONV 259 — 266 131 — 134
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A/D conversion time (tCONV)
Analog input
A/D conversion start sampling time
delay time (tD) (tSPL)
Write cycle
A/D synchronization time
(3 states) (to 14 states)
Address
Internal write
signal ADST write timing
Analog input
sampling signal
A/D converter Idle Sample-and-hold A/D conversion
ADF
End of A/D
conversion
Figure 14.5 A/D Conversion Timing
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14.4.4 External Triggering of A/D Conversion
A/D conversion can be externally triggered. To activate the A/D converter with an external trigger,
first set the pin functions with the PFC (pin function controller), then set the TRGE bit to 1 in the
A/D control register (ADCR). For the A/D0 converter module, also set the EXTRG bit in the A/D
trigger register (ADTRGR). When a low-level pulse is input to the ADTRG pin after these settings
have been made, the A/D converter detects the falling edge of the pulse and sets the ADST bit to
1. Figure 14.6 shows the timing for external trigger input.
The ADST bit is set to 1 one state after the A/D converter samples the falling edge on the ADTRG
pin. The timing from setting of the ADST bit until the start of A/D conversion is the same as when
1 is written into the ADST bit by software.
ADTRG pin sampled
ADTRG input
ADST bit
ADST = 1
Figure 14.6 External Trigger Input Timing
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14.4.5 A/D Converter Activation by ATU
The A/D0 converter module can be activated by an A/D conversion request from the ATU’s
channel 0 interval timer.
To activate the A/D converter by means of the ATU, set the TRGE bit to 1 in A/D control register
0 (ADCR0) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an ATU
channel 0 interval timer A/D conversion request is generated after these settings have been made,
the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D conversion is
the same as when 1 is written into the ADST bit by software.
14.4.6 ADEND Output Pin
When channel 15 is used in scan mode, the conversion timing can be monitored with the ADEND
output pin.
After the channel 15 analog voltage has been latched in scan mode, and conversion has started, the
ADEND pin goes high. The ADEND pin subsequently goes low when channel 15 conversion
ends.
ADEND
State of channel 12 A/D A/D

(AN12) Idle conversion Idle conversion Idle

(AN13) Idle conversion Idle conversion
State of channel 14 A/D

(AN14) Idle Idle
conversion

Idle Idle
(AN15) conversion conversion
Figure 14.7 ADEND Output Timing
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14.5 Interrupt Sources and DMA Transfer Requests

The A/D converter can generate an A/D conversion end interrupt request (ADI0 or ADI1) upon
completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the
A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0.
The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the
CPU.
When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically
cleared when data is transferred by the DMAC.
See section 9.4.3, Example of DMA Transfer between A/D Converter and Internal Memory, for an
example of this operation.
14.6 Usage Notes

The following points should be noted when using the A/D converter.
1. Analog input voltage range

The voltage applied to analog input pins during A/D conversion should be in the range AVSS ≤
ANn ≤ AVref.
2. Relation between AVCC, AVSS and VCC, VSS
When using the A/D converter, set AVCC = VCC ±10%, and AVSS = VSS. When the A/D
converter is not used, set AVSS = VSS , and do not leave the AVCC pin open.
3. AVref input range
Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref ≤ AVCC when not used..
If conditions 1, 2, and 3 above are not met, the reliability of the device may be adversely
affected.
4. Notes on board design
In board design, digital circuitry and analog circuitry should be as mutually isolated as
possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or
are in close proximity should be avoided as far as possible. Failure to do so may result in
incorrect operation of the analog circuitry due to inductance, adversely affecting A/D
conversion values.
Also, digital circuitry must be isolated from the analog input signals (ANn), analog reference
voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). The AVSS
should be connected at one point to a stable digital ground (VSS) on the board.
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5. Notes on noise countermeasures

A protection circuit connected to prevent damage due to an abnormal voltage such as an
excessive surge at the analog input pins (ANn) and analog reference voltage (AVref) should be
connected between AVCC and AVSS as shown in figure 14.8.
Also, the bypass capacitors connected to AVCC and AVref and the filter capacitor connected to
ANn must be connected to AVSS. If a filter capacitor is connected as shown in figure 14.8, the
input currents at the analog input pins (ANn) are averaged, and so an error may arise. Careful
consideration is therefore required when deciding the circuit constants.
AVCC
AVref
SH7050
Rin*2 100 Ω
*1 *1 AN0–AN15
AVSS
0.1 µF
Notes: 1.
10 µF 0.01 µF
2. Rin: Input impedance
Figure 14.8 Example of Analog Input Pin Protection Circuit
Table 14.5 Analog Pin Specifications
Item Min Max Unit

Analog input capacitance — 20 pF
Permissible signal source impedance — 3 kΩ
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6. A/D conversion precision definitions

A/D conversion precision definitions are given below.
a. Resolution
The number of A/D converter digital conversion output codes
b. Offset error
The deviation of the analog input voltage value from the ideal A/D conversion
characteristic when the digital output changes from the minimum voltage value
0000000000 to 0000000001 (see figure 14.9).
c. Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion
characteristic when the digital output changes from 1111111110 to 111111111 (see figure
14.9).
d. Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.8).
e. Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage
and the full-scale voltage. Does not include the offset error, full-scale error, or quantization
error.
f. Absolute precision
The deviation between the digital value and the analog input value. Includes the offset
error, full-scale error, quantization error, and nonlinearity error.
Digital output Digital output

Full-scale error
111 Ideal A/D conversion
Ideal A/D conversion characteristic
110 characteristic
101
100
011 Nonlinearity
error
010
Quantization
001 error Actual A/D conversion
characteristic
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS FS

Analog input voltage Offset error Analog input voltage
Figure 14.9 A/D Conversion Precision Definitions
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Section 15 Compare Match Timer (CMT)
15.1 Overview
The SH7050 series has an on-chip compare match timer (CMT) configured of 16-bit timers for
two channels. The CMT has 16-bit counters and can generate interrupts at set intervals.
15.1.1 Features
The CMT has the following features:
• Four types of counter input clock can be selected

 One of four internal clocks (φ/8, φ/32, φ/128, φ/512) can be selected independently for each
channel.
• Interrupt sources
 A compare match interrupt can be requested independently for each channel.
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Figure 15.1 shows a block diagram of the CMT.
CM10 φ/8 φ/32 φ/128 φ/512 CMI1 φ/8 φ/32 φ/128 φ/512
Control circuit Clock selection Control circuit Clock selection
Comparator
Comparator
CMCOR0
CMCOR1
CMCSR0
CMCSR1
CMCNT0
CMCNT1
CMSTR
Bus
Module bus interface
CMT
Internal bus
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match timer constant register
CMCNT: Compare match timer counter
CMI: Compare match interrupt
Figure 15.1 CMT Block Diagram
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Table 15.1 summarizes the CMT register configuration.
Initial Access
Channel Name Abbreviation R/W Value Address Size (Bits)
Shared Compare match CMSTR R/W H'0000 H'FFFF83D0 8, 16, 32
timer start register
0 Compare match CMCSR0 R/(W)* H'0000 H'FFFF83D2 8, 16, 32
timer control/status
register 0
Compare match CMCNT0 R/W H'0000 H'FFFF83D4 8, 16, 32
timer counter 0
Compare match CMCOR0 R/W H'FFFF H'FFFF83D6 8, 16, 32
timer constant
register 0
1 Compare match CMCSR1 R/(W)* H'0000 H'FFFF83D8 8, 16, 32
timer control/status
register 1
Compare match CMCNT1 R/W H'0000 H'FFFF83DA 8, 16, 32
timer counter 1
Compare match CMCOR1 R/W H'FFFF H'FFFF83DC 8, 16, 32
timer constant
register 1
Notes: With regard to access size, two cycles are required for byte access and word access, and
four cycles for longword access.
* The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to
clear the flags.
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15.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to
operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a
power-on reset and in standby modes.
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
— — — — — — STR1 STR0
Bit 1—Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1.
Bit 1: STR1 Description

0 CMCNT1 count operation halted (initial value)
1 CMCNT1 count operation
Bit 0—Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0.
Bit 0: STR0 Description

0 CMCNT0 count operation halted (initial value)
1 CMCNT0 count operation
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15.2.2 Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock
used for incrementation. It is initialized to H'0000 by a power-on reset and in hardware standby
mode and software standby mode.
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
CMF CMIE — — — — CKS1 CKS0
R/W: R/(W)* R/W R R R R R/W R/W
Note: * The only value that can be written is a 0 to clear the flag.
Bits 15–8 and 5–2—Reserved: These bits always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and
CMCOR values have matched.
Bit 7: CMF Description

0 CMCNT and CMCOR values have not matched (initial status)
Clear condition: Write a 0 to CMF after reading a 1 from it
1 CMCNT and CMCOR values have matched
Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).
Bit 6: CMIE Description

0 Compare match interrupts (CMI) disabled (initial status)
1 Compare match interrupts (CMI) enabled
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Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT
from among the four internal clocks obtained by dividing the system clock (φ). When the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and
CKS0.
Bit 1: CKS1 Bit 0: CKS0 Description

0 0 φ/8 (initial status)
1 φ/32
1 0 φ/128
1 φ/512
15.2.3 Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for
generating interrupt requests.
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT
value matches that of the compare match timer constant register (CMCOR), the CMCNT is
cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is
set to 1 at this time, a compare match interrupt (CMI) is requested.
The CMCNT is initialized to H'0000 by a power-on reset and in hardware standby mode and
Bit: 15 14 13 12 11 10 9 8
Bit: 7 6 5 4 3 2 1 0
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15.2.4 Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare
match period with the CMCNT.
The CMCOR is initialized to H'FFFF by a power-on reset and in hardware standby mode and
software standby mode. There is no initializing with manual reset.
Bit: 15 14 13 12 11 10 9 8
Bit: 7 6 5 4 3 2 1 0
15.3 Operation
15.3.1 Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 15.2 shows the compare match counter operation.
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CMCNT value Counter cleared by

CMCOR compare match
CMCOR
H'0000 Time
Figure 15.2 Counter Operation
15.3.2 CMCNT Count Timing
One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 15.3 shows the timing.
CK
Internal clock
CMCNT input
clock
CMCNT N–1 N N+1
Figure 15.3 Count Timing
15.4 Interrupts
15.4.1 Interrupt Sources and DTC Activation
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details.
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15.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 15.4 shows
the CMF bit set timing.
CK
CMCNT
input clock
CMCNT N 0
CMCOR N
Compare
match signal
CMF
CMI
Figure 15.4 CMF Set Timing
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15.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a
clear signal after a DTC transfer. Figure 15.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle

T1 T2
CK
CMF
Figure 15.5 Timing of CMF Clear by the CPU
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15.5 Notes on Use

Take care that the contentions described in sections 15.5.1–15.5.3 do not arise during CMT
operation.
15.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
15.6 shows the timing.
CMCNT write cycle
T1 T2
CK
Address CMCNT
Internal
write signal
Compare
match signal
CMCNT N H'0000
Figure 15.6 CMCNT Write and Compare Match Contention
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15.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 15.7 shows the timing.
CMCNT write cycle

T1 T2
CK
Address CMCNT
Internal
write signal
Compare
match signal
CMCNT N M
CMCNT write data
Figure 15.7 CMCNT Word Write and Increment Contention
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15.5.3 Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the writing side. The byte data on the side not
performing the writing is also not incremented, so the contents are those before the write.
Figure 15.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write
cycle.
CMCNT write cycle

T1 T2
CK
Address CMCNTH
Internal
write signal
CMCNT
input clock
CMCNTH N M
CMCNTH write data
CMCNTL X X
Figure 15.8 CMCNT Byte Write and Increment Contention
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Section 16 Pin Function Controller (PFC)
16.1 Overview
The pin function controller (PFC) consists of registers for selecting multiplex pin functions and
their input/output direction. Table 16.1 shows the SH7050’s multiplex pins.
Table 16.1 SH7050 Multiplex Pins
Function 1 Function 2 Function 3 Function 4

Port (Related Module) (Related Module) (Related Module) (Related Module)
A PA15 input/output (port) A15 output (BSC)
B PB11 input/output (port) A21 output (BSC) POD input (port)
B PB10 input/output (port) A20 output (BSC)
B PB5 input/output (port) TCLKB input (ATU)
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B PB4 input/output (port) TCLKA input (ATU)
B PB3 input/output (port) TO9 output (ATU)
C PC14 input/output (port) TOH10 output (ATU)
C PC13 input/output (port) TOG10 output (ATU)
C PC12 input/output (port) TOF10 output (ATU) DRAK1 output
(DMAC)
C PC11 input/output (port) TOE10 output (ATU) DRAK0 output
(DMAC)
C PC10 input/output (port) TOD10 output (ATU)
C PC9 input/output (port) TOC10 output (ATU)
C PC8 input/output (port) TOB10 output (ATU)
C PC7 input/output (port) TOA10 output (ATU)
C PC6 input/output (port) CS2 output (BSC) IRQ6 output ADEND output
(INTC) (A/D)
C PC5 input/output (port) CS1 output (BSC)
C PC4 input/output (port) CS0 output (BSC)
C PC3 input/output (port) RD output (BSC)
C PC2 input/output (port) WAIT input (BSC)
C PC1 input/output (port) WRH output (BSC)
C PC0 input/output (port) WRL output (BSC)
D PD15 input/output (port) D15 input/output (BSC)
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E PE14 input/output (port) TIOC3 input/output (ATU)
E PE13 input/output (port) TIOB3 input/output (ATU)
E PE12 input/output (port) TIOA3 input/output (ATU)
E PE11 input/output (port) TID0 input (ATU)
E PE10 input/output (port) TIC0 input (ATU)
E PE9 input/output (port) TIB0 input (ATU)
E PE8 input/output (port) TIA0 input (ATU)
E PE5 input/output (port) TIOF1 input/output (ATU)
E PE4 input/output (port) TIOE1 input/output (ATU)
E PE3 input/output (port) TIOD1 input/output (ATU)
E PE2 input/output (port) TIOC1 input/output (ATU)
F PF11 input/output (port) BREQ input (BSC) PULS7 output
(APC)
F PF10 input/output (port) BACK output (BSC) PULS6 output
(APC)
F PF9 input/output (port) CS3 output (BSC) IRQ7 input (INTC) PULS5 output
(APC)
F PF8 input/output (port) SCK2 input/output (SCI) PULS4 output
(APC)
F PF7 input/output (port) DREQ0 input (DMAC) PULS3 output
(APC)
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F PF6 input/output (port) DACK0 output (DMAC) PULS2 output
(APC)
F PF5 input/output (port) DREQ1 input (DMAC) PULS1 output
(APC)
F PF4 input/output (port) DACK1 input (DMAC) PULS0 output
(APC)
F PF3 input/output (port) IRQ3 input (INTC)
G PG15 input/output (port) IRQ5 input (INTC) TIOB5 input/output
(ATU)
G PG14 input/output (port) IRQ4 input (INTC) TIOA5 input/output
(ATU)
G PG13 input/output (port) TIOD4 input/output (ATU)
G PG12 input/output (port) TIOC4 input/output (ATU)
G PG11 input/output (port) TIOB4 input/output (ATU)
G PG10 input/output (port) TIOA4 input/output (ATU)
G PG9 input/output (port) TIOD3 input/output (ATU)
G PG8 input/output (port) RXD2 input (SCI)
G PG7 input/output (port) TXD2 output (SCI)
G PG4 input/output (port) SCK1 input/output (SCI)
G PG1 input/output (port) SCK0 input/output (SCI)
G PG0 input/output (port) ADTRG input (A/D) IRQOUT output
(INTC)
H PH15 input (port) AN15 input (A/D)
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PFC registers are listed in table 16.2.
Table 16.2 PFC Registers
Initial Access
Name Abbreviation R/W Value Address Size
Port A IO register PAIOR R/W H'0000 H'FFFF8382 8, 16
Port A control register PACR R/W H'0000 H'FFFF8384 8, 16
Port B IO register PBIOR R/W H'C0C0 H'FFFF8388 8, 16
Port B control register PBCR R/W H'80C0 H'FFFF838A 8, 16
Port C IO register PCIOR R/W H'8000 H'FFFF8392 8, 16
Port C control register 1 PCCR1 R/W H'C000 H'FFFF8394 8, 16
Port C control register 2 PCCR2 R/W H'0BFF H'FFFF8396 8, 16
Port D IO register PDIOR R/W H'0000 H'FFFF839A 8, 16
Port D control register PDCR R/W H'0000 H'FFFF839C 8, 16
CK control register* CKCR R/W H'FFFE H'FFFF839E 8, 16
Port E IO register PEIOR R/W H'8000 H'FFFF83A2 8, 16
Port E control register PECR R/W H'8000 H'FFFF83A4 8, 16
Port F IO register PFIOR R/W H'F000 H'FFFF83A8 8, 16
Port F control register 1 PFCR1 R/W H'FF00 H'FFFF83AA 8, 16
Port F control register 2 PFCR2 R/W H'00AA H'FFFF83AC 8, 16
Port G IO register PGIOR R/W H'0000 H'FFFF83B0 8, 16
Port G control register 1 PGCR1 R/W H'0AAA H'FFFF83B2 8, 16
Port G control register 2 PGCR2 R/W H'AA80 H'FFFF83B4 8, 16
Notes: A register access is performed in 2 cycles regardless of the access size.
* CK control register is only bult in the version of flash memory. it is not in the version of
mask ROM.
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16.3.1 Port A IO Register (PAIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/A15 to
PA0/A0. PAIOR is enabled when port A pins function as general input/output pins (PA15 to
PA0), and disabled otherwise.
When port A pins function as PA15 to PA0, a pin becomes an output when the corresponding bit
in PAIOR is set to 1, and an input when the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.2 Port A Control Register (PACR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port A control register (PACR) is a 16-bit readable/writable register that selects the functions
of the 16 multiplex pins in port A. PACR settings are not valid in all operating modes.
1. Expanded mode with on-chip ROM disabled

Port A pins function as address output pins, and PACR settings are invalid.
2. Expanded mode with on-chip ROM enabled
Port A pins are multiplexed as address output pins and general input/output pins. PACR
settings are valid.
3. Single-chip mode
Port A pins function as general input/output pins, and PACR settings are invalid.
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PACR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
Bit 15—PA15 Mode Bit (PA15MD): Selects the function of pin PA15/A15.
Description
Bit 15: Expanded Mode Expanded Mode
PA15MD with ROM Disabled with ROM Enabled Single-Chip Mode
0 Address output (A15) General input/output (PA15) General input/output (PA15)
(Initial value) (Initial value) (Initial value)
1 Address output (A15) Address output (A15) General input/output (PA15)
Description
Description
Description
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Description
Description
Description
Description
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Description
Description
Description
Description
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Description
Description
Description
Description
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16.3.3 Port B IO Register (PBIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
— — — —
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
R/W: R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W
The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 12 pins in port B. Bits PB11IOR to PB0IOR correspond to pins PB11/A21/POD to
PB0/TO6. PBIOR is enabled when port B pins function as general input/output pins (PB11 to
PB0), and disabled otherwise. PBIOR bits 4 and 5 should be cleared to 0 when ATU clock input is
selected.
When port B pins function as PB11 to PB0, a pin becomes an output when the corresponding bit
in PBIOR is set to 1, and an input when the bit is cleared to 0.
PBIOR is initialized to H'C0C0 by a power-on reset (excluding a WDT power-on reset), and in
16.3.4 Port B Control Register (PBCR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB11 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
— — —
MD1 MD0 MD MD MD MD MD MD MD MD MD MD MD
Initial value: 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
R/W: R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W
The port B control register (PBCR) is a 16-bit readable/writable register that selects the functions
of the 12 multiplex pins in port B.
PBCR is initialized to H'80C0 by a power-on reset (excluding a WDT power-on reset), and in
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Bits 14 and 13—PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the
function of pin PB11/A21/POD.
Description
Bit 14: Bit 13: Expanded Mode Expanded Mode
PB11MD1 PB11MD0 with ROM Disabled with ROM Enabled Single-Chip Mode
0 0 Address output (A21) General input/output General input/output
(PB11) (PB11)
1 Address output (A21) Address output (A21) General input/output
(PB11)
1 0 Address output (A21) Port output disable Port output disable
input (POD) input (POD)
1 Reserved Reserved Reserved
Bit 12—PB10 Mode Bit (PB10MD): Selects the function of pin PB10/A20.
Description
PB10MD with ROM Disabled with ROM Enabled Single-Chip Mode
0 Address output (A20) General input/output (PB10) General input/output (PB10)
1 Address output (A20) Address output (A20) General input/output (PB10)
Description
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REJ09B0273-0500
Description
Description
Description
Bit 5—PB5 Mode Bit (PB5MD): Selects the function of pin PB5/TCLKB.
Bit 5:
PB5MD Description
0 General input/output (PB5) (Initial value)
1 ATU clock input (TCLKB)
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REJ09B0273-0500
Bit 4—PB4 Mode Bit (PB4MD): Selects the function of pin PB4/TCLKA.
Bit 4:
PB4MD Description
1 ATU clock input (TCLKA)
Bit 3—PB3 Mode Bit (PB3MD): Selects the function of pin PB3/TO9.
Bit 3:
PB3MD Description
1 ATU PWM output (TO9)
Bit 2:
PB2MD Description
Bit 1:
PB1MD Description
Bit 0:
PB0MD Description
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REJ09B0273-0500
16.3.5 Port C IO Register (PCIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
—
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port C IO register (PCIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 15 pins in port C. Bits PC14IOR to PC0IOR correspond to pins PC14/TOH10 to
PC0/WRL. PCIOR is enabled when port C pins function as general input/output pins (PC14 to
PC0), and disabled otherwise.
When port C pins function as PC14 to PC0, a pin becomes an output when the corresponding bit
in PCIOR is set to 1, and an input when the bit is cleared to 0.
PCIOR is initialized to H'8000 by a power-on reset (excluding a WDT power-on reset), and in
16.3.6 Port C Control Registers 1 and 2 (PCCR1, PCCR2)
Port C control registers 1 and 2 (PCCR1, PCCR2) are 16-bit readable/writable registers that select
the functions of the 15 multiplex pins in port C. PCCR1 selects the functions of the pins for the
upper 7 bits in port C, and PCCR2 selects the functions of the pins for the lower 8 bits in port C.
PCCR1 and PCCR2 are initialized to H'C000 and H'0BFF, respectively, by a power-on reset
(excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in
software standby mode or sleep mode.
Port C control Register 1 (PCCR1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC14 PC14 PC13 PC13 PC12 PC12 PC11 PC11 PC10 PC10 PC9 PC9 PC8 PC8
— —
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value: 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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REJ09B0273-0500
Bits 13 and 12—PC14 Mode Bits 1 and 0 (PC14MD1, PC14MD0): These bits select the
function of pin PC14/TOH10.
Bit 13: Bit 12:

PC14MD1 PC14MD0 Description
0 0 General input/output (PC14) (Initial value)
1 ATU one-shot pulse output (TOH10)
1 0 Reserved
1 Reserved
Bits 11 and 10—PC13 Mode Bits 1 and 0 (PC13MD1, PC13MD0): These bits select the
function of pin PC13/TOG10.
Bit 11: Bit 10:

1 ATU one-shot pulse output (TOG10)
1 0 Reserved
1 Reserved
Bits 9 and 8—PC12 Mode Bits 1 and 0 (PC12MD1, PC12MD0): These bits select the function
of pin PC12/TOF10/DRAK1.
Bit 9: Bit 8:
1 ATU one-shot pulse output (TOF10)
1 0 DMAC DREQ1 acceptance signal output (DRAK1)
1 Reserved
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REJ09B0273-0500
of pin PC11/TOE10/DRAK0.
Bit 7: Bit 6:
1 ATU one-shot pulse output (TOE10)
1 0 DMAC DREQ0 acceptance signal output (DRAK0 )
1 Reserved
of pin PC10/TOD10.
Bit 5: Bit 4:
1 ATU one-shot pulse output (TOD10)
1 0 Reserved
1 Reserved
Bits 3 and 2—PC9 Mode Bits 1 and 0 (PC9MD1, PC9MD0): These bits select the function of
pin PC9/TOC10.
Bit 3: Bit 2:
1 ATU one-shot pulse output (TOC10)
1 0 Reserved
1 Reserved
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REJ09B0273-0500
pin PC8/TOB10.
Bit 1: Bit 0:
1 ATU one-shot pulse output (TOB10)
1 0 Reserved
1 Reserved
Port C Control Register 2 (PCCR2)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC7 PC7 PC6 PC6 PC5 PC4 PC3 PC2 PC1 PC0
— — — — — —
MD1 MD0 MD1 MD0 MD MD MD MD MD MD
Initial value: 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R R/W R R/W R R/W R R/W R R/W R R/W
pin PC7/TOA10.
Bit 15: Bit 14:

1 ATU one-shot pulse output (TOA10)
1 0 Reserved
1 Reserved
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REJ09B0273-0500
pin PC6/CS2/IRQ6/ADEND.
Description
Bit 13: Bit 12:
PC6MD1 PC6MD0 Expanded Mode Single-Chip Mode
0 0 General input/output (PC6) General input/output (PC6)
(Initial value)
(Initial value)
1 Chip select output (CS2) General input/output (PC6)
1 0 Interrupt request input (IRQ6) Interrupt request input (IRQ6)
1 A/D conversion end output A/D conversion end output
(ADEND) (ADEND)
Bit 10—PC5 Mode Bit (PC5MD): Selects the function of pin PC5/CS1.
Description
Bit 10:
PC5MD Expanded Mode Single-Chip Mode
0 General input/output (PC5) (Initial value) General input/output (PC5) (Initial value)
1 Chip select output (CS1) General input/output (PC5)
Bit 8—PC4 Mode Bit (PC4MD): Selects the function of pin PC4/CS0.
Description
Bit 8:
0 General input/output (PC4) General input/output (PC4)
1 Chip select output (CS0) (Initial value) General input/output (PC4) (Initial value)
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REJ09B0273-0500
Bit 6—PC3 Mode Bit (PC3MD): Selects the function of pin PC3/RD.
Description
Bit 6:
1 Read output (RD) (Initial value) General input/output (PC3) (Initial value)
Bit 4—PC2 Mode Bit (PC2MD): Selects the function of pin PC2/WAIT.
Description
Bit 4:
OC2ND Expanded Mode Single-Chip Mode
1 Wait state input (WAIT) (Initial value) General input/output (PC2) (Initial value)
Bit 2—PC1 Mode Bit (PC1MD): Selects the function of pin PC1/WRH.
Description
Bit 2:
1 High-end write (WRH) (Initial value) General input/output (PC1) (Initial value)
Bit 0—PC0 Mode Bit (PC0MD): Selects the function of pin PC0/WRL.
Description
Bit 0:
1 Low-end write (WRL) (Initial value) General input/output (PC0) (Initial value)
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REJ09B0273-0500
16.3.7 Port D IO Register (PDIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port D. Bits PD15IOR to PD0IOR correspond to pins PD15/D15 to
PD0/D0. PDIOR is enabled when port D pins function as general input/output pins (PD15 to
PD0), and disabled otherwise.
When port D pins function as PD15 to PD0, a pin becomes an output when the corresponding bit
in PDIOR is set to 1, and an input when the bit is cleared to 0.
PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby wode. It is not initialized in software standby mode or sleep mode.
16.3.8 Port D Control Register (PDCR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port D control register (PDCR) is a 16-bit readable/writable register that selects the functions
of the 16 multiplex pins in port D. PDCR settings are not valid in all operating modes.
1. Expanded mode with on-chip ROM disabled (area 0: 8-bit bus)

Port D pins D0 to D7 function as data bus input/output pins, and PDCR settings are invalid.
2. Expanded mode with on-chip ROM disabled (area 0: 16-bit bus)
Port D pins function as data bus input/output pins, and PDCR settings are invalid.
3. Expanded mode with on-chip ROM enabled
Port D pins are multiplexed as data bus input/output pins and general input/output pins. PDCR
settings are valid.
4. Single-chip mode
Port D pins function as general input/output pins, and PDCR settings are invalid.
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REJ09B0273-0500
PDCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
Bit 15—PD15 Mode Bit (PD15MD): Selects the function of pin PD15/D15.
Description
Expanded Mode Expanded Mode
Bit 15: with ROM Disabled with ROM Disabled Expanded Mode
PD15MD Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode
0 General input/output Data input/output General input/output General input/output
(PD15) (D15) (PD15) (PD15)
(Initial value) (Initial value) (Initial value) (Initial value)
1 Data input/output Data input/output Data input/output General input/output
(D15) (D15) (D15) (PD15)
Description
(PD14) (D14) (PD14) (PD14)
(D14) (D14) (D14) (PD14)
Description
(PD13) (D13) (PD13) (PD13)
(D13) (D13) (D13) (PD13)
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REJ09B0273-0500
Description
(PD12) (D12) (PD12) (PD12)
(D12) (D12) (D12) (PD12)
Description
(PD11) (D11) (PD11) (PD11)
(D11) (D11) (D11) (PD11)
Description
(PD10) (D10) (PD10) (PD10)
(D10) (D10) (D10) (PD10)
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REJ09B0273-0500
Description
(PD9) (D9) (PD9) (PD9)
(D9) (D9) (D9) (PD9)
Description
(PD8) (D8) (PD8) (PD8)
(D8) (D8) (D8) (PD8)
Description
PD7MD with ROM Disabled with ROM Enabled Single-Chip Mode
0 Data input/output (D7) General input/output (PD7) General input/output (PD7)
1 Data input/output (D7) Data input/output (D7) General input/output (PD7)
Rev. 5.00 Jan 06, 2006 page 497 of 818

REJ09B0273-0500
Description
Description
Description
Description
Rev. 5.00 Jan 06, 2006 page 498 of 818

REJ09B0273-0500
Description
Description
Description
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REJ09B0273-0500
16.3.9 Port E IO Register (PEIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
—
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 15 pins in port E. Bits PE14IOR to PE0IOR correspond to pins PE14/TIOC3 to
PE0/TIOA1. PEIOR is enabled when port E pins function as general input/output pins (PE14 to
PE0) or as ATU input/output pins, and disabled otherwise. PEIOR bits 8 to 11 should be cleared to
0 when ATU input capture input is selected.
When port E pins function as PE14 to PE0, a pin becomes an output when the corresponding bit in
PEIOR is set to 1, and an input when the bit is cleared to 0.
PEIOR is initialized to H'8000 by a power-on reset (excluding a WDT power-on reset), and in
16.3.10 Port E Control Register (PECR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
—
MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port E control register (PECR) is a 16-bit readable/writable register that selects the functions
of the 15 multiplex pins in port E.
PECR is initialized to H'8000 by a power-on reset (excluding a WDT power-on reset), and in
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REJ09B0273-0500
Bit 14—PE14 Mode Bit (PE14MD): Selects the function of pin PE14/TIOC3.
Bit 14:
PE14MD Description
0 General input/output (PE14) (Initial value)
1 ATU input capture input/output compare output (TIOC3)
Bit 13—PE13 Mode Bit (PE13MD): Selects the function of pin PE13/TIOB3.
Bit 13:
PE13MD Description
1 ATU input capture input/output compare output (TIOB3)
Bit 12—PE12 Mode Bit (PE12MD): Selects the function of pin PE12/TIOA3.
Bit 12:
PE12MD Description
1 ATU input capture input/output compare output (TIOA3)
Bit 11—PE11 Mode Bit (PE11MD): Selects the function of pin PE11/TID0.
Bit 11:
PE11MD Description
1 ATU input capture input (TID0
Bit 10—PE10 Mode Bit (PE10MD): Selects the function of pin PE10/TIC0.
Bit 10:
PE10MD Description
1 ATU input capture input (TIC0)
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REJ09B0273-0500
Bit 9—PE9 Mode Bit (PE9MD): Selects the function of pin PE9/TIB0.
Bit 9:
PE9MD Description
1 ATU input capture input (TIB0)
Bit 8—PE8 Mode Bit (PE8MD): Selects the function of pin PE8/TIA0.
Bit 8:
PE8MD Description
1 ATU input capture input (TIA0)
Bit 7:
PE7MD Description
Bit 6:
PE6MD Description
Bit 5—PE5 Mode Bit (PE5MD): Selects the function of pin PE5/TIOF1.
Bit 5:
PE5MD Description
1 ATU input capture input/output compare output (TIOF1)
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REJ09B0273-0500
Bit 4—PE4 Mode Bit (PE4MD): Selects the function of pin PE4/TIOE1.
Bit 4:
PE4MD Description
1 ATU input capture input/output compare output (TIOE1)
Bit 3—PE3 Mode Bit (PE3MD): Selects the function of pin PE3/TIOD1.
Bit 3:
PE3MD Description
1 ATU input capture input/output compare output (TIOD1)
Bit 2—PE2 Mode Bit (PE2MD): Selects the function of pin PE2/TIOC1.
Bit 2:
PE2MD Description
Bit 1:
PE1MD Description
Bit 0:
PE0MD Description
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REJ09B0273-0500
16.3.11 Port F IO Register (PFIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
— — — —
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 12 pins in port F. Bits PF11IOR to PF0IOR correspond to pins
PF11/BREQ/PULS7 to PF0/IRQ0. PFIOR is enabled when port F pins function as general
input/output pins (PF11 to PF0) or the PF8/SCK2/PULS4 pin has the serial clock function
(SCK2), and is disabled otherwise.
When port F pins function as PF11 to PF0 or include the SCK2 function, a pin becomes an output
when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0.
PFIOR is initialized to H'F000 by a power-on reset (excluding a WDT power-on reset), and in
16.3.12 Port F Control Registers 1 and 2 (PFCR1, PFCR2)
Port F control registers 1 and 2 (PFCR1, PFCR2) are 16-bit readable/writable registers that select
the functions of the 12 multiplex pins in port F. PFCR1 selects the functions of the pins for the
upper 4 bits in port F, and PFCR2 selects the functions of the pins for the lower 8 bits in port F.
PFCR1 and PFCR2 are initialized to H'FF00 and H'00AA, respectively, by a power-on reset
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REJ09B0273-0500
Port F Control Register 1 (PFCR1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF11 PF11 PF10 PF10 PF9 PF9 PF8 PF8
— — — — — — — —
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7 and 6—PF11 Mode Bits 1 and 0 (PF11MD1, PF11MD0): These bits select the function
of pin PF11/BREQ/PULS7.
Description
Bit 7: Bit 6:
PF11MD1 PF11MD0 Expanded Mode Single-Chip Mode
0 0 General input/output (PF11) General input/output (PF11)
(Initial value) (Initial value)
1 Bus request input (BREQ) General input/output (PF11)
1 0 APC pulse output (PULS7) APC pulse output (PULS7)
1 Reserved Reserved
Bits 5 and 4—PF10 Mode Bits 1 and 0 (PF10MD1, PF10MD0): These bits select the function
of pin PF10/BACK/PULS6.
Description
Bit 5: Bit 4:
1 Bus request acknowledge output General input/output (PF10)
(BACK)
1 Reserved Reserved
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REJ09B0273-0500
Bits 3 and 2—PF9 Mode Bits 1 and 0 (PF9MD1, PF9MD0): These bits select the function of
pin PF9/CS3/IRQ7/PULS5.
Description
Bit 3: Bit 2:
1 Chip select output (CS3) General input/output (PF9)
1 0 Interrupt request input (IRQ7) Interrupt request input (IRQ7)
1 APC pulse output (PULS5) APC pulse output (PULS5)
pin PF8/SCK/PULS4.
Bit 1: Bit 0:
PF8MD1 PF8MD0 Description
0 0 General input/output (PF8) (Initial value)
1 Serial clock input/output (SCK2)
1 0 APC pulse output (PULS4)
1 Reserved
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REJ09B0273-0500
Port F Control Register 2 (PFCR2)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — —
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD MD MD MD
Initial value: 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R R/W
pin PF7/DREQ0/PULS3.
Bit 15: Bit 14:

1 DMA transfer request input (DREQ0)
1 Reserved
pin PF6/DACK0/PULS2.
Description
Bit 13: Bit 12:
(Initial value)
1 DMA transfer request acceptance General input/output (PF6)
output (DACK0)
1 Reserved Reserved
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REJ09B0273-0500
pin PF5/DREQ1/PULS1.
Bit 11: Bit 10:

1 DMA transfer request input (DREQ1)
1 Reserved
pin PF4/DACK1/PULS0.
Description
Bit 9: Bit 8:
(Initial value)
1 DMA transfer request acceptance General input/output (PF4)
output (DACK1)
1 Reserved Reserved
Bit 6—PF3 Mode Bit (PF3MD): Selects the function of pin PF3/IRQ3.
Bit 6:
PE3MD Description
0 General input/output (PF3) (Initial value)
1 Interrupt request input (IRQ3)
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REJ09B0273-0500
Bit 4:
PE2MD Description
Bit 2:
PE1MD Description
Bit 0:
PE0MD Description
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REJ09B0273-0500
16.3.13 Port G IO Register (PGIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG1 PG1 PG1 PG1 PG1 PG1 PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
5 4 3 2 1 0 IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
IOR IOR IOR IOR IOR IOR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port G. Bits PG15IOR to PG0IOR correspond to pins
PG15/IRQ5/TIOB5 to PG0/ADTRG/IRQOUT. PGIOR is enabled when port G pins function as
general input/output pins (PG15 to PG0), serial clock pins (SCK1, SCK0), or timer input/output
pins (TIOD3, TIOA4, TIOB4, TIOC4, TIOD4, TIOA5, TIOB5), and is disabled otherwise.
When port G pins function as PG15 to PG0, SCK1 and SCK0, or TIOD3, TIOA4, TIOB4, TIOC4,
TIOD4, TIOA5, and TIOB5, a pin becomes an output when the corresponding bit in PGIOR is set
to 1, and an input when the bit is cleared to 0.
PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
16.3.14 Port G Control Registers 1 and 2 (PGCR1, PGCR2)
Port G control registers 1 and 2 (PGCR1, PGCR2) are 16-bit readable/writable registers that select
the functions of the 16 multiplex pins in port G. PGCR1 selects the functions of the pins for the
upper 8 bits in port G, and PGCR2 selects the functions of the pins for the lower 8 bits in port G.
PGCR1 and PGCR2 are initialized to H'0AAA and H'AA80, respectively, by a power-on reset
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REJ09B0273-0500
Port G Control Register 1 (PGCR1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG15 PG15 PG14 PG14 PG13 PG12 PG11 PG10 PG9 PG8
— — — — — —
MD1 MD0 MD1 MD0 MD0 MD0 MD MD MD MD
Initial value: 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
R/W: R/W R/W R/W R/W R R/W R R/W R R/W R R/W R R/W R R/W
Bits 15 and 14—PG15 Mode Bits 1 and 0 (PG15MD1, PG15MD0): These bits select the
function of pin PG15/IRQ5/TIOB5.
Bit 15: Bit 14:

PG15MD1 PG15MD0 Description
0 0 General input/output (PG15) (Initial value)
1 0 ATU input capture input/output compare output (TIOB5)
1 Reserved
Bits 13 and 12—PG14 Mode Bits 1 and 0 (PG14MD1, PG14MD0): These bits select the
function of pin PG14/IRQ4/TIOA5.
Bit 13: Bit 12:

1 0 ATU input capture input/output compare output (TIOA5)
1 Reserved
Bit 10—PG13 Mode Bit (PG13MD): Selects the function of pin PG13/TIOD4.
Bit 10:
PG13MD Description
0 General input/output (PG13) (Initial value)
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REJ09B0273-0500
Bit 8—PG12 Mode Bit (PG12MD): Selects the function of pin PG12/TIOC4.
Bit 8:
PG12MD Description
Bit 6—PG11 Mode Bit (PG11MD): Selects the function of pin PG11/TIOB4.
Bit 6:
PG11MD Description
Bit 4—PG10 Mode Bit (PG10MD): Selects the function of pin PG10/TIOA4.
Bit 4:
PG10MD Description
Bit 2—PG9 Mode Bit (PG9MD): Selects the function of pin PG9/TIOD3.
Bit 2:
PG9MD Description
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REJ09B0273-0500
Bit 0—PG8 Mode Bit (PG8MD): Selects the function of pin PG8/RXD2.
Bit 0:
PG8MD Description
1 Receive data input (RXD2)
Port G Control Register 2 (PGCR2)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PG0 IRQ IRQ
— — — — —
MD0 MD0 MD MD MD MD MD MD1 MD0 MD1 MD0
Initial value: 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0
R/W: R R/W R R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W
Bit 14—PG7 Mode Bit (PG7MD): Selects the function of pin PG7/TXD2.
Bit 14:
PG7MD Description
1 Transmit data output (TXD2)
Bit 12:
PG6MD Description
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REJ09B0273-0500
Bit 10:
PG5MD Description
Bit 8—PG4 Mode Bit (PG4MD): Selects the function of pin PG4/SCK1.
Bit 8:
PG4MD Description
Bit 6:
PG3MD Description
Bit 5:
PG2MD Description
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Bit 4—PG1 Mode Bit (PG1MD): Selects the function of pin PG1/SCK0.
Bit 4:
PG1MD Description
Bits 3 and 2—PG0 Mode Bits 1 and 0 (PG0MD1, PG0MD0): These bits select the function of
pin PG0/ADTRG/IRQOUT.
Bit 3: Bit 2:
1 A/D conversion trigger input (ADTRG)
1 0 Interrupt request output (IRQOUT)
1 Reserved
IRQOUT Mode Bits 1 and 0 (IRQMD1, IRQMD0): These bits select the
Bits 1 and 0—IRQOUT
IRQOUT function for pin PG0/ADTRG/IRQOUT.
Bit 1: Bit 0:
IRQMD1 IRQMD0 Description
0 0 IRQOUT is always high (Initial value)
1 Output on INTC interrupt request
1 0 Reserved
1 Reserved
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16.3.15 CK Control Register (CKCR)
CK control register (CKCR) is a 16-bit readable/writable register being used for controlling clock
output from CK terminal.
CKCR is initialized to H'FFFE by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode or sleep mode.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — — — — — — — — — — CKLO
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
R/W: R R R R R R R R R R R R R R R R/W
Bits 15 to 1—Reserved: This bit is always read as 1, and should only be written with 1.
Bit 0—CK low fixed bit (CKLO): This bit is used for selecting the internal clock output or low
level output for output from the CK terminal.
Bit 0:
CKLO Description
0 Selects the internal clock for the CK terminal output (Initial value)
1 Always selects the low level for the CK terminal output
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Section 17 I/O Ports (I/O)
17.1 Overview
The SH7050 series has eight ports: A, B, C, D, E, F, G, and H.
Ports A to G are input/output ports (A: 16 bits, B: 12 bits, C: 15 bits, D: 16 bits, E: 15 bits, F: 12
bits, G: 16 bits), and H is a 16-bit input port.
All the port pins are multiplexed as general input/output pins (general input pins in the case of port
H) and special function pins. The functions of the multiplex pins are selected by means of the pin
function controller (PFC). Each port is provided with a data register for storing the pin data.
17.2 Port A
Port A is an input/output port with the 16 pins shown in figure 17.1.
Expanded mode Expanded mode

with ROM disabled with ROM enabled Single-chip mode
A15 (output) PA15 (input/output)/A15 (output) PA15 (input/output)
Port A A8 (output) PA8 (input/output)/A8 (output) PA8 (input/output)
Figure 17.1 Port A
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The port A register is shown in table 17.1.
Table 17.1 Port A Register

Port A data register PADR R/W H'0000 H'FFFF8380 8, 16
Note: A register access is performed in two cycles regardless of the access size.
17.2.2 Port A Data Register (PADR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits
PA15DR to PA0DR correspond to pins PA15/A15 to PA0/A0.
When a pin functions as a general output, if a value is written to PADR, that value is output
directly from the pin, and if PADR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PADR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PADR is read the pin state, not the register value, is
returned directly. If a value is written to PADR, although that value is written into PADR it does
not affect the pin state. Table 17.2 summarizes port A data register read/write operations.
PADR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
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Table 17.2 Port A Data Register (PADR) Read/Write Operations
PAIOR Pin Function Read Write

0 General input Pin state Value is written to PADR, but does not affect
pin state
Other than general Pin state Value is written to PADR, but does not affect
input pin state
1 General output PADR value Write value is output from pin (POD pin = high)
High impedance regardless of PADR value
(POD pin = low)
Other than general PADR value Value is written to PADR, but does not affect
output pin state
17.3 Port B
Port B is an input/output port with the 12 pins shown in figure 17.2.

with ROM disabled with ROM enabled Single-chip mode
PB11 (input/output)/ PB11 (input/output)/
A21 (output)
A21 (output)/POD (input) POD (input)
A20 (output) PB10 (input/output)/A20 (output) PB10 (input/output)
Port B A16 (output) PB6 (input/output)/A16 (output) PB6 (input/output)
PB5 (input/output)/TCLKB (input)
PB4 (input/output)/TCLKA (input)
PB3 (input/output)/TO9 (output)
Figure 17.2 Port B
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The port B register is shown in table 17.3.
Table 17.3 Port B Register

Port B data register PBDR R/W H'C0C0 H'FFFF8386 8, 16
17.3.2 Port B Data Register (PBDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
— — — —
DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
R/W: R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits
PB11DR to PB0DR correspond to pins PB11/A21/POD to PB0/TO6.
When a pin functions as a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state. For PB6 to PB10, when the POD pin is driven low, general outputs go to the high-
impedance state regardless of the PBDR value. When the POD pin is driven high, the written
value is output from the pin.
When a pin functions as a general input, if PBDR is read the pin state, not the register value, is
returned directly. If a value is written to PBDR, although that value is written into PBDR it does
not affect the pin state. Table 17.4 summarizes port B data register read/write operations.
PBDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
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Table 17.4 Port B Data Register (PBDR) Read/Write Operations
(Bits 8 to 12)
PBIOR Pin Function Read Write
0 General input Pin state Value is written to PBDR, but does not affect
pin state
Other than general Pin state Value is written to PBDR, but does not affect
input pin state
1 General output PBDR value Write value is output from pin (POD pin = high)
High impedance regardless of PBDR value
(POD pin = low)
Other than general PBDR value Value is written to PBDR, but does not affect
output pin state
(Bits other than 8 to 12)

PBIOR Pin Function Read Write
0 General input Pin state Value is written to PBDR, but does not affect
pin state
Other than general Pin state Value is written to PBDR, but does not affect
input pin state
1 General output PBDR value Write value is output from pin
Other than general PBDR value Value is written to PBDR, but does not affect
output pin state
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17.4 Port C
Port C is an input/output port with the 15 pins shown in figure 17.3.
Expanded mode Single-chip mode

PC14 (input/output)/TOH10 (output)
PC13 (input/output)/TOG10 (output)
PC12 (input/output)/TOF10 (output)/DRAK1 (output)
PC11 (input/output)/TOE10 (output)/DRAK0 (output)
PC10 (input/output)/TOD10 (output)
PC9 (input/output)/TOC10 (output)
PC87 (input/output)/TOB10 (output)
Port C PC7 (input/output)/TOA10 (output)
PC6 (input/output)/CS2 (output)/ PC6 (input/output)/IRQ6 (input)/
IRQ6 (input)/ADEND (output) ADEND (output)
PC5 (input/output)/CS1 (output) PC5 (input/output)
PC4 (input/output)/CS0 (output) PC4 (input/output)
PC3 (input/output)/RD (output) PC3 (input/output)
PC2 (input/output)/WAIT (input) PC2 (input/output)
PC1 (input/output)/WRH (output) PC1 (input/output)
PC0 (input/output)/WRL (output) PC0 (input/output)
Figure 17.3 Port C
The port C register is shown in table 17.5.
Table 17.5 Port C Register

Port C data register PCDR R/W H'8000 H'FFFF8390 8, 16
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17.4.2 Port C Data Register (PCDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
—
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port C data register (PCDR) is a 16-bit readable/writable register that stores port C data. Bits
PC14DR to PC0DR correspond to pins PC14/TOH10 to PC0/WRL.
When a pin functions as a general output, if a value is written to PCDR, that value is output
directly from the pin, and if PCDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PCDR is read the pin state, not the register value, is
returned directly. If a value is written to PCDR, although that value is written into PCDR it does
not affect the pin state. Table 17.6 summarizes port C data register read/write operations.
PCDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
Table 17.6 Port C Data Register (PCDR) Read/Write Operations
PCIOR Pin Function Read Write

0 General input Pin state Value is written to PCDR, but does not affect
pin state
Other than general Pin state Value is written to PCDR, but does not affect
input pin state
1 General output PCDR value Write value is output from pin
Other than general PCDR value Value is written to PCDR, but does not affect
output pin state
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17.5 Port D
Port D is an input/output port with the 16 pins shown in figure 17.4.

Expanded mode Single-chip
with ROM disabled with ROM disabled
with ROM enabled mode
(area 0: 8 bits) (area 0: 16 bits)
PD15 (input/output)/ PD15 (input/output)/
D15 (input/output) PD15 (input/output)
D15 (input/output) D15 (input/output)
Port D D8 (input/output) D8 (input/output)
PD7 (input/output)/
D7 (input/output)
PD6 (input/output)/
D6 (input/output)
PD5 (input/output)/
D5 (input/output)
PD4 (input/output)/
D4 (input/output)
PD3 (input/output)/
D3 (input/output)
PD2 (input/output)/
D2 (input/output)
PD2 (input/output)/
D1 (input/output)
PD0 (input/output)/
D0 (input/output)
Figure 17.4 Port D
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The port D register is shown in table 17.7.
Table 17.7 Port D Register

Port D data register PDDR R/W H'0000 H'FFFF8398 8, 16
17.5.2 Port D Data Register (PDDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data. Bits
PD15DR to PD0DR correspond to pins PD15/D15 to PD0/D0.
When a pin functions as a general output, if a value is written to PDDR, that value is output
directly from the pin, and if PDDR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PDDR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PDDR is read the pin state, not the register value, is
returned directly. If a value is written to PDDR, although that value is written into PDDR it does
not affect the pin state. Table 17.8 summarizes port D data register read/write operations.
PDDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
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Table 17.8 Port D Data Register (PDDR) Read/Write Operations
PDIOR Pin Function Read Write

0 General input Pin state Value is written to PDDR, but does not affect
pin state
Other than general Pin state Value is written to PDDR, but does not affect
input pin state
1 General output PDDR value Write value is output from pin (POD pin = high)
High impedance regardless of PDDR value
(POD pin = low)
Other than general PDDR value Value is written to PDDR, but does not affect
output pin state
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17.6 Port E
Port E is an input/output port with the 15 pins shown in figure 17.5.
PE14 (input/output)/TIOC3 (input/output)

PE13 (input/output)/TIOB3 (input/output)
PE12 (input/output)/TIOA3 (input/output)
PE11 (input/output)/TID0 (input)
PE10 (input/output)/TIC0 (input)
PE9 (input/output)/TIB0 (input)
PE8 (input/output)/TIA0 (input)
Port E
PE5 (input/output)/TIOF1 (input/output)
PE4 (input/output)/TIOE1 (input/output)
PE3 (input/output)/TIOD1 (input/output)
PE2 (input/output)/TIOC1 (input/output)
Figure 17.5 Port E
The port E register is shown in table 17.9.
Table 17.9 Port E Register

Port E data register PEDR R/W H'8000 H'FFFF83A0 8, 16
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17.6.2 Port E Data Register (PEDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
—
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits
PE14DR to PE0DR correspond to pins PE14/TIOC3 to PE0/TIOA1.
When a pin functions as a general output, if a value is written to PEDR, that value is output
directly from the pin, and if PEDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PEDR is read the pin state, not the register value, is
returned directly. If a value is written to PEDR, although that value is written into PEDR it does
not affect the pin state. Table 17.10 summarizes port E data register read/write operations.
PEDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
Table 17.10 Port E Data Register (PEDR) Read/Write Operations
PEIOR Pin Function Read Write

0 General input Pin state Value is written to PEDR, but does not affect
pin state
Other than general Pin state Value is written to PEDR, but does not affect
input pin state
1 General output PEDR value Write value is output from pin
Other than general PEDR value Value is written to PEDR, but does not affect
output pin state
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17.7 Port F
Port F is an input/output port with the 12 pins shown in figure 17.6.
Expanded mode Single-chip mode

PF11 (input/output)/BREQ (input)/PULS7 (output) PF11 (input/output)/PULS7 (output)
PF10 (input/output)/BACK (output)/PULS6 (output) PF10 (input/output)/PULS6 (output)
PF9 (input/output)/CS3 (output)/IRQ7 (input)/ PF9 (input/output)/IRQ7 (input)/
PULS5 (output) PULS5 (output)
PF8 (input/output)/SCK2 (output)/PULS4 (output)

PF7 (input/output)/DREQ0 (input)/PULS3 (output)
Port F PF6 (input/output)/DACK0 (output)/PULS2 (output) PF6 (input/output)/PULS2 (output)
PF5 (input/output)/DREQ1 (input)/PULS1 (output)
PF4 (input/output)/DACK1 (output)/PULS0 (output) PF4 (input/output)/PULS0 (output)
PF3 (input/output)/IRQ3 (input)
Figure 17.6 Port F
The port F register is shown in table 17.11.
Table 17.11 Port F Register

Port F data register PFDR R/W H'F000 H'FFFF83A6 8, 16
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17.7.2 Port F Data Register (PFDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — —
DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits
PF11DR to PF0DR correspond to pins PF11/BREQ/PULS7 to PF0/IRQ0.
When a pin functions as a general output, if a value is written to PFDR, that value is output
directly from the pin, and if PFDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PFDR is read the pin state, not the register value, is
returned directly. If a value is written to PFDR, although that value is written into PFDR it does
not affect the pin state. Table 17.12 summarizes port F data register read/write operations.
PFDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
Table 17.12 Port F Data Register (PFDR) Read/Write Operations
PFIOR Pin Function Read Write

0 General input Pin state Value is written to PFDR, but does not affect
pin state
Other than general Pin state Value is written to PFDR, but does not affect
input pin state
1 General output PFDR value Write value is output from pin
Other than general PFDR value Value is written to PFDR, but does not affect
output pin state
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17.8 Port G
Port G is an input/output port with the 16 pins shown in figure 17.7.
PG15 (input/output)/IRQ5 (input)/TIOB5 (input/output)

PG14 (input/output)/IRQ4 (input)/TIOA5 (input/output)
PG13 (input/output)/TIOD4 (input/output)
PG12 (input/output)/TIOC4 (input/output)
PG11 (input/output)/TIOB4 (input/output)
PG10 (input/output)/TIOA4 (input/output)
PG9 (input/output)/TIOD3 (input/output)
Port G PG8 (input/output)/RXD2 (input)
PG7 (input/output)/TXD2 (output)
PG6 (input/output)/RXD1 (input)
PG4 (input/output)/SCK1 (input/output)
PG3 (input/output)/RXD0 (input)
PG1 (input/output)/SCK0 (input/output)
PG0 (input/output)/ADTRG (input)/IRQOUT (output)
Figure 17.7 Port G
The port G register is shown in table 17.13.
Table 17.13 Port G Register

Port G data register PGDR R/W H'0000 H'FFFF83AE 8, 16
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17.8.2 Port G Data Register (PGDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits
PG15DR to PG0DR correspond to pins PG15/TIOB5/IRQ5 to PG0/ADTRG/IRQOUT.
When a pin functions as a general output, if a value is written to PGDR, that value is output
directly from the pin, and if PGDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PGDR is read the pin state, not the register value, is
returned directly. If a value is written to PGDR, although that value is written into PGDR it does
not affect the pin state. Table 17.14 summarizes port G data register read/write operations.
PGDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
Table 17.14 Port G Data Register (PGDR) Read/Write Operations
PGIOR Pin Function Read Write

0 General input Pin state Value is written to PGDR, but does not affect
pin state
Other than general Pin state Value is written to PGDR, but does not affect
input pin state
1 General output PGDR value Write value is output from pin
Other than general PGDR value Value is written to PGDR, but does not affect
output pin state
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17.9 Port H
Port H is an input port with the 16 pins shown in figure 17.8.
PH15 (input)/AN15 (input)

Port H PH8 (input)/AN8 (input)
Figure 17.8 Port H
The port H register is shown in table 17.15.
Table 17.15 Port H Register

Port H data register PHDR R Undefined H'FFFF83B6 8, 16
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17.9.2 Port H Data Register (PHDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PH15 PH14 PH13 PH12 PH11 PH10 PH9 PH8 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The port H data register (PHDR) is a 16-bit read-only register that stores port H data. Bits
PH15DR to PH0DR correspond to pins PH15/AN15 to PH0/AN0.
Writes to these bits are ignored, and do not affect the pin states. When these bits are read, the pin
state, not the register value, is returned directly. However, 1 will be returned while A/D converter
analog input is being sampled. Table 17.16 summarizes port H data register read/write operations.
PHDR is not initialized by a power-on reset, or in hardware standby mode, software standby
mode, or sleep mode. (The bits always reflect the pin states.)
Table 17.16 Port H Data Register (PHDR) Read/Write Operations
Pin Input/Output Pin Function Read Write

Input General input Pin state is read Ignored (does not affect pin state)
ANn 1 is read Ignored (does not affect pin state)
n = 0 to 15
17.10 POD (Port Output Disable)

The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0)
can be controlled by the POD (port output disable) pin input level. However, this function is
enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated
as general output ports.
Output buffer control by means of POD is performed asynchronously from bus cycles.
Address Bus Pins (A20 to A0) and Data Bus Pins (D15 to D0)
POD (when Designated as Output Ports)
0 Enabled (high-impedance)
1 Disabled (general output)
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Section 18 ROM (128 kB Version)
18.1 Features
The SH7050 has 128 kbytes of on-chip flash memory. The features of the flash memory are
summarized below.
• Four flash memory operating modes

 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Block erase (in single-block units) can be
performed. Erasing the entire memory requires erasure of each block in turn. Block erasing can
be performed as required on 1 kB, 28 kB, and 32 kB blocks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.).
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
With data transfer in boot mode, the SH7050’s bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Flash memory emulation in RAM
flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are two protect modes, hardware and software, which allow protected status to be
designated for flash memory program/erase/verify operations
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• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
18.2 Overview
Internal address bus
Internal data bus (32 bits)

Module bus
FLMCR1
FLMCR2 Operating FWE pin
Bus interface/controller
EBR1 mode Mode pin
RAMER
Flash memory
(128 kB)
Legend:
FLMCR1: Flash memory control register 1
EBR1: Erase block register 1
Figure 18.1 Block Diagram of Flash Memory
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18.2.2 Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
SH7050 enters one of the operating modes shown in figure 18.2. In user mode, flash memory can
be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
MD1 = 1, Reset state

FWE = 0
*1
RES = 0
User mode RES = 0
MD1 = 1, *2
RES = 0
FWE = 1
FWE = 1 FWE = 0 MD1 = 0, RES = 0

FWE = 1
Programmer
mode
*1
User
program mode
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. MD0 = 1, MD1 = 0, MD2 = 1, MD3 = 1
Figure 18.2 Flash Memory Mode Transitions
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18.2.3 On-Board Programming Modes
Boot Mode
1. Initial state 2. Programming control program transfer

The old program version or data remains written When boot mode is entered, the boot program in
in the flash memory. The user should prepare the the SH7050 (originally incorporated in the chip) is
programming control program and new started and the programming control program in
application program beforehand in the host. the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host Host
Programming control
program
New application New application
program program
SH7050 SH7050
SCI SCI
Boot program Boot program
Flash memory RAM Flash memory RAM
Boot program area
Application program Application program Programming control

(old version) (old version) program
3. Flash memory initialization 4. Writing new application program

The erase program in the boot program area (in The programming control program transferred
RAM) is executed, and the flash memory is from the host to RAM is executed, and the new
initialized (to H'FF). In boot mode, entire flash application program in the host is written into the
memory erasure is performed, without regard to flash memory.
blocks.
Host Host
New application
program
SH7050 SH7050
SCI SCI
Boot program area Boot program area
Flash memory Programming control New application Programming control

erase program program program
Program execution state
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User Program Mode
1. Initial state 2. Programming/erase control program transfer

The FWE assessment program that confirms that When user program mode is entered, user
user program mode has been entered, and the software confirms this fact, executes transfer
program that will transfer the programming/erase program in the flash memory, and transfers the
control program from flash memory to on-chip programming/erase control program to RAM.
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host
or in the flash memory.
Host Host
Programming/
erase control program
program program
SH7050 SH7050
SCI SCI

FWE assessment FWE assessment
program program
Transfer program Transfer program
Programming/
Application program Application program

(old version) (old version)

The programming/erase program in RAM is Next, the new application program in the host is
executed, and the flash memory is initialized (to written into the erased flash memory blocks. Do
H'FF). Erasing can be performed in block units, not write to unerased blocks.
but not in byte units.
Host Host
New application
program
SH7050 SH7050
SCI SCI

program program
Transfer program
Programming/ Programming/
erase control program erase control program
Flash memory New application

erase program
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18.2.4 Flash Memory Emulation in RAM
Emulation should be performed in user mode or user program mode. When the emulation block
set in RAMER is accessed while the emulation function is being executed, data written in the
overlap RAM is read.
User Mode
• User Program Mode
SCI
Flash memory RAM

Overlap RAM
(emulation is performed
on data written in RAM)
Application program
Execution state
Emulation block
When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and
writes should actually be performed to the flash memory.
When the programming control program is transferred to RAM, ensure that the transfer
destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to
be rewritten.
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SCI
Flash memory RAM
Overlap RAM
(programming data)
Programming control
program execution state
Application program
Programming data
18.2.5 Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode

Entire memory erase Yes Yes
Block erase No Yes
Programming control program* (2) (1) (2) (3)
(1) Erase/erase-verify
(2) Program/program-verify
(3) Emulation
Note: * To be provided by the user, in accordance with the recommended algorithm.
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18.2.6 Block Configuration
The flash memory is divided into three 32 kB blocks, one 28 kB blocks, and four 1 kB blocks.
Address H'00000
32 kB
32 kB
128 kB 32 kB
28 kB
1 kB
1 kB
1 kB
1 kB
Address H'1FFFF
18.3 Pin Configuration

The flash memory is controlled by means of the pins shown in table 18.1.
Table 18.1 Flash Memory Pins

Reset RES Input Reset
Flash memory enable FWE Input Flash program/erase protection by hardware
Mode 3 MD3 Input Sets SH7050 operating mode
Transmit data TxD1 Output Serial transmit data output
Receive data RxD1 Input Serial receive data input
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The registers used to control the on-chip flash memory when enabled are shown in table 18.2.
Table 18.2 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address Access Size

R/W* H'00*
1 3
Flash memory control FLMCR1 H'FFFF8580 8
register 1
R*
2
Flash memory control FLMCR2 H'00 H'FFFF8581 8
register 2
R/W* H'00*
1 4
Erase block register 1 EBR1 H'FFFF8582 8
Notes: FLMCR1, FLMCR2, and EBR1 are 8-bit registers, and RAMER is a 16-bit register.
Only byte accesses are valid for FLMCR1, FLMCR2, and EBR1, the access requiring 3
cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a
longword access.
When a longword write is performed on RAMER, 0 must always be written to the lower
word (address H'FFFF8630). Operation is not guaranteed if any other value is written.
1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.
2. A read in a mode in which on-chip flash memory is disabled will return H'00.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
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18.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by
setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase
mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting
the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby
mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low
level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
Writes to bits SWE, ESU, PSU, EV, and PV in FLMCR1 are enabled only when FWE = 1 and
SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit
only when FWE = 1, SWE = 1, and PSU = 1.
Bit: 7 6 5 4 3 2 1 0
FWE SWE ESU PSU EV PV E P
Initial value: 1/0 0 0 0 0 0 0 0
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7:
FWE Description
0 When a low level is input to the FWE pin (hardware-protected state) (Initial value)
1 When a high level is input to the FWE pin
Bit 6—Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should
be set before setting bits 5 to 0, and EBR1 bits 7 to 0.
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Bit 6:
SWE Description
0 Writes disabled (Initial value)
1 Writes enabled
[Setting condition]
When FWE = 1
Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU,
EV, PV, E, or P bit at the same time.
Bit 5:
ESU Description
0 Erase setup cleared (Initial value)
1 Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the
SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 4:
PSU Description
0 Program setup cleared (Initial value)
1 Program setup
[Setting condition]
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3:
EV Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
[Setting condition]
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Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the
SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2:
PV Description
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode
[Setting condition]
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,
PV, or P bit at the same time.
Bit 1:
E Description
0 Erase mode cleared (Initial value)
1 Transition to erase mode
[Setting condition]
When FWE = 1, SWE = 1, and ESU1 = 1
Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0:
P Description
0 Program mode cleared (Initial value)
1 Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU1 = 1
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FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection). FLMCR2 is initialized to H'00 by a reset, and in hardware standby
mode.
When on-chip flash memory is disabled, a read will return H'00.
Bit: 7 6 5 4 3 2 1 0
FLER — — — — — — —
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7:
FLER Description
0 Flash memory is operating normally. (Initial value)
Flash memory program/erase protection (error protection) is disabled.
Reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing.
Flash memory program/erase protection (error protection) is enabled.
[Setting condition]
See section 18.8.3, Error Protection.
Bits 6 to 0—Reserved: These bits are always read as 0.
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18.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by
block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby
mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin
and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Set only one bit in EBR1 (more than one bit
cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory block configuration is shown in table 18.3.
Bit: 7 6 5 4 3 2 1 0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Table 18.3 Flash Memory Erase Blocks
Block (Size) Address

EB0 (32 kB) H'000000–H'007FFF
EB1 (32 kB) H'008000–H'00FFFF
EB2 (32 kB) H'010000–H'017FFF
EB3 (28 kB) H'018000–H'01EFFF
EB4 (1 kB) H'01F000–H'01F3FF
EB5 (1 kB) H'01F400–H'01F7FF
EB6 (1 kB) H'01F800–H'01FBFF
EB7 (1 kB) H'01FC00–H'01FFFF
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RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode. (For details, see the description of the BSC.)
Flash memory area divisions are shown in table 18.4. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 2:
RAMS Description
0 Emulation not selected (Initial value)
Program/erase-protection of all flash memory blocks is disabled
1 Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 18.4.)
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Table 18.4 Flash Memory Area Divisions
Addresses Block Name RAMS RAM1 RAM0

H'FFE800–H'FFEBFF RAM area 1 kB 0 * *
H'01F000–H'01F3FF EB4 (1 kB) 1 0 0
H'01F400–H'01F7FF EB5 (1 kB) 1 0 1
H'01F800–H'01FBFF EB6 (1 kB) 1 1 0
H'01FC00–H'01FFFF EB7 (1 kB) 1 1 1
18.6 On-Board Programming Modes

When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
18.5. For a diagram of the transitions to the various flash memory modes, see figure 18.2.
Table 18.5 Setting On-Board Programming Modes
Mode PLL Multiple FWE MD3 MD2 MD1 MD0

Boot mode Expanded mode ×1 1 0 0 0 0
Single chip mode 0 0 0 1
Expanded mode ×2 0 1 0 0
User program Expanded mode ×1 1 0 0 1 0
mode Single chip mode 0 0 1 1
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18.6.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI to be used is set to channel asynchronous mode.
When a reset-start is executed after the SH7050 pins have been set to boot mode, the boot program
built into the SH7050 is started and the programming control program prepared in the host is
serially transmitted to the SH7050 via the channel 1 SCI. In the SH7050, the programming control
program received via the channel 1 SCI is written into the programming control program area in
on-chip RAM. After the transfer is completed, control branches to the start address of the
programming control program area and the programming control program execution state is
entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 18.3, and the boot mode execution
procedure in figure 18.4.
SH7050
Flash memory
Host Write data reception

RXD1
Verify data transmission SCI1 On-chip RAM
TXD1
Figure 18.3 System Configuration in Boot Mode
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Start
Set pins to boot mode

and execute reset-start
Host transfers data (H'00)

continuously at prescribed bit rate
SH7050 measures low period Host transmits number

of H'00 data transmitted by host of programming control program
bytes (N), upper byte followed
SH7050 calculates bit rate and by lower byte
sets value in bit rate register
SH7050 transmits received
After bit rate adjustment, SH7050 number of bytes to host as verify
transmits one H'00 data byte to data (echo-back)
host to indicate end of adjustment
n=1
Host confirms normal reception
of bit rate adjustment end Host transmits programming control
indication (H'00), and transmits program sequentially in byte units
one H'55 data byte
After receiving H'55,
programming control program to n+1→n
SH7050 transmits one H'AA
host as verify data (echo-back)
data byte to host
Transfer received programming
control program to on-chip RAM
No
n = N?
Yes
End of transmission
Check flash memory data, and

if data has already been written,
erase all blocks
After confirming that all flash

memory data has been erased,
SH7050 transmits one H'AA data
byte to host
Execute programming control

program transferred to on-chip RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 18.4 Boot Mode Execution Procedure
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Automatic SCI Bit Rate Adjustment
Start Stop
D0 D1 D2 D3 D4 D5 D6 D7
bit bit
Low period (9 bits) measured (H'00 data) High period

(1 or more bits)
When boot mode is initiated, the SH7050 measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7050 calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7050. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host’s transmission bit rate and the SH7050’s system clock
frequency, there will be a discrepancy between the bit rates of the host and the SH7050. To ensure
correct SCI operation, the host’s transfer bit rate should be set to 4800bps, 9600bps.
Table 18.6 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the SH7050 bit rate is possible. The boot program should be executed within this
system clock range.
Table 18.6 System Clock Frequencies for which Automatic Adjustment of SH7050 Bit Rate
is Possible
System Clock Frequency for which Automatic Adjustment

Host Bit Rate of SH7050 Bit Rate is Possible
9600bps 8 to 20MHz
4800bps 4 to 20MHz
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On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the programming control program is
transferred via the SCI, as shown in figure 18.5. The boot program area cannot be used until the
execution state in boot mode switches to the programming control program transferred from the
host.
H'FFFFE800
Boot program area
( 2 kbytes)
H'FFFFEFFF
Programming
control program area
(4 kbytes)
H'FFFFFFFF
Figure 18.5 RAM Areas in Boot Mode
Note: The boot program area cannot be used until a transition is made to the execution state for
the programming control program transferred to RAM. Note also that the boot program
remains in this area of the on-chip RAM even after control branches to the programming
control program.
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18.6.2 User Program Mode
After setting FWE, the user should branch to, and execute, the previously prepared
programming/erase control program.
As the flash memory itself cannot be read while flash memory programming/erasing is being
executed, the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Use the following procedure (figure 18.6) to execute the programming control program that writes
to flash memory (when transferred to RAM).
Write FWE assessment program

1 and transfer program
FWE = 1
2
(user program mode)
Transfer programming/erase
3
control program to RAM
Execute programming/
4 erase control program in RAM
(flash memory rewriting)
Execute user application

5
program
Figure 18.6 User Program Mode Execution Procedure
Note: When programming and erasing, start the watchdog timer so that measures can be taken to
prevent program runaway, etc. Memory cells may not operate normally if
overprogrammed or overerased due to program runaway.
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18.7 Programming/Erasing Flash Memory

A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(programming control program) that controls flash memory programming/erasing should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR1 is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming should be performed in the erased state. Do not perform additional
programming on previously programmed addresses.
18.7.1 Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 18.7 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a
time.
Following the elapse of 10 µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the program data area in RAM is written consecutively to the
program address (the lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60,
H'80, H'A0, H'C0, or H'E0). Thirty-two consecutive byte data transfers are performed. The
program address and program data are latched in the flash memory. A 32-byte data transfer must
be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSU bit in FLMCR1, and after the elapse of 50 µs or more, the
operating mode is switched to program mode by setting the P bit in FLMCR1. The time during
which the P bit is set is the flash memory programming time. Use a fixed 500 µs pulse for the
write time.
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18.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSUn bit is cleared at least 10 µs later). The watchdog timer is
cleared after the elapse of 10 µs or more, and the operating mode is switched to program-verify
mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of 4 µs or more. When the flash memory is read in this state (verify data is read in
32-bit units), the data at the latched address is read. Wait at least 2 µs after the dummy write
before performing this read operation. Next, the written data is compared with the verify data, and
reprogram data is computed (see figure 18.7) and transferred to the reprogram data area. After 32
bytes of data have been verified, exit program-verify mode, wait for at least 4 µs, then clear the
SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the
program/program-verify sequence as before. However, ensure that the program/program-verify
sequence is not repeated more than 400 times on the same bits.
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Start
Data writes must be performed in the memory-
Set SWE-bit of FLMCR1 erased state. Do not write additional data to an
address to which data is already written.
Wait 10 µs
Store 32 bytes write data in write *4

data area and rewrite data area
n=1
m=0
Successively write 32-byte data in rewrite data *1

area in RAM to flash memory
Enable WDT
Set PSU-bit of FLMCR1
Wait 50 µs
Set P-bit of FLMCR1 Write start
Wait 500 µs
Clear P-bit of FLMCR1 Write end
Wait 10 µs
Clear PSU-bit of FLMCR1

n←n+1
Wait 10 µs
Disable WDT
Set PV-bit of FLMCR1
Wait 4 µs
Perform dummy-write of H'FF to verify address
Wait 2 µs
Read verify data *2
Increment address
NG
Write data= Verify data?
OK m=1
Operate rewrite data *3
*4
Transfer rewrite data to rewrite data area
32 byte data
NG verify complete?
OK
Clear PV-bit of FLMCR1
RAM Wait 4 µs
Write data storage area
(32 byte) NG NG
m = 0? n ≥ 400?
Rewrite data storage area OK OK
(32 byte) Clear SWE bit of FLMCR1 Clear SWE bit of FLMCR1
Write end Write failure
Notes: 1. Transfer data in a byte unit. The lower eight bits of the start address to which data is written must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or
H'E0. Transfer 32-byte data even when writing fewer than 32 bytes. In this case, Set H'FF in unused addresses.
2. Read verify data in logword form (32 bits).
3. Even for bits to which data is already written, an additional write should be performed if their verify result is NG.
4. The write data storage area (32 bytes) and rewrite data storage area (32 bytes) must be located in RAM. The contents of the rewrite data storage
area are rewritten as writing progresses.
Source data (D) Verify data (V) Rewrite data (X) Description
0 0 1 Rewrite should not be performed to bits already written to.
0 1 0 Write is incomplete; rewrite should be performed.
1 0 1 —
1 1 1 Left in the erased state.
Figure 18.7 Program/Program-Verify Flowchart
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18.7.3 Erase Mode
To perform data or program erasure, set the 1 bit flash memory area to be erased in erase block
register 1 (EBR1) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1
(FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program
runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for erase mode
(erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of 200 µs or
more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time
during which the E bit is set is the flash memory erase time. Ensure that the erase time does not
exceed 5 ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all “0”) is not necessary before starting the erase procedure.
18.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit is cleared at least 10 µs later), the watchdog timer is cleared after the elapse of 10 µs or
more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1.
Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses
to be read. The dummy write should be executed after the elapse of 20 µs or more. When the flash
memory is read in this state (verify data is read in 32-bit units), the data at the latched address is
read. Wait at least 2 µs after the dummy write before performing this read operation. If the read
data has been erased (all “1”), a dummy write is performed to the next address, and erase-verify is
performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-
verify sequence in the same way. However, ensure that the erase/erase-verify sequence is not
repeated more than 60 times. When verification is completed, exit erase-verify mode, and wait for
at least 5 µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1.
If there are any unerased blocks, set 1 bit for the flash memory area to be erased, and repeat the
erase/erase-verify sequence in the same way.
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Start *1
Set SWE bit in FLMCR1
Wait 10 µs
n=1
Set EBR1 *3
WDT Enable
Set ESU-bit of FLMCR1
Wait 200 µs
Set E-bit of FLMCR1 Erase start
Wait 5ms
Clear E-bit of FLMCR1 Erase stop
Wait 10 µs
Clear ESU-bit of FLMCR1
Wait 10 µs
WDT Disable
Set EV-bit of FLMCR1
Wait 20 µs
n←n+1
Set top block address to verify address
Dummy write H'FF to verify address
Wait 2 µs
Address Read verify data *2

increment
NG
Verify data = all "1"?
OK
NG
Last block address?
OK
Clear EV-bit of FLMCR1 Clear EV-bit of FLMCR1
Wait 5 µs Wait 5 µs
*4 All
NG NG
objective blocks n ≥ 61?
erased?
OK OK
Clear SWE-bit in FLMCR1 Clear SWE-bit of FLMCR1
Erase complete Erase error
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 18.8 Erase/Erase-Verify Flowchart
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18.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
18.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1) and erase block register 1 (EBR1). The FLMCR1 and EBR1 settings are retained in
the error-protected state. (See table 18.7.)
Table 18.7 Hardware Protection
Functions
Item Description Program Erase
FWE pin protection • When a low level is input to the FWE pin, Yes Yes
FLMCR1 and EBR1 are initialized, and the
program/erase-protected state is entered.
Reset/standby • In a reset (including a WDT overflow Yes Yes
protection reset) and in standby mode, FLMCR1 and
EBR1 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section.
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18.8.2 Software Protection
Software protection can be implemented by setting erase block register 1 (EBR1) and the RAMS
bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P
or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program
mode or erase mode. (See table 18.8.)
Table 18.8 Software Protection
Functions
SWE pin protection • Clearing the SWE bit to 0 in FLMCR1 sets Yes Yes
the program/erase-protected state for all
blocks.
• (Execute in on-chip RAM or external
memory.)
Block specification • Erase protection can be set for individual — Yes
protection blocks by settings in erase block register 1
(EBR1).
• Setting EBR1 to H'00 places all blocks in
the erase-protected state.
Emulation protection • Setting the RAMS bit to 1 in the RAM Yes Yes
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
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18.8.3 Error Protection
In error protection, an error is detected when SH7050 runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the SH7050 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1 and EBR1 settings are retained,
but program mode or erase mode is aborted at the point at which the error occurred. Program
mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit
setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 18.9 shows the flash memory state transition diagram.
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Program mode Reset or standby

Erase mode RES = 0 or HSTBY = 0 (hardware protection)
RD VF PR ER FLER = 0 RD VF PR ER FLER = 0
RES = 0 or
Error occurrence HSTBY = 0 FLMCR1, EBR1
(software standby) initialization state
Error RES = 0 or
occurrence HSTBY = 0
Software Error protection mode

Error protection mode
standby mode (software standby)
Software standby
mode release
FLMCR1, EBR1
initialization state
Legend:
RD: Memory read possible RD: Memory read not possible
VF: Verify-read possible VF: Verify-read not possible
PR: Programming possible PR: Programming not possible
ER: Erasing possible ER: Erasing not possible
Figure 18.9 Flash Memory State Transitions
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18.9 Flash Memory Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped
onto the flash memory area so that data to be written to flash memory can be emulated in RAM in
real time. After the RAMER setting has been made, accesses cannot be made from the flash
memory area or the RAM area overlapping flash memory. Emulation can be performed in user
mode and user program mode. Figure 18.10 shows an example of emulation of real-time flash
memory programming.
Start emulation program
Set RAMER
Write tuning data to overlap

RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMER
Write to flash memory emulation

block
End of emulation program
Figure 18.10 Flowchart for Flash Memory Emulation in RAM
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H'000000
Flash memory
EB0 to EB3
This area can be accessed

H'01F000 from both the RAM area
EB4 and flash memory area
H'01F400
EB5
H'01F800
EB6
H'01FC00
H'01FFFF EB7
H'FFFFE800
H'FFFFEBFF
On-chip RAM
Figure 18.11 Example of RAM Overlap Operation
Example in Which Flash Memory Block Area (EB4) is Overlapped
1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 1, to overlap part of RAM onto the
area (EB4) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB4).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM1 and RAM0 (emulation protection). In this state,
setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a
transition to program mode or erase mode. When actually programming a flash
memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
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18.10 Note on Flash Memory Programming/Erasing

In the on-board programming modes (user mode and user program mode), NMI input should be
disabled to give top priority to the program/erase operations (including RAM emulation).
18.11 Flash Memory Programmer Mode

Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, flash memory read mode, auto-program mode, auto-
erase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and
status read mode, a status polling procedure is used, and in status read mode, detailed internal
signals are output after execution of an auto-program or auto-erase operation.
In programmer mode, set the mode pins to PLLx2 mode (see table 18.9) and input a 6 MHz input
clock, so that the SH7050 runs at 12 MHz.
Table 18.9 shows the pin settings for programmer mode. For the pin names in programmer mode,
see section 1.3.3, Pin Assignments.
Table 18.9 PROM Mode Pin Settings
Pin Names Settings

Mode pins: MD3, MD2, MD1, MD0 1101 (PLL × 2)
FWE pin High level input (in auto-program and auto-erase
modes)
RES pin Power-on reset circuit
XTAL, EXTAL, PLLVCC, PLLCAP, Oscillator circuit
PLLVSS pins
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18.11.1 Socket Adapter Pin Correspondence Diagram
Connect the socket adapter to the chip as shown in figure 18.13. This will enable conversion to a
32-pin arrangement. The on-chip ROM memory map is shown in figure 18.12, and the socket
adapter pin correspondence diagram in figure 18.13.
Addresses in Addresses in
MCU mode programmer mode
H'00000000 H'00000
On-chip ROM space

128 kB
H'0001FFFF H'1FFFF
Figure 18.12 On-Chip ROM Memory Map
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SH7050 (128 kB Version) Socket Adapter HN28F101P (32 Pins)

Pin No. Pin Name (Conversion to 32-Pin Pin No. Pin Name
Arrangement)
118 FWE 1 FWE
112 A9 26 A9
38 A16 2 A16
36 A15 3 A15
42 WE 31 WE
85 D0 13 I/O0
86 D1 14 I/O1
87 D2 15 I/O2
88 D3 17 I/O3
90 D4 18 I/O4
92 D5 19 I/O5
93 D6 20 I/O6
94 D7 21 I/O7
17 A0 12 A0
18 A1 11 A1
19 A2 10 A2
20 A3 9 A3
22 A4 8 A4
24 A5 7 A5
25 A6 6 A6
26 A7 5 A7
27 A8 27 A8
28 OE 24 OE
30 A10 23 A10
32 A11 25 A11
33 A12 4 A12
34 A13 28 A13
35 A14 29 A14
41 CE 22 CE
1, 2, 5, 13, 21, 29, 37, 47, 55, 32 VCC
72, 79, 89, 97, 105, 109, 111, VCC 16 VSS
113, 120, 124, 130, 142, 149, 30 A17
150, 158
7, 15, 23, 31, 39, 49, 57, 64, Legend:
FWE: Flash write enable
70, 81, 91, 99, 107, 115, 119, VSS
I/O7–I/O0: Data input/output
136, 144, 152, 164
A17–A0: Address input
40 A17 OE: Output enable
126 RES Power-on reset circuit CE: Chip enable
108 XTAL WE: Write enable
Oscillator circuit
110 EXTAL
121 PLLVCC
122 PLLCAP PLL circuit
123 PLLVSS
Other than the above N.C.(OPEN)
Note: Use address pin A17 as VSS.
Figure 18.13 Socket Adapter Pin Correspondence Diagram
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18.11.2 Programmer Mode Operation
Table 18.10 shows how the different operating modes are set when using programmer mode, and
table 18.11 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode

Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-programming.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the D6 signal. In status read mode, error information is output if an error
occurs.
Table 18.10 Settings for Various Operating Modes In Programmer Mode
Pin Names
Mode FWE CE OE WE D0–D7 A0–A17
Read H or L L L H Data output Ain
Output disable H or L L H H Hi-z X
Command write H or L L H L Data input *Ain
Chip disable H or L H X X Hi-z X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. *Ain indicates that there is also address input in auto-program mode.
3. For command writes in auto-program and auto-erase modes, input a high level to the
FWE pin.
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Table 18.11 Programmer Mode Commands
1st Cycle 2nd Cycle

Number
Command Name of Cycles Mode Address Data Mode Address Data
Memory read mode 1+n Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 Write X H'20
Status read mode 2 Write X H'71 Write X H'71
Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
18.11.3 Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the

command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. Once memory read mode has been entered, consecutive reads can be performed.
4. After powering on, memory read mode is entered.
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Table 18.12 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes

Command write cycle tnxtc 20 µs
CE hold time tceh 0 ns
CE setup time tces 0 ns
Data hold time tdh 50 ns
Data setup time tds 50 ns
Write pulse width twep 70 ns
WE rise time tr 30 ns
WE fall time tf 30 ns
Command write Memory read mode
A16–A0 Address stable
tces tceh tnxtc
CE
OE
twep
tf tr
WE
tds tdh
I/O7–I/O0
Note: Data is latched on the rising edge of WE.
Figure 18.14 Timing Waveforms for Memory Read after Memory Write
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Table 18.13 AC Characteristics in Transition from Memory Read Mode to Another Mode

Memory read mode Other mode command write
tnxtc tces tceh
CE
OE
twep
tf tr
WE
tds tdh
I/O7–I/O0
Note: Do not enable WE and OE at the same time.
Figure 18.15 Timing Waveforms in Transition from Memory Read Mode to Another Mode
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Table 18.14 AC Characteristics in Memory Read Mode

Access time tacc 20 µs
CE output delay time tce 150 ns
OE output delay time toe 150 ns
Output disable delay time tdf 100 ns
Data output hold time toh 5 ns
A16–A0 Address stable Address stable
CE VIL
OE VIL
WE VIH tacc tacc

toh toh
I/O7–I/O0
Figure 18.16 CE and OE Enable State Read Timing Waveforms
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tce tce
CE
toe toe
OE
WE VIH tacc tacc

tdf
tdf toh
toh
I/O7–I/O0
Figure 18.17 CE and OE Clock System Read Timing Waveforms
18.11.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
3. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
4. Memory address transfer is performed in the third cycle (figure 18.13). Do not perform transfer
after the second cycle.
5. Do not perform a command write during a programming operation.
6. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
7. Confirm normal end of auto-programming by checking D6. Alternatively, status read mode
can also be used for this purpose (D7 status polling uses the auto-program operation end
identification pin).
8. Status polling D6 and D7 pin information is retained until the next command write. As long as
the next command write has not been performed, reading is possible by enabling CE and OE.
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Table 18.15 AC Characteristics in Auto-Program Mode

Status polling start time twsts 1 ms
Status polling access time tspa 150 ns
Address setup time tas 0 ns
Address hold time tah 60 ns
Memory write time twrite 1 3000 ms
Write setup time tpns 100 ns
Write end setup time tpnh 100 ns
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FWE
tpnh
Address
A16–A0 stable
tpns tces tceh tnxtc tnxtc
CE
OE twep
tf tr tas tah twsts tspa
WE
Data transfer
tds tdh twrite
1 to 128byte
I/O7 Write operation complete verify signal
I/O6 Write normal complete verify signal
I/O5–I/O0 H'40 H'00
Figure 18.18 Auto-Program Mode Timing Waveforms
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18.11.5 Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.

2. Do not perform a command write during auto-erasing..
3. Confirm normal end of auto-erasing by checking D6. Alternatively, status read mode can also
be used for this purpose (D7 status polling uses the auto-erase operation end identification
pin).
Table 18.16 AC Characteristics in Auto-Erase Mode

Status polling start time tests 1 ms
Memory erase time terase 100 40000 ms
Erase setup time tens 100 ns
Erase end setup time tenh 100 ns
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FWE
tenh
A16–A0
tens tces tceh tnxtc tnxtc
CE
OE twep
tf tr tests tspa
WE
tds tdh terase
I/O7 Erase complete

verify signal
I/O6 Erase normal

complete
verify signal
I/O5–I/O0 H'20 H'20 H'00
Figure 18.19 Auto-Erase Mode Timing Waveforms
18.11.6 Status Read Mode
1. Status read mode is provided to specify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
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Table 18.17 AC Characteristics in Status Read Mode

Read time after command write tstrd 20 µs
Disable delay time tdf 100 ns
A16–A0
tces tceh tnxtc tces tceh tnxtc tnxtc
CE
tce
OE twep twep
tf tr tf tr toe
WE
tdf
tds tdh tds tdh
I/O7–I/O0 H'71 H'71
Note: I/O2 and I/O3 are undefined.
Figure 18.20 Status Read Mode Timing Waveforms
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Table 18.18 Status Read Mode Return Commands

Pin Name D7 D6 D5 D4 D3 D2 D1 D0
Attribute Normal Command Program- Erase — — Program- Effective
end error ming error error ming or address
identification erase count error
exceeded
Initial value 0 0 0 0 0 0 0 0
Indications Normal Command Program- Erasing — — Count Effective
end: 0 Error: 1 ming Error: 1 exceeded: 1 address
Abnormal Otherwise: 0 Error: 1 Otherwise: 0 Otherwise: 0 Error: 1
end: 1 Otherwise: 0 Otherwise: 0
Note: D2 and D3 are undefined at present.
18.11.7 Status Polling
1. D7 status polling is a flag that indicates the operating status in auto-program/auto-erase mode.
2. D6 status polling is a flag that indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 18.19 Status Polling Output Truth Table
During Internal
Pin Name Operation Abnormal End Normal End
D7 0 1 0 1
D6 0 0 1 1
D0–D5 0 0 0 0
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18.11.8 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 18.20 Stipulated Transition Times to Command Wait State

Standby release (oscillation tosc1 10 ms
stabilization time)
Programmer mode setup time tbmv 10 ms
VCC hold time tdwn 0 ms
Memory read
mode Command wait state
Command Automatic write mode Normal/abnormal
wait state Automatic erase mode complete verify
tOSC1 tbmv tdwn
VCC
RES
FWE
Note : For the level of FWE input pin, set VIL when using other than the automatic write mode
and automatic erase mode.
Figure 18.21 Oscillation Stabilization Time, Boot Program Transfer Time,

and Power-Down Sequence
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18.11.9 Notes On Memory Programming
1. When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
2. When performing programming using PROM mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Additional programming cannot be performed on previously programmed address
blocks.
18.12 Notes when Converting the F-ZTAT Application Software to the

Mask-ROM Versions
Please note the following when converting the F-ZTAT application software to the mask-ROM
versions.
The values read from the internal registers for the flash ROM of the mask-ROM version and F-
ZTAT version differ as follows.
Status
Register Bit F-ZTAT Version Mask-ROM Version
FLMCR1 FWE 0: Application software running 0: Is not read out
1: Programming 1: Application software running
Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have
different ROM size.
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19.1 Features
The SH7051 has 256 kbytes of on-chip flash memory. The features of the flash memory are
summarized below.
• Four flash memory operating modes

 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Block erase (in single-block units) can be
performed. Block erasing can be performed as required on 1 kB, 28 kB, and 32 kB blocks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.).
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
With data transfer in boot mode, the SH7050’s bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are two protect modes, hardware and software, which allow protected status to be
designated for flash memory program/erase/verify operations
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
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19.2 Overview
Internal address bus

Module bus
FLMCR1
FLMCR2 Operating FWE pin
Bus interface/controller
EBR1 mode Mode pin
EBR2
RAMER
Flash memory
(256 kB)
Legend:
Figure 19.1 Block Diagram of Flash Memory
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19.2.2 Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
SH7050 enters one of the operating modes shown in figure 19.2. In user mode, flash memory can
be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
MD1 = 1, Reset state

FWE = 0
*1
RES = 0
User mode RES = 0
MD1 = 1, *2
RES = 0
FWE = 1
FWE = 1 FWE = 0 MD1 = 0, RES = 0

FWE = 1
Programmer
mode
*1
User
program mode
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. MD0 = 1, MD1 = 0, MD2 = 1, MD3 = 1
Figure 19.2 Flash Memory Mode Transitions
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19.2.3 On-Board Programming Modes
Boot Mode
1. Initial state 2. Programming control program transfer

The old program version or data remains written When boot mode is entered, the boot program in
in the flash memory. The user should prepare the the SH7051 (originally incorporated in the chip) is
programming control program and new started and the programming control program in
application program beforehand in the host. the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host Host
Programming control
program
program program
SH7051 SH7051
SCI SCI
Boot program area
Application program Application program Programming control

(old version) (old version) program

The erase program in the boot program area (in The programming control program transferred
RAM) is executed, and the flash memory is from the host to RAM is executed, and the new
initialized (to H'FF). In boot mode, total flash application program in the host is written into the
memory erasure is performed, without regard to flash memory.
blocks.
Host Host
New application
program
SH7051 SH7051
SCI SCI
Flash memory ÅqRAMÅr Flash memory RAM
Boot program area Boot program area

Flash memory
Programming control New application Programming control
preprogramming program program
program
erase
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User Program Mode
1. Initial state 2. Programming/erase control program transfer

The FWE assessment program that confirms that When user program mode is entered, user
user program mode has been entered, and the software confirms this fact, executes transfer
program that will transfer the programming/erase program in the flash memory, and transfers the
control program from flash memory to on-chip programming/erase control program to RAM.
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host
or in the flash memory.
Host Host
Programming/
program program
SH7051 SH7051
SCI SCI

program program
Transfer program Transfer program
Programming/
Application program Application program

(old version) (old version)

The programming/erase program in RAM is Next, the new application program in the host is
executed, and the flash memory is initialized (to written into the erased flash memory blocks. Do
H'FF). Erasing can be performed in block units, not write to unerased blocks.
but not in byte units.
Host Host
New application
program
SH7051 SH7051
SCI SCI

program program
Transfer program
Programming/ Programming/
erase control program erase control program
Flash memory New application

erase program
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19.2.4 Flash Memory Emulation in RAM
Emulation should be performed in user mode or user program mode. When the emulation block
set in RAMER is accessed while the emulation function is being executed, data written in the
overlap RAM is read.
User Mode
SCI
Flash memory RAM

Overlap RAM
(emulation is performed
on data written in RAM)
Application program
Execution state
Emulation block
When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and
writes should actually be performed to the flash memory.
When the programming control program is transferred to RAM, ensure that the transfer
destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to
be rewritten.
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SCI
Flash memory RAM
Overlap RAM
(programming data)
Programming control
program execution state
Application program
Programming data
19.2.5 Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode

Total erase Yes No
Block erase No Yes
Programming control program* (2) (1) (2) (3)
(1) Erase/erase-verify
(2) Program/program-verify
(3) Emulation
Note: * To be provided by the user, in accordance with the recommended algorithm.
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19.2.6 Block Configuration
The flash memory is divided into seven 32 kB blocks, one 28 kB blocks, and four 1 kB blocks.
Address H'00000
32 kB
32 kB
32 kB
32 kB
256 kB 32 kB
32 kB
32 kB
28 kB
1 kB
1 kB
1 kB
1 kB
Address H'3FFFF
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19.3 Pin Configuration

The flash memory is controlled by means of the pins shown in table 19.1.
Table 19.1 Flash Memory Pins

Reset RES Input Reset
Flash memory enable FWE Input Flash program/erase protection by hardware
Transmit data TxD1 Output Serial transmit data output
Receive data RxD1 Input Serial receive data input
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The registers used to control the on-chip flash memory when enabled are shown in table 19.2.
Table 19.2 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address Access Size

R/W* H'00*
1 2
register 1
R/W* H'00*
1 3
register 2
R/W* H'00*
1 3
R/W* H'00*
1 3
Notes: FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit register.
Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access
requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6
cycles for a longword access.
When a longword write is performed on RAMER, 0 must always be written to the lower
word (address H'FFFF8630). Operation is not guaranteed if any other value is written.
1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
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or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 when FWE
= 1, then setting the EV1 or PV1 bit. Program mode for addresses H'00000 to H'1FFFF is entered
by setting SWE to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase
mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 when FWE = 1, then
setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in
hardware standby mode and software standby mode. Its initial value is H'80 when a high level is
input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled,
a read will return H'00, and writes are invalid.
Writes to bits SWE, ESU1, PSU1, EV1, and PV1 in FLMCR1 are enabled only when FWE = 1
and SWE = 1; writes to the E1 bit only when FWE = 1, SWE = 1, and ESU1 = 1; and writes to the
P1 bit only when FWE = 1, SWE = 1, and PSU1 = 1.
Bit: 7 6 5 4 3 2 1 0
FWE SWE ESU1 PSU1 EV1 PV1 E1 P1
Initial value: 1/0 0 0 0 0 0 0 0
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7:
FWE Description
0 When a low level is input to the FWE pin (hardware-protected state)
1 When a high level is input to the FWE pin
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Bit 6—Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should
be set when setting bits 5 to 0, FLMCR2 bits 5 to 0, EBR1 bits 3 to 0, and EBR2 bits 7 to 0.
Bit 6:
SWE Description
0 Writes disabled (Initial value)
1 Writes enabled
[Setting condition]
When FWE = 1
Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode (applicable addresses:
H'00000 to H'1FFFFF). Do not set the SWE, PSU1, EV1, PV1, E1, or P1 bit at the same time.
Bit 5:
ESU1 Description
1 Erase setup
[Setting condition]
Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode (applicable
addresses: H'00000 to H'1FFFFF). Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the
same time.
Bit 4:
PSU1 Description
1 Program setup
[Setting condition]
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Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing (applicable

addresses: H'00000 to H'1FFFFF). Do not set the SWE, ESU1, PSU1, PV1, E1, or P1 bit at the
same time.
Bit 3:
EV1 Description
[Setting condition]
Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing (applicable

addresses: H'00000 to H'1FFFFF). (Do not set the SWE, ESU1, PSU1, EV1, E1, or P1 bit at the
same time.
Bit 2:
PV1 Description
[Setting condition]
Bit 1—Erase 1 (E1): Selects erase mode transition or clearing (applicable addresses: H'00000 to
H'1FFFFF). Do not set the SWE, ESU1, PSU1, EV1, PV1, or P1 bit at the same time.
Bit 1:
E1 Description
[Setting condition]
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Bit 0—Program 1 (P1): Selects program mode transition or clearing (applicable addresses:
H'00000 to H'1FFFFF). Do not set the SWE, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Bit 0:
P1 Description
[Setting condition]
or erase-verify mode for addresses H'20000 to H'3FFFF is entered by setting SWE (FLMCR1) to
1 when FWE (FLMCR1) = 1, then setting the EV2 or PV2 bit. Program mode for addresses
H'20000 to H'3FFFF is entered by setting SWE (FLMCR1) to 1 when FWE (FLMCR1) = 1, then
setting the PSU2 bit, and finally setting the P2 bit. Erase mode for addresses H'20000 to H'3FFFF
is entered by setting SWE (FLMCR1) to 1 when FWE (FLMCR1) = 1, then setting the ESU2 bit,
and finally setting the E2 bit. FLMCR2 is initialized to H'00 by a reset, in hardware standby mode
and software standby mode, when a low level is input to the FWE pin, and when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set (the exception is the FLER bit, which
is initialized only by a reset and in hardware standby mode). When on-chip flash memory is
disabled, a read will return H'00, and writes are invalid.
Writes to bits SWE, ESU2, PSU2, EV2, and PV2 in FLMCR2 are enabled only when FWE
(FLMCR1) = 1 and SWE (FLMCR1) = 1; writes to the E2 bit only when FWE (FLMCR1) = 1,
SWE (FLMCR1) = 1, and ESU2 = 1; and writes to the P2 bit only when FWE (FLMCR1) = 1,
SWE (FLMCR1) = 1, and PSU2 = 1.
Bit: 7 6 5 4 3 2 1 0
FLER — ESU2 PSU2 EV2 PV2 E2 P2
R/W: R R R/W R/W R/W R/W R/W R/W
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Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7:
FLER Description
0 Flash memory is operating normally. (Initial value)
Flash memory program/erase protection (error protection) is disabled.
Reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing.
Flash memory program/erase protection (error protection) is enabled.
[Setting condition]
See section 19.8.3, Error Protection.
Bit 6—Reserved: This bit is always read as 0.
Bit 5—Erase Setup Bit 2 (ESU2): Prepares for a transition to erase mode (applicable addresses:
H'20000 to H'3FFFF). Do not set the PSU2, EV2, PV2, E2, or P2 bit at the same time.
Bit 5:
ESU2 Description
1 Erase setup
[Setting condition]
Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode (applicable
addresses: H'20000 to H'3FFFF). Do not set the ESU2, EV2, PV2, E2, or P2 bit at the same time.
Bit 4:
PSU2 Description
1 Program setup
[Setting condition]
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Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing (applicable

addresses: H'20000 to H'3FFFF). Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time.
Bit 3:
EV2 Description
[Setting condition]
Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or clearing (applicable

addresses: H'20000 to H'3FFFF). Do not set the ESU2, PSU2, EV2, E2, or P2 bit at the same time.
Bit 2:
PV2 Description
[Setting condition]
Bit 1—Erase 2 (E2): Selects erase mode transition or clearing (applicable addresses: H'20000 to
H'3FFFF). Do not set the ESU2, PSU2, EV2, PV2, or P2 bit at the same time.
Bit 1:
E2 Description
[Setting condition]
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Bit 0—Program 2 (P2): Selects program mode transition or clearing (applicable addresses:
H'20000 to H'3FFFF). Do not set the ESU2, PSU2, EV2, PV2, or E2 bit at the same time.
Bit 0:
P2 Description
[Setting condition]
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit. When on-chip flash memory is disabled, a read will return H'00, and writes
are invalid.
Bit: 7 6 5 4 3 2 1 0
— — — — EB3 EB2 EB1 EB0
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EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit. When on-chip flash memory is disabled, a read will return H'00, and writes
are invalid.
Bit: 7 6 5 4 3 2 1 0
EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4
Table 19.3 Flash Memory Erase Blocks
Block (Size) Address

EB0 (32 kB) H'000000–H'007FFF
EB1 (32 kB) H'008000–H'00FFFF
EB2 (32 kB) H'010000–H'017FFF
EB3 (32 kB) H'018000–H'01FFFF
EB4 (32 kB) H'020000–H'027FFF
EB5 (32 kB) H'028000–H'02FFFF
EB6 (32 kB) H'030000–H'037FFF
EB7 (28 kB) H'038000–H'03EFFF
EB8 (1 kB) H'03F000–H'03F3FF
EB9 (1 kB) H'03F400–H'03F7FF
EB10 (1 kB) H'03F800–H'03FBFF
EB11 (1 kB) H'03FC00–H'03FFFF
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RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode. (For details, see the description of the BSC.)
Flash memory area divisions are shown in table 19.4. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit: 15 14 13 12 11 10 9 8
— — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 2:
RAMS Description
0 Emulation not selected (Initial value)
Program/erase-protection of all flash memory blocks is disabled
Program/erase-protection of all flash memory blocks is enabled
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Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 19.4.)
Table 19.4 Flash Memory Area Divisions
Addresses Block Name RAMS RAM1 RAM0

H'FFD800–H'FFDBFF RAM area 1 kB 0 * *
H'03F000–H'03F3FF EB8 (1 kB) 1 0 0
H'03F400–H'03F7FF EB9 (1 kB) 1 0 1
H'03F800–H'03FBFF EB10 (1 kB) 1 1 0
H'03FC00–H'03FFFF EB11 (1 kB) 1 1 1
19.6 On-Board Programming Modes

When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
19.5. For a diagram of the transitions to the various flash memory modes, see figure 19.2.
Table 19.5 Setting On-Board Programming Modes
Mode PLL Multiple FWE MD3 MD2 MD1 MD0

Boot mode Expanded mode ×1 1 0 0 0 0
User program Expanded mode ×1 1 0 0 1 0
mode Single chip mode 0 0 1 1
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19.6.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI to be used is set to channel asynchronous mode.
When a reset-start is executed after the SH7051 pins have been set to boot mode, the boot program
built into the SH7051 is started and the programming control program prepared in the host is
serially transmitted to the SH7051 via the channel 1 SCI. In the SH7051, the programming control
program received via the channel 1 SCI is written into the programming control program area in
on-chip RAM. After the transfer is completed, control branches to the start address of the
programming control program area and the programming control program execution state is
entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 19.3, and the boot mode execution
procedure in figure 19.4.
SH7051
Flash memory
Host Write data reception

RXD1
Verify data transmission SCI1 On-chip RAM
TXD1
Figure 19.3 System Configuration in Boot Mode
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Start
Set pins to boot mode

and execute reset-start
Host transfers data (H'00)

continuously at prescribed bit rate
SH7051 measures low period Host transmits number

of H'00 data transmitted by host of programming control program
bytes (N), upper byte followed
SH7051 calculates bit rate and by lower byte
sets value in bit rate register
After bit rate adjustment, SH7051 number of bytes to host as verify
transmits one H'00 data byte to data (echo-back)
host to indicate end of adjustment
n=1
Host confirms normal reception
of bit rate adjustment end Host transmits programming control
indication (H'00), and transmits program sequentially in byte units
one H'55 data byte
After receiving H'55,
programming control program to n+1→n
SH7051 transmits one H'AA
host as verify data (echo-back)
data byte to host
Transfer received programming
control program to on-chip RAM
No
n = N?
Yes
End of transmission
Check flash memory data, and

if data has already been written,
erase all blocks
After confirming that all flash

memory data has been erased,
SH7051 transmits one H'AA data
byte to host
Execute programming control

program transferred to on-chip RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 19.4 Boot Mode Execution Procedure
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Automatic SCI Bit Rate Adjustment
Start Stop
D0 D1 D2 D3 D4 D5 D6 D7
bit bit
Low period (9 bits) measured (H'00 data) High period

(1 or more bits)
When boot mode is initiated, the SH7051 measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7051 calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7051. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host’s transmission bit rate and the SH7051’s system clock
frequency, there will be a discrepancy between the bit rates of the host and the SH7051. To ensure
correct SCI operation, the host’s transfer bit rate should be set to 4800bps, 9600bps.
Table 19.6 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the SH7051 bit rate is possible. The boot program should be executed within this
system clock range.
Table 19.6 System Clock Frequencies for which Automatic Adjustment of SH7051 Bit Rate
is Possible
System Clock Frequency for which Automatic Adjustment

Host Bit Rate of SH7051 Bit Rate is Possible
9600bps 8 to 20MHz
4800bps 4 to 20MHz
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On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the programming control program is
transferred via the SCI, as shown in figure 19.5. The boot program area cannot be used until the
execution state in boot mode switches to the programming control program transferred from the
host.
H'FFFFD800
Boot program area
( 2 kbytes)
H'FFFFDFFF
Programming
control program area
(8 kbytes)
H'FFFFFFFF
Figure 19.5 RAM Areas in Boot Mode
Note: The boot program area cannot be used until a transition is made to the execution state for
the programming control program transferred to RAM. Note also that the boot program
remains in this area of the on-chip RAM even after control branches to the programming
control program.
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19.6.2 User Program Mode
After setting FWE, the user should branch to, and execute, the previously prepared
programming/erase control program.
As the flash memory itself cannot be read while flash memory programming/erasing is being
executed, the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Use the following procedure (figure 19.6) to execute the programming control program that writes
to flash memory (when transferred to RAM).
Write FWE assessment program

1 and transfer program
FWE = 1
2
(user program mode)
Transfer programming/erase
3
control program to RAM
Execute programming/
4 erase control program in RAM
(flash memory rewriting)
Execute user application

5
program
Figure 19.6 User Program Mode Execution Procedure
Note: When programming and erasing, start the watchdog timer so that measures can be taken to
prevent program runaway, etc. Memory cells may not operate normally if
overprogrammed or overerased due to program runaway.
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19.7 Programming/Erasing Flash Memory

A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'00000 to
H'1FFFF, or the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2 for addresses H'20000 to
H'3FFFF.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(programming control program) that controls flash memory programming/erasing should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1, or the ESU2, PSU2, EV2, PV2, E2, and P2 bits in
FLMCR2, is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming should be performed in the erased state. Do not perform additional
programming on previously programmed addresses.
4. Do not program addresses H'00000 to H'1FFFF and H'20000 to H'3FFFF
simultaneously. Operation is not guaranteed if this is done.
19.7.1 Program Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for Addresses

H'20000 to H'3FFFF)
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 19.7 should be followed. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a
time.
Following the elapse of 10 µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the program data area in RAM is written consecutively to the
program address (the lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60,
H'80, H'A0, H'C0, or H'E0). Thirty-two consecutive byte data transfers are performed. The
program address and program data are latched in the flash memory. A 32-byte data transfer must
be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra addresses.
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Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSUn bit in FLMCRn, and after the elapse of 50 µs or more, the
operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during
which the Pn bit is set is the flash memory programming time. Use a fixed 500 µs pulse for the
write time.
19.7.2 Program-Verify Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for

Addresses H'20000 to H'3FFFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared, then the PSUn bit is cleared at least 10 µs later). The watchdog timer is
cleared after the elapse of 10 µs or more, and the operating mode is switched to program-verify
mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of 4 µs or more. When the flash memory is read in this state (verify data is read in
32-bit units), the data at the latched address is read. Wait at least 2 µs after the dummy write
before performing this read operation. Next, the written data is compared with the verify data, and
reprogram data is computed (see figure 19.7) and transferred to the reprogram data area. After 32
bytes of data have been verified, exit program-verify mode, wait for at least 4 µs, then clear the
SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the
program/program-verify sequence as before. However, ensure that the program/program-verify
sequence is not repeated more than 400 times on the same bits.
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Start
Data writes must be performed in the memory-
Set SWE-bit of FLMCR1 erased state. Do not write additional data to an
address to which data is already written.
Wait 10 µs
Store 32 bytes write data in write *4

data area and rewrite data area
n=1
m=0
Successively write 32-byte data in rewrite data *1

area in RAM to flash memory
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Wait 50 µs
Set P1 (2) bit in FLMCR1 (2) Write start
Wait 500 µs
Clear P1 (2) bit in FLMCR1 (2) Write end
Wait 10 µs
Clear PSU1 (2) bit in FLMCR1 (2)

n←n+1
Wait 10 µs
Disable WDT
Set PV1 (2) bit of FLMCR1 (2)
Wait 4 µs
Perform dummy-write H'FF to verify address
Wait 2 µs
Read verify data *2
Increment address
NG
Write data= Verify data?
OK m=1
Operate rewrite data *3
*4
Transfer rewrite data to rewrite data area
32 byte data
NG verify complete?
OK
Clear PV1 (2) bit of FLMCR1 (2)
RAM
Wait 4 µs
Write data storage area
(32 byte) NG NG
m = 0? n ≥ 400?
OK OK
Rewrite data storage area
(32 byte) Clear SWE bit om FLMCR1 Clear SWE bit in FLMCR1
Write end Write failure
Notes: 1. Transfer data in a byte unit. The lower eight bits of the start address to which data is written must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0.
Transfer 32-byte data even when writing fewer than 32 bytes. In this case, Set H'FF in unused addresses.
2. Read verify data in logword form (32 bits).
3. Even for bits to which data is already written, an additional write should be performed if their verify result is NG.
4. The write data storage area (32 bytes) and rewrite data storage area (32 bytes) must be located in RAM. The contents of the rewrite data storage area are
rewritten as writing progresses.
Source data (D) Verify data (V) Rewrite data (X) Description
0 0 1 Rewrite should not be performed to bits already written to.
0 1 0 Write is incomplete; rewrite should be performed.
1 0 1 —
1 1 1 Left in the erased state.
Figure 19.7 Program/Program-Verify Flowchart
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19.7.3 Erase Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for Addresses H'20000
to H'3FFFF)
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.8 should be
followed.
To perform data or program erasure, set the flash memory area to be erased in erase block register
n (EBRn) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1
(FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program
runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for erase mode
(erase setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of 200 µs or
more, the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time
during which the En bit is set is the flash memory erase time. Ensure that the erase time does not
exceed 5 ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all “0”) is not necessary before starting the erase procedure.
19.7.4 Erase-Verify Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for Addresses

H'20000 to H'3FFFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of a the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then
the ESUn bit is cleared at least 10 µs later), the watchdog timer is cleared after the elapse of 10 µs
or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in
FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of 20 µs or more.
When the flash memory is read in this state (verify data is read in 32-bit units), the data at the
latched address is read. Wait at least 2 µs after the dummy write before performing this read
operation. If the read data has been erased (all “1”), a dummy write is performed to the next
address, and erase-verify is performed. The erase-verify operation is carried out on all the erase
blocks; the erase block register bit for an erased block should be cleared to prevent excessive
application of the erase voltage. When verification is completed, exit erase-verify mode, and wait
for at least 5 µs. If erasure has been completed on all the erase blocks after completing erase-verify
operations on all these blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, set
erase mode again, and repeat the erase/erase-verify sequence as before. However, ensure that the
erase/erase-verify sequence is not repeated more than 60 times.
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Start *1
Set SWE bit in FLMCR1
Wait (10) µs
n=1
Set EBR1(2) *3
Enable WDT
Set ESU1(2) bit in FLMCR1(2)
Wait (200) µs
Set E1(2) bit in FLMCR1(2) Start erase
Wait (5) ms
Clear E1(2) bit in FLMCR1(2) Halt erase
Wait (10) µs
Clear ESU1(2) bit in FLMCR1(2)
Wait (10) µs
Disable WDT
n←n+1
Set EV1(2) bit in FLMCR1(2)
Wait (20) µs
Set block start address to verify address
H'FF dummy write to verify address
Wait (2) µs
Increment Read verify data *2

address
NG
Verify data = all "1"?
OK
NG
Last address of block?
OK
Clear EV1(2) bit in FLMCR1(2) Clear EV1(2) bit in FLMCR1(2)
Wait (5) µs Wait (5) µs
*4 End of
NG NG
erasing of all erase n ≥ 61?
blocks?
OK OK
Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1
End of erasing Erase failure
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1(2). More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 19.8 Erase/Erase-Verify Flowchart
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19.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
19.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state. (See table 19.7.)
Table 19.7 Hardware Protection
Functions
FWE pin protection • When a low level is input to the FWE pin, Yes Yes
FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/erase-
protected state is entered.
Reset/standby • In a reset (including a WDT overflow Yes Yes
protection reset) and in standby mode, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section.
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19.8.2 Software Protection
Software protection can be implemented by setting erase block register 1 (EBR1), erase block
register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software
protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or
the P2 or E2 bit in flash memory control register 2 (FLMCR2), does not cause a transition to
program mode or erase mode. (See table 19.8.)
Table 19.8 Software Protection
Functions
SWE pin protection • Clearing the SWE bit to 0 in FLMCR1 sets Yes Yes
the program/erase-protected state for all
blocks.
• (Execute in on-chip RAM or external
memory.)
Block specification • Erase protection can be set for individual — Yes
protection blocks by settings in erase block register 1
(EBR1) and erase block register 2
(EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation protection • Setting the RAMS bit to 1 in the RAM Yes Yes
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
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19.8.3 Error Protection
In error protection, an error is detected when SH7051 runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the SH7051 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or E2
bit. However, PV1, PV2, EV1, and EV2 bit setting is enabled, and a transition can be made to
verify mode.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 19.9 shows the flash memory state transition diagram.
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Program mode Reset or standby

Erase mode RES = 0 or HSTBY = 0 (hardware protection)
RES = 0 or
Error occurrence
HSTBY = 0 FLMCR1, FLMCR2,
(software standby) EBR1, EBR2
Error RES = 0 or initialization state
occurrence HSTBY = 0
Software Error protection mode

Error protection mode
standby mode (software standby)
Software standby
mode release
FLMCR1, FLMCR2, EBR1,
EBR2 initialization state
Legend:
RD: Memory read possible RD: Memory read not possible
VF: Verify-read possible VF: Verify-read not possible
PR: Programming possible PR: Programming not possible
ER: Erasing possible ER: Erasing not possible
Figure 19.9 Flash Memory State Transitions
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19.9 Flash Memory Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped
onto the flash memory area so that data to be written to flash memory can be emulated in RAM in
real time. After the RAMER setting has been made, accesses cannot be made from the flash
memory area or the RAM area overlapping flash memory. Emulation can be performed in user
mode and user program mode. Figure 19.10 shows an example of emulation of real-time flash
memory programming.
Start emulation program
Set RAMER
Write tuning data to overlap

RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMER
Write to flash memory emulation

block
End of emulation program
Figure 19.10 Flowchart for Flash Memory Emulation in RAM
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H'000000
Flash memory
EB0 to EB7
This area can be accessed

H'03F000 from both the RAM area
EB8 and flash memory area
H'03F400
EB9
H'03F800
EB10
H'03FC00
H'03FFFF EB11
H'FFFFD800
H'FFFFDBFF
On-chip RAM
Figure 19.11 Example of RAM Overlap Operation
Example in which Flash Memory Block Area (EB8) is Overlapped
1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 0, to overlap part of RAM onto the
area (EB8) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB8).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM1 and RAM0 (emulation protection). In this state,
setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2
bit in flash memory control register 2 (FLMCR2), will not cause a transition to
program mode or erase mode. When actually programming or erasing a flash memory
area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
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19.10 Note on Flash Memory Programming/Erasing

In the on-board programming modes (user mode and user program mode), NMI input should be
disabled to give top priority to the program/erase operations Including RAM emulation).
19.11 Flash Memory Programmer Mode

Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, flash memory read mode, auto-program mode, auto-
erase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and
status read mode, a status polling procedure is used, and in status read mode, detailed internal
signals are output after execution of an auto-program or auto-erase operation.
In programmer mode, set the mode pins to PLLx2 mode (see table 19.9) and input a 6 MHz input
clock, so that the SH7051 runs at 12 MHz.
Table 19.9 shows the pin settings for programmer mode. For the pin names in programmer mode,
see section 1.3.3, Pin Assignments.
Table 19.9 PROM Mode Pin Settings
Pin Names Settings

Mode pins: MD3, MD2, MD1, MD0 1101 (PLL × 2)
FWE pin High level input (in auto-program and auto-erase
modes)
RES pin Power-on reset circuit
XTAL, EXTAL, PLLVCC, PLLCAP, Oscillator circuit
PLLVSS pins
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19.11.1 Socket Adapter Pin Correspondence Diagram
Connect the socket adapter to the chip as shown in figure 19.13. This will enable conversion to a
32-pin arrangement. The on-chip ROM memory map is shown in figure 19.12, and the socket
adapter pin correspondence diagram in figure 19.13.
Addresses in Addresses in
MCU mode programmer mode
H'00000000 H'00000
On-chip ROM space

256 kB
H'0003FFFF H'3FFFF
Figure 19.12 On-Chip ROM Memory Map
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SH7051 (256 kB Version) Socket Adapter HN28F101P (32 Pins)

Pin No. Pin Name (Conversion to 32-Pin Pin No. Pin Name
Arrangement)
118 FWE 1 FWE
112 A9 26 A9
38 A16 2 A16
36 A15 3 A15
42 WE 31 WE
85 D0 13 I/O0
86 D1 14 I/O1
87 D2 15 I/O2
88 D3 17 I/O3
90 D4 18 I/O4
92 D5 19 I/O5
93 D6 20 I/O6
94 D7 21 I/O7
17 A0 12 A0
18 A1 11 A1
19 A2 10 A2
20 A3 9 A3
22 A4 8 A4
24 A5 7 A5
25 A6 6 A6
26 A7 5 A7
27 A8 27 A8
28 OE 24 OE
30 A10 23 A10
32 A11 25 A11
33 A12 4 A12
34 A13 28 A13
35 A14 29 A14
41 CE 22 CE
1, 2, 5, 13, 21, 29, 37, 47, 55, 32 VCC
72, 79, 89, 97, 105, 109, 111, VCC 16 VSS
113, 120, 124, 130, 142, 149, 30 A17
150, 158
7, 15, 23, 31, 39, 49, 57, 64, Legend:
FWE: Flash write enable
70, 81, 91, 99, 107, 115, 119, VSS
I/O7–I/O0: Data input/output
136, 144, 152, 164
A17–A0: Address input
40 A17 OE: Output enable
126 RES Power-on reset circuit CE: Chip enable
108 XTAL WE: Write enable
Oscillator circuit
110 EXTAL
121 PLLVCC
122 PLLCAP PLL circuit
123 PLLVSS
Other than the above N.C.(OPEN)
Figure 19.13 Socket Adapter Pin Correspondence Diagram
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19.11.2 Programmer Mode Operation
Table 19.10 shows how the different operating modes are set when using programmer mode, and
table 19.11 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode

Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-programming.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the D6 signal. In status read mode, error information is output if an error
occurs.
Table 19.10 Settings for Various Operating Modes In Programmer Mode
Pin Names
Mode FWE CE OE WE D0–D7 A0–A17
Read H or L L L H Data output Ain
Output disable H or L L H H Hi-z X
Command write H or L L H L Data input *Ain
Chip disable H or L H X X Hi-z X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. *Ain indicates that there is also address input in auto-program mode.
3. For command writes in auto-program and auto-erase modes, input a high level to the
FWE pin.
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Table 19.11 Programmer Mode Commands
1st Cycle 2nd Cycle

Number
Command Name of Cycles Mode Address Data Mode Address Data
Memory read mode 1+n Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 Write X H'20
Status read mode 2 Write X H'71 Write X H'71
Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
19.11.3 Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the

command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. Once memory read mode has been entered, consecutive reads can be performed.
4. After powering on, memory read mode is entered.
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Table 19.12 AC Characteristics in Transition to Memory Read Mode

Command write Memory read mode
tces tceh tnxtc
CE
OE
twep
tf tr
WE
tds tdh
I/O7–I/O0
Note: Data is latched on the rising edge of WE.
Figure 19.14 Timing Waveforms for Memory Read after Memory Write
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Table 19.13 AC Characteristics in Transition from Memory Read Mode to Another Mode

Memory read mode Other mode command write
tnxtc tces tceh
CE
OE
twep
tf tr
WE
tds tdh
I/O7–I/O0
Note: Do not enable WE and OE at the same time.
Figure 19.15 Timing Waveforms in Transition from Memory Read Mode to Another Mode
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Table 19.14 AC Characteristics in Memory Read Mode

Access time tacc 20 µs
Output disable delay time tdf 100 ns
Data output hold time toh 5 ns
CE VIL
OE VIL
WE VIH tacc tacc

toh toh
I/O7–I/O0
Figure 19.16 CE and OE Enable State Read Timing Waveforms
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tce tce
CE
toe toe
OE
WE VIH tacc tacc

tdf
tdf toh
toh
I/O7–I/O0
Figure 19.17 CE and OE Clock System Read Timing Waveforms
19.11.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
3. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
4. Memory address transfer is performed in the third cycle (figure 18.13). Do not perform transfer
after the second cycle.
5. Do not perform a command write during a programming operation.
6. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
7. Confirm normal end of auto-programming by checking D6. Alternatively, status read mode
can also be used for this purpose (D7 status polling uses the auto-program operation end
identification pin).
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Table 19.15 AC Characteristics in Auto-Program Mode

Status polling start time twsts 1 ms
Address setup time tas 0 ns
Address hold time tah 60 ns
Memory write time twrite 1 3000 ms
Write setup time tpns 100 ns
Write end setup time tpnh 100 ns
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FWE
tpnh
Address
A16–A0 stable
tpns tces tceh tnxtc tnxtc
CE
OE twep
tf tr tas tah twsts tspa
WE
Data transfer
tds tdh twrite
1 to 128byte
I/O7 Write operation complete verify signal
I/O6 Write normal complete verify signal
I/O5–I/O0 H'40 H'00
Figure 19.18 Auto-Program Mode Timing Waveforms
19.11.5 Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.

2. Do not perform a command write during auto-erasing..
3. Confirm normal end of auto-erasing by checking D6. Alternatively, status read mode can also
be used for this purpose (D7 status polling uses the auto-erase operation end identification
pin).
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Table 19.16 AC Characteristics in Auto-Erase Mode

Status polling start time tests 1 ms
Memory erase time terase 100 40000 ms
Erase setup time tens 100 ns
Erase end setup time tenh 100 ns
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FWE
tenh
A16–A0
tens tces tceh tnxtc tnxtc
CE
OE twep
tf tr tests tspa
WE
tds tdh terase
I/O7 Erase complete

verify signal
I/O6 Erase normal

complete
verify signal
I/O5–I/O0 H'20 H'20 H'00
Figure 19.19 Auto-Erase Mode Timing Waveforms
19.11.6 Status Read Mode
1. Status read mode is provided to specify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
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Table 19.17 AC Characteristics in Status Read Mode

Read time after command write tstd 20 µs
Disable delay time tdf 100 ns
A16–A0
tces tceh tnxtc tces tceh tnxtc tnxtc
CE
tce
OE twep twep
tf tr tf tr toe
WE
tds tdh tds tdh tdf
I/O7–I/O0 H'71 H'71
Note: I/O2 and I/O3 are undefined.
Figure 19.20 Status Read Mode Timing Waveforms
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Table 19.18 Status Read Mode Return Commands

Pin Name D7 D6 D5 D4 D3 D2 D1 D0
Attribute Normal Command Program- Erase — — Program- Effective
end error ming error error ming or address
identification erase count error
exceeded
Initial value 0 0 0 0 0 0 0 0
Indications Normal Command Program- Erasing — — Count Effective
end: 0 Error: 1 ming Error: 1 exceeded: 1 address
Abnormal Otherwise: 0 Error: 1 Otherwise: 0 Otherwise: 0 Error: 1
end: 1 Otherwise: 0 Otherwise: 0
Note: D2 and D3 are undefined at present.
19.11.7 Status Polling
1. D7 status polling is a flag that indicates the operating status in auto-program/auto-erase mode.
2. D6 status polling is a flag that indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 19.19 Status Polling Output Truth Table
During Internal
Pin Name Operation Abnormal End — Normal End
D7 0 1 0 1
D6 0 0 1 1
D0–D5 0 0 0 0
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19.11.8 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 19.20 Stipulated Transition Times to Command Wait State

Standby release (oscillation tosc1 10 ms
stabilization time)
Programmer mode setup time tbmv 10 ms
VCC hold time tdwn 0 ms
Memory read
mode Command wait state
Command Automatic write mode Normal/abnormal
wait state Automatic erase mode complete verify
tOSC1 tbmv tdwn
VCC
RES
FWE
Note : For the level of FWE input pin, set VIL when using other than the automatic write mode
and automatic erase mode.
Figure 19.21 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-
Down Sequence
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19.11.9 Cautions Concerning Memory Programming
1. When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
2. When performing programming using PROM mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Additional programming cannot be performed on previously programmed address
blocks.
19.12 Notes when Converting the F-ZTAT Application Software to the

Mask-ROM Versions
Please note the following when converting the F-ZTAT application software to the mask-ROM
versions.
The values read from the internal registers for the flash ROM of the mask-ROM version and F-
ZTAT version differ as follows.
Status
Register Bit F-ZTAT Version Mask-ROM Version
FLMCR1 FWE 0: Application software running 0: Is not read out
1: Programming 1: Application software running
Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have
different ROM size.
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Section 20 RAM
Section 20 RAM
20.1 Overview
The SH7050 has 6 kbytes/the SH7051 has 10 kbytes of on-chip RAM. The on-chip RAM is linked
to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 20.1). The
CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The DMAC can access 8 or 16
bit widths. On-chip RAM data can always be accessed in one state, making the RAM ideal for use
as a program area, stack area, or data area, which require high-speed access. The contents of the
on-chip RAM are held in both the sleep and software standby modes. When the RAME bit (see
below) is cleared to 0, the on-chip RAM contents are also held in hardware standby mode.
Memory area 0 addresses H'FFFFF800 to H'FFFFFFFF (SH7050) and H'FFFF0800 to
H'FFFFFFFF (SH7051) are allocated to the on-chip RAM.
SH7050
H'FFFFF800 H'FFFFF801 H'FFFFF802 H'FFFFF803

H'FFFFF804 H'FFFFF805 H'FFFFF806 H'FFFFF807
On-chip RAM
H'FFFFFFFC H'FFFFFFFD H'FFFFFFFE H'FFFFFFFF

SH7051
H'FFFFD800 H'FFFFD801 H'FFFFD802 H'FFFFD803

H'FFFFD804 H'FFFFD805 H'FFFFD806 H'FFFFD807
On-chip RAM
H'FFFFFFFC H'FFFFFFFD H'FFFFFFFE H'FFFFFFFF
Figure 20.1 Block Diagram of RAM
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Section 20 RAM
20.2 Operation
The on-chip RAM is controlled by means of the system control register (SYSCR).
When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses
H'FFFFE800–H'FFFFFFFF (SH7050) and H'FFFFD800–H'FFFFFFFF (SH7051) are then directed
to the on-chip RAM.
When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will
return an undefined value, and a write is invalid. If a transition is made to hardware standby mode
after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held.
For details of SYSCR, see 21.2.2, System Control Register (SYSCR), in section 21, Power-Down
State.
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Section 21 Power-Down State
21.1 Overview
In the power-down state, the CPU functions are halted. This enables a great reduction in power
consumption.
21.1.1 Power-Down States
The power-down state is effected by the following three modes:
1. Hardware standby mode

A transition to hardware standby mode is made according to the input level of the RES and
HSTBY pins.
In hardware standby mode, all chip functions are halted.
This state is exited by means of a power-on reset.
2. Software standby mode
A transition to software standby mode is made by means of software (a CPU instruction).
In software standby mode, all chip functions are halted.
This state is exited by means of a power-on reset or an NMI interrupt.
3. Sleep mode
A transition to sleep mode is made by means of a CPU instruction.
In software standby mode, basically only the CPU is halted, and all on-chip peripheral modules
operate.
This state is exited by means of a power-on reset, interrupt, or DMA address error.
Table 21.1 describes the transition conditions for entering the modes from the program execution
state as well as the CPU and peripheral function status in each mode and the procedures for
canceling each mode.
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Table 21.1 Power-Down State Conditions
State
On-Chip
Entering CPU Peripheral I/O Canceling
Mode Procedure Clock CPU Registers Modules RAM Ports Procedure
Undefined Held* Initialized High-level
2
Hardware Low-level Halted Halted Halted
standby input at input at
HSTBY pin HSTBY pin,
executing
power-on
reset
Halt*
1
Software Execute Halt Halt Held Held Held or • NMI
standby SLEEP high interrupt
instruction impe- • Power-on
dance*
3
with SBY bit reset
set to 1 in
SBYCR
Sleep Execute Run Halt Held Run Held Held • Interrupt
SLEEP • DMAC
instruction address
with SBY bit error
set to 0 in
SBYCR • Power-on
reset
Notes: 1. SBYCR: standby control register. SBY: standby bit
2. Some bits within on-chip peripheral module registers are initialized by the standby
mode; some are not. Refer to table 21.3, Register States in the Standby Mode, in
section 21.4.1, Transition to Standby Mode. Also refer to the register descriptions for
each peripheral module.
3. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of
the SBYCR. Refer to section 21.2, Standby Control Register (SBYCR). For pin status
other than for the I/O port, refer to Appendix B, Pin States.
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Pins related to power-down modes are shown in table 21.2.

Hardware standby input pin HSTBY Input Input level determines transition to
hardware standby mode.
Power-on reset input pin RES Input Power-on reset signal input pin
21.1.3 Related Register
Table 21.3 shows the register used for power-down state control.
Table 21.3 Related Register

Standby control register SBYCR R/W H'1F H'FFFF8614 8
System control register SYSCR R/W H'01 H'FFFF83C8 8
Note: SBYCR is accessed in three cycles , and SYSCR in two cycles.
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21.2.1 Standby Control Register (SBYCR)
The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to
standby mode, and the port status in standby mode. The SBYCR is initialized to H'1F by reset.
Bit: 7 6 5 4 3 2 1 0
SSBY HIZ — — — — — —
R/W: R/W R/W R R R R R R
Bit 7—Standby (SSBY): Specifies transition to the standby mode. The SSBY bit cannot be set to
1 while the watchdog timer is running (when the timer enable bit (TME) of the WDT timer
control/status register (TCSR) is set to 1). To enter the standby mode, always halt the WDT by 0
clearing the TME bit, then set the SSBY bit.
Bit 7: SSBY Description

0 Executing SLEEP instruction puts the LSI into sleep mode (initial value)
1 Executing SLEEP instruction puts the LSI into standby mode
Bit 6—Port High Impedance (HIZ): In the standby mode, this bit selects whether to set the I/O
port pin to high impedance or hold the pin status. The HIZ bit cannot be set to 1 when the TME bit
of the WDT timer control/status register (TCSR) is set to 1. When making the I/O port pin status
high impedance, always clear the TME bit to 0 before setting the HIZ bit.
Bit 6: HIZ Description

0 Holds pin status while in standby mode (initial value)
1 Keeps pin at high impedance while in standby mode
Bits 5–0—Reserved: Bit 5 always reads as 0. Always write 0 to bit 5. Bits 4–0 always read as 1.
Always write 1 to these bits.
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21.2.2 System Control Register (SYSCR)
Bit: 7 6 5 4 3 2 1 0
— — — — — — — RAME
The system control register (SYSCR) is an 8-bit readable/writable register that enables or disables
accesses to the on-chip RAM.
SYSCR is initialized to H'01 by the rising edge of a power-on reset.
Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When
RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be
accessed. In this case, a read or instruction fetch from on-chip RAM will return an undefined
value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts
to access on-chip RAM immediately after the SYSCR write instruction, as normal access cannot
be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction
immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an on-chip
RAM access instruction is placed immediately after the SYSCR write instruction.
Bit 0: RAME Description

0 On-chip RAM disabled
1 On-chip RAM enabled (initial value)
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21.3 Hardware Standby Mode
21.3.1 Transition to Hardware Standby Mode
The chip enters hardware standby mode when the HSTBY pin goes low. Hardware standby mode
reduces power consumption drastically by halting all chip functions. As the transition to hardware
standby mode is made by means of external pin input, the transition is made asynchronously,
regardless of the current state of the chip, and therefore the chip state prior to the transition is not
preserved. However, on-chip RAM data is retained as long as the specified voltage is supplied. To
retain on-chip RAM data, clear the RAM enable bit (RAME) to 0 in the system control register
(SYSCR) before driving the HSTBY pin low. See “Pin States” for the pin states in hardware
standby mode.
21.3.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by means of the HSTBY pin and RES pin. When HSTBY is
driven high while RES is low, the clock oscillator starts running. The RES pin should be held low
long enough for clock oscillation to stabilize. When RES is driven high, power-on reset exception
handling is started and a transition is made to the program execution state.
21.3.3 Hardware Standby Mode Timing
Figure 21.1 shows sample pin timings for hardware standby mode. A transition to hardware
standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware
standby mode is exited by driving HSTBY high, waiting for clock oscillation to stabilize, then
switching RES from low to high.
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Oscillator
RES
HSTBY
RES pulse Oscillation Reset

width tRESW stabilization exception
time handling
Figure 21.1 Hardware Standby Mode Timing
21.4 Software Standby Mode
21.4.1 Transition to Software Standby Mode
To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.
The LSI moves from the program execution state to the standby mode. In the standby mode,
power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip
peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the
prescribed voltages are applied (when the RAME bit in SYSCR is 0). The register contents of
some on-chip peripheral modules are initialized, but some are not (table 21.4). The I/O port status
can be selected as held or high impedance by the port high impedance bit (HIZ) of the SBYCR.
For pin status other than for the I/O port, refer to Appendix B, Pin States.
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Table 21.4 Register States in the Standby Mode
Module Registers Initialized Registers that Retain Data

Interrupt controller (INTC) — All registers
User break controller (UBC) — All registers
Bus state controller (BSC) — All registers
Direct memory access All registers —
controller (DMAC)
Advanced timer unit (ATU) All registers —
Advanced pulse controller — All registers
Watchdog timer • Bits 7–5 (OVF, WT/IT, TME) • Bits 2–0 (CKS2–CKS0) of
(WDT) of the timer control status the TCSR
register (TCSR)
• Reset control/status register
(RSTCSR)
• Timer counter (TCNT)
Compare match timer (CMT) All registers —
Serial communication All registers —
interface (SCI)
A/D converter (A/D) All registers —
Pin function controller (PFC) — All registers
I/O port (I/O) — All registers
Power-down state related — • Standby control register
(SBYCR)
• System control register
(SYSCR)
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21.4.2 Canceling the Software Standby Mode
The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.
Cancellation by an NMI: Clock oscillation starts when a rising edge or falling edge (selected by
the NMI edge select bit (NMIE) of the interrupt control register (ICR) of the INTC) is detected in
the NMI signal. This clock is supplied only to the watchdog timer. A WDT overflow occurs if the
time established by the clock select bits (CKS2–CKS0) in the TCSR of the WDT elapses before
transition to the standby mode. The occurrence of this overflow is used to indicate that the clock
has stabilized, so the clock is supplied to the entire chip, the standby mode is canceled, and NMI
exception processing begins.
When canceling standby mode with NMI interrupts, set the CKS2–CKS0 bits so that the WDT
overflow period is longer than the oscillation stabilization time.
When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level
upon entering standby (when the clock is halted) is high level, and that the NMI pin level upon
returning from standby (when the clock starts after oscillation stabilization) is low level. When
canceling standby mode with an NMI pin set for rising edge, be sure that the NMI pin level upon
entering standby (when the clock is halted) is low level, and that the NMI pin level upon returning
from standby (when the clock starts after oscillation stabilization) is high level.
Cancellation by a Power-On Reset: A power-on reset caused by setting the RES pin to low level
cancels the standby mode.
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21.4.3 Software Standby Mode Application Example
This example describes a transition to standby mode on the falling edge of an NMI signal, and a
cancellation on the rising edge of the NMI signal. The timing is shown in figure 21.2.
When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) of the
ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to
1 (rising edge detection) by an NMI exception service routine, the standby bit (SBY) of the
SBYCR is set to 1, and a SLEEP instruction is executed, standby mode is entered. Thereafter,
standby mode is canceled when the NMI pin is changed from low to high level.
Oscillator
CK
NMI pin
NMIE bit
SSBY bit
Program NMI Exception Software Oscillation WDT NMI exception

Chip state exception
execution handling service routine standby mode start time set time handling
Oscillation settling time
Figure 21.2 Standby Mode NMI Timing (Application Example)
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21.5 Sleep Mode
21.5.1 Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the
program execution state to the sleep mode. Although the CPU halts immediately after executing
the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip
peripheral modules continue to run during the sleep mode.
21.5.2 Canceling Sleep Mode
Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt
exception processing is executed. The sleep mode is not canceled if the interrupt cannot be
accepted because its priority level is equal to or less than the mask level set in the CPU’s status
register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral
module.
Cancellation by a DMAC Address Error: If a DMAC address error occurs, the sleep mode is
canceled and DMAC address error exception processing is executed.
Cancellation by a Power-On Reset: A power-on reset resulting from setting the RES pin to low
level cancels the sleep mode.
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Section 22 Electrical Characteristics
22.1 Absolute Maximum Ratings

Table 22.1 shows the absolute maximum ratings.
Table 22.1 Absolute Maximum Ratings
Item Symbol Rating Unit

Power supply voltage VCC –0.3 to +7.0 V
Input voltage (other than A/D ports) Vin –0.3 to VCC + 0.3 V
Input voltage (A/D ports) Vin –0.3 to AVCC + 0.3 V
Analog supply voltage AVCC –0.3 to +7.0 V
Analog reference voltage AVref –0.3 to AVCC + 0.3 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature (exclding overwrite) Topr –40 to +85 °C
Overwrite temperature Twe –20 to +85 °C
Storage temperature Tstg –55 to +125 °C
Note: Operating the LSI in excess of the absolute maximum ratings may result in permanent
damage.
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22.2 DC Characteristics
Table 22.2 DC Characteristics
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V,
Ta = –40 to +85°C
Measurement
Item Pin Symbol Min Typ Max Unit Conditions
Input high- RES, NMI, VIH VCC – 0.7 — VCC + 0.3 V —
level MD3–MD0,
voltage HSTBY
EXTAL VCC × 0.7 — VCC + 0.3 V —
A/D port 2.2 — AVCC + 0.3 V —
Other input pins 2.2 — VCC + 0.3 V —
Input low- RES, NMI, VIL –0.3 — 0.5 V —
level MD3–MD0,
voltage HSTBY
Other input pins –0.3 — 0.8 V —
+
Schmitt TIA0–TID0, VT 4.0 — — V —
trigger TIOA1–TIOF1,
input TIOA2–TIOF2, –
VT — — 1.0 V —
voltage TIOA3–TIOF3,
TIOA4–TIOF4,
+ –
TIOA5, TIOB5, VT – VT 0.4 — — V —
TCLKA, TCLKB
Input leak RES, NMI, | Iin | — — 1.0 µA Vin =
current MD3–MD0, 0.5 to VCC – 0.5 V
HSTBY
A/D port — — 1.0 µA Vin =
0.5 to AVCC – 0.5 V
Other input pins — — 1.0 µA Vin =
0.5 to VCC – 0.5 V
Three- A21–A0, | ITSI | — — 1.0 µA Vin =
state leak D15–D0, 0.5 to VCC – 0.5 V
current CS3–CS0,
(while off) WRH, WRL, RD
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Measurement
Item Pin Symbol Min Typ Max Unit Conditions
Output All output pins VOH VCC – 0.5 — — V IOH = –200 µA
high-level 3.5 — — V IOH = –1 mA
voltage
Output All output pins VOL — — 0.4 V IOL = 1.6 mA
low-level — — 1.2 V IOL = 8 mA
voltage
Input RES Cin — — 60 pF Vin = 0 V,
capacitance NMI — — 30 pF f = 1 MHz,
Ta = 25°C
All other input — — 20 pF
pins
Current Ordinary ICC — 100 150 mA f = 20 MHz
consump- operation (90)*
tion Sleep — 80 130 mA f = 20 MHz
(70)*
Standby — 1 20 µA Ta ≤ 50°C
— — 80 µA Ta > 50°C
Write operation — 110 150 µA –20°C ≤ Ta ≤ 85°C
f = 20 MHz
Analog During A/D AICC — 1.5 5 mA
supply conversion
current Awaiting A/D — 0.5 5 µA
conversion
Reference During A/D AIref — 1.0 5 mA AVref = 5.0 V
power conversion
supply Awaiting A/D — 0.5 5 µA
current conversion
RAM standby voltage VRAM 2.0 — — V
Note: * Mask version
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Table 22.3 Permitted Output Current Values
Ta = –40 to +85°C
Item Symbol Min Typ Max Unit

Output low-level permissible current (per pin) IOL — — 8.0 mA
Output low-level permissible current (total) ∑ IOL — — 80 mA
Output high-level permissible current (per pin) –IOH — — 2.0 mA
Output high-level permissible current (total) ∑ (–IOH) — — 25 mA
Note: To assure LSI reliability, do not exceed the output values listed in this table.
22.2.1 Notes on Using
1. When the A/D converter is not used (including during standby), do not release the AVCC, AVSS,
and AVref pins. Connect the AVCC and AVref pins to VCC and the AVSS pin to VSS.
2. The current consumption is measured when VIHmin = VCC – 0.5 V, VIL max = 0.5 V, with all
output pins unloaded.
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22.3 AC Characteristics
Input output reference voltage level and loading current of AC characteristics measuring
conditions are same as defined in figure 22.22.
22.3.1 Clock Timing
Table 22.4 Clock Timing
Ta = –40 to +85°C
Item Symbol Min Max Unit Figures

Operating frequency fOP 4 20 MHz 22.1
Clock cycle time tcyc 50 250 ns
Clock low-level pulse width tCL 20 — ns
Clock high-level pulse width tCH 20 — ns
Clock rise time tCR — 5 ns
Clock fall time tCF — 5 ns
EXTAL clock input frequency fEX 4 10 MHz 22.2
EXTAL clock input cycle time tEXcyc 100 250 ns
EXTAL clock low-level input pulse width tEXL 30 — ns
EXTAL clock high-level input pulse width tEXH 30 — ns
EXTAL clock input rise time tEXR — 5 ns
EXTAL clock input fall time tEXF — 5 ns
Reset oscillation settling time tOSC1 10 — ms 22.3
Standby return clock settling time tOSC2 10 — ms
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tcyc
tCH tCL
CK 1/2 VCC 1/2 VCC
tCF tCR
Figure 22.1 System Clock Timing
TEXCYC
TEXH TEXL
EXTAL
1/2 VCC 1/2 VCC
TEXF TEXR
Figure 22.2 EXTAL Clock Input Timing
CK
VCC VCC min

tosc2
HSTBY
tosc1 tosc1
RES
Figure 22.3 Oscillation Settling Time
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22.3.2 Control Signal Timing
Table 22.5 Control Signal Timing
Ta = –40 to +85°C
Item Symbol Min Max Unit Figure

RES pulse width tRESW 20 — tcyc 22.4
RES setup time tRESS 30 — ns
NMI setup time* tNMIS 30 — ns 22.4, 22.5
IRQ7–IRQ0 setup time (edge detection)* tIRQES 30 — ns
IRQ7–IRQ0 setup time (level detection)* tIRQLS 30 — ns
NMI hold time tNMIH 50 — ns 22.5
IRQ7–IRQ0 hold time tIRQEH 30 — ns
IRQOUT hold time tIRQOD — 25 ns 22.6
Bus request setup time tBRQS 30 — ns 22.7
Bus acknowledge delay time 1 tBACKD1 — 25 ns
Bus acknowledge delay time 2 tBACKD2 — 25 ns
Bus three-state delay time tBZD — 50 ns
Note: * The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup
times shown here are provided, the signals are considered to have produced changes
at clock fall. If the setup times are not provided, recognition is delayed until the next
clock rise or fall.
CK
tRESS tRESS
RES
VIH VIH
VIL VIL
tRESW
Figure 22.4 Reset Input Timing
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CK
tNMIH tNMIS
VIH
NMI
VIL
tIRQEH tIRQES
VIH
IRQ edge
VIL
tIRQLS
IRQ level
Figure 22.5 Interrupt Signal Input Timing
CK
tIRQOD tIRQOD
IRQOUT
Figure 22.6 Interrupt Signal Output Timing
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CK
tBRQS tBRQS
BREQ
(Input)
tBACKD1 tBACKD2
BACK
(Output)
tBZD
RD, CSn,
WRH, WRL
tBZD
A21–A0,
D15–D0
Figure 22.7 Bus Right Release Timing
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22.3.3 Bus Timing
Table 22.6 Bus Timing
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ±10%, AVREF = 4.5 V – AVCC, VSS = AVSS = 0 V,
Ta = –40 to +85°C

Address delay time tAD — 25 ns 22.8, 22.9
CS delay time 1 tCSD1 — 25 ns
CS delay time 2 tCSD2 — 25 ns
Read strobe delay time 1 tRSD1 — 25 ns
Read strobe delay time 2 tRSD2 — 25 ns
Read data setup time tRDS 28 — ns
Read data hold time tRDH 0 — ns
Write address setup time tAS 0 — ns
Write address hold time tWR 5 — ns
Write strobe delay time 1 tWSD1 — 25 ns
Write strobe delay time 2 tWSD2 — 25 ns
Write data delay time tWDD — 35 ns
Write data hold time tWDH tcyc × m — ns
WAIT setup time tWTS 15 — ns 22.10
WAIT hold time tWTH 0 — ns
Read data access time tACC tcyc × (n + 2) – 45 — ns 22.8, 22.9
Access time from read strobe tOE tcyc × (n + 1.5) – 45 — ns
DACK delay time tDACKD1 — 25 ns
Note: n is the number of waits.
m=1: CS assort extended cycle
m=0: Normal cycle (CS assort non-extended cycle)
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T1 T2
CK
tAD
A21–A0
tCSD1 tCSD2
CSn
tRSD1 tOE tRSD2
RD
(During read)
tACC tRDS tRDH
D15–D0
(During read)
tWSD1 tWSD2 tWR
WRx
(During write) tAS
tWDD tWDH
D15–D0
(During write)
tDACKD tDACKD
DACKn
Note: tRDH is specified from the first negate timing for A21–A0, CSn, and RD.
Figure 22.8 Basic Cycle (No Waits)
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T1 Tw T2
CK
tAD
A21–A0
tCSD1 tCSD2
CSn
tRSD1 tOE tRSD2
RD
(During read)
tACC tRDS tRDH
D15–D0
(During read)
tWSD1 tWSD2 tWR
WRx
(During write) tAS
tWDD tWDH
D15–D0
(During write)
tDACKD tDACKD
DACKn
Note: tRDH is specified from the first negate timing for A21ÐA0, CSn, and RD.
Figure 22.9 Basic Cycle (Software Waits)
Rev. 5.00 Jan 06, 2006 page 664 of 818

REJ09B0273-0500
T1 Tw Tw Two T2
CK
A21–A0
CSn
RD
(During read)
D15–D0
(During read)
WRx
(During write)
D15–D0
(During write)
tWTS tWTH tWTS tWTH
WAIT
DACKn
Figure 22.10 Basic Cycle (2 Software Waits + Wait due to WAIT Signal)
Rev. 5.00 Jan 06, 2006 page 665 of 818

REJ09B0273-0500
22.3.4 Direct Memory Access Controller Timing
Table 22.7 Direct Memory Access Controller Timing
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVREF = 4.5 V to AVCC, VSS = AVSS = 0 V,
Ta = –40 to +85°C

DREQ0 and DREQ1 setup time tDRQS 27 — ns 22.11
DREQ0 and DREQ1 hold time tDRQH 30 — ns
DREQ0 and DREQ1 pulse width tDRQW 1.5 — tcyc 22.12
DRAK output delay time tDRAKD — 25 ns 22.13
CK
tDRQS
DREQ0,
DREQ1
level
tDRQS tDRQH
DREQ0,
DREQ1
edge
tDRQS
DREQ0,
DREQ1
level release
Figure 22.11 DREQ0 and DREQ1 Input Timing (1)
Rev. 5.00 Jan 06, 2006 page 666 of 818

REJ09B0273-0500
CK
DREQ0,
DREQ1
edge
tDRQW
Figure 22.12 DREQ0 and DREQ1 Input Timing (2)
CK
tDRAKD tDRAKD
DRAKn
Figure 22.13 DRAK Output Delay Time
Rev. 5.00 Jan 06, 2006 page 667 of 818

REJ09B0273-0500
22.3.5 Advanced Timer Unit Timing and Advanced Pulse Controller Timing
Table 22.8 Advanced Timer Unit Timing and Advanced Pulse Controller Timing
Ta = –40 to +85°C

Output compare output delay time tTOCD — 50 ns 22.14
Input capture input setup time tTICS 35 — ns
PULS output delay time tPLSD — 50 ns
Timer input setup time tTCKS 50 — ns 22.15
Timer clock pulse width (single edge tTCKWH/L 1.5 — tcyc
specification)
Timer clock pulse width (both edges tTCKWH/L 2.5 — tcyc
specified)
CK
tTOCD
Timer output
tTICS
Input capture
input
PULS output
tPLSD
Figure 22.14 ATU I/O Timing
Rev. 5.00 Jan 06, 2006 page 668 of 818

REJ09B0273-0500
CK
tTCKS tTCKS
TCLKA, TCLKB
tTCKWL tTCKWH
Figure 22.15 ATU Clock Input Timing
22.3.6 I/O Port Timing
Table 22.9 I/O Port Timing
Ta = –40 to +85°C

Port output data delay time tPWD — 100 ns 22.16
Port input hold time tPRH 50 — ns
Port input setup time tPRS 50 — ns
CK
tPRS tPRH
Port
(read)
tPWD
Port
(write)
Figure 22.16 I/O Port I/O Timing
Rev. 5.00 Jan 06, 2006 page 669 of 818

REJ09B0273-0500
22.3.7 Watchdog Timer Timing
Table 22.10 Watchdog Timer Timing
Ta = –40 to +85°C

WDTOVF delay time tWOVD — 100 ns 22.17
CK tWOVD tWOVD
WDTOVF
Figure 22.17 Watchdog Timer Timing
22.3.8 Serial Communication Interface Timing
Table 22.11 Serial Communication Interface Timing
Ta = –40 to +85°C

Input clock cycle tscyc 4 — tcyc 22.18
Input clock cycle (clock sync) tscyc 6 — tcyc
Input clock pulse width tsckw 0.4 0.6 tscyc
Input clock rise time tsckr — 1.5 tcyc
Input clock fall time tsckf — 1.5 tcyc
Transmit data delay time (clock sync) tTXD — 100 ns 22.19
Receive data setup time (clock sync) tRXS 100 — ns
Receive data hold time (clock sync) tRXH 100 — ns
Rev. 5.00 Jan 06, 2006 page 670 of 818

REJ09B0273-0500
tsckw
tsckr tsckf
SCK0, SCK1
tscyc
Figure 22.18 Input Clock Timing
tscyc
SCK0, SCK1
tTXD
TXD0, TXD1
(Transmit data)
tRXS
tRXH
RXD0, RXD1
(Receive data)
Figure 22.19 SCI I/O Timing (Clock Sync Mode)
22.3.9 A/D Converter Timing
Table 22.12 A/D Converter Timing
Ta = –40 to +85°C

External trigger input start delay time tTRGS 50 — ns 22.20
A/D conversion time (266 states) tCONV — 266 tcyc 22.21
A/D conversion time (134 states) tCONV — 134
Rev. 5.00 Jan 06, 2006 page 671 of 818

REJ09B0273-0500
1 state
CK
ADTRG
input
tTRGS
ADCR
Figure 22.20 External Trigger Input Timing
tCONV
tD tSPL
3 states Max. 14 states
CK
Address
Analog input
sampling
signal
ADF
Figure 22.21 Analog Conversion Timing
Rev. 5.00 Jan 06, 2006 page 672 of 818

REJ09B0273-0500
22.3.10 Measuring Conditions for AC Characteristics
• Input reference levels:

 High level: 2.2 V
 Low level: 0.8 V
• Output reference levels:
 High level: 2.0 V
 Low level: 0.8 V
IOL
IOH, IOL
LSI output pin DUT output
CL V VREF
| IOH |
Note: CL is set with the following pins, including the total capacitance of the
measurement jig, etc:
30 pF: CK, CS0–CS3, BREQ, BACK, DACK0, DACK1, and IRQOUT
50 pF: A21–A0, D15–D0, RD, WRx
70 pF: Port output and peripheral module output pins other than the above.
IOL, IOH: IOL = 1.6 mA, IOH = –200 µA
Figure 22.22 Output Test Circuit
Rev. 5.00 Jan 06, 2006 page 673 of 818

REJ09B0273-0500
22.4 A/D Converter Characteristics

Table 22.13 A/D Converter Timing
Ta = –40 to +85°C
20 MHz
Item Min Typ Max Unit
Resolution 10 10 10 Bits
Conversion time (when CKS = 1) — — 6.7 µs
Analog input capacitance — — 20 pF
Permitted signal source impedance — — 3 kΩ
Non-linear error — — ±1.5 LSB
Offset error — — ±1.5 LSB
Full-scale error — — ±1.5 LSB
Quantization error — — ±0.5 LSB
Absolute error — — ±2.0 LSB
Rev. 5.00 Jan 06, 2006 page 674 of 818

REJ09B0273-0500
Appendix A On-Chip Supporting Module Registers
A.1 Addresses
On-chip supporting module register addresses and bit names are shown below. 16-bit and 32-bit
registers are shown in two and four rows, respectively.
Table A.1 Two-Cycle, 8-Bit Access Space (8-Bit and 16-Bit Access Permitted; 32-Bit
Access Prohibited)
Bit Names
Register
Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'FFFF8000 — — — — — — — — — —
to
H'FFFF819F
H'FFFF81A0 SMR0 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI
H'FFFF81A1 BRR0 (channel 0)
H'FFFF81A2 SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFF81A3 TDR0
H'FFFF81A4 SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FFFF81A5 RDR0
H'FFFF81A6 — — — — — — — — —
to
H'FFFF81AF
H'FFFF81B0 SMR1 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI
H'FFFF81B1 BRR1 (channel 1)
H'FFFF81B2 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFF81B3 TDR1
H'FFFF81B4 SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FFFF81B5 RDR1
H'FFFF81B6 — — — — — — — — —
to
H'FFFF81BF
H'FFFF81C0 SMR2 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI
H'FFFF81C1 BRR2 (channel 2)
H'FFFF81C2 SCR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0

H'FFFF81C3 TDR2
H'FFFF81C4 SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT
H'FFFF81C5 RDR2
H'FFFF81C6 — — — — — — — — —
to
H'FFFF81FF
Rev. 5.00 Jan 06, 2006 page 675 of 818

REJ09B0273-0500
Table A.2 Two-Cycle, 16-Bit Access Space (In Principle, 8-Bit, 16-Bit, and 32-Bit Access
Permitted)
Bit Names
Register
H'FFFF8200 TMDR*1 — — — — — T5PWM T4PWM T3PWM ATU
(channels
H'FFFF8201 — — — — — — — — —
3–5)
1
H'FFFF8202 TIERDH* — — — OVE3 IME3D IME3C IME3B IME3A
H'FFFF8203 TSRDH*1 — — — OVF3 IMF3D IMF3C IMF3B IMF3A
1
H'FFFF8204 TIERDL* OVE4 IME4D IME4C IME4B IME4A OVE5 IME5B IME5A
1
H'FFFF8205 TSRDL* OVF4 IMF4D IMF4C IMF4B IMF4A OVF5 IMF5B IMF5A
2
H'FFFF8206 TCR3* — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0 ATU
(channel 3)
2
H'FFFF8207 TCR4* — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0 ATU
(channel 4)
H'FFFF8208 TIOR3A*2 CCI3B IO3B2 IO3B1 IO3B0 CCI3A IO3A2 IO3A1 IO3A0 ATU
(channel 3)
H'FFFF8209 TIOR3B*2 CCI3D IO3D2 IO3D1 IO3D0 CCI3C IO3C2 IO3C1 IO3C0
H'FFFF820A TIOR4A*2 CCI4B IO4B2 IO4B1 IO4B0 CCI4A IO4A2 IO4A1 IO4A0 ATU
(channel 4)
H'FFFF820B TIOR4B*2 CCI4D IO4D2 IO4D1 IO4D0 CCI4C IO4C2 IO4C1 IO4C0
H'FFFF820C TCR5*2 — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0 ATU
(channel 5)
H'FFFF820D TIOR5A*2 CCI5B IO5B2 IO5B1 IO5B0 CCI5A IO5A2 IO5A1 IO5A0
H'FFFF820E TCNT3*3 ATU
(channel 3)
H'FFFF820F
H'FFFF8210 GR3A*3
H'FFFF8211
H'FFFF8212 GR3B*3
H'FFFF8213
H'FFFF8214 GR3C*3
H'FFFF8215
H'FFFF8216 GR3D*3
H'FFFF8217
Rev. 5.00 Jan 06, 2006 page 676 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF8218 TCNT4*3 ATU
(channel 4)
H'FFFF8219
H'FFFF821A GR4A*3
H'FFFF821B
3
H'FFFF821C GR4B*
H'FFFF821D
3
H'FFFF821E GR4C*
H'FFFF821F
3
H'FFFF8220 GR4D*
H'FFFF8221
3
H'FFFF8222 TCNT5* ATU
(channel 5)
H'FFFF8223
3
H'FFFF8224 GR5A*
H'FFFF8225
H'FFFF8226 GR5B*3
H'FFFF8227
H'FFFF8228 — — — — — — — — — —
to
H'FFFF823F
H'FFFF8240 TIERE*1 — CME6 — CME7 — CME8 — CME9 ATU
(channels
H'FFFF8241 TSRE*1 — CMF6 — CMF7 — CMF8 — CMF9
6–9)
2
H'FFFF8242 TCR7* — — — — — CKSEL2 CKSEL1 CKSEL0 ATU
(channel 7)
H'FFFF8243 TCR6*2 — — — — — CKSEL2 CKSEL1 CKSEL0 ATU
(channel 6)
(channel 9)
(channel 8)
Rev. 5.00 Jan 06, 2006 page 677 of 818

REJ09B0273-0500
Bit Names
Register
(channel 6)
H'FFFF8247
H'FFFF8248 CYLR6*3
H'FFFF8249
3
H'FFFF824A BFR6*
H'FFFF824B
3
H'FFFF824C DTR6*
H'FFFF824D
3
H'FFFF824E TCNT7* ATU
(channel 7)
H'FFFF824F
3
H'FFFF8250 CYLR7*
H'FFFF8251
3
H'FFFF8252 BFR7*
H'FFFF8253
H'FFFF8254 DTR7*3
H'FFFF8255
(channel 8)
H'FFFF8257
H'FFFF8258 CYLR8*3
H'FFFF8259
H'FFFF825A BFR8*3
H'FFFF825B
H'FFFF825C DTR8*3
H'FFFF825D
H'FFFF825E TCNT9*3 ATU
(channel 9)
H'FFFF825F
H'FFFF8260 CYLR9*3
H'FFFF8261
H'FFFF8262 BFR9*3
H'FFFF8263
H'FFFF8264 DTR9*3
H'FFFF8265
Rev. 5.00 Jan 06, 2006 page 678 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF8266 — — — — — — — — — —
to
H'FFFF827F
1
H'FFFF8280 TGSR* — — — — — TRG0D — TRG0A ATU
(channel 0)
H'FFFF8281 TIOR0A*1 IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0
1
H'FFFF8282 ITVRR* ITVAD3 ITVAD2 ITVAD1 ITVAD0 ITVE3 ITVE2 ITVE1 ITVE0
1
H'FFFF8283 TSRAH* — — — — IIF3 IIF2 IIF1 IIF0
1
H'FFFF8284 TIERA* — — — OVE0 ICE0D ICE0C ICE0B ICE0A
1
H'FFFF8285 TSRAL* — — — OVF0 ICF0D ICF0C ICF0B ICF0A
H'FFFF8286 — — — — — — — — —
H'FFFF8287 — — — — — — — — —
4
H'FFFF8288 TCNT0H*
H'FFFF8289
H'FFFF828A TCNT0L*4
H'FFFF828B
H'FFFF828C ICR0AH*4
H'FFFF828D
H'FFFF828E ICR0AL*4
H'FFFF828F
H'FFFF8290 ICR0BH*4
H'FFFF8291
H'FFFF8292 ICR0BL*4
H'FFFF8293
H'FFFF8294 ICR0CH*4
H'FFFF8295
H'FFFF8296 ICR0CL*4
H'FFFF8297
H'FFFF8298 ICR0DH*4
H'FFFF8299
H'FFFF829A ICR0DL*4
H'FFFF829B
H'FFFF829C — — — — — — — — — —
to
H'FFFF82BF
Rev. 5.00 Jan 06, 2006 page 679 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF82C0 TCR1*2 — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0 ATU
2 (channel 1)
H'FFFF82C1 TIOR1A* — IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0
H'FFFF82C2 TIOR1B*2 — IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0
2
H'FFFF82C3 TIOR1C* — IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0
1
H'FFFF82C4 TIERB* — OVE1 IME1F IME1E IME1D IME1C IME1B IME1A
1
H'FFFF82C5 TSRB* — OVF1 IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A
2
H'FFFF82C6 TCR2* — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0 ATU
2 (channel 2)
H'FFFF82C7 TIOR2A* — IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0
1
H'FFFF82C8 TIERC* — — — — — OVE2 IME2B IME2A
1
H'FFFF82C9 TSRC* — — — — — OVF2 IMF2B IMF2A
3
H'FFFF82CA TCNT2*
H'FFFF82CB
3
H'FFFF82CC GR2A*
H'FFFF82CD
H'FFFF82CE GR2B*3
H'FFFF82CF
H'FFFF82D0 TCNT1*3 ATU
(channel 1)
H'FFFF82D1
H'FFFF82D2 GR1A*3
H'FFFF82D3
H'FFFF82D4 GR1B*3
H'FFFF82D5
H'FFFF82D6 GR1C*3
H'FFFF82D7
H'FFFF82D8 GR1D*3
H'FFFF82D9
H'FFFF82DA GR1E*3
H'FFFF82DB
H'FFFF82DC GR1F*3
H'FFFF82DD
H'FFFF82DE OSBR*3
H'FFFF82DF
Rev. 5.00 Jan 06, 2006 page 680 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF82E0 TCR10*2 — CKSEL2A CKSEL1A CKSEL0A — CKSEL2B CKSEL1B CKSEL0B ATU
2 (channel
H'FFFF82E1 TCNR* CN10H CN10G CN10F CN10E CN10D CN10C CN10B CN10A
10)
H'FFFF82E2 TIERF*1 OSE10H OSE10G OSE10F OSE10E OSE10D OSE10C OSE10B OSE10A
1
H'FFFF82E3 TSRF* OSF10H OSF10G OSF10F OSF10E OSF10D OSF10C OSF10B OSF10A
H'FFFF82E4 — — — — — — — — —
1
H'FFFF82E5 DSTR* DST10H DST10G DST10F DST10E DST10D DST10C DST10B DST10A
H'FFFF82E6 — — — — — — — — —
H'FFFF82E7 — — — — — — — — —
H'FFFF82E8 — — — — — — — — — ATU (all
1 channels)
H'FFFF82E9 PSCR1* — — — PSCE PSCD PSCC PSCB PSCA
3
H'FFFF82EA TSTR* — — — — — — STR9 STR8
H'FFFF82EB STR7 STR6 STR5 STR4 STR3 STR2 STR1 STR0
H'FFFF82EC — — — — — — — — — —
to
H'FFFF82EF
H'FFFF82F0 DCNT10A*3 ATU
(channel
H'FFFF82F1
10)
H'FFFF82F2 DCNT10B*3
H'FFFF82F3
H'FFFF82F4 DCNT10C*3
H'FFFF82F5
H'FFFF82F6 DCNT10D*3
H'FFFF82F7
H'FFFF82F8 DCNT10E*3
H'FFFF82F9
H'FFFF82FA DCNT10F*3
H'FFFF82FB
H'FFFF82FC DCNT10G*3
H'FFFF82FD
H'FFFF82FE DCNT10H*3
H'FFFF82FF
Rev. 5.00 Jan 06, 2006 page 681 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF8300 — — — — — — — — — INTC
to
H'FFFF8347
H'FFFF8348 IPRA
H'FFFF8349
H'FFFF834A IPRB
H'FFFF834B
H'FFFF834C IPRC
H'FFFF834D
H'FFFF834E IPRD
H'FFFF834F
H'FFFF8350 IPRE
H'FFFF8351
H'FFFF8352 IPRF
H'FFFF8353
H'FFFF8354 IPRG
H'FFFF8355
H'FFFF8356 IPRH
H'FFFF8357
H'FFFF8358 ICR NMIL — — — — — — NMIE
H'FFFF8359 IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S
H'FFFF835A ISR — — — — — — — —
H'FFFF835B IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F
H'FFFF835C — — — — — — — — —
to
H'FFFF837F
H'FFFF8380 PADR*2 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR Port A
H'FFFF8381 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
H'FFFF8382 PAIOR*2 PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR
H'FFFF8383 PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR
H'FFFF8384 PACR*2 PA15MD PA14MD PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD
H'FFFF8385 PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD
Rev. 5.00 Jan 06, 2006 page 682 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF8386 PBDR*2 — — PB11DR PB10DR PB9DR PB8DR PB7DR PB6DR Port B
H'FFFF8387 — — PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
H'FFFF8388 PBIOR*2 — — PB11IOR PB10IOR PB9IOR PB8IOR PB7IOR PB6IOR
H'FFFF8389 — — PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR PB0IOR
2
H'FFFF838A PBCR* — PB11MD PB11MD PB10MD PB9MD PB8MD PB7MD PB6MD
1 0
H'FFFF838B — — PB5MD PB4MD PB3MD PB2MD PB1MD PB0MD
H'FFFF838C — — — — — — — — — —
to
H'FFFF838F
2
H'FFFF8390 PCDR* — PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR PC8DR Port C
H'FFFF8391 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
2
H'FFFF8392 PCIOR* — PC14IOR PC13IOR PC12IOR PC11IOR PC10IOR PC9IOR PC8IOR
H'FFFF8393 PC7IOR PC6IOR PC5IOR PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR
H'FFFF8394 PCCR1*2 — — PC14MD1 PC14MD0 PC13MD1 PC13MD0 PC12MD1 PC12MD0
H'FFFF8395 PC11MD1 PC11MD0 PC10MD1 PC10MD0 PC9MD1 PC9MD0 PC8MD1 PC8MD0

H'FFFF8396 PCCR2*2 PC7MD1 PC7MD0 PC6MD1 PC6MD0 — PC5MD — PC4MD
H'FFFF8397 — PC3MD — PC2MD — PC1MD — PC0MD
H'FFFF8398 PDDR*2 PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR Port D
H'FFFF8399 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
H'FFFF839A PDIOR*2 PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR
H'FFFF839B PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR
H'FFFF839C PDCR*2 PD15MD PD14MD PD13MD PD12MD PD11MD PD10MD PD9MD PD8MD
H'FFFF839D PD7MD PD6MD PD5MD PD4MD PD3MD PD2MD PD1MD PD0MD
H'FFFF839E CKCR — — — — — — — — Port
H'FFFF839F — — — — — — — CKLO
H'FFFF83A0 PEDR*2 — PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR Port E
H'FFFF83A1 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
H'FFFF83A2 PEIOR*2 — PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR
H'FFFF83A3 PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR
2
H'FFFF83A4 PECR* — PE14MD PE13MD PE12MD PE11MD PE10MD PE9MD PE8MD
H'FFFF83A5 PE7MD PE6MD PE5MD PE4MD PE3MD PE2MD PE1MD PE0MD
Rev. 5.00 Jan 06, 2006 page 683 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF83A6 PFDR*2 — — — — PF11DR PF10DR PF9DR PF8DR Port F
H'FFFF83A7 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR
H'FFFF83A8 PFIOR*2 — — — — PF11IOR PF10IOR PF9IOR PF8IOR
H'FFFF83A9 PF7IOR PF6IOR PF5IOR PF4IOR PF3IOR PF2IOR PF1IOR PF0IOR
2
H'FFFF83AA PFCR1* — — — — — — — —
H'FFFF83AB PF11MD1 PF11MD0 PF10MD1 PF10MD0 PF9MD1 PF9MD0 PF8MD1 PF8MD0
2
H'FFFF83AC PFCR2* PF7MD1 PF7MD0 PF6MD1 PF6MD0 PF5MD1 PF5MD0 PF4MD1 PF4MD0
H'FFFF83AD — PF3MD — PF2MD — PF1MD — PF0MD
2
H'FFFF83AE PGDR* PG15DR PG14DR PG13DR PG12DR PG11DR PG10DR PG9DR PG8DR Port G
H'FFFF83AF PG7DR PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR
2
H'FFFF83B0 PGIOR* PG15IOR PG14IOR PG13IOR PG12IOR PG11IOR PG10IOR PG9IOR PG8IOR
H'FFFF83B1 PG7IOR PG6IOR PG5IOR PG4IOR PG3IOR PG2IOR PG1IOR PG0IOR
2
H'FFFF83B2 PGCR1* PG15MD1 PG15MD0 PG14MD1 PG14MD0 — PG13MD — PG12MD
H'FFFF83B3 — PG11MD — PG10MD — PG9MD — PG8MD
H'FFFF83B4 PGCR2*2 — PG7MD — PG6MD — PG5MD — PG4MD
H'FFFF83B5 — PG3MD PG2MD PG1MD PG0MD1 PG0MD0 IRQMD1 IRQMD0
H'FFFF83B6 PHDR*2 PH15DR PH14DR PH13DR PH12DR PH11DR PH10DR PH9DR PH8DR Port H
H'FFFF83B7 PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR
H'FFFF83B8 ADTRGR*1 EXTRG — — — — — — — AD0
H'FFFF83B9 — — — — — — — — — —
to
H'FFFF83BF
H'FFFF83C0 POPCR*2 PULSE7ROE PULSE6ROE PULSE5ROE PULSE4ROE PULSE3ROE PULSE2ROE PULSE1ROE PULSE0ROE APC
H'FFFF83C1 PULSE7SOE PULSE6SOE PULSE5SOE PULSE4SOE PULSE3SOE PULSE2SOE PULSE1SOE PULSE0SOE
H'FFFF83C2 — — — — — — — — — —
to
H'FFFF83C7
H'FFFF83C8 SYSCR*1 — — — — — — — RAME (Power-
down
state)
H'FFFF83C9 — — — — — — — — — —
to
H'FFFF83CF
Rev. 5.00 Jan 06, 2006 page 684 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF83D0 CMSTR — — — — — — — — CMT (both
channels)
H'FFFF83D1 — — — — — — STR1 STR0
H'FFFF83D2 CMCSR0 — — — — — — — — CMT
(channel 0)
H'FFFF83D3 CMF CMIE — — — — CKS1 CKS0
H'FFFF83D4 CMCNT0
H'FFFF83D5
H'FFFF83D6 CMCOR0
H'FFFF83D7
H'FFFF83D8 CMCSR1 — — — — — — — — CMT
(channel 1)
H'FFFF83D9 CMF CMIE — — — — CKS1 CKS0
H'FFFF83DA CMCNT1
H'FFFF83DB
H'FFFF83DC CMCOR1
H'FFFF83DD
H'FFFF83DE — — — — — — — — — —
to
H'FFFF83FF
Notes: 1. Only 8-bit access permitted; 16-bit and 32-bit access prohibited.
2. 8-bit and 16-bit access permitted; 32-bit access prohibited.
3. Only 16-bit access permitted; 8-bit and 32-bit access prohibited.
4. Only 32-bit access permitted; 8-bit and 16-bit access prohibited
Rev. 5.00 Jan 06, 2006 page 685 of 818

REJ09B0273-0500
Table A.3 Three-Cycle, 8-Bit Access Space (8-Bit and 16-bit Access Permitted; 32-Bit
Access Prohibited)
Bit Names
Register
H'FFFF8400 — — — — — — — — — —
to
H'FFFF857F
H'FFFF8580 FLMCR1* FWE VPPE ESU PSU EV PV E P Flash
H'FFFF8581 FLMCR2* FLER — — — — — — —
H'FFFF8582 EBR1* EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
H'FFFF8583 — — — — — — — — — —
to
H'FFFF85CF
H'FFFF85D0 ADDR0H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD0
H'FFFF85D1 ADDR0L AD1 AD0 — — — — — —
H'FFFF85D2 ADDR1H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85DA ADDR5H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85DB ADDR5L AD1 AD0 — — — — — —
H'FFFF85DC ADDR6H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85DD ADDR6L AD1 AD0 — — — — — —
H'FFFF85DE ADDR7H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85DF ADDR7L AD1 AD0 — — — — — —
H'FFFF85E0 ADDR8H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85E1 ADDR8L AD1 AD0 — — — — — —
H'FFFF85E8 ADCSR0 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0
H'FFFF85E9 ADCR0 TRGE CKS ADST — — — — —
Rev. 5.00 Jan 06, 2006 page 686 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF85EA — — — — — — — — — —
to
H'FFFF85EF
H'FFFF85F0 ADDR12H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1
H'FFFF85F1 ADDR12L AD1 AD0 — — — — — —
H'FFFF85F2 ADDR13H AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FFFF85F8 ADCSR1 ADF ADIE ADST SCAN CKS — CH1 CH0
H'FFFF85F9 ADCR1 TRGE — — — — — — —
H'FFFF85FA — — — — — — — — — —
to
H'FFFF85FF
Note: * Only 8-bit access permitted; 16-bit and 32-bit access prohibited.
Rev. 5.00 Jan 06, 2006 page 687 of 818

REJ09B0273-0500
Table A.4 Three-Cycle, 16-Bit Access Space (In Principle, 8-Bit, 16-Bit, and 32-Bit Access
Permitted)
Bit Names
Register
H'FFFF8600 UBARH UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24 UBC
H'FFFF8601 UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16
H'FFFF8602 UBARL UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8
H'FFFF8603 UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0
H'FFFF8604 UBAMRH UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
H'FFFF8605 UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16
H'FFFF8606 UBAMRL UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8
H'FFFF8607 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0
H'FFFF8608 UBBR — — — — — — — —
H'FFFF8609 CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0
H'FFFF860A — — — — — — — — — —
to
H'FFFF860F
H'FFFF8610 TCSR*4 OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT
H'FFFF8611 TCNT*4
H'FFFF8612 — — — — — — — — —
H'FFFF8613 RSTCSR*4 WOVF RSTE — — — — — —
H'FFFF8614 SBYCR*1 SSBY HIZ — — — — — — (Power-
down
state)
H'FFFF8615 — — — — — — — — — —
to
H'FFFF861F
H'FFFF8620 BCR1 — — — — — — — — BSC
H'FFFF8621 — — — — A3SZ A2SZ A1SZ A0SZ
H'FFFF8622 BCR2 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00
H'FFFF8623 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0
H'FFFF8624 WCR1 W33 W32 W31 W30 W23 W22 W21 W20
H'FFFF8625 W13 W12 W11 W10 W03 W02 W01 W00
H'FFFF8626 WCR2 — — — — — — — —
H'FFFF8627 — — — — DSW3 DSW2 DSW1 DSW0
Rev. 5.00 Jan 06, 2006 page 688 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF8628 RAMER — — — — — — — — Flash
H'FFFF8629 — — — — — RAMS RAM1 RAM0
H'FFFF862A — — — — — — — — — —
to
H'FFFF86AF
2
H'FFFF86B0 DMAOR* — — — — — — PR1 PR0 DMAC (all
channels)
H'FFFF86B1 — — — — — AE NMIF DME
H'FFFF86B2 — — — — — — — — — —
to
H'FFFF86BF
5
H'FFFF86C0 SAR0* DMAC
(channel 0)
H'FFFF86C1
H'FFFF86C2
H'FFFF86C3
H'FFFF86C4 DAR0*5
H'FFFF86C5
H'FFFF86C6
H'FFFF86C7
H'FFFF86C8 DMATCR0*3 — — — — — — — —
H'FFFF86C9
H'FFFF86CA
H'FFFF86CB
H'FFFF86CC CHCR0*5 — — — — — — — —
H'FFFF86CD — — — — — RL AM AL
H'FFFF86CE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
H'FFFF86CF — DS TM TS1 TS0 IE TE DE
Rev. 5.00 Jan 06, 2006 page 689 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF86D0 SAR1*5 DMAC
(channel 1)
H'FFFF86D1
H'FFFF86D2
H'FFFF86D3
5
H'FFFF86D4 DAR1*
H'FFFF86D5
H'FFFF86D6
H'FFFF86D7
3
H'FFFF86D8 DMATCR1* — — — — — — — —
H'FFFF86D9
H'FFFF86DA
H'FFFF86DB
5
H'FFFF86DC CHCR1* — — — — — — — —
H'FFFF86DD — — — — — RL AM AL
H'FFFF86DE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
H'FFFF86DF — DS TM TS1 TS0 IE TE DE
H'FFFF86E0 SAR2*5 DMAC
(channel 2)
H'FFFF86E1
H'FFFF86E2
H'FFFF86E3
H'FFFF86E4 DAR2*5
H'FFFF86E5
H'FFFF86E6
H'FFFF86E7
H'FFFF86E8 DMATCR2*3 — — — — — — — —
H'FFFF86E9
H'FFFF86EA
H'FFFF86EB
H'FFFF86EC CHCR2*5 — — — — — — — —
H'FFFF86ED — — — — RO — — —
H'FFFF86EE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
H'FFFF86EF — — TM TS1 TS0 IE TE DE
Rev. 5.00 Jan 06, 2006 page 690 of 818

REJ09B0273-0500
Bit Names
Register
H'FFFF86F0 SAR3*5 DMAC
(channel 3)
H'FFFF86F1
H'FFFF86F2
H'FFFF86F3
5
H'FFFF86F4 DAR3*
H'FFFF86F5
H'FFFF86F6
H'FFFF86F7
3
H'FFFF86F8 DMATCR3* — — — — — — — —
H'FFFF86F9
H'FFFF86FA
H'FFFF86FB
5
H'FFFF86FC CHCR3* — — — — — — — —
H'FFFF86FD — — — DI — — — —
H'FFFF86FE DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
H'FFFF86FF — — TM TS1 TS0 IE TE DE
H'FFFF8700 — — — — — — — — — —
to
H'FFFF87FF
Notes: 1. Only 8-bit access permitted; 16-bit and 32-bit access prohibited.
4. This is the read address. The write address is H'FFFF8610 for the TCSR and TCNT,
and H'FFFF8612 for RSTCSR.
For details, see 12.2.4, Register Access, in section 12, Watchdog Timer.
5. 16-bit and 32-bit access permitted; 8-bit access prohibited.
Rev. 5.00 Jan 06, 2006 page 691 of 818

REJ09B0273-0500
A.2 Registers
Register name Abbreviation Address onto Access

of register which register size
name is mapped Name of on-chip
supporting
module
Serial Mode Register (SMR) H'FFFF81A0 (Channel 0) 8/16 SCI
Bit No. Bit: 7 6 5 4 3 2 1 0

Bit name: C/A CHR PE O/E STOP MP CKS1 CKS0
Initial Initial value: 0 0 0 0 0 0 0 0
value R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit names
Bit Bit Name Value Description (abbreviations).
Bits marked “—”
7 Communication mode (C/A) 0 Asynchronous mode (Initial value) are reserved.
1 Synchronous mode
6 Character length (CHR) 0 8-bit data (Initial value)
1 7-bit data
5 Parity enable (PE) 0 Parity bit addition and check disabled
(Initial value)
Type of access permitted 1 Parity bit addition and check enabled
R Read only 4 Parity mode (O/E) 0 Even parity (Initial value)
W Write only 1 Odd parity
R/W Read or write
3 Stop bit length (STOP) 0 1 stop bit (Initial value)
1 2 stop bits
2 Multiprocessor bit (MP) 0 Multiprocessor function disabled
(Initial value)
1, 0 Clock select 1, 0 0 0 φ clock (Initial value)
(CKS1, CKS0) 1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Full name Description

of bit of bit function
Rev. 5.00 Jan 06, 2006 page 692 of 818

REJ09B0273-0500
Serial Mode Register (SMR) H'FFFF81A0 (Channel 0) 8/16 SCI

H'FFFF81B0 (Channel 1)
H'FFFF81C0 (Channel 2)
Bit: 7 6 5 4 3 2 1 0
Bit name: C/A CHR PE O/E STOP MP CKS1 CKS0
Bit Bit Name Value Description

7 Communication mode (C/A) 0 Asynchronous mode (Initial value)
1 Synchronous mode
6 Character length (CHR) 0 8-bit data (Initial value)
1 7-bit data
5 Parity enable (PE) 0 Parity bit addition and check disabled
(Initial value)
1 Parity bit addition and check enabled
4 Parity mode (O/E) 0 Even parity (Initial value)
1 Odd parity
3 Stop bit length (STOP) 0 1 stop bit (Initial value)
1 2 stop bits
2 Multiprocessor bit (MP) 0 Multiprocessor function disabled (Initial value)
1, 0 Clock select 1, 0 0 0 φ clock (Initial value)
(CKS1, CKS0) 1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Rev. 5.00 Jan 06, 2006 page 693 of 818

REJ09B0273-0500
Bit Rate Register (BRR) H'FFFF81A1 (Channel 0) 8/16 SCI

Bit: 7 6 5 4 3 2 1 0
Bit name:
Bit Bit Name Description

7–0 (Bit mode setting) Serial transmit/receive bit rate setting
Rev. 5.00 Jan 06, 2006 page 694 of 818

REJ09B0273-0500
Serial Control Register (SCR) H'FFFF81A2 (Channel 0) 8/16 SCI

Bit: 7 6 5 4 3 2 1 0
Bit name: TIE RIE TE RE MPIE TEIE CKE1 CKE0

7 Transmit interrupt 0 Transmit-data-empty interrupt request (TXI) is disabled (Initial value)
enable (TIE)
1 Transmit-data-empty interrupt request (TXI) is enabled
6 Receive interrupt enable 0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
(RIE) (Initial value)
1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
5 Transmit enable (TE) 0 Transmitting is disabled (Initial value)
1 Transmitting is enabled
4 Receive enable (RE) 0 Receiving is disabled (Initial value)
1 Receiving is enabled
3 Multiprocessor interrupt 0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
enable (MPIE)
1. Clearing MPIE to 0
2. When data with MPB = 1 is received
1 Multiprocessor interrupts are enabled
Receive data full interrupt (RXI) and receive error interrupt (ERI) requests, and
setting of RDRF, FER, and ORER flags in SSR, are disabled until data with the
multiprocessor bit set to 1 is received.
2 Transmit-end interrupt 0 Transmit-end interrupt requests (TEI) are disabled (Initial value)
enable (TEIE)
1 Transmit-end interrupt requests (TEI) are enabled
1, 0 Clock enable 1 and 0 0 0 Asynchronous mode Internal clock, SCK pin used as input pin (input signal
(CKE1, CKE0) ignored) or output pin (output level undefined)
Synchronous mode Internal clock, SCK pin used for serial clock output
1 Asynchronous mode Internal clock, SCK pin used for clock output
Synchronous mode Internal clock, SCK pin used for serial clock output
1 0 Asynchronous mode External clock, SCK pin used for clock input
Synchronous mode External clock, SCK pin used for serial clock input
1 Asynchronous mode External clock, SCK pin used for clock input
Synchronous mode External clock, SCK pin used for serial clock input
Rev. 5.00 Jan 06, 2006 page 695 of 818

REJ09B0273-0500
Transmit Data Register (TDR) H'FFFF81A3 (Channel 0) 8/16 SCI

Bit: 7 6 5 4 3 2 1 0
Bit name:

7–0 (Transmit data storage) Serial transmit data
Rev. 5.00 Jan 06, 2006 page 696 of 818

REJ09B0273-0500
Serial Status Register (SSR) H'FFFF81A4 (Channel 0) 8/16 SCI

Bit: 7 6 5 4 3 2 1 0
Bit name: TDRE RDRF ORER FER PER TEND MPB MPBT
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W
Note: * Only 0 can be written to clear the flag.

7 Transmit data 0 Valid transmit data has been written in TDR.
register empty [Clearing conditions]
(TDRE)
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
1 There is no valid transmit data in TDR (Initial value)
1. Power-on reset, or transition to hardware standby mode or software
standby mode
2. TE is cleared to 0 in SCR
3. Data is transferred from TDR to TSR, enabling new data to be written
in TDR
6 Receive data 0 There is no valid receive data in RDR (Initial value)
register full [Clearing conditions]
(RDRF)
standby mode
2. Read RDRF when RDRF = 1, then write 0 in RDRF
3. The DMAC reads data from RDR
1 There is valid receive data in RDR
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
5 Overrun error 0 Receiving in progress, or completed normally (Initial value)
(ORER) [Clearing conditions]
standby mode
2. Read ORER when ORER = 1, then write 0 in ORER
1 Overrun error occurred during reception
[Setting condition]
Overrun error (reception of next serial data ends while RDRF = 1)
Rev. 5.00 Jan 06, 2006 page 697 of 818

REJ09B0273-0500

4 Framing error 0 Receiving in progress, or completed normally (Initial value)
(FER) [Clearing conditions]
standby mode
2. Read FER when FER = 1, then write 0 in FER
1 Framing error occurred during reception
[Setting condition]
Framing error (stop bit is 0)
3 Parity error (PER) 0 Receiving in progress, or completed normally (Initial value)
standby mode
2. Read PER when PER = 1, then write 0 in PER
1 Parity error occurred during reception
[Setting condition]
Parity error (parity of receive data does not match parity setting of O/E bit
in SMR)
2 Transmit end 0 Transmitting in progress
(TEND) [Clearing conditions]
1. Read TDRE when TDRE = 1, then write 0 in TDRE
2. The DMAC writes data in TDR
1 Transmitting has ended (Initial value)
standby mode
2. TE is cleared to 0 in SCR
3. TDRE = 1 when last bit of 1-byte serial transmit character is
transmitted
1 Multiprocessor bit 0 Multiprocessor bit value in receive data is 0 (Initial value)
(MPB) 1 Multiprocessor bit value in receive data is 1
0 Multiprocessor bit 0 Multiprocessor bit value in transmit data is 0 (Initial value)
transfer (MPBT) 1 Multiprocessor bit value in transmit data is 1
Rev. 5.00 Jan 06, 2006 page 698 of 818

REJ09B0273-0500
Receive Data Register (RDR) H'FFFF81A5 (Channel 0) 8/16 SCI

Bit: 7 6 5 4 3 2 1 0
Bit name:

7–0 (Receive data storage) Serial receive data
Rev. 5.00 Jan 06, 2006 page 699 of 818

REJ09B0273-0500
Timer Mode Register (TMDR) H'FFFF8200 8 ATU

(Channels 3 to 5)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — T5PWM T4PWM T3PWM

2 PWM mode 5 (T5PWM) 0 Channel 5 is in input capture/output compare mode
(Initial value)
1 Channel 5 is in PWM mode
(Initial value)
(Initial value)
Rev. 5.00 Jan 06, 2006 page 700 of 818

REJ09B0273-0500
Timer Interrupt Enable Register DH H'FFFF8202 8 ATU

(TIERDH) (Channels 3 to 5)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — OVE3 IME3D IME3C IME3B IME3A

4 Overflow interrupt enable 0 OVI3 interrupt requested by OVF3 flag is disabled
(OVE3) (Initial value)
1 OVI3 interrupt requested by OVF3 flag is enabled
3 Input capture/compare 0 IMI3D interrupt requested by IMF3D flag is
match interrupt enable disabled (Initial value)
(IME3D) 1 IMI3D interrupt requested by IMF3D flag is enabled
2 Input capture/compare 0 IMI3C interrupt requested by IMF3C flag is
(IME3C) 1 IMI3C interrupt requested by IMF3C flag is enabled
1 Input capture/compare 0 IMI3B interrupt requested by IMF3B flag is
(IME3B) 1 IMI3B interrupt requested by IMF3B flag is enabled
0 Input capture/compare 0 IMI3A interrupt requested by IMF3A flag is
(IME3A) 1 IMI3A interrupt requested by IMF3A flag is enabled
Rev. 5.00 Jan 06, 2006 page 701 of 818

REJ09B0273-0500
Timer Status Register DH H'FFFF8203 8 ATU

(TSRDH) (Channels 3 to 5)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — OVF3 IMF3D IMF3C IMF3B IMF3A

4 Overflow flag 0 [Clearing condition] (Initial value)
(OVF3) Read OVF3 when OVF3 =1, then write 0 in OVF3
TCNT3 overflowed from H'FFFF to H'0000
3 Input capture/ 0 [Clearing condition] (Initial value)
compare match flag Read IMF3D when IMF3D =1, then write 0 in IMF3D
(IMF3D)
1. TCNT3 value is transferred to GR3D by an input capture signal
when GR3D functions as an input capture register
2. TCNT3 = GR3D when GR3D functions as an output compare
register
compare match flag Read IMF3C when IMF3C =1, then write 0 in IMF3C
(IMF3C)
1. TCNT3 value is transferred to GR3C by an input capture signal
when GR3C functions as an input capture register
2. TCNT3 = GR3C when GR3C functions as an output compare
register
compare match flag Read IMF3B when IMF3B =1, then write 0 in IMF3B
(IMF3B)
1. TCNT3 value is transferred to GR3B by an input capture signal
when GR3B functions as an input capture register
2. TCNT3 = GR3B when GR3B functions as an output compare
register
compare match flag Read IMF3A when IMF3A =1, then write 0 in IMF3A
(IMF3A)
1. TCNT3 value is transferred to GR3A by an input capture signal
when GR3A functions as an input capture register
2. TCNT3 = GR3A when GR3A functions as an output compare
register
Rev. 5.00 Jan 06, 2006 page 702 of 818

REJ09B0273-0500
Timer Interrupt Enable Register DL H'FFFF8204 8 ATU

(TIERDL) (Channels 3 to 5)
Bit: 7 6 5 4 3 2 1 0
Bit name: OVE4 IME4D IME4C IME4B IME4A OVE5 IME5B IME5A

Rev. 5.00 Jan 06, 2006 page 703 of 818

REJ09B0273-0500
Timer Status Register DL H'FFFF8205 8 ATU

(TSRDL) (Channels 3 to 5)
Bit: 7 6 5 4 3 2 1 0
Bit name: OVF4 IMF4D IMF4C IMF4B IMF4A OVF5 IMF5B IMF5A

compare match Read IMF4D when IMF4D =1, then write 0 in IMF4D
flag (IMF4D)
1. TCNT4 value is transferred to GR4D by an input capture
signal when GR4D functions as an input capture register
2. TCNT4 = GR4D when GR4D functions as an output
compare register
compare match Read IMF4C when IMF4C =1, then write 0 in IMF4C
flag (IMF4C)
1. TCNT4 value is transferred to GR4C by an input capture
signal when GR4C functions as an input capture register
2. TCNT4 = GR4C when GR4C functions as an output
compare register
compare match Read IMF4B when IMF4B =1, then write 0 in IMF4B
flag (IMF4B)
1. TCNT4 value is transferred to GR4B by an input capture
signal when GR4B functions as an input capture register
2. TCNT4 = GR4B when GR4B functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 704 of 818

REJ09B0273-0500

compare match Read IMF4A when IMF4A =1, then write 0 in IMF4A
flag (IMF4A)
1. TCNT4 value is transferred to GR4A by an input capture
signal when GR4A functions as an input capture register
2. TCNT4 = GR4A when GR4A functions as an output
compare register
compare match Read IMF5B when IMF5B =1, then write 0 in IMF5B
flag (IMF5B)
1. TCNT5 value is transferred to GR5B by an input capture
signal when GR5B functions as an input capture register
compare register
compare match Read IMF5A when IMF5A =1, then write 0 in IMF5A
flag (IMF5A)
1. TCNT5 value is transferred to GR5A by an input capture
signal when GR5A functions as an input capture register
compare register
Rev. 5.00 Jan 06, 2006 page 705 of 818

REJ09B0273-0500
Timer Control Registers 1 to 5 H'FFFF82C0 (Channel 1) 8/16 ATU

(TCR1 to TCR5) H'FFFF82C6 (Channel 2) 8/16
H'FFFF8206 (Channel 3) 8/16
H'FFFF820C (Channel 5) 8/16
Bit: 7 6 5 4 3 2 1 0
Bit name: — — CKEG1 CKEG0 — CKSEL2 CKSEL1 CKSEL0
R/W: R R R/W R/W R R/W R/W R/W

5, 4 Clock edge 1 and 0 0 0 Rising edges counted (Initial value)
(CKEG1, CKEG0) 1 Falling edges counted
1 0 Both edges counted
1 External clock counting disabled
2, 1, 0 Clock select 2 to 0 0 0 0 Internal clock φ": counting on φ' (Initial value)
(CKSEL2 to CKSEL0) 1 Internal clock φ": counting on φ'/2
1 0 External clock: counting on TCLKA input
1 External clock: counting on TCLKB input
Rev. 5.00 Jan 06, 2006 page 706 of 818

REJ09B0273-0500
Timer I/O Control Registers H'FFFF8208 (Channel 3, 3A) 8/16 ATU

3A, 3B, 4A, 4B, 5A H'FFFF8209 (Channel 3, 3B) 8/16
(TIOR3A, TIORA3B, TIOR4A, H'FFFF820A (Channel 4, 4A) 8/16
TIOR4B, TIOR5A) H'FFFF820B (Channel 4, 4B) 8/16
H'FFFF820D (Channel 5, 5A) 8/16
TIOR3A
Bit: 7 6 5 4 3 2 1 0
Bit name: CCI3B IO3B2 IO3B1 IO3B0 CCI3A IO3A2 IO3A1 IO3A0
TIOR3B
Bit: 7 6 5 4 3 2 1 0
Bit name: CCI3D IO3D2 IO3D1 IO3D0 CCI3C IO3C2 IO3C1 IO3C0
TIOR4A
Bit: 7 6 5 4 3 2 1 0
TIOR4B
Bit: 7 6 5 4 3 2 1 0
Bit name: CCI4D IO4D2 IO4D1 IO4D0 CCI4C IO4C2 IO4C1 IO4C0
TIOR5A
Bit: 7 6 5 4 3 2 1 0
Rev. 5.00 Jan 06, 2006 page 707 of 818

REJ09B0273-0500

7 Clear counter enable flags 0 TCNT clearing disabled (Initial value)
3B, 3D, 4B, 4D, 5B 1 TCNT cleared by GR compare match
(CCI3B, CCI3D, CCI4B,
CCI4D, CCI5B)
6, 5, 4 I/O control 3B2–3B0, 3D2–3D0, 0 0 0 GR is output 0 output regardless of compare
4B2–4B0, 4D2–4D0, 5B2–5B0 compare match (Initial value)
(IO3B2–IO3B0, IO3D2–IO3D0, 1 register 0 output at GR compare match
IO4B2–IO4B0, IO4D2–IO4D0,
IO5B2–IO5B0) 1 0 1 output at GR compare match
1 Output toggles at GR compare
match
1 0 0 GR is input Input capture disabled
1 capture Input capture to GR at rising edge
register
1 0 Input capture to GR at falling edge
1 Input capture to GR at both edges
3 Clear counter enable flags 0 TCNT clearing disabled (Initial value)
3A, 3C, 4A, 4C, 5A 1 TCNT cleared by GR compare match
(CCI3A, CCI3C, CCI4A,
CCI4C, CCI5A)
2, 1, 0 I/O control 3A2–3A0, 3C2–3C0, 0 0 0 GR is output 0 output regardless of compare
4A2–4A0, 4C2–4C0, 5A2–5A0 compare match (Initial value)
(IO3A2–IO3A0, IO3C2–IO3C0, 1 register 0 output at GR compare match
IO4A2–IO4A0, IO4C2–IO4C0,
IO5A2–IO5A0) 1 0 1 output at GR compare match
match
1 capture Input capture to GR at rising edge
register
1 0 Input capture to GR at falling edge
1 Input capture to GR at both edges
Rev. 5.00 Jan 06, 2006 page 708 of 818

REJ09B0273-0500
Free-Running Counters 1 to 5 H'FFFF82D0 (Channel 1) 16 ATU

(TCNT1 to TCNT5) H'FFFF82CA (Channel 2) 16
H'FFFF820E (Channel 3) 16
H'FFFF8218 (Channel 4) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15–0 (16-bit up-counter, initial value H'0000) Counts input clock pulses
General Registers H'FFFF8210 (Channel 3, 3A) 16 ATU

3A to 3D, 4A to 4D, 5A, 5B H'FFFF8212 (Channel 3, 3B) 16
(GR3A to GR3D, GR4A to GR4D, H'FFFF8214 (Channel 3, 3C) 16
GR5A, GR5B) H'FFFF8216 (Channel 3, 3D) 16
H'FFFF821A (Channel 4, 4A) 16
H'FFFF821C (Channel 4, 4B) 16
H'FFFF821E (Channel 4, 4C) 16
H'FFFF8220 (Channel 4, 4D) 16
H'FFFF8224 (Channel 5, 5A) 16
H'FFFF8226 (Channel 5, 5B) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15–0 (Dual-function input capture/output 1. Input capture register: Stores TCNT1 value
compare register) when input capture signal is generated
2. Output compare register: Set with compare
match value
Rev. 5.00 Jan 06, 2006 page 709 of 818

REJ09B0273-0500
Timer Interrupt Enable Register E H'FFFF8240 8 ATU

(TIERE) (Channels 6 to 9)
Bit: 7 6 5 4 3 2 1 0
Bit name: — CME6 — CME7 — CME8 — CME9

6 Cycle register compare 0 CMI6 interrupt requested by CMF6 flag is disabled
match interrupt enable (Initial value)
(CME6) 1 CMI6 interrupt requested by CMF6 flag is enabled
Rev. 5.00 Jan 06, 2006 page 710 of 818

REJ09B0273-0500
Timer Status Register E (TSRE) H'FFFF8241 8 ATU

(Channels 6 to 9)
Bit: 7 6 5 4 3 2 1 0
Bit name: — CMF6 — CMF7 — CMF8 — CMF9
R/W: R R/(W)* R R/(W)* R R/(W)* R R/(W)*

6 Cycle register compare 0 [Clearing condition] (Initial value)
match flag (CMF6) Read CMF6 when CMF6 =1, then write 0 in CMF6
TCNT6 = CYLR6
TCNT7 = CYLR7
TCNT8 = CYLR8
TCNT9 = CYLR9
Rev. 5.00 Jan 06, 2006 page 711 of 818

REJ09B0273-0500
Timer Control Registers 6 to 9 H'FFFF8243 (Channel 6) 8/16 ATU

(TCR6 to TCR9) H'FFFF8242 (Channel 7) 8/16
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — CKSEL2 CKSEL1 CKSEL0

2, 1, 0 Clock select 2 to 0 0 0 0 Internal clock φ": counting on φ' (Initial value)
(CKSEL2 to CKSEL0)
1 0 —
1 —
Rev. 5.00 Jan 06, 2006 page 712 of 818

REJ09B0273-0500
Free-Running Counters 6 to 9 H'FFFF8246 (Channel 6) 16 ATU

(TCNT6 to TCNT9) H'FFFF824E (Channel 7) 16
H'FFFF825E (Channel 9) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Cycle Registers 6 to 9 H'FFFF8248 (Channel 6) 16 ATU

(CYLR6 to CYLR9) H'FFFF8250 (Channel 7) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15–0 (Cycle register) PWM cycle storage
Rev. 5.00 Jan 06, 2006 page 713 of 818

REJ09B0273-0500
Buffer Registers 6 to 9 H'FFFF824A (Channel 6) 16 ATU

(BFR6 to BFR9) H'FFFF8252 (Channel 7) 16
H'FFFF825A (Channel 8) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15–0 (Buffer register) BFR value is transferred to DTR by compare match with
corresponding cycle register, CYLR
Duty Registers 6 to 9 H'FFFF824C (Channel 6) 16 ATU

(DTR6 to DTR9) H'FFFF8254 (Channel 7) 16
H'FFFF825C (Channel 8) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15–0 (Duty register) PWM duty storage
Rev. 5.00 Jan 06, 2006 page 714 of 818

REJ09B0273-0500
Trigger Selection Register H'FFFF8280 (Channel 0) 8 ATU

(TGSR)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — TRG0D — TRG0A
R/W: R R R R R R/W R R/W

2 ICR0D input trigger 0 Input trigger is input pin (TID0) (Initial value)
(TRG0D) 1 Input trigger is channel 1 compare match signal
(TRG1A)
0 ICR0A input trigger 0 Input trigger is input pin (TIA0) (Initial value)
(TRG0A) 1 Input trigger is channel 1 compare match signal
(TRG1A)
Rev. 5.00 Jan 06, 2006 page 715 of 818

REJ09B0273-0500
Timer I/O Control Register 0A H'FFFF8281 (Channel 0) 8 ATU

(TIOR0A)
Bit: 7 6 5 4 3 2 1 0
Bit name: IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0

7, 6 I/O control 0D1, D0 0 0 Input capture disabled (Initial value)
(IO0D1, IO0D0) 1 Input capture to ICR0D at rising edge
1 0 Input capture to ICR0D at falling edge
1 Input capture to ICR0D at both edges
5, 4 I/O control 0C1, C0 0 0 Input capture disabled (Initial value)
(IO0C1, IO0C0) 1 Input capture to ICR0C at rising edge
1 0 Input capture to ICR0C at falling edge
1 Input capture to ICR0C at both edges
3, 2 I/O control 0B1, B0 0 0 Input capture disabled (Initial value)
(IO0B1, IO0B0) 1 Input capture to ICR0B at rising edge
1 0 Input capture to ICR0B at falling edge
1 Input capture to ICR0B at both edges
1, 0 I/O control 0A1, A0 0 0 Input capture disabled (Initial value)
(IO0A1, IO0A0) 1 Input capture to ICR0A at rising edge
1 0 Input capture to ICR0A at falling edge
1 Input capture to ICR0A at both edges
Rev. 5.00 Jan 06, 2006 page 716 of 818

REJ09B0273-0500
Interval Interrupt Request Register H'FFFF8282 (Channel 0) 8 ATU

(ITVRR)
Bit: 7 6 5 4 3 2 1 0
Bit name: ITVAD3 ITVAD2 ITVAD1 ITVAD0 ITVE3 ITVE2 ITVE1 ITVE0

7 A/D converter interval 0 A/D converter activation by ATU is disabled
activation bit 3 (ITVAD3) (Initial value)
3 Interval interrupt bit 3 0 Interval interrupt generation is disabled
(ITVE3) (Initial value)
1 Interval interrupt generation is enabled
Rev. 5.00 Jan 06, 2006 page 717 of 818

REJ09B0273-0500
Timer Status Register AH H'FFFF8283 (Channel 0) 8 ATU

(TSRAH)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — IIF3 IIF2 IIF1 IIF0
R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)*

3 Interval interrupt flag 0 [Clearing condition] (Initial value)
(IIF3) Read IIF3 when IIF3 =1, then write 0 in IIF3
When 1 is generated by AND of ITVE3 in ITVRR
and bit 13 of TCNT0L
Rev. 5.00 Jan 06, 2006 page 718 of 818

REJ09B0273-0500
Timer Interrupt Enable Register A H'FFFF8284 (Channel 0) 8 ATU

(TIERA)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — OVE0 ICE0D ICE0C ICE0B ICE0A

3 Input capture interrupt 0 ICI0D interrupt requested by ICF0D flag is disabled
enable (ICE0D) (Initial value)
1 ICI0D interrupt requested by ICF0D flag is enabled
2 Input capture interrupt 0 ICI0C interrupt requested by ICF0C flag is disabled
enable (ICE0C) (Initial value)
1 ICI0C interrupt requested by ICF0C flag is enabled
1 Input capture interrupt 0 ICI0B interrupt requested by ICF0B flag is disabled
enable (ICE0B) (Initial value)
1 ICI0B interrupt requested by ICF0B flag is enabled
0 Input capture interrupt 0 ICI0A interrupt requested by ICF0A flag is disabled
enable (ICE0A) (Initial value)
1 ICI0A interrupt requested by ICF0A flag is enabled
Rev. 5.00 Jan 06, 2006 page 719 of 818

REJ09B0273-0500
Timer Status Register AL (TSRAL) H'FFFF8285 (Channel 0) 8 ATU
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — OVF0 ICF0D ICF0C ICF0B ICF0A

TCNT0 overflowed from H'FFFFFFFF to H'00000000
3 Input capture flag 0 [Clearing condition] (Initial value)
(ICF0D) Read ICF0D when ICF0D =1, then write 0 in ICF0D
TCNT0 value is transferred to input capture register
ICR0D by an input capture signal
(ICF0C) Read ICF0C when ICF0C =1, then write 0 in ICF0C
ICR0C by an input capture signal
1 Input capture flag 0 [Clearing conditions] (Initial value)
(ICF0B) 1. Read ICF0B when ICF0B =1, then write 0 in ICF0B
2. When cleared by the DMAC in data transfer
ICR0B by an input capture signal
(ICF0A) Read ICF0A when ICF0A =1, then write 0 in ICF0A
ICR0A by an input capture signal
Rev. 5.00 Jan 06, 2006 page 720 of 818

REJ09B0273-0500
Free-Running Counters 0H, 0L H'FFFF8288 (Channel 0) 32 ATU

(TCNT0H, TCNT0L) H'FFFF828A (Channel 0)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rev. 5.00 Jan 06, 2006 page 721 of 818

REJ09B0273-0500
Input Capture Registers H'FFFF828C (Channel 0) 32 ATU

0AH, L to 0DH, L H'FFFF828E (Channel 0)
(ICR0AH, L to ICR0DH, L) H'FFFF8290 (Channel 0) 32
H'FFFF8292 (Channel 0)
H'FFFF8296 (Channel 0)
H'FFFF829A (Channel 0)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31–0 (Dedicated input capture register) Stores TCNT value when input capture signal is
generated
Rev. 5.00 Jan 06, 2006 page 722 of 818

REJ09B0273-0500
Timer I/O Control Registers H'FFFF82C1 (Channel 1, 1A) 8/16 ATU

1A to 1C, 2A H'FFFF82C2 (Channel 1, 1B) 8/16
(TIOR1A to TIOR1C, TIOR2A) H'FFFF82C3 (Channel 1, 1C) 8/16
H'FFFF82C7 (Channel 2, 2A) 8/16
TIOR1A
Bit: 7 6 5 4 3 2 1 0
Bit name: — IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0
TIOR1B
Bit: 7 6 5 4 3 2 1 0
Bit name: — IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0
TIOR1C
Bit: 7 6 5 4 3 2 1 0
Bit name: — IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0
TIOR2A
Bit: 7 6 5 4 3 2 1 0
Bit name: — IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0
Rev. 5.00 Jan 06, 2006 page 723 of 818

REJ09B0273-0500

6, 5, 4 I/O control 1B2–IB0, ID2–ID0, 0 0 0 GR is output 0 output regardless of compare
IF2–1F0, 2B2–2B0 compare match (Initial value)
(IO1B2–IO1B0, IO1D2–IO1D0, register
1 0 output at GR compare match
IO1F2–IO1F0, IO2B2–IO2B0)
1 0 1 output at GR compare match
match
capture
1 Input capture to GR at rising edge
register
1 0 Input capture to GR at falling
edge
1 Input capture to GR at both
edges
2, 1, 0 I/O control 1A2–1A0, 0 0 0 GR is output 0 output regardless of compare
IC2–IC0, 1E2–1E0, 2A2–2A0 compare match (Initial value)
(IO1A2–IO1A0, IO1C2–IO1C0, register
1 0 output at GR compare match
IO1E2–IO1E0, IO2A2–IO2A0)
1 0 1 output at GR compare match
match
capture
1 Input capture to GR at rising edge
register
1 0 Input capture to GR at falling
edge
1 Input capture to GR at both
edges
Rev. 5.00 Jan 06, 2006 page 724 of 818

REJ09B0273-0500
Timer Interrupt Enable Register B H'FFFF82C4 (Channel 1) 8 ATU

(TIERB)
Bit: 7 6 5 4 3 2 1 0
Bit name: — OVE1 IME1F IME1E IME1D IME1C IME1B IME1A

5 Input capture/compare 0 IMI1F interrupt requested by IMF1F flag is disabled
(IME1F) 1 IMI1F interrupt requested by IMF1F flag is enabled
4 Input capture/compare 0 IMI1E interrupt requested by IMF1E flag is
(IME1E) 1 IMI1E interrupt requested by IMF1E flag is enabled
Rev. 5.00 Jan 06, 2006 page 725 of 818

REJ09B0273-0500
Timer Status Register B (TSRB) H'FFFF82C5 (Channel 1) 8 ATU
Bit: 7 6 5 4 3 2 1 0
Bit name: — OVF1 IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A
R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*

compare match flag Read IMF1F when IMF1F =1, then write 0 in IMF1F
(IMF1F)
1. TCNT1 value is transferred to GR1F by an input
capture signal when GR1F functions as an input
capture register
2. TCNT1 = GR1F when GR1F functions as an output
compare register
compare match flag Read IMF1E when IMF1E =1, then write 0 in IMF1E
(IMF1E)
1. TCNT1 value is transferred to GR1E by an input
capture signal when GR1E functions as an input
capture register
2. TCNT1 = GR1E when GR1E functions as an output
compare register
compare match flag Read IMF1D when IMF1D =1, then write 0 in IMF1D
(IMF1D)
1. TCNT1 value is transferred to GR1D by an input
capture signal when GR1D functions as an input
capture register
2. TCNT1 = GR1D when GR1D functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 726 of 818

REJ09B0273-0500

compare match flag Read IMF1C when IMF1C =1, then write 0 in IMF1C
(IMF1C)
1. TCNT1 value is transferred to GR1C by an input
capture signal when GR1C functions as an input
capture register
2. TCNT1 = GR1C when GR1C functions as an output
compare register
compare match flag Read IMF1B when IMF1B =1, then write 0 in IMF1B
(IMF1B)
1. TCNT1 value is transferred to GR1B by an input
capture signal when GR1B functions as an input
capture register
compare register
compare match flag Read IMF1A when IMF1A =1, then write 0 in IMF1A
(IMF1A)
1. TCNT1 value is transferred to GR1A by an input
capture signal when GR1A functions as an input
capture register
compare register
Rev. 5.00 Jan 06, 2006 page 727 of 818

REJ09B0273-0500
Timer Interrupt Enable Register C H'FFFF82C8 (Channel 2) 8 ATU

(TIERC)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — OVE2 IME2B IME2A

Rev. 5.00 Jan 06, 2006 page 728 of 818

REJ09B0273-0500
Timer Status Register C (TSRC) H'FFFF82C9 (Channel 2) 8 ATU
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — OVF2 IMF2B IMF2A
R/W: R R R R R R/(W)* R/(W)* R/(W)*

2 Overflow flag (OVF2) 0 [Clearing condition] (Initial value)
Read OVF2 when OVF2 =1, then write 0 in OVF2
1 Input capture/compare 0 [Clearing condition] (Initial value)
match flag (IMF2B) Read IMF2B when IMF2B =1, then write 0 in
IMF2B
1. TCNT2 value is transferred to GR2B by an
input capture signal when GR2B functions as
an input capture register
2. TCNT2 = GR2B when GR2B functions as an
output compare register
0 Input capture/compare 0 [Clearing condition] (Initial value)
match flag (IMF2A) Read IMF2A when IMF2A =1, then write 0 in
IMF2A
1. TCNT2 value is transferred to GR2A by an
input capture signal when GR2A functions as
an input capture register
2. TCNT2 = GR2A when GR2A functions as an
output compare register
Rev. 5.00 Jan 06, 2006 page 729 of 818

REJ09B0273-0500
General Registers 2A, 2B H'FFFF82CC (Channel 2, 2A) 16 ATU

(GR2A, GR2B) H'FFFF82CE (Channel 2, 2B) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

match value
General Registers 1A to 1F H'FFFF82D2 (Channel 1, 1A) 16 ATU

(GR1A to GR1F) H'FFFF82D4 (Channel 1, 1B) 16
H'FFFF82D6 (Channel 1, 1C) 16
H'FFFF82D8 (Channel 1, 1D) 16
H'FFFF82DA (Channel 1, 1E) 16
H'FFFF82DC (Channel 1, 1F) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

match value
Rev. 5.00 Jan 06, 2006 page 730 of 818

REJ09B0273-0500
Offset Base Register (OSBR) H'FFFF82DE (Channel 1) 16 ATU
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15–0 Dedicated input capture register with Stores TCNT1 value at edge(s) selected by
signal from channel 0 ICR0A as input TIORA bits 0 and 1
trigger
Rev. 5.00 Jan 06, 2006 page 731 of 818

REJ09B0273-0500
Timer Control Register 10 H'FFFF82E0 (Channel 10) 8/16 ATU

(TCR10)
Bit: 7 6 5 4 3 2 1 0
Bit name: — CKSEL2A CKSEL1A CKSEL0A — CKSEL2B CKSEL1B CKSEL0B

6, 5, 4 Clock select 2A–0A 0 0 0 Internal clock φ": counting on φ' (Initial value)
(CKSEL2A–CKSEL0A) 1 Internal clock φ": counting on φ'/2
1 0 —
1 —
2, 1, 0 Clock select 2B–0B 0 0 0 Internal clock φ": counting on φ' (Initial value)
(CKSEL2B–CKSEL0B) 1 Internal clock φ": counting on φ'/2
1 0 —
1 —
Rev. 5.00 Jan 06, 2006 page 732 of 818

REJ09B0273-0500
Timer Connection Register H'FFFF82E1 (Channel 10) 8/16 ATU

(TCNR)
Bit: 7 6 5 4 3 2 1 0
Bit name: CN10H CN10G CN10F CN10E CN10D CN10C CN10B CN10A

7 Connection flag 10H 0 Connection between DST10H and OFF2B is disabled
(CN10H) (Initial value)
1 Connection between DST10H and OFF2B is enabled
6 Connection flag 10G 0 Connection between DST10G and OFF2A is disabled
(CN10G) (Initial value)
1 Connection between DST10G and OFF2A is enabled
5 Connection flag 10F 0 Connection between DST10F and OFF1F is disabled
(CN10F) (Initial value)
1 Connection between DST10F and OFF1F is enabled
4 Connection flag 10E 0 Connection between DST10E and OFF1E is disabled
(CN10E) (Initial value)
1 Connection between DST10E and OFF1E is enabled
3 Connection flag 10D 0 Connection between DST10D and OFF1D is disabled
(CN10D) (Initial value)
1 Connection between DST10D and OFF1D is enabled
2 Connection flag 10C 0 Connection between DST10C and OFF1C is disabled
(CN10C) (Initial value)
1 Connection between DST10C and OFF1C is enabled
1 Connection flag 10B 0 Connection between DST10B and OFF1B is disabled
(CN10B) (Initial value)
1 Connection between DST10B and OFF1B is enabled
0 Connection flag 10A 0 Connection between DST10A and OFF1A is disabled
(CN10A) (Initial value)
1 Connection between DST10A and OFF1A is enabled
Rev. 5.00 Jan 06, 2006 page 733 of 818

REJ09B0273-0500
Timer Interrupt Enable Register F H'FFFF82E2 (Channel 10) 8 ATU

(TIERF)
Bit: 7 6 5 4 3 2 1 0
Bit name: OSE10H OSE10G OSE10F OSE10E OSE10D OSE10C OSE10B OSE10A

7 One-shot pulse 0 OSI10H interrupt requested by OSF10H flag is disabled
interrupt enable (Initial value)
(OSE10H) 1 OSI10H interrupt requested by OSF10H flag is enabled
6 One-shot pulse 0 OSI10G interrupt requested by OSF10G flag is disabled
(OSE10G) 1 OSI10G interrupt requested by OSF10G flag is enabled
5 One-shot pulse 0 OSI10F interrupt requested by OSF10F flag is disabled
(OSE10F) 1 OSI10F interrupt requested by OSF10F flag is enabled
4 One-shot pulse 0 OSI10E interrupt requested by OSF10E flag is disabled
(OSE10E) 1 OSI10E interrupt requested by OSF10E flag is enabled
3 One-shot pulse 0 OSI10D interrupt requested by OSF10D flag is disabled
(OSE10D) 1 OSI10D interrupt requested by OSF10D flag is enabled
2 One-shot pulse 0 OSI10C interrupt requested by OSF10C flag is disabled
(OSE10C) 1 OSI10C interrupt requested by OSF10C flag is enabled
1 One-shot pulse 0 OSI10B interrupt requested by OSF10B flag is disabled
(OSE10B) 1 OSI10B interrupt requested by OSF10B flag is enabled
0 One-shot pulse 0 OSI10A interrupt requested by OSF10A flag is disabled
(OSE10A) 1 OSI10A interrupt requested by OSF10A flag is enabled
Rev. 5.00 Jan 06, 2006 page 734 of 818

REJ09B0273-0500
Timer Status Register F (TSRF) H'FFFF82E3 (Channel 10) 8 ATU
Bit: 7 6 5 4 3 2 1 0
Bit name: OSF10H OSF10G OSF10F OSF10E OSF10D OSF10C OSF10B OSF10A

7 One-shot pulse 0 [Clearing condition] (Initial value)
flag (OSF10H) Read OSF10H when OSF10H =1, then write 0 in OSF10H
Down-counter (DCNT10H) value underflowed
flag (OSF10G) Read OSF10G when OSF10G =1, then write 0 in OSF10G
Down-counter (DCNT10G) value underflowed
flag (OSF10F) Read OSF10F when OSF10F =1, then write 0 in OSF10F
Down-counter (DCNT10F) value underflowed
flag (OSF10E) Read OSF10E when OSF10E =1, then write 0 in OSF10E
Down-counter (DCNT10E) value underflowed
flag (OSF10D) Read OSF10D when OSF10D =1, then write 0 in OSF10D
Down-counter (DCNT10D) value underflowed
flag (OSF10C) Read OSF10C when OSF10C =1, then write 0 in OSF10C
Down-counter (DCNT10C) value underflowed
Rev. 5.00 Jan 06, 2006 page 735 of 818

REJ09B0273-0500

flag (OSF10B) Read OSF10B when OSF10B =1, then write 0 in OSF10B
Down-counter (DCNT10B) value underflowed
flag (OSF10A) Read OSF10A when OSF10A =1, then write 0 in OSF10A
Down-counter (DCNT10A) value underflowed
Rev. 5.00 Jan 06, 2006 page 736 of 818

REJ09B0273-0500
Down-Count Start Register (DSTR) H'FFFF82E5 (Channel 10) 8 ATU
Bit: 7 6 5 4 3 2 1 0
Bit name: DST10H DST10G DST10F DST10E DST10D DST10C DST10B DST10A
Note: * Only 1 can be written.

7 Down-count start flag 0 DCNT10H is halted (Initial value)
10H (DST10H) [Clearing condition]
DCNT10H value underflowed
1 DCNT10H counts
Offset one-shot pulse function: Set by GR2B compare-match, or
by user program
6 Down-count start flag 0 DCNT10G is halted (Initial value)
10G (DST10G)
DCNT10G value underflowed
1 DCNT10G counts
Offset one-shot pulse function: Set by GR2A compare-match, or
by user program
5 Down-count start flag 0 DCNT10F is halted (Initial value)
10F (DST10F)
DCNT10F value underflowed
1 DCNT10F counts
Offset one-shot pulse function: Set by GR1F compare-match, or
by user program
Rev. 5.00 Jan 06, 2006 page 737 of 818

REJ09B0273-0500

4 Down-count start flag 0 DCNT10E is halted (Initial value)
10E (DST10E)
DCNT10E value underflowed
1 DCNT10E counts
Offset one-shot pulse function: Set by GR1E compare-match, or
by user program
3 Down-count start flag 0 DCNT10D is halted (Initial value)
10D (DST10D) [Clearing condition]
DCNT10D value underflowed
1 DCNT10D counts
Offset one-shot pulse function: Set by GR1D compare-match, or
by user program
2 Down-count start flag 0 DCNT10C is halted (Initial value)
10C (DST10C) [Clearing condition]
DCNT10C value underflowed
1 DCNT10C counts
Offset one-shot pulse function: Set by GR1C compare-match, or
by user program
1 Down-count start flag 0 DCNT10B is halted (Initial value)
10B (DST10B) [Clearing condition]
DCNT10B value underflowed
1 DCNT10B counts
Offset one-shot pulse function: Set by GR1B compare-match, or
by user program
0 Down-count start flag 0 DCNT10A is halted (Initial value)
10A (DST10A)
DCNT10A value underflowed
1 DCNT10A counts
Offset one-shot pulse function: Set by GR1A compare-match, or
by user program
Rev. 5.00 Jan 06, 2006 page 738 of 818

REJ09B0273-0500
Prescaler Register 1 (PSCR1) H'FFFF82E9 8 ATU

(All Channels)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — PSCE PSCD PSCC PSCB PSCA

4–0 (Prescaler register) Counter clock φ' value
Rev. 5.00 Jan 06, 2006 page 739 of 818

REJ09B0273-0500
Timer Start Register (TSTR) H'FFFF82EA 16 ATU

(All Channels)
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — STR9 STR8
Bit: 7 6 5 4 3 2 1 0
Bit name: STR7 STR6 STR5 STR4 STR3 STR2 STR1 STR0

9 Counter start 9 (STR9) 0 TCNT9 is halted (Initial value)
1 TCNT9 counts
1 TCNT8 counts
1 TCNT7 counts
1 TCNT6 counts
1 TCNT5 counts
1 TCNT4 counts
1 TCNT3 counts
1 TCNT2 counts
1 TCNT1 counts
1 TCNT0 counts
Rev. 5.00 Jan 06, 2006 page 740 of 818

REJ09B0273-0500
Down-Counters 10A to 10H H'FFFF82F0 (Channel 10, 10A) 16 ATU

(DCNT10A to DCNT10H) H'FFFF82F2 (Channel 10, 10B) 16
H'FFFF82F4 (Channel 10, 10C) 16
H'FFFF82F6 (Channel 10, 10D) 16
H'FFFF82F8 (Channel 10, 10E) 16
H'FFFF82FA (Channel 10, 10F) 16
H'FFFF82FC (Channel 10, 10G) 16
H'FFFF82FE (Channel 10, 10H) 16
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15–0 (Down-counter) Decremented by input clock pulses
Rev. 5.00 Jan 06, 2006 page 741 of 818

REJ09B0273-0500
Interrupt Priority Registers A to H H'FFFF8348 (IPRA) 8/16/32 INTC

(IPRA to IPRH) H'FFFF834A (IPRB)
H'FFFF834C (IPRC)
H'FFFF834E (IPRD)
H'FFFF8350 (IPRE)
H'FFFF8352 (IPRF)
H'FFFF8354 (IPRG)
H'FFFF8356 (IPRH)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Register 15–12 11–8 7–4 3–0
Interrupt priority register A IRQ0 IRQ1 IRQ2 IRQ3
Interrupt priority register B IRQ4 IRQ5 IRQ6 IRQ7
Interrupt priority register C DMAC0, 1 DMAC2, 3 ATU01 ATU02
Interrupt priority register D ATU03 ATU11 ATU12 ATU13
Interrupt priority register E ATU2 ATU31 ATU32 ATU41
Interrupt priority register F ATU42 ATU5 ATU6–9 ATU101
Interrupt priority register G ATU102 ATU103 CMT0, A/D0 CMT1, A/D1
Interrupt priority register H SCI0 SCI1 SCI2 WDT
Rev. 5.00 Jan 06, 2006 page 742 of 818

REJ09B0273-0500
Interrupt Control Register (ICR) H'FFFF8358 8/16/32 INTC
Bit: 15 14 13 12 11 10 9 8
Bit name: NMIL — — — — — — NMIE
Initial value: * 0 0 0 0 0 0 0
Bit: 7 6 5 4 3 2 1 0
Bit name: IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S
Note: * 1 when the NMI pin is high, 0 when low.

15 NMI input level (NMIL) 0 Low level input at NMI pin
1 High level input at NMI pin
8 NMI edge select (NMIE) 0 Interrupt request detected on falling edge of NMI
input (Initial value)
1 Interrupt request detected on rising edge of NMI
input
7–0 IRQ0 to IRQ7 sense select 0 Interrupt request detected on low level of IRQ input
(IRQ0S to IRQ7S) (Initial value)
1 Interrupt request detected on falling edge of IRQ
input
Rev. 5.00 Jan 06, 2006 page 743 of 818

REJ09B0273-0500
IRQ Status Register (ISR) H'FFFF835A 8/16/32 INTC
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F
Detection
Bit Bit Name Value Setting Description
7–0 IRQ0 to IRQ7 flags 0 Level There is no IRQn interrupt request
(IRQ0F to IRQ7F) detection [Clearing condition]
IRQn input is high
Edge IRQn interrupt request has not been
detection detected (Initial value)
1. Read IRQnF when IRQnF =1, then
write 0 in IRQnF
2. IRQn interrupt exception handling is
carried out
1 Level There is an IRQn interrupt request
detection [Setting condition]
IRQn input is low
Edge IRQn interrupt request has been detected
detection [Setting condition]
Falling edge in IRQn input
Rev. 5.00 Jan 06, 2006 page 744 of 818

REJ09B0273-0500
Port A Data Register (PADR) H'FFFF8380 8/16 Port A
Bit: 15 14 13 12 11 10 9 8
Bit name: PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
Bit Value Pin Function Read Write

15–0 0 Generic input Pin state PADR can be written to, but the pin state is
not affected
Other than Pin state PADR can be written to, but the pin state is
generic input not affected
1 Generic output PADR value Write value is output at the pin (POD pin is
high)
High-impedance regardless of PADR value
(POD pin is low)
Other than PADR value PADR can be written to, but the pin state is
generic output not affected
Rev. 5.00 Jan 06, 2006 page 745 of 818

REJ09B0273-0500
Port A IO Register (PAIOR) H'FFFF8382 8/16 Port A
Bit: 15 14 13 12 11 10 9 8
Bit name: PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR

15–0 Port A IO register 0 Input (Initial value)
(PA15IOR to PA0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 746 of 818

REJ09B0273-0500
Port A Control Register (PACR) H'FFFF8384 8/16 Port A
Bit: 15 14 13 12 11 10 9 8
Bit name: PA15MD PA14MD PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD
Bit: 7 6 5 4 3 2 1 0
Bit name: PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD
Pin Function
Bit Bit Name Value with ROM Disabled with ROM Enabled Single-Chip Mode
15 PA15 mode bit 0 Address output (A15) Generic input/output Generic input/output (PA15)
(PA15MD) (Initial value) (PA15) (Initial value) (Initial value)
1 Address output (A15) Address output (A15) Generic input/output (PA15)
Rev. 5.00 Jan 06, 2006 page 747 of 818

REJ09B0273-0500
Pin Function
Rev. 5.00 Jan 06, 2006 page 748 of 818

REJ09B0273-0500
Port B Data Register (PBDR) H'FFFF8386 8/16 Port B
Bit: 15 14 13 12 11 10 9 8
Bit name: — — PB11DR PB10DR PB9DR PB8DR PB7DR PB6DR
Bit: 7 6 5 4 3 2 1 0
Bit name: — — PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR

13, 5–0 0 Generic input Pin state PBDR can be written to, but the pin state is
not affected
Other than Pin state PBDR can be written to, but the pin state is
1 Generic output PBDR value Write value is output at the pin (POD pin is
high)
High-impedance regardless of PBDR value
(POD pin is low)
Other than PBDR value PBDR can be written to, but the pin state is
12–8 0 Generic input Pin state PBDR can be written to, but the pin state is
not affected
Other than Pin state PBDR can be written to, but the pin state is
1 Generic output PBDR value Write value is output at the pin
Other than PBDR value PBDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 749 of 818

REJ09B0273-0500
Port B IO Register (PBIOR) H'FFFF8388 8/16 Port B
Bit: 15 14 13 12 11 10 9 8
Bit name: — — PB11IOR PB10IOR PB9IOR PB8IOR PB7IOR PB6IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: — — PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR PB0IOR

13–8, Port B IO register 0 Input (Initial value)
5–0 (PB11IOR to PB6IOR, PB5IOR to PB0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 750 of 818

REJ09B0273-0500
Port B Control Register (PBCR) H'FFFF838A 8/16 Port B
Bit: 15 14 13 12 11 10 9 8
Bit name: — PB11MD1 PB11MD0 PB10MD PB9MD PB8MD PB7MD PB6MD
Bit: 7 6 5 4 3 2 1 0
Bit name: — — PB5MD PB4MD PB3MD PB2MD PB1MD PB0MD
Pin Function
14, PB11 mode bit 0 0 Address output (A21) Generic input/output Generic input/output (PB11)
13 1, 0 (PB11MD1, (Initial value) (PB11) (Initial value) (Initial value)
PB11MD0)
1 Address output (A21) Address output (A21) Generic input/output (PB11)
1 0 Address output (A21) Port output disable input Port output disable input
(POD) (POD)
1 Reserved Reserved Reserved
12 PB10 mode bit 0 Address output (A20) Generic input/output Generic input/output (PB10)
(PB10MD) (Initial value) (PB10) (Initial value) (Initial value)
Rev. 5.00 Jan 06, 2006 page 751 of 818

REJ09B0273-0500
Pin Function
5 PB5 mode bit 0 Generic input/output (PB5) (Initial value)
(PB5MD)
1 ATU clock input (TCLKB)
(PB4MD)
1 ATU clock input (TCLKA)
(PB3MD)
(PB2MD)
(PB1MD)
(PB0MD)
Rev. 5.00 Jan 06, 2006 page 752 of 818

REJ09B0273-0500
Port C Data Register (PCDR) H'FFFF8390 8/16 Port C
Bit: 15 14 13 12 11 10 9 8
Bit name: — PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR PC8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

14–0 0 Generic input Pin state PCDR can be written to, but the pin state is
not affected
Other than Pin state PCDR can be written to, but the pin state is
1 Generic output PCDR value Write value is output at the pin (POD pin is
high)
High-impedance regardless of PCDR value
(POD pin is low)
Other than PCDR value PCDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 753 of 818

REJ09B0273-0500
Port C IO Register (PCIOR) H'FFFF8392 8/16 Port C
Bit: 15 14 13 12 11 10 9 8
Bit name: — PC14IOR PC13IOR PC12IOR PC11IOR PC10IOR PC9IOR PC8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PC7IOR PC6IOR PC5IOR PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR

14–0 Port C IO register 0 Input (Initial value)
(PC14IOR to PC0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 754 of 818

REJ09B0273-0500
Port C Control Registers 1 and 2 H'FFFF8394 (PCCR1) 8/16 Port C

(PCCR1, PCCR2) H'FFFF8396 (PCCR2)
PCCR1
Bit: 15 14 13 12 11 10 9 8
Bit name: — — PC14MD1 PC14MD0 PC13MD1 PC13MD0 PC12MD1 PC12MD0
Bit: 7 6 5 4 3 2 1 0
Bit name: PC11MD1 PC11MD0 PC10MD1 PC10MD0 PC9MD1 PC9MD0 PC8MD1 PC8MD0
Pin Function
Bit Bit Name Value Expanded Mode Single-Chip Mode
13, 12 PC14 mode bit 0 0 Generic input/output (PC14) Generic input/output (PC14)
1, 0 (PC14MD1, (Initial value) (Initial value)
PC14MD0) 1 ATU one-shot pulse output ATU one-shot pulse
(TOH10) output (TOH10)
1 0 Reserved Reserved
1 Reserved Reserved
(TOG10) output (TOG10)
1 Reserved Reserved
(TOF10) output (TOF10)
1 0 DMAC DREQ1 acknowledge DMAC DREQ1 acknowledge
signal output (DRAK1) signal output (DRAK1)
1 Reserved Reserved
Rev. 5.00 Jan 06, 2006 page 755 of 818

REJ09B0273-0500
Pin Function
(TOE10) output (TOE10)
1 0 DMAC DREQ0 acknowledge DMAC DREQ0 acknowledge
signal output (DRAK0) signal output (DRAK0)
1 Reserved Reserved
PC10MD0) 1 ATU one-shot pulse output ATU one-shot pulse output
(TOD10) (TOD10)
1 Reserved Reserved
(TOC10) (TOC10)
1 Reserved Reserved
(TOB10) (TOB10)
1 Reserved Reserved
Rev. 5.00 Jan 06, 2006 page 756 of 818

REJ09B0273-0500
PCCR2
Bit: 15 14 13 12 11 10 9 8
Bit name: PC7MD1 PC7MD0 PC6MD1 PC6MD0 — PC5MD — PC4MD
R/W: R/W R/W R/W R/W R R/W R R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: — PC3MD — PC2MD — PC1MD — PC0MD
Pin Function
(TOA10) (TOA10)
1 Reserved Reserved
PC6MD0) 1 Chip select output (CS2) Generic input/output (PC6)
1 0 Interrupt request input Interrupt request input
(IRQ6) (IRQ6)
1 A/D conversion end output A/D conversion end output
(ADEND) (ADEND)
10 PC5 mode bit 0 Generic input/output (PC5) Generic input/output (PC5)
(PC5MD) (Initial value) (Initial value)
1 Chip select output (CS1) Generic input/output (PC5)
(PC4MD) 1 Chip select output (CS0) Generic input/output (PC4)
6 PC3 mode bit 1 0 Generic input/output (PC3) Generic input/output (PC3)
(PC3MD) 1 Read output (RD) Generic input/output (PC3)
Rev. 5.00 Jan 06, 2006 page 757 of 818

REJ09B0273-0500
Pin Function
(PC2MD) 1 Wait state input (WAIT) Generic input/output (PC2)
(PC1MD) 1 Upper write (WRH) Generic input/output (PC1)
(PC0MD) 1 Lower write (WRL) Generic input/output (PC0)
Rev. 5.00 Jan 06, 2006 page 758 of 818

REJ09B0273-0500
Port D Data Register (PDDR) H'FFFF8398 8/16 Port D
Bit: 15 14 13 12 11 10 9 8
Bit name: PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

15–0 0 Generic input Pin state PDDR can be written to, but the pin state is
not affected
Other than Pin state PDDR can be written to, but the pin state is
1 Generic output PDDR value Write value is output at the pin (POD pin is
high)
High-impedance regardless of PDDR value
(POD pin is low)
Other than PDDR value PDDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 759 of 818

REJ09B0273-0500
Port D IO Register (PDIOR) H'FFFF839A 8/16 Port D
Bit: 15 14 13 12 11 10 9 8
Bit name: PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR

15–0 Port D IO register 0 Input (Initial value)
(PD15IOR to PD0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 760 of 818

REJ09B0273-0500
Port D Control Register (PDCR) H'FFFF839C 8/16 Port D
Bit: 15 14 13 12 11 10 9 8
Bit name: PD15MD PD14MD PD13MD PD12MD PD11MD PD10MD PD9MD PD8MD
Bit: 7 6 5 4 3 2 1 0
Bit name: PD7MD PD6MD PD5MD PD4MD PD3MD PD2MD PD1MD PD0MD
Pin Function
with ROM Disabled with ROM Disabled Expanded Mode
Bit Bit Name Value Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode
15 PD15 mode bit 0 Generic input/output Data input/output Generic input/output Generic input/output
(PD15MD) (PD15) (Initial value) (D15) (Initial value) (PD15) (Initial value) (PD15) (Initial value)
1 Data input/output Data input/output Data input/output Generic input/output
(D15) (D15) (D15) (PD15)
(D14) (D14) (D14) (PD14)
(D13) (D13) (D13) (PD13)
(D12) (D12) (D12) (PD12)
(D11) (D11) (D11) (PD11)
(D10) (D10) (D10) (PD10)
(D9) (D9) (D9) (PD9)
Rev. 5.00 Jan 06, 2006 page 761 of 818

REJ09B0273-0500
Pin Function
with ROM Disabled with ROM Disabled Expanded Mode
Bit Bit Name Value Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode
(D8) (D8) (D8) (PD8)
with ROM Disabled with ROM Enabled Single-Chip Mode
7 PD7 mode bit 0 Data input/output (D7) Generic input/output (PD7) Generic input/output (PD7)
(PD7MD) (Initial value) (Initial value) (Initial value)
1 Data input/output (D7) Data input/output (D7) Generic input/output (PD7)
6 PD6mode bit 0 Data input/output (D6) Generic input/output (PD6) Generic input/output (PD6)
Rev. 5.00 Jan 06, 2006 page 762 of 818

REJ09B0273-0500
Port Control Register (CKCR) H'FFFF839E 8/16 Port
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — — CKLO

0 CKLO 0 Selects the internal clock for the CK terminal output (Initial value)
1 Always selects the low level for the CK terminal output
Rev. 5.00 Jan 06, 2006 page 763 of 818

REJ09B0273-0500
Port E Data Register (PEDR) H'FFFF83A0 8/16 Port E
Bit: 15 14 13 12 11 10 9 8
Bit name: — PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR

14–0 0 Generic input Pin state PEDR can be written to, but the pin state is
not affected
Other than Pin state PEDR can be written to, but the pin state is
1 Generic output PEDR value Write value is output at the pin
Other than PEDR value PEDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 764 of 818

REJ09B0273-0500
Port E IO Register (PEIOR) H'FFFF83A2 8/16 Port E
Bit: 15 14 13 12 11 10 9 8
Bit name: — PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR

14–0 Port E IO register 0 Input (Initial value)
(PE14IOR to PE0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 765 of 818

REJ09B0273-0500
Port E Control Register (PECR) H'FFFF83A4 8/16 Port E
Bit: 15 14 13 12 11 10 9 8
Bit name: — PE14MD PE13MD PE12MD PE11MD PE10MD PE9MD PE8MD
Bit: 7 6 5 4 3 2 1 0
Bit name: PE7MD PE6MD PE5MD PE4MD PE3MD PE2MD PE1MD PE0MD
Bit Bit Name Value Pin Function

14 PE14 mode bit 0 Generic input/output (PE14) (Initial value)
(PE14MD) 1 ATU input capture input/output compare output (TIOC3)
(PE13MD) 1 ATU input capture input/output compare output (TIOB3)
(PE12MD) 1 ATU input capture input/output compare output (TIOA3)
(PE11MD) 1 ATU input capture input (TID0)
(PE10MD) 1 ATU input capture input (TIC0)
(PE9MD) 1 ATU input capture input (TIB0)
(PE8MD) 1 ATU input capture input (TIA0)
(PE5MD) 1 ATU input capture input/output compare output (TIOF1)
Rev. 5.00 Jan 06, 2006 page 766 of 818

REJ09B0273-0500

(PE4MD) 1 ATU input capture input/output compare output (TIOE1)
(PE3MD) 1 ATU input capture input/output compare output (TIOD1)
(PE2MD) 1 ATU input capture input/output compare output (TIOC1)
Rev. 5.00 Jan 06, 2006 page 767 of 818

REJ09B0273-0500
Port F Data Register (PFDR) H'FFFF83A6 8/16 Port F
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — PF11DR PF10DR PF9DR PF8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR

11–0 0 Generic input Pin state PFDR can be written to, but the pin state is
not affected
Other than Pin state PFDR can be written to, but the pin state is
1 Generic output PFDR value Write value is output at the pin
Other than PFDR value PFDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 768 of 818

REJ09B0273-0500
Port F IO Register (PFIOR) H'FFFF83A8 8/16 Port F
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — PF11IOR PF10IOR PF9IOR PF8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PF7IOR PF6IOR PF5IOR PF4IOR PF3IOR PF2IOR PF1IOR PF0IOR

11–0 Port F IO register 0 Input (Initial value)
(PF11IOR to PF0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 769 of 818

REJ09B0273-0500
Port F Control Registers 1 and 2 H'FFFF83AA (PFCR1) 8/16 Port F

(PFCR1, PFCR2) H'FFFF83AC (PFCR2)
PFCR1
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: PF11MD1 PF11MD0 PF10MD1 PF10MD0 PF9MD1 PF9MD0 PF8MD1 PF8MD0
Pin Function
7, 6 PF11 mode bit 1, 0 0 0 Generic input/output (PF11) Generic input/output (PF11)
(PF11MD1, PF11MD0) (Initial value) (Initial value)
1 Bus request input (BREQ) Generic input/output (PF11)
1 Reserved Reserved
1 Bus request acknowledge Generic input/output (PF10)
output (BACK)
1 Reserved Reserved
1 Chip select output (CS3) Generic input/output (PF9)
1 0 Interrupt request input Interrupt request input (IRQ7)
(IRQ7)
1 APC pulse output (PULS5) APC pulse output (PULS5)
1 Serial clock input/output (SCK2) Serial clock input/output (SCK2)
1 Reserved Reserved
Rev. 5.00 Jan 06, 2006 page 770 of 818

REJ09B0273-0500
PFCR2
Bit: 15 14 13 12 11 10 9 8
Bit name: PF7MD1 PF7MD0 PF6MD1 PF6MD0 PF5MD1 PF5MD0 PF4MD1 PF4MD0
Bit: 7 6 5 4 3 2 1 0
Bit name: — PF3MD — PF2MD — PF1MD — PF0MD
Pin Function
1 DMA transfer request input DMA transfer request input
(DREQ0) (DREQ0)
1 Reserved Reserved
(PF6MD1, PF6MD0) (Initial value)
1 DMA transfer request Generic input/output (PF6)
acknowledge output (DACK0)
1 Reserved Reserved
1 DMA transfer request input DMA transfer request input
(DREQ1) (DREQ1)
1 Reserved Reserved
(PF4MD1, PF4MD0) (Initial value)
1 DMA transfer request Generic input/output (PF4)
acknowledge output (DACK1)
1 Reserved Reserved
Rev. 5.00 Jan 06, 2006 page 771 of 818

REJ09B0273-0500
Pin Function
6 PF3 mode bit 0 Generic input/output (PF3) Generic input/output (PF3)
(PF3MD) (Initial value) (Initial value)
1 Interrupt request input Interrupt request input (IRQ3)
(IRQ3)
1 Interrupt request input Interrupt request input
(IRQ2) (IRQ2)
(IRQ1) (IRQ1)
(IRQ0) (IRQ0)
Rev. 5.00 Jan 06, 2006 page 772 of 818

REJ09B0273-0500
Port G Data Register (PGDR) H'FFFF83AE 8/16 Port G
Bit: 15 14 13 12 11 10 9 8
Bit name: PG15DR PG14DR PG13DR PG12DR PG11DR PG10DR PG9DR PG8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PG7DR PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR

15–0 0 Generic input Pin state PGDR can be written to, but the pin state is
not affected
Other than Pin state PGDR can be written to, but the pin state is
1 Generic output PGDR value Write value is output at the pin
Other than PGDR value PGDR can be written to, but the pin state is
Rev. 5.00 Jan 06, 2006 page 773 of 818

REJ09B0273-0500
Port G IO Register (PGIOR) H'FFFF83B0 8/16 Port G
Bit: 15 14 13 12 11 10 9 8
Bit name: PG15IORPG14IORPG13IORPG12IORPG11IORPG10IOR PG9IOR PG8IOR
Bit: 7 6 5 4 3 2 1 0
Bit name: PG7IOR PG6IOR PG5IOR PG4IOR PG3IOR PG2IOR PG1IOR PG0IOR

15–0 Port G IO register 0 Input (Initial value)
(PG15IOR to PG0IOR) 1 Output
Rev. 5.00 Jan 06, 2006 page 774 of 818

REJ09B0273-0500
Port G Control Registers 1 and 2 H'FFFF83B2 (PGCR1) 8/16 Port G

(PGCR1, PGCR2) H'FFFF83B4 (PGCR2)
PGCR1
Bit: 15 14 13 12 11 10 9 8
Bit name: PG15MD1 PG15MD0 PG14MD1 PG14MD0 — PG13MD — PG12MD
R/W: R/W R/W R/W R/W R R/W R R/W
Bit: 7 6 5 4 3 2 1 0
Bit name: — PG11MD — PG10MD — PG9MD — PG8MD

15, 14 PG15 mode bit 1, 0 0 0 Generic input/output (PG15) (Initial value)
(PG15MD1, PG15MD0) 1 Interrupt request input (IRQ5)
1 0 ATU input capture input/output compare output (TIOB5)
1 Reserved
(PG14MD1, PG14MD0) 1 Interrupt request input (IRQ4)
1 0 ATU input capture input/output compare output (TIOA5)
1 Reserved
10 PG13 mode bit 0 Generic input/output (PG13) (Initial value)
(PG13MD) 1 ATU input capture input/output compare output (TIOD4)
(PG12MD) 1 ATU input capture input/output compare output (TIOC4)
(PG11MD) 1 ATU input capture input/output compare output (TIOB4)
(PG10MD) 1 ATU input capture input/output compare output (TIOA4)
(PG9MD) 1 ATU input capture input/output compare output (TIOD3)
(PG8MD) 1 Receive data input (RXD2)
Rev. 5.00 Jan 06, 2006 page 775 of 818

REJ09B0273-0500
PGCR2
Bit: 15 14 13 12 11 10 9 8
Bit name: — PG7MD — PG6MD — PG5MD — PG4MD
Bit: 7 6 5 4 3 2 1 0
Bit name: — PG3MD PG2MD PG1MD PG0MD1 PG0MD0 IRQMD1 IRQMD0

14 PG7 mode bit (PG7MD) 0 Generic input/output (PG7) (Initial value)
1 Receive data output (RXD1)
1 Receive data output (RXD0)
(PG0MD1, PG0MD0) 1 A/D conversion trigger input (ADTRG)
1 0 Interrupt request output (IRQOUT)
1 Reserved
1, 0 IRQOUT mode bit 1, 0 0 0 IRQOUT is always high
(IRQMD1, IRQMD0) 1 Output on INTC interrupt request
1 0 Output on refresh request
1 Output on INTC interrupt request and refresh request
Rev. 5.00 Jan 06, 2006 page 776 of 818

REJ09B0273-0500
Port H Data Register (PHDR) H'FFFF83B6 8/16 Port H
Bit: 15 14 13 12 11 10 9 8
Bit name: PH15DR PH14DR PH13DR PH12DR PH11DR PH10DR PH9DR PH8DR
Bit: 7 6 5 4 3 2 1 0
Bit name: PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR
Pin Input/Output Pin Function Read Write

Input Generic Pin state is read Ignored (pin state is not affected)
ANn 1 is read Ignored (pin state is not affected)
n = 0–15
A/D Trigger Register (ADTRGR) H'FFFF83B8 8 A/D
Bit: 7 6 5 4 3 2 1 0
Bit name: EXTRG — — — — — — —

7 Trigger enable 0 A/D conversion is triggered by the ATU channel 0
(EXTRG) interval timer interrupt
1 A/D conversion is triggered by external pin input
(ADTRG) (Initial value)
Rev. 5.00 Jan 06, 2006 page 777 of 818

REJ09B0273-0500
Pulse Output Port Control Register H'FFFF83C0 8/16 APC

(POPCR)
Bit: 15 14 13 12 11 10 9 8
Bit name: PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0
ROE ROE ROE ROE ROE ROE ROE ROE
Bit: 7 6 5 4 3 2 1 0
Bit name: PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0
SOE SOE SOE SOE SOE SOE SOE SOE

15–8 PULS7 to PULS0 0 0 output to APC pulse output pin (PULS7–PULS0) is
reset output enable disabled (Initial value)
(PULS7ROE to 1 0 output to APC pulse output pin (PULS7–PULS0) is
PULS0ROE) enabled
7–0 PULS7 to PULS0 set 0 1 output to APC pulse output pin (PULS7–PULS0) is
output enable disabled (Initial value)
(PULS7SOE to 1 1 output to APC pulse output pin (PULS7–PULS0) is
PULS0SOE) enabled
Rev. 5.00 Jan 06, 2006 page 778 of 818

REJ09B0273-0500
System Control Register H'FFFF83C8 8 Power-Down State

(SYSCR)
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — — RAME

0 RAM enable (RAME) 0 On-chip RAM disabled
1 On-chip RAM enabled (Initial value)
Compare Match Timer Start Register H'FFFF83D0 8/16/32 CMT

(CMSTR) (All Channels)
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — — STR1 STR0

1 Count start 1 (STR1) 0 CMCNT1 halted (Initial value)
1 CMCNT1 counts
0 Count start 0 (STR0) 0 CMCNT0 halted (Initial value)
1 CMCNT0 counts
Rev. 5.00 Jan 06, 2006 page 779 of 818

REJ09B0273-0500
Compare Match Timer Control/ H'FFFF83D2 (Channel 0) 8/16/32 CMT

Status Register (CMCSR) H'FFFF83D8 (Channel 1)
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: CMF CMIE — — — — CKS1 CKS0
R/W: R/(W)* R/W — — — — R/W R/W

7 Compare match flag 0 CMCNT and CMCOR values do not match
(CMF) (Initial value)
Read CMF when CMF =1, then write 0 in CMF
1 CMCNT and CMCOR values match
6 Compare match interrupt 0 Compare match interrupt (CMI) disabled
enable (CMIE) (Initial value)
1 Compare match interrupt (CMI) enabled
1, 0 Clock select 1 and 0 0 0 φ/8 (Initial value)
(CKS1, CKS0) 1 φ/32
1 0 φ/128
1 φ/512
Rev. 5.00 Jan 06, 2006 page 780 of 818

REJ09B0273-0500
Compare Match Timer Counter H'FFFF83D4 (Channel 0) 8/16/32 CMT

(CMCNT) H'FFFF83DA (Channel 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15–0 (Count value) Input clock count value
Compare Match Timer Constant H'FFFF83D6 (Channel 0) 8/16/32 CMT

Register (CMCOR) H'FFFF83DC (Channel 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

15–0 (Compare match cycle) Set with compare match cycle
Rev. 5.00 Jan 06, 2006 page 781 of 818

REJ09B0273-0500
Flash Memory Control Register 1 H'FFFF8580 8 Flash Memory

(FLMCR1)
Bit: 7 6 5 4 3 2 1 0
Bit name: FWE SWE ESU PSU EV PV E P
Initial value: 1/0 0 0 0 0 0 0 0

7 Flash write enable 0 Low-level input at FWE pin (hardware protect
(FWE) state)
1 High-level input at FWE pin
6 Software write enable 0 Writes disabled (Initial value)
(SWE) 1 Writes enabled
[Setting condition]
FWE = 1
5 Erase setup (ESU) 0 Erase setup released (Initial value)
1 Erase setup
4 Program setup (PSU) 0 Program setup released (Initial value)
1 Program setup
3 Erase-verify (EV) 0 Exit from erase-verify mode (Initial value)
2 Program-verify (PV) 0 Exit from program-verify mode (Initial value)
1 Erase (E) 0 Exit from erase mode (Initial value)
0 Program (P) 0 Exit from program mode (Initial value)
Rev. 5.00 Jan 06, 2006 page 782 of 818

REJ09B0273-0500
Flash Memory Control Register 2 H'FFFF8581 8 Flash Memory

(FLMCR2)
Bit: 7 6 5 4 3 2 1 0
Bit name: FLER — — — — — — —

7 Flash memory error 0 Flash memory operates normally (Initial value)
(FLER) Flash memory is not write/erase-protected (is not in
error protect mode)
Reset or transition to hardware standby mode
1 Error occurred during flash memory write/erase
Flash memory is write/erase-protected (is in error
protect mode)
[Setting condition]
See Error Protect Mode
Erase Block Register 1 (EBR1) H'FFFF8582 8 Flash Memory
Bit: 7 6 5 4 3 2 1 0
Bit name: EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

7–0 (Block specification) Specifies flash memory erase area, block by
block
Rev. 5.00 Jan 06, 2006 page 783 of 818

REJ09B0273-0500
A/D Data Registers 0(H/L) to 15(H/L) H'FFFF85D0 8/16 A/D

(ADDR0(H/L) to ADDR15(H/L)) H'FFFF85D2
H'FFFF85D4
H'FFFF85D6
H'FFFF85D8
H'FFFF85DA
H'FFFF85DC
H'FFFF85DE
H'FFFF85E0
H'FFFF85E2
H'FFFF85E4
H'FFFF85E6
H'FFFF85F0
H'FFFF85F2
H'FFFF85F4
H'FFFF85F6
Bit: 15 14 13 12 11 10 9 8
Bit name: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Bit: 7 6 5 4 3 2 1 0
Bit name: AD1 AD0 — — — — — —

15–8 A/D data register 9 to 2 Upper 8 bits of A/D conversion result
7, 6 A/D data register 1 and 0 Lower 2 bits of A/D conversion result
Rev. 5.00 Jan 06, 2006 page 784 of 818

REJ09B0273-0500
A/D Control/Status Register 0 H'FFFF85E8 8/16 A/D

(ADCSR0)
Bit: 7 6 5 4 3 2 1 0
Bit name: ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0
R/W: R/(W)* R/W R/W R/W R/W R/W R/W R/W

7 A/D end flag (ADF) 0 A/D0 executing A/D conversion or in idle state (Initial value)
1. Read ADF when ADF =1, then write 0 in ADF
2. DMAC activated by ADI0 interrupt
1 A/D0 has ended A/D conversion and digital value has been transferred to
ADDR
1. Single mode: A/D conversion ends
2. Scan mode: All A/D conversion ends within one selected analog group
6 A/D interrupt enable 0 ADI0 A/D interrupt is disabled (Initial value)
(ADIE) 1 ADI0 A/D interrupt is enabled
5, 4 A/D mode 1 and 0 0 0 Single mode
(ADM1, ADM0) 1 4-channel scan mode (analog group 0/group 1/group 2)
1 0 8-channel scan mode (analog groups 0 and 1)
1 12-channel scan mode (analog groups 0, 1, and 2)
3, 2, Channel select 3 to 0 Analog Input Channels
1, 0 (CH3 to CH0) 4-Channel 8-Channel 12-Channel
Single Mode Scan Mode Scan Mode Scan Mode
0 0 0 0 AN0 AN0 AN0, 4 AN0, 4, 8
(Initial value)
1 AN1 AN0, 1 AN0, 1, 4, 5 AN0, 1, 4, 5, 8, 9
1 0 AN2 AN0–2 AN0–2, 4–6 AN0–2, 4–6,
8–10
1 AN3 AN0–3 AN0–7 AN0–11
1 0 0 AN4 AN4 AN0, 4 AN0, 4, 8
1 AN5 AN4, 5 AN0, 1, 4, 5 AN0, 1, 4, 5, 8, 9
1 0 AN6 AN4–6 AN0–2, 4–6 AN0–2, 4–6,
8–10
1 AN7 AN4–7 AN0–7 AN0–11
1 2
1 0* 0 0 AN8 AN8 Reserved* AN0, 4, 8
1 AN9 AN8, 9 AN0, 1, 4, 5, 8, 9
1 0 AN10 AN8–10 AN0–2, 4–6, 8–10
1 AN11 AN8–11 AN0–11
Notes: 1. Must be cleared to 0.
2. Reserved for future expansion. Do not use these settings.
Rev. 5.00 Jan 06, 2006 page 785 of 818

REJ09B0273-0500
A/D Control Register 0 (ADCR0) H'FFFF85E9 8/16 A/D
Bit: 7 6 5 4 3 2 1 0
Bit name: TRGE CKS ADST — — — — —
R/W: R/W R/W R/W R R R R R

7 Trigger enable 0 Starting of A/D conversion by external trigger or ATU
(TRGE) trigger is disabled (Initial value)
1 Starting of A/D conversion by external trigger or ATU
trigger is enabled
6 Clock select (CKS) 0 Conversion time = 266 states (maximum) (Initial value)
5 A/D start (ADST) 0 A/D conversion is stopped (Initial value)
1 A/D conversion is in progress
1. Single mode: ADST is cleared automatically when
A/D conversion ends
2. Scan mode: Confirm that ADF in ADCSR0 is 1, then
write 0 in ADST
Rev. 5.00 Jan 06, 2006 page 786 of 818

REJ09B0273-0500
A/D Control/Status Register 1 H'FFFF85F8 8/16 A/D

(ADCSR1)
Bit: 7 6 5 4 3 2 1 0
Bit name: ADF ADIE ADST SCAN CKS — CH1 CH0
R/W: R/(W)* R/W R/W R/W R/W R R/W R/W

7 A/D end flag (ADF) 0 A/D1 executing A/D conversion or in idle state (Initial value)
1. Read ADF when ADF =1, then write 0 in ADF
2. DMAC activated by ADI1 interrupt
1 A/D1 has ended A/D conversion and digital value has been
transferred to ADDR
1. Single mode: A/D conversion ends
2. Scan mode: All A/D conversion ends within one selected
analog group
6 A/D interrupt enable 0 ADI1 A/D interrupt is disabled (Initial value)
(ADIE) 1 ADI1 A/D interrupt is enabled
5 A/D start (ADST) 0 A/D conversion is stopped (Initial value)
1 A/D conversion is in progress
1. Single mode: ADST is cleared automatically when A/D
conversion ends
2. Scan mode: Confirm that ADF in ADCSR1 is 1, then write 0
in ADST
4 Scan mode (SCAN) 0 Single mode (Initial value)
1 Scan mode
3 Clock select (CKS) 0 Conversion time = 266 states (maximum) (Initial value)
Single Mode Scan Mode
1, 0 Channel select 1 and 0 0 0 AN12 (Initial value) AN12
(CH1, CH0)
1 AN13 AN12, 13
1 0 AN14 AN12–14
1 AN15 AN12–15
Rev. 5.00 Jan 06, 2006 page 787 of 818

REJ09B0273-0500
A/D Control Register 1 (ADCR1) H'FFFF85F9 8/16 A/D
Bit: 7 6 5 4 3 2 1 0
Bit name: TRGE — — — — — — —

7 Trigger enable (TRGE) 0 Starting of A/D conversion by external trigger or
ATU trigger is disabled (Initial value)
1 Starting of A/D conversion by external trigger or
ATU trigger is enabled
User Break Address Register H H'FFFF8600 8/16/32 UBC

(UBARH)
Bit: 15 14 13 12 11 10 9 8
Bit name: UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24
Bit: 7 6 5 4 3 2 1 0

15–0 User break address 31 to 16 Upper half (bits 31 to 16) of the address taken as
(UBA31 to UBA16) the break condition
Rev. 5.00 Jan 06, 2006 page 788 of 818

REJ09B0273-0500
User Break Address Register L H'FFFF8602 8/16/32 UBC

(UBARL)
Bit: 15 14 13 12 11 10 9 8
Bit: 7 6 5 4 3 2 1 0

15–0 User break address 15 to 0 Lower half (bits 15 to 0) of the address taken as
(UBA15 to UBA0) the break condition
User Break Address Mask Register H H'FFFF8604 8/16/32 UBC

(UBAMRH)
Bit: 15 14 13 12 11 10 9 8
Bit name: UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
Bit: 7 6 5 4 3 2 1 0

15–0 User break address mask 31 to 16 Specifies bits to be masked in break address set
(UBM31 to UBM16) in UBARH
Rev. 5.00 Jan 06, 2006 page 789 of 818

REJ09B0273-0500
User Break Address Mask Register L H'FFFF8606 8/16/32 UBC

(UBAMRL)
Bit: 15 14 13 12 11 10 9 8
Bit: 7 6 5 4 3 2 1 0

15–0 User break address mask 15 to 0 Specifies bits to be masked in break address set
(UBM15 to UBM0) in UBARL
Rev. 5.00 Jan 06, 2006 page 790 of 818

REJ09B0273-0500
User Break Bus Cycle Register (UBBR) H'FFFF8608 8/16/32 UBC
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0

7, 6 CPU cycle/peripheral 0 0 User break interrupt not generated (Initial value)
cycle select 1 CPU cycle taken as the break condition
(CP1, CP0)
1 0 Peripheral cycle taken as the break condition
1 CPU cycle and peripheral cycle both taken as break
conditions
5, 4 Instruction fetch/data 0 0 User break interrupt not generated (Initial value)
access select 1 Instruction fetch cycle taken as the break condition
(ID1, ID0)
1 0 Data access cycle taken as the break condition
1 Instruction fetch cycle and data access cycle both
taken as break conditions
3, 2 Read/write select 0 0 User break interrupt not generated (Initial value)
(RW1, RW0) 1 Read cycle taken as the break condition
1 0 Write cycle taken as the break condition
1 Read and write cycles both taken as break conditions
1, 0 Operand size select 0 0 Operand size not included in the break condition
(SZ1, SZ0) (Initial value)
1 Byte access taken as the break condition
1 0 Word access taken as the break condition
1 Longword access taken as the break condition
Rev. 5.00 Jan 06, 2006 page 791 of 818

REJ09B0273-0500
Timer Control/Status Register (TCSR) H'FFFF8610 8 WDT
Bit: 7 6 5 4 3 2 1 0
Bit name: OVF WT/IT TME — — CKS2 CKS1 CKS0
R/W: R/(W)* R/W R/W R R R/W R/W R/W
Note: * To prevent TCSR from being modified easily, the write method differs from that used for
general registers. For details, see section 12.2.4, Register Access.

7 Overflow flag (OVF) 0 No TCNT overflow in interval timer mode
(Initial value)
Read OVF, then write 0 in OVF
1 TCNT overflow in interval timer mode
6 Timer mode select 0 Interval timer mode: Interval timer interrupt (ITI)
(WT/IT) request sent to CPU when TCNT overflows
(Initial value)
1 Watchdog timer mode: WDTOVF signal output
externally when TCNT overflows
5 Timer enable (TME) 0 Timer disabled: TCNT is initialized to H'00 and
halted (Initial value)
1 Timer enabled: TCNT starts counting
WDTOVF signal or interrupt generated when
TCNT overflows
Overflow Interval*
Clock (When φ = 20 MHz)
2–0 Clock select 2 to 0 0 0 0 φ/2 (Initial value) 25.6 µs
(CKS2 to CKS0) 1 φ/64 819.2 µs
1 0 φ/128 1.6 ms
1 φ/256 3.3 ms
1 0 0 φ/512 6.6 ms
1 φ/1024 13.1 ms
1 0 φ/4096 52.4 ms
1 φ/8192 104.9 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev. 5.00 Jan 06, 2006 page 792 of 818

REJ09B0273-0500
Timer Counter (TCNT) H'FFFF8611 8 WDT
Bit: 7 6 5 4 3 2 1 0
Bit name:

7–0 (Count value) Input count clock value
Reset Control/Status Register H'FFFF8613 8 WDT

(RSTCSR)
Bit: 7 6 5 4 3 2 1 0
Bit name: WOVF RSTE — — — — — —
R/W: R/(W)* R/W R R R R R R

7 Watchdog timer 0 No TCNT overflow in watchdog timer mode (Initial value)
overflow flag [Clearing condition]
(WOVF)
Read WOVF when WOVF =1, then write 0 in WOVF
1 TCNT overflow in watchdog timer mode
6 Reset enable 0 No internal reset when TCNT overflows (Initial value)
(RSTE) 1 Internal reset when TCNT overflows
Note: The SH7050 chip is not reset internally, but TCNT and TCSR are reset in the watchdog
timer.
Rev. 5.00 Jan 06, 2006 page 793 of 818

REJ09B0273-0500
Standby Control Register H'FFFF8614 8 Power-Down State

(SBYCR)
Bit: 7 6 5 4 3 2 1 0
Bit name: SSBY HIZ — — — — — —
R/W: R/W R/W R R R R R R

7 Software standby 0 Transition to sleep mode on execution of SLEEP
(SSBY) instruction (Initial value)
1 Transition to software standby mode on execution of
SLEEP instruction
6 Port high-impedance 0 Pin states retained in software standby mode
(HIZ) (Initial value)
1 Pins set to high-impedance in software standby mode
Rev. 5.00 Jan 06, 2006 page 794 of 818

REJ09B0273-0500
Bus Control Register 1 (BCR1) H'FFFF8620 8/16/32 BSC
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — A3SZ A2SZ A1SZ A0SZ

3 CS3 space size 0 CS3 space has byte (8-bit) bus size
specification (A3SZ) 1 CS3 space has word (16-bit) bus size (Initial value)
Note: A0SZ is valid only in on-chip ROM enabled mode In on-chip ROM disabled mode, the bus
size for the CS0 space is set by the mode pins.
Rev. 5.00 Jan 06, 2006 page 795 of 818

REJ09B0273-0500
Bus Control Register 2 (BCR2) H'FFFF8622 8/16/32 BSC
Bit: 15 14 13 12 11 10 9 8
Bit name: IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00
Bit: 7 6 5 4 3 2 1 0
Bit name: CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0

15 Inter-cycle idle specification 0 0 No CS3 space idle cycle
14 (IW31, IW30) 1 One CS3 space idle cycle
1 0 Two CS3 space idle cycles
1 Three CS3 space idle cycles (Initial
value)
value)
value)
value)
Rev. 5.00 Jan 06, 2006 page 796 of 818

REJ09B0273-0500

7 Idle specification for 0 No idle cycle in CS3 space access
continuous access (CW3) 1 One idle cycle in CS3 space access(Initial
value)
value)
value)
value)
3 CS assert extension 0 No CS3 space CS assert extension
specification (SW3) 1 CS3 space CS assert extension (Initial
value)
value)
value)
value)
Rev. 5.00 Jan 06, 2006 page 797 of 818

REJ09B0273-0500
Wait Control Register 1 (WCR1) H'FFFF8624 8/16/32 BSC
Bit: 15 14 13 12 11 10 9 8
Bit name: W33 W32 W31 W30 W23 W22 W21 W20
Bit: 7 6 5 4 3 2 1 0
Bit name: W13 W12 W11 W10 W03 W02 W01 W00

15–12 CS3 space wait specification 0 0 0 0 No wait, external wait input disabled
(W33, W32, W31, W30)
0 0 0 1 One wait, external wait input enabled
··
·
1 1 1 1 15 waits, external wait input enabled
(Initial value)
(W23, W22, W21, W20)
··
·
(Initial value)
(W13, W12, W11, W10)
··
·
(Initial value)
(W03, W02, W01, W00)
··
·
(Initial value)
Rev. 5.00 Jan 06, 2006 page 798 of 818

REJ09B0273-0500
Wait Control Register 2 (WCR2) H'FFFF8626 8/16/32 BSC
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — DSW3 DSW2 DSW1 DSW0

3–0 Wait specification for CS 0 0 0 0 No wait, external wait input disabled
space single address mode 0 0 0 1 One wait, external wait input enabled
access (DSW3, DSW2,
DSW1, DSW0) to
(Initial value)
Rev. 5.00 Jan 06, 2006 page 799 of 818

REJ09B0273-0500
RAM Emulation Register (RAMER) H'FFFF8628 8/16/32 Flash Memory
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — — —
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — RAMS RAM1 RAM0

2 RAM select (RAMS) 0 Emulation not selected
Write/erase protection disabled for all flash
memory blocks (Initial value)
Write/erase protection enabled for all flash memory
blocks
1, 0 RAM Area Specification Selection of flash memory area overlapping RAM
(RAM1, RAM0)
RAM Area RAMS RAM1 RAM0

H'FFFFE800–H'FFF EBFF 0 * *
H'0001F000–H'0001F3FF 1 0 0
H'0001F400–H'0001F7FF 1 0 1
H'0001F800–H'0001FBFF 1 1 0
H'0001FC00–H'0001FFFF 1 1 1
Rev. 5.00 Jan 06, 2006 page 800 of 818

REJ09B0273-0500
DMAC Operation Register H'FFFF86B0 16 DMAC

(DMAOR) (All Channels)
Bit: 15 14 13 12 11 10 9 8
Bit name: — — — — — — PR1 PR0
Bit: 7 6 5 4 3 2 1 0
Bit name: — — — — — AE NMIF DME
R/W: R R R R R R R/(W)* R/W
Note: * Only 0 can be written in bits AE and NMIF, after reading 1 from these bits.

9, 8 Priority mode 1 and 0 0 0 Fixed priority order (CH0 > CH1 > CH2 > CH3)
(PR1, PR0) (Initial value)
1 Fixed priority order (CH0 > CH2 > CH3 > CH1)
1 0 Fixed priority order (CH2 > CH0 > CH1 > CH3)
1 Round robin mode
2 Address error flag (AE) 0 No address error, DMA transfer enabled (Initial value)
Read AE when AE =1, then write 0 in AE
1 Address error present, DMA transfer disabled
[Setting condition]
Address error due to DMAC
1 NMI flag (NMIF) 0 No NMI input, DMA transfer enabled (Initial value)
Read NMIF when NMIF =1, then write 0 in NMIF
1 NMI input present, DMA transfer disabled
[Setting condition]
NMI interrupt generated
0 DMAC master enable 0 Operation disabled on all channels (Initial value)
(DME) 1 Operation enabled on all channels
Rev. 5.00 Jan 06, 2006 page 801 of 818

REJ09B0273-0500
DMA Source Address Registers 0 to 3 H'FFFF86C0 (Channel 0) 16/32 DMAC

(SAR0 to SAR3) H'FFFF86D0 (Channel 1) 16/32
H'FFFF86E0 (Channel 2) 16/32
H'FFFF86F0 (Channel 3) 16/32
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name:
Initial value: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: — — — — — — — — — — — — — — — —

31–0 (Transfer source address specification) Specifies DMA transfer source address
Rev. 5.00 Jan 06, 2006 page 802 of 818

REJ09B0273-0500
DMA Destination Address Registers 0 to 3 H'FFFF86C4 (Channel 0) 16/32 DMAC

(DAR0 to DAR3) H'FFFF86D4 (Channel 1) 16/32
H'FFFF86E4 (Channel 2) 16/32
H'FFFF86F4 (Channel 3) 16/32
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name:
Initial value: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: — — — — — — — — — — — — — — — —

31–0 (Transfer destination address Specifies DMA transfer destination address
specification)
Rev. 5.00 Jan 06, 2006 page 803 of 818

REJ09B0273-0500
DMA Transfer Count Registers 0 to 3 H'FFFF86C8 (Channel 0) 32 DMAC

(DMATCR0 to DMATCR3) H'FFFF86D8 (Channel 1) 32
H'FFFF86E8 (Channel 2) 32
H'FFFF86F8 (Channel 3) 32
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name: — — — — — — — —
Initial value: 0 0 0 0 0 0 0 0 — — — — — — — —
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: — — — — — — — — — — — — — — — —

23 –0 (DMA transfer count specification) Specifies the number of DMA transfers (number of
bytes, words, or longwords)
During DMAC operation, indicates the remaining
number of transfers
Rev. 5.00 Jan 06, 2006 page 804 of 818

REJ09B0273-0500
DMA Channel Control Registers 0 to 3 H'FFFF86CC (Channel 0) 16/32 DMAC

(CHCR0 to CHCR3) H'FFFF86DC (Channel 1) 16/32
H'FFFF86EC (Channel 2) 16/32
H'FFFF86FC (Channel 3) 16/32
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit name: — — — — — — — — — — — DI RO RL AM AL
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name: DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 — DS TM TS1 TS0 IE TE DE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/(W) R/W
Notes: 1. Only 0 can be written in the TE bit, after reading 1 from this bit.
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.

20 Direct/indirect select 0 Channel 3 operates in direct address mode (Initial value)
(DI)
1 Channel 3 operates in indirect address mode
19 Source address reload 0 Source address not reloaded (Initial value)
(RO)
1 Source address reloaded
18 Request check level 0 Active-high DRAK output (Initial value)
(RL)
1 Active-low DRAK output
17 Acknowledge mode 0 DACK output in read cycle (Initial value)
(AM)
1 DACK output in write cycle
16 Acknowledge level 0 Active-high output (Initial value)
(AL)
1 Active-low output
15, 14 Destination address 0 0 Destination address fixed (Initial value)
mode 1 and 0
1 Destination address incremented (+1 for 8-bit transfer, +2 for 16-bit
(DM1, DM0)
transfer, +4 for 32-bit transfer)
1 0 Destination address decremented (–1 for 8-bit transfer, –2 for 16-bit
transfer, –4 for 32-bit transfer)
1 Setting prohibited
Rev. 5.00 Jan 06, 2006 page 805 of 818

REJ09B0273-0500

13, 12 Source address mode 0 0 Source address fixed (Initial value)
1 and 0 (SM1, SM0)
1 Source address incremented (+1 for 8-bit transfer, +2 for 16-bit
transfer, +4 for 32-bit transfer)
1 0 Source address decremented (–1 for 8-bit transfer, –2 for 16-bit
transfer, –4 for 32-bit transfer)
11–8 Resource select 0 0 0 0 External request, dual address mode (Initial value)
3, 2, 1, and 0
(RS3, RS2, RS1, RS0)
1 0 External request, single address mode
External address space to external device
1 External request, single address mode
External device to external address space
1 0 0 Auto-request
1 0 ATU, compare match 6 (CMI6)
1 ATU, input capture 0B (ICI0B)
1 SCI0 reception
1 0 SCI1 transmission
1 SCI1 reception
1 0 0 SCI2 transmission
1 SCI2 reception
1 0 On-chip A/D0
1 On-chip A/D1
6 DREQ select (DS) 0 Low level detection (Initial value)
1 Falling edge detection
5 Transmit mode (TM) 0 Cycle steal mode
1 Burst mode
4, 3 Transmit size 1 and 0 0 0 Byte size (8 bits) (Initial value)
(TS1, TS0)
1 Word size (16 bits)
1 0 Longword size (32 bits)
2 Interrupt enable (IE) 0 No interrupt request generated at end of number of transfers specified
in DMATCR (Initial value)
1 Interrupt request generated at end of number of transfers specified in
DMATCR
Rev. 5.00 Jan 06, 2006 page 806 of 818

REJ09B0273-0500

1 Transfer end (TE) 0 Number of transfers specified in DMATCR not completed(Initial value)
Read TE when TE =1, then write 0 in TE
Power-on reset or transition to standby mode
1 Number of transfers specified in DMATCR completed
0 DMAC enable (DE) 0 Operation on corresponding channel disabled (Initial value)
1 Operation on corresponding channel enabled
Rev. 5.00 Jan 06, 2006 page 807 of 818

REJ09B0273-0500
A.3 Register States at Reset and in Power-Down State

Reset Power-Down State
Registers Power- Hardware Software
Type (Abbreviations) On Standby Standby Sleep
CPU R0–R15 Initialized Initialized Held Held
SR
GBR
VBR
MACH, MACL
PR
PC
Interrupt controller IPRA–IPRH Initialized Initialized Held Held
(INTC) ICR
ISR
User break controller UBARH, UBARL Initialized Initialized Held Held
(UBC) UBAMRH, UBAMRL
UBBR
Bus state controller BCR1, BCR2 Initialized Initialized Held Held
(BSC) WCR1, WCR2
Direct memory SAR0–SAR3 Initialized Initialized Initialized Held
access controller DAR0–DAR3
(DMAC)
DMATCR0–DMATCR3
CHCR0–CHCR3
DMAOR
Rev. 5.00 Jan 06, 2006 page 808 of 818

REJ09B0273-0500

Advanced timer unit PSCR1 Initialized Initialized Initialized Held
(ATU) TSTR
TGSR
TIOR0A,
TIOR1A–TIOR1C,
TIOR2A, TIOR3A,
TIOR3B, TIOR4A,
TIOR4B, TIOR5A
ITVRR
TSRAH, TSRAL,
TSRB, TSRC, TSRDH,
TSRDL, TSRE, TSRF
TIERA, TIERB, TIERC
TIERDH, TIERDL,
TIERE, TIERF
TCNT0H, TCNT0L,
TCNT1–TCNT9
ICR0AH,L–ICR0DH,L
TCR1–TCR10
GR1A–GR1F, GR2A,
GR2B, GR3A–GR3D,
GR4A–GR4D, GR5A,
GR5B
OSBR
TMDR
CYLR6–CYLR9
BFR6–BFR9
DTR6–DTR9
TCNR
DSTR
DCNT10A–DCNT10H
Rev. 5.00 Jan 06, 2006 page 809 of 818

REJ09B0273-0500

Advanced pulse POPCR Initialized Initialized Held Held
controller (APC)
Watchdog timer TCNT Initialized Initialized Initialized Held
(WDT) TCSR *
RSTCSR Initialized
Serial communication SMR0–SMR2 Initialized Initialized Initialized Held
interface (SCI) BRR0–BRR2
SCR0–SCR2
TDR0–TDR2
SSR0–SSR2
RDR0–RDR2
A/D converter ADDR0(H/L)– Initialized Initialized Initialized Held
ADDR15(H/L)
ADCSR0, ADCSR1
ADCR0, ADCR1
ADTRGR
Compare match timer CMSTR Initialized Initialized Initialized Held
(CMT) CMCSR0, CMCSR1
CMCNT0, CMCNT1
CMCOR0, CMCOR1
Pin function controller PAIOR, PBIOR, Initialized Initialized Held Held
(PFC) PCIOR, PDIOR,
PEIOR, PFIOR,
PGIOR
PACR, PBCR, PCCR1,
PCCR2, PDCR, PECR,
PFCR1, PFCR2,
PGCR1, PGCR2
Rev. 5.00 Jan 06, 2006 page 810 of 818

REJ09B0273-0500

I/O ports PADR, PBDR, PCDR, Initialized Initialized Held Held
PDDR, PEDR, PFDR,
PGDR, PHDR
Flash ROM FLMCR1 Initialized Initialized Initialized Held
FLMCR2 Held
EBR1 Initialized
RAMER Held
Power-down state SBYCR Initialized Initialized Held Held
related SYSCR
Note: * Bits 7 to 5 (OVF, WT/IT, and TME) are initialized, and bits 2 to 0 (CKS2 to CKS0) are
held.
Rev. 5.00 Jan 06, 2006 page 811 of 818

REJ09B0273-0500
Appendix B Pin States
B.1 Pin States at Reset and in Power-Down, and Bus Right Released
State
Table B.1 shows the SH7050 pin states at reset and in power-down, and bus right released state.
Table B.1 Pin States at Reset and in Power-Down, and Bus Right Released State
Pin Function Pin State
Reset Power-Down
Power-On Reset by RES pin Bus-
Item Pins Hardware Software Released
ROMless, ROMless,
Expanded, Single- Standby Standby Sleep State
Expanded, Expanded,
with ROM Chip
8-Bit 16-Bit
Clock EXTAL I I I I Z Z I I
XTAL O O O O Z Z O O
CK O O O O Z H* O O
Operating FWE, I I I I I I I I
Mode MD0–MD3
Selection
HSTBY I I I I I I I I
System RES I I I I I I I I
Control
WDTOVF O O O O Z H* O O
BREQ — — — — Z Z I I
BACK — — — — Z Z O O
Interrupt NMI I I I I I I I I
IRQ0– — — — — Z Z I I
IRQ7
IRQOUT — — — — Z H* O O
Address A0–A21 L L — — Z Z O Z
Bus
Data Bus D0–D7 Z Z — — Z Z I/O Z
D8–D15 — Z — — Z Z I/O Z
Rev. 5.00 Jan 06, 2006 page 812 of 818

REJ09B0273-0500

Reset Power-Down
ROMless, ROMless,
Expanded, Expanded,
with ROM Chip
8-Bit 16-Bit
Bus CS0 H H H — Z Z O Z
Control
CS1–CS3 — — — — Z Z O Z
RD H H H — Z Z O Z
WRH, H H H — Z Z O Z
WRL
WAIT I I I — Z Z I Z
Direct DREQ0, — — — — Z Z I I
Memory DREQ1
Access
DRAK0, — — — — Z O* O O
Controller
DRAK1
(DMAC)
DACK0, — — — — Z O* O O
DACK1
Advanced TCLKA, — — — — Z Z I I
Timer Unit TCLKB
(ATU)
TIA0–TID0 — — — — Z Z I I
TIOA1– — — — — Z K* I/O I/O
TIOF1
TIOA2, — — — — Z K* I/O I/O
TIOB2
TIOA3– — — — — Z K* I/O I/O
TIOD3
TIOA4– — — — — Z K* I/O I/O
TIOD4
TIOA5, — — — — Z K* I/O I/O
TIOB5
TO6–TO9 — — — — Z O* O O
TOA10– — — — — Z O* O O
TOH10
Advanced PULS0– — — — — Z O* O O
Pulse PULS7
Controller
(APC)
Rev. 5.00 Jan 06, 2006 page 813 of 818

REJ09B0273-0500

Reset Power-Down
ROMless, ROMless,
Expanded, Expanded,
with ROM Chip
8-Bit 16-Bit
Serial TxD0– — — — — Z O* O O
Communi- TxD2
cation
RxD0– — — — — Z Z I I
Interface
RxD2
(SCI)
SCK0– — — — — Z K* I/O I/O
SCK2
A/D AN0–AN15 Z Z Z Z Z Z I I
Converter
ADTRG — — — — Z Z I I
ADEND — — — — Z O* O O
I/O Port POD — — — — Z Z I I
PA0–PA15 — — Z Z Z K* I/O I/O
PB0–PB5 Z Z Z Z Z K* I/O I/O
PB6–PB11 — — Z Z Z K* I/O I/O
PC0–PC4 — — — Z Z K* I/O I/O
PC5–PC14 Z Z Z Z Z K* I/O I/O
PD0–PD7 — — Z Z Z K* I/O I/O
PD8–PD15 Z — Z Z Z K* I/O I/O
PE0–PE14 Z Z Z Z Z K* I/O I/O
PF0–PF11 Z Z Z Z Z K* I/O I/O
PG0–PG15 Z Z Z Z Z K* I/O I/O
PH0–PH15 Z Z Z Z Z Z I I
I: Input
O: Output
H: High-level Output
L: Low-level Output
Z: High-impedance
K: Input pins are in the high-impedance state; output pins maintain their previous state.
Note: * When the HIZ bit of the standby control register (SBYCR) is set to 1, output pins are in
high impedance state.
Rev. 5.00 Jan 06, 2006 page 814 of 818

REJ09B0273-0500
B.2 Pin States of Bus Related Signals

Table B.2 shows the SH7050 pin states of BUS related signals.
Table B.2 Pin States of BUS Related Signals
On-Chip Peripheral Module

On-Chip On-Chip 16-Bit Space
Pins 8-Bit
ROM RAM Upper Lower Word/
Space
Byte Byte Long Word
CS0 to CS3 H H H H H H
RD R H H H H H H
W — H H H H H
WRH R H H H H H H
W — H H H H H
WRL R H H H H H H
W — H H H H H
A21 to A0 Address Address Address Address Address Address
D15 to D8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
D7 to D0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
External Common Space

Pins
8-Bit Space Upper Byte Lower Byte Word/Long Word
CS0 to CS3 Valid Valid Valid Valid
RD R L L L L
W H H H H
WRH R H H H H
W H L H L
WRL R H H H H
W L H L L
A21 to A0 Address Address Address Address
D15 to D8 Hi-Z Data Hi-Z Data
D7 to D0 Data Hi-Z Data Data
Note: R is reading operation.
W is writing operation.
Rev. 5.00 Jan 06, 2006 page 815 of 818

REJ09B0273-0500
Appendix C Product Code Lineup
Appendix C Product Code Lineup

Table C.1 shows SH7050 series product code lineup.
Table C.1 SH7050 Series Product Code Lineup
Product Type Product Code Mark Code Package

SH7050 Mask ROM HD6437050F20 HD6437050(***)F20 168 pin Plastic QFP
Flash memory HD64F7050SF20 HD64F7050SF20 (PRQP0168JA-A)
SH7051 Flash memory HD64F7051SF20 HD64F7051SF20

Note: For mask ROM versions, (***) is the ROM code.
Rev. 5.00 Jan 06, 2006 page 816 of 818

REJ09B0273-0500
Appendix D Package Dimensions

Figure D.1 shows the SH7050 series package dimensions (PRQP0168JA-A).
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-QFP168-28x28-0.65 PRQP0168JA-A FP-168/FP-168V 5.3g
HD
*1
D
126 85
127 84 NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
HE
b1
E
*2
c1
c
Reference Dimension in Millimeters
Symbol
ZE
Min Nom Max
43 Terminal cross section D
168 28
1 42
E 28
A2 3.20
ZD
HD 30.9 31.2 31.5
F
HE 30.9 31.2 31.5
A 3.56
A2
A1
A
0.00 0.15 0.25
c
bp 0.24 0.32 0.40
θ
L b1 0.30
A1
e *3 bp L1 c 0.12 0.17 0.22
y x M
c1 0.15
Detail F
θ 0° 8°
e 0.65
x 0.13
y 0.10
ZD 0.68
ZE 0.68
L 0.5 0.8 1.1
L1 1.6
Figure D.1 Package Dimensions
Rev. 5.00 Jan 06, 2006 page 817 of 818

REJ09B0273-0500
Rev. 5.00 Jan 06, 2006 page 818 of 818

REJ09B0273-0500
Renesas 32-Bit RISC Microcomputer
Hardware Manual
SH7050 Group, SH7050F-ZTAT , SH7051F-ZTAT

Publication Date: 1st Edition, March 1997
Rev.5.00, January 06, 2006
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 5.0
SH7050 Group, SH7050F-ZTAT,
SH7051F-ZTAT
Hardware Manual

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REJ09B0273-0500

The revision list can be viewed directly by

The revision list summarizes the locations of

SH7050 Group, SH7050F-ZTAT™,

Renesas 32-Bit RISC Microcomputer

Notes regarding these materials

Rev. 5.00 Jan 06, 2006 page ii of xx

SH7050 series instructions

SH-1/SH-2/SH-DSP Software Manual (Document No. REJ09B0171-0500O)

Rev. 5.00 Jan 06, 2006 page iii of xx

d12 format — dddddddddddd:

13.2.8 Bit Rate 385 Description amended

22.2 DC 655 Table amended

Table 22.3 656 Table amended

Rev. 5.00 Jan 06, 2006 page v of xx

Section 1 Overview ............................................................................................................. 1

Section 2 CPU ...................................................................................................................... 21

Section 3 Operating Modes............................................................................................... 51

Section 4 Clock Pulse Generator (CPG) ....................................................................... 53

Rev. 5.00 Jan 06, 2006 page vii of xx

Section 5 Exception Processing....................................................................................... 61

Section 6 Interrupt Controller (INTC) ........................................................................... 75

Rev. 5.00 Jan 06, 2006 page viii of xx

Section 7 User Break Controller (UBC) ....................................................................... 95

Section 8 Bus State Controller (BSC) ........................................................................... 109

Rev. 5.00 Jan 06, 2006 page ix of xx

Section 9 Direct Memory Access Controller (DMAC) ............................................ 135

Rev. 5.00 Jan 06, 2006 page x of xx

Section 10 Advanced Timer Unit (ATU) ..................................................................... 195

Rev. 5.00 Jan 06, 2006 page xi of xx

Section 11 Advanced Pulse Controller (APC) ............................................................ 345

Rev. 5.00 Jan 06, 2006 page xii of xx

Section 12 Watchdog Timer (WDT) .............................................................................. 355

Section 13 Serial Communication Interface (SCI) .................................................... 369

Rev. 5.00 Jan 06, 2006 page xiii of xx

Section 14 A/D Converter ................................................................................................. 431

Rev. 5.00 Jan 06, 2006 page xiv of xx

Section 15 Compare Match Timer (CMT) ................................................................... 459

Section 16 Pin Function Controller (PFC) ................................................................... 473

Rev. 5.00 Jan 06, 2006 page xv of xx

Section 17 I/O Ports (I/O) ................................................................................................. 517

Section 18 ROM (128 kB Version) ................................................................................ 535

Rev. 5.00 Jan 06, 2006 page xvi of xx

Section 19 ROM (256 kB Version) ................................................................................ 585

Rev. 5.00 Jan 06, 2006 page xvii of xx

Rev. 5.00 Jan 06, 2006 page xviii of xx

Section 21 Power-Down State ......................................................................................... 641

Section 22 Electrical Characteristics.............................................................................. 653

Rev. 5.00 Jan 06, 2006 page xix of xx

Appendix B Pin States ....................................................................................................... 812

Appendix C Product Code Lineup.................................................................................. 816

Appendix D Package Dimensions .................................................................................. 817

Rev. 5.00 Jan 06, 2006 page xx of xx

The features of the SH7050 series are summarized in table 1.1.

Note: F-ZTAT is a trademark of Renesas Technology Corp.

Rev. 5.00 Jan 06, 2006 page 1 of 818

Table 1.1 SH7050 Series Features

Rev. 5.00 Jan 06, 2006 page 2 of 818

Rev. 5.00 Jan 06, 2006 page 3 of 818

Rev. 5.00 Jan 06, 2006 page 4 of 818