Logic Assignment

Arba Minch University
Institute of Technology (AMiT)

Faculty of Electrical and Computer Engineering
Digital Logic Design - (ECEG-3114) Assignment & worksheet
1- Using Karnaugh Map method implement the minimum SOP expression for the logic function
specified in the truth table in Figure below.
2- Using Karnaugh Map SOP minimization, simplify the following Boolean functions.
a) F(A,B,C)= A’B’C + A’BC + A’BC’ + AB’C + ABC
b) F(A, B, C, D) = ABCD + AB’C’D’ + AB’C + AB
c) F(A, B, C, D) = F(A,B,C,D)= Σ(0,2,3,5,7,8, 13) + d(1,6, 12)
i. Without using don’t care terms
ii. Using don’t care terms
3- Using Karnaugh Map POS minimization, simplify the following Boolean functions.
F(A, B, C,D) = (A+B’+C+D’)( A’+B+C’+D)( A’+B’+C’+D’)
4- Design a circuit with a 4-bit BCD input A, B, C, D that produces an output W, X, Y, Z that is
equal to the input + 3 in binary. For example, 9 (1001) + 3 (0011) = 12 (1100). The outputs
for invalid BCD codes are don’t-cares.
5- Design a Gray code–to–BCD code converter that gives output code 1111 for all invalid input
combinations. Assume that the Gray code sequence for decimal numbers 0 through 9 is 0000,
0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, and 1101. All other input combinations
should be considered to be invalid.
1 AMIT - ECE
6- Complete the design of the BCD–to–seven-segment decoder by performing the following
steps:
a) Plot the seven maps for each of the outputs for the BCD–to–seven segment decoder
specified in Table below.
b) Simplify the seven output functions in sum-of-products form, and determine the total
number of gate inputs that will be needed to implement the decoder.
c) Verify that the seven output functions listed in the text give a valid simplification.
Compare the number of gate inputs with that obtained in part (b) and explain the
difference.
7- Implement the following Boolean function

i. using only NAND gates
ii. using only NOR gates
F = (AB' + CD')E + BC(A + B)
2 AMIT - ECE
8- Construct a 16 x 1 multiplexer :(using only block diagrams)
i. With two 8 x 1 and one 2 X 1 multiplexers.
ii. With only five 4x1 multiplexer
9- Design a combinational circuit using a ROM which accepts a 2-bit number and generate a
binary number equal to the cube of the input binary number.
10- A combinational circuit is defined by the functions
F1(A, B, C) = ∑(1, 2, 3, 5)
F2(ABC) = ∑(0, 2, 4, 6)
Implement the circuit with PLA having three inputs, four product terms, and two outputs.
11- The waveforms shown in Figure below, (a) are to be applied to the circuit shown in Figure
(b); assuming the initial value of Q = 0, determine the Q output.
a)
b)
12- The waveforms shown in Figure below are to be applied to two different FFs:
a. Positive-edge-triggered J-K
b. Negative-edge-triggered J-K
Draw the Q waveform response for each of these FFs, assuming that Q = 0 initially.
3 AMIT - ECE
13- A sequential circuit with two D flip-flops A and B, one input Y, and one output Z is
specified by the following input equations: DA = BY + AY, DB = Y, Z = A B
(a) Draw the logic diagram of the circuit.
(b) Derive the state table.
(c) Derive the state diagram.
14- A sequential circuit has two JK flip-flops, A and B; two inputs, x and y; and one out output,
z. the flip-flop input functions and the circuit output function are as follows;
JA=Bx+B’y’ KA=B’xy’
JB=A’x KB=A+xy’
z=Axy+Bx’y’
15- A JN flip-flop has two inputs, J and N. Input J behaves like the J input of a JKflip-flop and
input N behaves like the complement of the k input of a JK flip flop (that is, N=K’).
a) Tabulate the characteristic table of the flip-flop.
b) Tabulate the excitation table of the flip-flop.
c) Show that by connecting the two inputs together, one obtains a D flip-flop.
16- Design a sequential circuit with two D flip-flops A and B and one input X. When X = 0, the
state of the circuit remains the same. When X = 1, the circuit goes through the state
transitions from 00 to 10 to 11 to 01, back to 00, and then repeats.
17- Construct a MOD- 13 asynchronous counter that will count from 0000 (zero) through 1100
(decimal 12), and show their timing diagrams by applying 16-clock pulse to clock inputs
18- Design a synchronous counter to produce the following binary sequence. Use J-K flip-flops.
0, 9, 1, 8, 2, 7, 3, 6, 4, 5, 0, ...
Assignment: - All: Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12
4 AMIT - ECE

Logic Assignment

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Logic Assignment

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Arba Minch University

Institute of Technology (AMiT)

7- Implement the following Boolean function

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